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mk53761 july 1993 repertory dialer . single chip dtmf and pulse dialer . softswitch changes signaling mode from pulse to tone . nine number repertory plus recall of last number dialed (18 digits each) . flash key input initiates timed hook flash . 8 tone per second dialing in tone mode and 10 pps in pulse mode . dtmf active until key release . minimum dtmf duration/separation guaranteed (74/54 ms) . pacifier tone provides audible indi- cation of valid key input for non- dtmf key entries . powered from telephone line, low operating voltage for long loop ap- plications description the mk53761 is a silicon gate cmos ic that pro- vides necessary signals for either dtmf or loop dis- connect (pulse) dialing. the mk53761 buffers up to 18 digits into memory that can be later redialed with a single key input. up to nine repertory numbers may be stored. users can store all 12 signaling keys and access several unique functions with single key entries. these functions include : last number di- aled (lnd), softswitch, and flash. figure 2 shows the keypad configuration. a lnd key input automatically redials the last num- ber dialed. the prog key provides an easy way to program a number into any memory location (1-9) whether on-hook on off-hook. the mem key allows easy redialing of the number stored in memory lo- cations (1-9). the flash key simulates a 560 ms hook flash to transfer calls or to activate other special features provided by the pabx or a central office. dip18 so20 figure 1 : pin connections. v+ mode c1 c2 c3 osc1 v- osc2 c4 1 3 2 4 5 6 7 8 9 dtmf output pacifier tone/ chip disable mute output r3 r4 r2 r1 hks pulse output 18 17 16 15 14 12 13 11 10 d93tl017 dip18 ordering numbers : mk53761n00 MK53761D v+ mode c1 c2 c3 osc1 v- osc2 c4 dtmf output pacifier tone/ chip disable mute output r3 r4 r2 r1 hks pulse output 1 3 2 4 5 6 7 8 9 18 17 16 15 14 12 13 11 19 10 20 n.c. n.c. d93tl018 so20 1/11
functional pin description (dip18 only) v+ pin 1. v+ is the positive supply for the circuit and must meet the maximum and minimum voltage re- quirements. (see electrical specifications). mode input. pin 2. mode determines the dialer's default operating mode. when the device is powered up or the hookswitch inputis switched from on-hook, (v+), to off-hook, (v), the default determines the signal- ing mode. a v+ connection defaults to tone mode operation and a v connection defaults to pulse mode operation. when dialing in the pulse mode, a softswitch feature will allow a change to the tone mode whenever the * key, or softswitch, is depressed. subsequent * key inputs will causethe dtmf code for an * to be dialed. the softswitch will only switch from pulse to tone. af- ter returning to on-hook and back to off-hook, the part will be in pulse mode. redial by the lnd key will repeat the softswitch. c1, c2, c3, c4, r4, r3, r2, r1 keyboard inputs. the mk53761 interfaces with either the standard 2-of-8 with negative common or the singlecontact (form a) keyboard. a valid keypad entry is either a single row con- nected to a single column or v simultaneouslypre- sented to both a single row and column. in its qui- escent or standby state, during normal off-hook op- eration, either the rows or the columns are at a logic level 1 (v+). pulling one input low enables the on-chip oscillator. keyboard scanning then begins. scanning consists of rows and columns alternately switching high through on-chip pullups. after both a row and column key have been detected, the de- bounce counter is enabled and any noise (bouncing contacts, etc.) is ignored for a debounce period (tk d ) of 32ms. at this time, the keyboard is sampled and if both row and column information are valid, the information is buffered into the lnd location. if switched on-hook (pin 17 to pin 1), the keyboard in- puts all pull high through on-chip pullup resistors. figure 2 : keypad configuration. in the tone mode, if 2 or more keys in the same row or if 2 or more keys in the same column are de- pressed a single tone will be output. the tone will corres-pond to the row or column for which the 2 keys were pushed. this feature is for test purposes, and single tones will not be redialed. also in the tone mode, the outputtone is continuous is manual dialing as long as the key is pushed. the output tone duration follows the table 1. table 1 : output tone duration. key-push time, t* tone outpu t* t 32ms no output ignored by mk53761 32ms t 75ms + t kd 75ms duration output t 75ms + t kd output duration = t t kd * tkd is the key pad debounce time which is typically 32 ms. whenredialing in the tone mode, eachdtmf output is 75ms duration, and the tone separation (intersig- nal delay) is 50ms. v input. pin 6 is the negative supply input to the de- vice. this is the voltage reference for all specifica- tions. osc1, osc2 pin 7 (input), pin 8 (output). osc1 and osc2 are connections to an on-chip inverter used as the tim- ing reference forthe circuit. it has sufficient loopgain to oscillate when used with a low-cost television color-burst crystal. the nominal crystal frequency is 3.579545mhz and any deviation from this standard is directly reflected in the tone output frequencies. the crystal oscillator provides the time reference for all circuit functions. a ceramic resonator with toler- ance of 0.25 % may also be used. dtmf output output. pin 10. an npn transistor emitter with a col- lector tied to v+ drives the dtmf output pin. the transistor base is connected to an on-chip opera- tional amplifier that mixes the row and column tones. figure 7 shows the timing at this pin. the dtmf output is the summation of a single row frequency and a single column frequency. a typical single tone sine wave is shown in figure 4. this waveform is synthesized using a resistor tree with sinusoidally weighted taps. the mk53761 is designed to operate from an un- regulated supply ; the tone level is supply inde- pendent, and the single row tone output level will be typically : t oi = 12 dbm 1db the dc componentof the dtmf output while active is described by the following equation : vdc 1 = 0.3 v+ + 0.5 volts mk53761 2/11
figure 3 : mk53761 functional block diagram. figure 5 : typical dual tone. figure 4 : typical single tone. mk53761 3/11
table 2 : dtmf output frequency. key input standard frequency actual frequency % deviation row 1 2 3 4 697 770 852 941 699.1 766.2 847.4 948.0 + 0.31 0.49 0.54 + 0.74 col 1 2 3 1209 1336 1477 1215.9 1331.7 1471.9 + 0.57 0.32 0.35 pacifier tone output/chip disable input output. pin 11. the pacifier tone provides audible figure 6 : typical spectral response. feed-back, confirming that the key has been prop- erly entered and accepted. a 500 hz square wave is activated upon acceptance of a valid key input, af- ter the 32 ms debounce time. the square wave ter- minates after a maximum of 30 ms or when the valid key is no longer present. in pulse mode, all key en- tries activate the pacifier tone. in tone mode, any non-dtmf key (lnd, flash, mem, prog) entry activates the pacifier tone. when programming the chip, all valid key entries activate the pacifier tone in either pulse or tone mode. the chip disable is an input. when pin 11 is switched low through a resistor (10 k to 100 k), the mk53761 is enabled. when pin 11 is switched to v+ through the resistor, all keypad inputs are pulled high, and the mk53761 will ignore all keypad inputs. when the chip is disabled, it will not dial, and it can- not be programmed. the chip can only be disabled when the circuit is inactive (not dialing) and pin 12 is switched high. mute output output. pin 12. this pin is the mute output for both tone and pulse modes. timing is dependent upon mode. the mute output consists of an open drain n- channel device. during standby, the output is high impedance and generally has an external pullup re- sistor to the positive supply. in the tone mode, mute output is used to re- move the transmitter and the receiver from the net- work during dtmf signaling. during dialing, mute output is active continuously until dialing is com- pleted. mute output goes active when any key is pushed. in the pulse mode, mute output is used to re- move the receiver and the network from the line. dif- ferent circuitry is required for tone and pulse muting externalto the ic and applicationsusing both modes would not necessarily share circuitry. mute out- put timing is shown in figure 8 for pulse mode sig- naling and figure 7 for tone mode signaling. mute output is active during each digit, and not active during the interdigit time. in both tone and pulse modes, mute output goes active 40 ms before pulse output for a flash. figure 8 illustrates the timing for this pin. hks input. pin 17. pin 17 is the hookswitch input to the mk53761. this is a high-impedanceinput and must be switched high for on-hook operation or low for off- hook operation. a transition on this input causes the on-chip logic to initialize, terminating any operation in progress at the time. the signaling mode defaults to the mode selected at pin 2. pulse output output. pin 18. this is an output consisting of an open drain n-channel device. in either pulse or tone mode, the flash key will cause a 560 ms output pulse at pin 18. mk53761 4/11
figure 8 : pulse mode timing. figure 7 : tone mode timing. notes : 1. for this example, key entries are 75 ms, but 32 ms. 2. mute goes active after any key is depressed. mk53761 5/11
device operation when the mk53761 is not actively dialing, it con- sumes very little current. row and column inputs assume opposite states off-hook. the circuit verifies that a valid key has been entered by alternately scanning the row and column inputs. if the input is still valid following 32 ms of debounce, the digit is stored into memory, and dialing begins after a pre- signal delay of approximately 40 ms (measured from initial key closure). output tone duration is shown in table 1. the mk53761 allows manual dialing of an indefinite numberof digits, but if more than 18 digits are dialed per number, the 53761 will owrap aroundo. that is, the extra digits beyond 18 will be stored at the be- ginning of the lnd buffer, and the first 18 digits will no longer be available for redial. during autodial fromlnd or any memory location,key inputsare not accepted, but they will suspend dialing until re- leased. normal dialing (off-hook) d d d ...etc lnd d flash d ...etc normal dialing is straightforward, all keyboard en- tries will be stored in the buffer and signaled in suc- cession. last number dialed (lnd) last number dialing is accomplished by entering the lnd key. hook flash hook flash may be entered into the dialed sequence at any point by keying in the function key, flash. flash consists of a timed break of 560 ms. the flash function is stored in memory, but it will not be redialed as such. when a flash key is pressed, no further key inputs will be accepted until the hook- flash function (560 ms break) has been dialed. the key input following a flash will be stored as the in- itial digit of a new number (overwriting the number dialed prior to the flash) unless it is another flash. consecutive flash entries after a number is dialed will be stored sequentiallyin the lnd mem- ory and a subsequentlnd entrywill cause the redial of that number with a delay, but not hookflash breaks, at the end of the redialing sequence. when redialing in tone mode, mute output will remain active during the flash delay period. softswitch whendialing in the pulse mode, a softswitch feature will allow a change to the tone mode whenever the * key is depressed. subsequent * key inputs will cause the dtmf code for an * to be dialed. the soft- switch will only switch from pulse to tone. after re- turning to on-hook and back to off-hook, the part will be in pulse mode. redial by the lnd key will repeat the softswitch. programming and repertory dialing programming is independent of hks (pin 17) and mode (pin 2). to program, enter the following : prog, digit 1, digit 2, ..., mem, location (1-9). when programming, dialing in inhibited. to dail a numberfrom repertory memory (hks must be low) enter the following : mem, location (1-9). to save the last number dialed : prog, mem, lo- cation (1-9). mk53761 6/11
absolute maximum ratings* parameter value unit dc supply voltage 6.5 v operating temperature 20 to +60 c storage temperature 55 to + 125 c maximum power dissipation (25 c) 500 mw maximum voltage on any pin (v + )+.3;(v ) .3 v * all specifications are for 2.5 volt operation and full operating temperature range unless otherwise stated. dc characteristics symbol parameter min. typ. max. unit notes v+ tone dc operating voltage (tone mode) 2.5 6.0 v v mr memory retention voltage 1.5 v 1. 6 i s standby current 0.4 1.0 m a1 i mr memory retention current 0.15 0.75 m a5.6 v mute mute output operating voltage 1.8 v 7 i t operating current (tone) 300 600 m a2 i p operating current (pulse) 150 250 m a2 operating current on-hook program mode key operated no-key operated 200 1 m a m a i ml mute output (2.5 volts) sink current (4.0 volts) 1.0 3.0 ma ma 3 i pl pulse output sink current 1.0 2.0 ma 3 i pc pacifier tone sink/source 250 500 m a4 k ru keypad pullup resistance 100 k w k rd keypad pulldown resistance 500 w v il keypad input level-low 0 0.3 v + v v ih keypad input level-high 0.7 v + v+ v v pulse operating voltage (pulse mode) 1.8 6.0 v notes : 1. all inputs unloaded. quiescent mode (oscillator off). 2. all outputs unloaded, single key input. 3. v out = 0.4 volts. 4. sink current for v out = 0.5 volts, source current for v out = 2.0 volts. 5. memory retention voltage is the point where memory is guaranteed but circuit operation is not. 6. proper memory retention is guaranteed if either the minimum i mr is provided or the minimum v mr . the design does not have to provide both the minimum current or voltage simultaneously. 7. minimum voltage where activation of mute output with key entry is ensured. electrical characteristics (t amb =25 c unless otherwise specified) table 3 : special function delays. function first/auto pulse tone softswitch first auto 0.40 1.10 each delay shown below represents the time required from after the special function key is depressed until a new digit can be dialed. the time is considered ofirsto key is all previous inputs have been completed dialed. the time is considered oautoo if in redial, or previous dialing is still in progress. mk53761 7/11
ac characteristics tone mode n symbol parameter min. typ. max. unit notes t nk tone output no key down 80 dbm 1 t oi tone output (independent) 13 173 12 194 11 218 dbm mv rms 1, 2 3 pe i pre-emphasis, high band 1.4 2.0 2.6 db dc i tone output dc bias v + = 2.5 v + = 3.5 1.25 1.5 v r e tone output load 10 k w 4 t ris tone output rise time 1.0 ms 5 dis output distortion 5.0 8.0 % 3 tr tone signaling rate 8.0 1/sec 1t psd pre-signal delay 40 ms 6 2t isd inter-signal delay (repertory) 54 ms t dur tone output duration (repertory) 74 ms notes : 1. o dbm equals 1 mw power into 600 w or 775 mvolts.important note : the mk53761 is designed to drive a 10 k w load. the 600 w load is only for reference. 2. single tone (low group), as measured at pin 10, t a =25 c. 3. supply voltage = 2.5v; r e =10k w. t oi increases typically of 10mvrms with v s =6v. 4. supply voltage = 2.5 volts. 5. time from beginning of tone output waveform to 90 % of final magnitude of either frequency. crystal parameters suggested for proper operation are r s < 100 w ,l m = 96 mh, c m = 0.02 pf, c h = 5 pf, f = 3.579545 mhz, and c l =18pf. 6. time from initial key input until beginnig of signaling. ac characteristics keypad inputs, pacifier tone (numbers in left hand column refer to the timing diagrams.) n symbol parameter min. typ. max. unit notes 3t kd keypad debounce time 32 ms 1 f ks keypad scan frequency 250 hz 1 f pt frequency pacifier tone 500 hz 1 4t pt pacifier tone duration 30 ms 1 t hfp hookflash timing 560 ms 1 ac characteristics pulse mode operation n symbol parameter min. typ. max. unit notes p r pulse rate 10 pps 1 5 pdp predigital pause 48 ms 2 6 idp interdigital pause 740 ms 2 7t mo mute overlap time 2 ms 2 8t b break time 60 ms 2 9t m make time 40 ms 2 notes : 1. 10 pps is the nominal rate. 2. figure 8 illustrates this relationship. electrical characteristics (continued) note : 1. crystal oscillator accuracy directly affects these times mk53761 8/11
so20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 o (typ.) d 12.6 13.0 0.496 0.510 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.4 7.6 0.291 0.300 l 0.5 1.27 0.020 0.050 m 0.75 0.030 s8 o (max.) mk53761 9/11
dip18 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.064 b 0.46 0.018 b1 0.25 0.010 d 23.24 0.914 e 8.5 0.335 e 2.54 0.100 e3 20.32 0.800 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.27 1.59 0.050 0.062 mk53761 10/11
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifica- tions mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pre- viously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. mk53761 11/11

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