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future technology devices international ltd. http://www.vinculum.com copyright ? future technology devices international ltd. 2006 vinculum VNC1L embedded usb host controller i.c. the vinculum VNC1L is the rst of ftdi?s vinculum family of embedded usb host controller integrated circuit devices. not only is it able to handle the usb host interface, and data transfer functions but owing to the inbuilt mcu and embedded flash memory, vinculum can encapsulate the usb device classes as well. when interfacing to mass storage devices such as usb flash drives, vinculum also transparently handles the fat file structure communicating via uart, spi or parallel fifo interfaces via a simple to implement command set. vinculum provides a new cost effective solution for providing usb host capability into products that previously did not have the hardware resources available. the VNC1L is available in pb-free (rohs compliant) compact 48-lead lqfp package. ? ?
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 2 1.3 typical applications ? single chip embedded usb host / slave controller i.c. device ? entire usb protocol handled on the chip ? 8 / 32 bit v-mcu core ? twin dma controllers for hardware acceleration ? integrated 12 mhz to 48 mhz clock multiplier ? integrated power-on-reset circuit with optional reset# input pin ? 64k byte embedded flash rom program memory ? 4k byte internal data sram ? standard usb rmware library supplied by ftdi ? program or update rmware via usb flash disk or uart interface ? firmware easily upgradable in the eld ? prog# rmware programming control pin ? two independent usb 2.0 low speed / full speed usb host / slave ports with integrated pull-up and pull-down resistors ? four fully con gurable data i/o and control buses ? uart interface mode for data i/o, rmware programming, and command monitor interface ? fifo interface mode with 8 bit bi-directional data bus and simple 4 wire handshake for data i/o and command monitor interface ? spi slave interface mode for data i/o and command monitor interface ? up to 28 gpio interface pins for data i/o and command monitor interface ? interface to mcu / pld / fpga via uart, fifo, or spi interface ? legacy ps/2 keyboard and mouse interfaces ? multi-processor con guration capable ? support for usb suspend and resume ? support for bus powered, self powered, and high- power bus powered usb device con gurations ? 3.3v operation with 5v safe inputs ? low operating and usb suspend current (25ma running / 2ma stnadby) ? fully compliant with usb 2.0 speci cation - usb full speed (12 mbps) and low speed (1.5 mbps) usb host and slave device compatible ? 0c to 70c operating temperature range ? full driver support for target / slave applications ? available in compact pb-free and green 48 pin lqfp package (rohs compliant) ? full range of reference designs and evaluation kits available 1 . f e a t u r e s 1. features ? add usb host capability to embedded products ? interface usb flash drive to mcu / pld / fpga ? usb flash drive to usb flash drive le transfer interface ? digital camera to usb flash drive or other usb slave device interface ? pda to usb flash driver or other usb slave device interface ? mp3 player to usb flash drive or other usb slave device interface ? usb mp3 player to usb mp3 player ? mobile phone to usb flash drive or other usb slave device interface ? gps to mobile phone interface ? instrumentation usb flash drive or other usb slave device interfacing ? datalogger usb flash drive or other usb slave device interface ? set top box - usb device interface ? usb slave device and usb flash disk interface with selectable uart / fifo / spi interface or usb slave device as the command monitor port (vdif rmware) ? ftdi usb slave device and usb flash disk interface with selectable uart / fifo / spi interface as the command monitor port (vdap rmware) ? usb flash disk to usb flash disk with gpio command monitor interface (vdfc rmware) ? ftdi usb slave device and usb flash disk interface with selectable uart / fifo / spi interface as the command monitor port with audio playback command extensions (vmsc rmware) 1.2 standard firmware 1.1 hardware features
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 3 2 . b l o c k d i a g r a m 2. block diagram 2.1 simpli ed block diagram figure 1 - simpli ed block diagram xtin xtout program and test logic reset# prog# test pll filter 64k x 8 e-flash program rom vinculum mcu core vinculum 32-bit npu dma controller 1 4k x 8 data sram clock multiplier pll 48 mhz usb host / slave transceiver 1 usb1dp usb1dm usb2dp usb2dm usb host / slave transceiver 2 usb host / slave sie 1 usb host / slave sie 2 12 mhz oscillator 24 mhz dma controller 2 uart prescaler 48 mhz nmi int internal io bus bootstrap loader rom uart & fifo i/f logic 24 mhz system timer int internal io bus adbus[0 ...7] spi i/f logic external io bus gpio 3 i/f logic gpio 2 i/f logic gpio 1 i/f logic gpio 0 i/f logic acbus[0 ...7] bdbus[0 ...7] bcbus[0 ...3]
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 4 2.2 functional block descriptions usb host / slave transceivers 1 and 2 - t he two usb transceiver cells provide the usb host / slave physical usb 1.1 / usb 2.0 full-speed device interface. on each the output drivers provide 3.3v level slew rate control signalling, whilst a differential receiver and two single ended receivers provide usb data in, seo and usb reset condition detection. these cells also incorporate internal usb pull-up or pull down resistors as required for host or slave mode. usb host / slave serial interface engine ( sie ) - t hese blocks handle the parallel to serial and serial to parallel conversion of the usb physical layer including bit suf ng / unstuf ng, crc generation / checking, usb frame generation and error checking. 12 mhz oscillator - the 12mhz oscillator cell generates a 12mhz reference clock input to the clock multiplier pll from an exteral 12mhz crystal. clock multiplier pll - the clock multiplier pll takes the 12mhz input from the oscillator cell and generates 24mhz and 48mhz reference clock signals, which is used by the usb sie blocks, the mcu core, system timer and uart prescaler blocks. program and test logic - this block provides a means of programming the onboard e-flash memory. when prog# is pulled low and the device is reset, the onboard e-flash memory is bypassed by an internal hard coded bootstrap loader rom which contains code to allow the e-flash memory to be programmed via commands to the uart interface. ftdi provides a software utility which allows the VNC1L to be programmed using this method. the test pin is used in manufacturing to enhance the testability of the various internal blocks and should be tied to gnd. dma controller 1 and 2 - the twin dma controllers in the VNC1L greatly enhance performance by allowing data from the two usb sie controllers, uart, fifo and spi to be transferred between each other via the data sram with minimal mcu intervention. data sram - this 4k x 8bit block acts as the data ( variable ) memory for the vinculum mcu, though it can also be accessed transparently to the mcu by the twin dma controllers. npu ( numeric coprocessor ) - most vinclum mcu operations are 8-bit, however there are some scenarios such as transversing disk fat tables which involve extensive 32 bit arithmetic. in order to speed up these operations, the mcu has a dedicated 32 bit co-processor block. uart prescaler - this block provides the master transmit / receive clock for the uart block. by varying the prescalar value, the baud rate of the uart can be adjusted over a range of 300 baud to 1m baud. system timer - the system timer provides a regular interrupt to the vinculum mcu, typically at 1ms intervals. this is used by the mcu to provide timeouts and other timing functions. vinculum mcu core - the ?heart? of the VNC1L is the vmcu core based on ftdi?s proprietary 8-bit embedded mcu ( emcu ) architectiure. vmcu has a harvard architecture i.e. separate code and data space and supports 64k byes of program code, 64k byes of ( paged ) data space and 256 bytes of io space. it uses ?enhanced cisc? technology - typically vncu instructions would replace several lines of code in conventional cisc or risc processors giving risc like performance in a cisc architecture with the advantage over both of excellent code compression in the program rom space. e-flash program rom - the vncl1l has 64k bytes of embedded flash ( e-flash ) memory. no special programming voltages are necessary for programming the onboard e-flash as these are provided internally on-chip. common methods of programming the e-flash ( both under control of the vmcu ) are via the uart by pulling the prog# pin low and resetting the device or by using the programming via a usb flash drive feature provided in many of the VNC1L rmware packages. bootstrap loader rom - this is a small block of hard encoded rom ( 512 x 8 bits ) whivh bypasses the main e_flash memory when prog# is pulled low. this provides a means of programming the entire e-flash memory via the uart interface. uart and fifo logic - these provide optional serial and parallel interfaces to the VNC1L equivalent to the interfaces on ftdi?s ft232 and ft245 usb uart and fifo products. gpio blocks - general purpose io pins. see the tables below to determine which are available for any speci c con guration.
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 5 2 . d e v i c e p i n o u t a n d s i g n a l d e s c r i p t i o n s 2. device pin out and signal descriptions adbus6 adbus7 gnd vccio acbus0 acbus1 acbus2 acbus3 agnd bdbus2 vccio adbus1 adbus0 adbus2 adbus3 adbus4 adbus5 37 48 1 12 13 24 25 36 ftdi VNC1L-1a yyww acbus4 acbus5 acbus6 acbus7 gnd vcc avcc xtin xtout pllfltr test reset# prog# bdbus0 bdbus1 bdbus3 bdbus4 bdbus5 vccio bdbus6 bdbus7 bcbus0 bcbus1 bcbus2 bcbus3 gnd usb2dm usb1dp usb1dm gnd usb2dp xxxxxxxxx xxxxxx 20 21 22 23 11 12 13 14 15 16 18 19 41 42 43 44 46 45 47 48 31 32 33 34 6 39 27 24 1 2 3 40 30 17 adbus0 adbus1 adbus2 adbus3 g n d g n d a g n d v c c i o v c c i o v c c i o v c c g n d g n d a v c c acbus0 acbus1 acbus2 acbus3 bdbus0 bdbus1 bdbus2 bdbus3 bdbus4 bdbus5 bdbus6 bdbus7 bcbus0 bcbus1 bcbus2 bcbus3 26 25 8 usb1dp usb1dm reset# prog# pllfltr test usb2dp usb2dm 4 5 xtin xtout acbus4 acbus5 acbus6 acbus7 VNC1L 7 10 9 29 28 35 36 37 38 adbus7 adbus6 adbus5 adbus4 2.1 48 lead lqfp pin out figure 2 - 48 pin lqfp package pin out figure 3 - VNC1L pin out - schematic
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 6 2.2 48 lead lqfp package signal descriptions table 1 - pin out description pin no. name type description usb interface group 25 usb1dp i/o usb host / slave port 1 - usb data signal plus with integrated pull up / pull down resistor. 26 usb1dm i/o usb host / slave port 1 - usb data signal minus with integrated pull up / pull down resistor. 28 usb2dp i/o usb host / slave port 2 - usb data signal plus with integrated pull up / pull down resistor. 29 usb2dm i/o usb host / slave port 2 - usb data signal minus with integrated pull up / pull down resistor. power and ground group 1, 24, 27, 39 gnd pwr device ground supply pins 2 vcc pwr 3.3v supply to the device core. 3 avcc pwr +3.3v supply to the internal clock multiplier. this pin requires a 100 nf decoupling capacitor. 6 agnd pwr device analog ground supply for internal clock multiplier 17, 30, 40 vccio pwr +3.3v supply to the adbus, acbus, bdbus and bcbus interface pins (11...16, 18...23, 31...38, 41...48). miscellaneous signal group 4 xtin input input to 12mhz oscillator cell. connect 12 mhz crystal across pins 4 and 5, with suitable loading capacitors to gnd. this pin can also be driven by an external 12 mhz clock signal. note that the switching threshold of this pin is vcc/2, so if driving from an external source, the source must be driving at 5v cmos level, or a.c. coupled to centre around vcc/2. 5 xtout output output from 12mhz oscillator cell. connect 12 mhz crystal across pins 4 and 5, with suitable loading capacitors to gnd. xtout stops oscillating during usb suspend, so take care using this signal to clock external logic. 7 pllfltr input external pll lter circuit input. rc lter circuit must be tted on this pin. 8 test input puts the device into i.c. test mode. must be tied to gnd for normal operation. 9 reset# input can be used by an external device to reset the VNC1L. this pin can be used in combination with prog# and the uart interface to program rmware into the VNC1L. if not required pull up to vcc via a 10 k resistor.* 10 prog# input this pin is used in combination with the reset# pin and the uart interface to program rmware into the VNC1L.* data and control bus signals interface mode uart inter- face parallel fifo interface spi slave interface i/o port 11 bdbus0 i/o 5v safe bidirectional data / control bus, bd bit 0 portbd0 12 bdbus1 i/o 5v safe bidirectional data / control bus, bd bit 1 portbd1 13 bdbus2 i/o 5v safe bidirectional data / control bus, bd bit 2 portbd2 14 bdbus3 i/o 5v safe bidirectional data / control bus, bd bit 3 portbd3 15 bdbus4 i/o 5v safe bidirectional data / control bus, bd bit 4 portbd4 16 bdbus5 i/o 5v safe bidirectional data / control bus, bd bit 5 portbd5 18 bdbus6 i/o 5v safe bidirectional data / control bus, bd bit 6 portbd6 19 bdbus7 i/o 5v safe bidirectional data / control bus, bd bit 7 portbd7 20 bcbus0 i/o 5v safe bidirectional data / control bus, bc bit 0 ps2clk1** ps2clk1** ps2clk1** portbc0 21 bcbus1 i/o 5v safe bidirectional data / control bus, bc bit 1 ps2data1** ps2data1** ps2data1** portbc1 22 bcbus2 i/o 5v safe bidirectional data / control bus, bc bit 2 ps2clk2** ps2clk2** ps2clk2** portbc2 23 bcbus3 i/o 5v safe bidirectional data / control bus, bc bit 3 ps2data2** ps2data2** ps2data2** portbc3 31 adbus0 i/o 5v safe bidirectional data / control bus, ad bit 0 txd d0 sclk portad0 32 adbus1 i/o 5v safe bidirectional data / control bus, ad bit 1 rxd d1 sdi portad1 33 adbus2 i/o 5v safe bidirectional data / control bus, ad bit 2 rts# d2 sdo portad2 34 adbus3 i/o 5v safe bidirectional data / control bus, ad bit 3 cts# d3 cs portad3 35 adbus4 i/o 5v safe bidirectional data / control bus, ad bit 4 dtr# d4 portad4 36 adbus5 i/o 5v safe bidirectional data / control bus, ad bit 5 dsr# d5 portad5 37 adbus6 i/o 5v safe bidirectional data / control bus, ad bit 6 dcd# d6 portad6 38 adbus7 i/o 5v safe bidirectional data / control bus, ad bit 7 ri# d7 portad7 41 acbus0 i/o 5v safe bidirectional data / control bus, ac bit 0 txden# rxf# portac0
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 7 42 acbus1 i/o 5v safe bidirectional data / control bus, ac bit 1 txe# portac1 43 acbus2 i/o 5v safe bidirectional data / control bus, ac bit 2 rd# portac2 44 acbus3 i/o 5v safe bidirectional data / control bus, ac bit 3 wr portac3 45 acbus4 i/o 5v safe bidirectional data / control bus, ac bit 4 portac4 46 acbus5 i/o 5v safe bidirectional data / control bus, ac bit 5 portac5 47 acbus6 i/o 5v safe bidirectional data / control bus, ac bit 6 portac6 48 acbus7 i/o 5v safe bidirectional data / control bus, ac bit 7. to use a 12 mhz crystal with the VNC1L t a 47 k pull-down resistor. alternatively, tting a 47 k pull-up resistor on this pin will switch off the inter- nal clock multiplier, allowing the device to be fed with an external 48mz clock signal into xtin. portac7 * these pins are pulled to vcc via internal 200k resistors. ** ps/2 ports can be available while uart, fifo, or spi interface is enabled. 2.3 uart interface signal descriptions table 4 - data and control bus signal mode options - uart interface pin no. name type description 31 txd output transmit asynchronous data output 32 rxd input receive asynchronous data input 33 rts# output request to send control output / handshake signal 34 cts# input clear to send control input / handshake signal 35 dtr# output data terminal ready control output / handshake signal 36 dsr# input data set ready control input / handshake signal 37 dcd# input data carrier detect control input 38 ri# input ring indicator control input. when the remote wake up option is enabled in the eeprom, taking ri# low can be used to resume the pc usb host controller from suspend. 41 txden output enable transmit data for rs485 designs 2.4 parallel fifo interface signal descriptions and timing diagrams table 5 - data and control bus signal mode options - parallel fifo interface pin no. name type description 31 d0 i/o fifo data bus bit 0 32 d1 i/o fifo data bus bit 1 33 d2 i/o fifo data bus bit 2 34 d3 i/o fifo data bus bit 3 35 d4 i/o fifo data bus bit 4 36 d5 i/o fifo data bus bit 5 37 d6 i/o fifo data bus bit 6 38 d7 i/o fifo data bus bit 7 41 rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing rd# low, then high again. 42 txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr high, then low. 43 rd# input writes the data byte on the d0...d7 pins into the transmit fifo buffer when wr goes from high to low. 44 wr input enables the current fifo data byte on d0...d7 when low. fetched the next fifo data byte (if avail- able) from the receive fifo buffer when rd# goes from high to low table 1 continued - pin out description
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 8 figure 4 - fifo read cycle rxf# rd# d[7...0] t3 t1 t5 t6 t2 t4 valid data table 6 - fifo read cycle timings time description min max unit t1 rd active pulse width 50 - ns t2 rd to rd pre-charge time 50 + t6 - ns t3 rd active to valid data* 20 50 ns t4 valid data hold time from rd inactive* 0 - ns t5 rd inactive to rxf# 0 25 ns t6 rxf inactive after rd cycle 80 - ns * load = 30pf figure 5 - fifo write cycle valid data d[7...0] wr txe# t7 t12 t11 t8 t9 t10 table 7 - fifo write cycle timings time description min max unit t7 wr active pulse width 50 - ns t8 wr to rd pre-charge time 50 - ns t9 data setup time before wr inactive 20 - ns t10 data hold time from wr inactive 0 - ns t11 wr inactive to txe# 5 25 ns t12 txe inactive after wr cycle 80 - ns
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 9 2.5 spi interface signal descriptions and timing diagrams table 8 - data and control bus signal mode options - spi interface pin no. name type description 31 sclk input spi clock input, 12mhz maximum. 32 sdi input spi serial data input 33 sdo output spi serial data output 34 cs input spi chip select input figure 6 - spi slave data read cycle spiclk spi data in spi data out spi cs r/w add d0 d1 d2 d3 d4 d5 d6 d7 11 0 from start - spi cs must be held high for the entire read cycle, and must be taken low for at least one clock period after the read is completed. the rst bit on spi data in is the r/w bit - inputting a ?1? here allows data to be read from the chip. the next bit is the address bit, add, which is used to indicate whether the data register (?0?) or the status register (?1?) is read from. during the spi read cycle a byte of data will start being output on spi data out on the next clock cycle after the address bit, msb rst. after the data has been clocked out of the chip, the status of spi data out should be checked to see if the data read is new data. a ?0? level here on spi data out means that the data read is new data. a ?1? indicates that the data read is old data, and the read cycle should be repeated to get new data. remember that cs must be held low for at least one clock period before being taken high again to continue with the next read or write cycle. figure 7 - spi slave data write cycle spiclk spi data in spi data out spi cs r/w add d0 d1 d2 d3 d4 d5 d6 d7 1 0 0 from start - spi cs must be held high for the entire write cycle, and must be taken low for at least one clock period after the write is completed. the rst bit on spi data in is the r/w bit - inputting a ?0? here allows data to be written to the chip. the next bit is the address bit, add, which is used to indicate whether the data register (?0?) or the status start status status start
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 10 table 9 - spi slave data timing time description min typical max unit t1 spiclk period 83 - - ns t2 spiclk high 20 - - ns t3 spiclk low 20 - - ns t4 input setup time 10 - - ns t5 input hold time 10 - - ns t6 output hold time 2 - - ns t7 output valid time - - 20 ns table 10 - status register (add = ?1?) bit description 0 rxf# 1 txe# 2- 3- 4 rxf irqen 5 txe irqen 6- 7- t1 t2 t3 t4 t5 t6 t7 spiclk spics / spi data in spi data out register (?1?) is written to. during the spi write cycle a byte of data can be input to spi data in on the next clock cycle after the address bit, msb rst. after the data has been clocked in to the chip, the status of spi data out should be checked to see if the data read was accepted. a ?0? level on spi data out means that the data write was accepted. a ?1? indicates that the internal buffer is full, and the write should be repeated. remember that cs must be held low for at least one clock period before being taken high again to continue with the next read or write cycle. figure 8 - spi slave data timing diagrams
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 11 2.6 ps/2 keyboard and mouse interface table 11 - data and control bus signal mode options - ps/2 keyboard and mouse interface pin no. name type description 20 ps2clk1 i/o ps/2 keyboard or mouse interface 1 clock signal 21 ps2data1 i/o ps/2 keyboard or mouse interface 1 data signal 22 ps2clk2 i/o ps/2 keyboard or mouse interface 2 clock signal 23 ps2data2 i/o ps/2 keyboard or mouse interface 2 data signal
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 12 3 . p a c k a g e p a r a m e t e r s 3. package parameters 3.1 lqfp-48 dimensions the VNC1L is supplied in a 48 pin lqfp package as standard. pin# 1 0.25 1.60 max 12 o +/- 1 o 1.4 +/- 0.05 0.2 min 0.6 +/- 0.15 1.0 0.05 min 0.15 max 0.24 +/- 0.07 0.22 +/- 0.05 0.09 min 0.2 max 0.09 min 0.16 max 7 9 79 pin# 48 0.5 0.22+/- 0.05 VNC1L-1a yyww xxxxxxxxx xxxxxx ftdi figure 9 - lqfp-48 package dimensions the VNC1L is supplied in a rohs compliant 48 pin lqfp package. the package is lead ( pb ) free and uses a ?green? compound. the package is fully compliant with european union directive 2002/95/ec. this package has a 7.00mm x 7.00 mm body ( 9.00 mm x 9.00 mm including pins ). the pins are on a 0.50 mm pitch. the above mechanical drawing shows the lqfp-48 package ? all dimensions are in millimetres. the date code format is yyww where ww = 2 digit week number, yy = 2 digit year number. an alternative 6mm x 6mm leadless qfn package is also available for projects where pcb area is critical. contact ftdi for availabillity.
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 13 3.2 solder re ow pro le the VNC1L is supplied in pb free 48 ld lqfp package. the recommended solder re ow pro le is shown in below. figure 10 - VNC1L solder re ow pro le the recommended values for the solder re ow pro le are detailed in table 4. values are shown for both a completely pb free solder process (i.e. the VNC1L is used with pb free solder), and for a non-pb free solder process (i.e. the VNC1L is used with non-pb free solder). table 12 - re ow pro le parameter values pro le feature pb free solder process non-pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 180 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 10 to 30 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minutes max. 6 minutes max. critical zone: when t is in the range t to t temperature, t (degrees c) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 14 4.1 absolute maximum ratings the absolute maximum ratings for the VNC1L devices are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. table 13 - absolute maximum ratings parameter value unit storage temperature -65c to 150c degrees c floor life (out of bag) at factory ambient ( 30c / 60% relative humidity) 168 hours (ipc/jedec j-std-033a msl level 3 compliant)* hours ambient temperature (power applied) 0c to 70c degrees c. vcc supply voltage 0 to 3.6 v d.c. input voltage - usbdp and usbdm --0.5 to +(vcc +0.5) v d.c. input voltage - high impedance bidirectionals -0.5 to +5.00 v d.c. input voltage - all other inputs -0.5 to +(vcc +0.5) v d.c. output current - outputs 8 ma dc output current - low impedance bidirectionals 8 ma power dissipation (vcc = 3.6v) 250 mw * if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of 125 c and baked for up to 17 hours. 4.2 dc characteristics dc characteristics ( ambient temperature = 0 o c to +70 o c ) table 14 - operating voltage and current parameter description min typ max units conditions vcc1 vcc operating supply voltage 3.0 3.3 3.6 v vcc2 vccio operating supply voltage 3.0 3.3 3.6 v icc1 operating supply current - 25 - ma normal operation icc2 operating supply current 1 - 2 m a usb suspend table 15 - uart and cbus i/o pin characteristics parameter description min typ max units conditions voh output voltage high vcc-0.4 v i source = 8ma vol output voltage low 0.4 v i sink = 8ma vin input switching threshold 0.8 1.4 2.0 v ** table 16 - reset# and prog# pin characteristics parameter description min typ max units conditions vin input switching threshold 0.8 1.4 2.0 v 4 . d e v i c e c h a r a c t e r i s t i c s a n d r a t i n g s 4. device characteristics and ratings
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 15 table 17 - usb i/o pin (usbdp, usbdm) characteristics parameter description min typ max units conditions uvoh i/o pins static output ( high) 2.8 3.6 v uvol i/o pins static output ( low ) 0 0.3 v uvse single ended rx threshold 0.8 2.0 v ucom differential common mode 0.8 2.5 v uvdif differential input sensitivity 0.2 v udrvz driver output impedance 28 44 ohms *** ***driver output impedance includes the external usb series resistors on usbdp and usbdm pins. table 18 - xtin, xtout pin characteristics parameter description min typ max units conditions voh output voltage high 0.6 v fosc = 12mhz vol output voltage low 0.2 v fosc = 12mhz vin input switching threshold 0.4 v
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 16 5 . d e v i c e c o n f i g u r a t i o n s 5. device configurations 5.1 example VNC1L schematic ( mcu - uart interface ) txd rxd cts# rts# vcc 20 21 22 23 11 12 13 14 15 16 18 19 41 42 43 44 46 45 47 48 31 32 33 34 6 39 27 24 1 2 3 40 30 17 adbus0 adbus1 adbus2 adbus3 g n d g n d a g n d v c c i o v c c i o v c c i o v c c g n d g n d a v c c acbus0 acbus1 acbus2 acbus3 bdbus0 bdbus1 bdbus2 bdbus3 bdbus4 bdbus5 bdbus6 bdbus7 bcbus0 bcbus1 bcbus2 bcbus3 26 25 9 10 8 usb1dp usb1dm reset# prog# pllfltr test 29 28 usb2dp usb2dm 4 5 xtin xtout acbus4 acbus5 acbus6 acbus7 microcontroller gnd + 100nf 4.7uf 5v 1 2 3 4 gnd 5 47pf 47pf ferrite bead usb a connector 3v3 txd rxd cts# rts# 100nf gnd 3v3 gnd 3v3 27r 27r 47k 47k 47k gnd 10nf 1nf 12mhz gnd 10pf 10pf 0r gnd gnd gnd 3.3v ldo regulator 3v3 + 4.7uf 100nf gnd gnd i g o VNC1L gnd 47k 47k 47k 3v3 led2 led1 7 330r 330r 3v3
vinculum VNC1L embedded usb host controller i.c. datasheet version 0.97 ? future technology devices intl ltd. 2006-2007 page 17 disclaimer copyright ? future technology devices international limited , 2006. version 0.90 - initial datasheet created july 2006 version 0.95 - datasheet update september 2006 version 0.96 - datasheet update march 2007 version 0.97 - update table 5. june 2007 neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd. will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. this document provides preliminary information that may be subject to change without notice. contact ftdi head of ce - future technology devices international ltd. 373 scotland street, glasgow g5 8qb, united kingdom tel. : +(44) 141 429 2777 fax. : +(44) 141 429 2758 e-mail (sales) : vinculum.sales@ftdichip.com e-mail (support) : v inculum.support1@ftdichip.com e-mail (general enquiries) : admin1@ftdichip.com regional sales of ces - future technology devices international ltd. (taiwan) 4f, no 18-3, sec. 6 mincyuan east road, neihu district, taipei 114, taiwan, r.o.c. tel.: +886 2 8791 3570 fax: +886 2 8791 3576 e-mail (sales): tw.sales1@ftdichip.com e-mail (support): tw.support@ftdichip.com e-mail (general enquiries): tw.admin@ftdichip.com future technology devices international ltd. (usa) 7235 nw evergreen parkway, suite 600 hillsboro, or 97124-5803 usa tel.: +1 (503) 547-0988 fax: +1 (503) 547-0987 e-mail (sales): us.sales@ftdichip.com e-mail (support): us.support@ftdichip.com e-mail (general enquiries): us.admin@ftdichip.com ftdi company website url : http://www.ftdichip.com vinculum dedicated product website url : http://www.vinculum.com

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