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xrd87l94 rev. 1.00 1996 exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 features 12-bit adc with dnl = + 1 lsb, inl = + 2.5 lsb snr > 60 db sampling frequency < 1 mhz single 3.3 v supply rail-to-rail input range v ref range: 1.5 v to v dd cmos low power: 30 mw (typ) 1/4, 1/2 and 3/4 scale reference resistor taps three-state outputs binary and two's complement digital output mode latch-up proof esd: 2000 v minimum protection cmos, 1 msps, 12-bit analog-to-digital converter with parallel logic interface port applications scanners digital cameras instrumentation medical imaging digital oscilloscopes spectrum analysis ...the analog plus company tm march 1996-3 general description the xrd87l94 is a 1 msps 12-bit subranging analog-to-digital converter with dnl = + 1 lsb and inl = + 2.5 lsb. the xrd87l94 contains an internal track and hold and an analog input bandwidth of 10 mhz. the xrd87l94 operates with a single 3.3 v supply while consuming 30 mw of power (typical). separate pins for reference ladder terminals and power supplies allow flexibility for various a in , v ref , and power supply ranges. data is presented at the parallel output port every clock cycle after a 2.5 cycle pipeline delay from sample edge. the digital output port is also equipped with a 3-state function. minv enables binary and 2's complement data formatting. through pins r1-r3, transfer function adjustment can be accommodated. simplified block diagram fine comp. coarse comp. s/h minv db0-db11 clk v rb r1-r3 v rt a in clock logic oe n n1 n2 n2 n1 m 12 12 3 l a t c h r o m l a t c h av dd agnd 3 3 11 1 aperture
xrd87l94 2 rev. 1.00 ordering information package type temperature range part no. dnl (lsb) pdip 40 to +85 c XRD87L94AIP 1 inl (lsb) 2.5 soic (eiaj) 40 to +85 c xrd87l94aik 1 2.5 soic (jedec) 40 to +85 c xrd87l94aid 1 2.5 pin configurations 28 pin pdip (0.600o) 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 11 12 13 14 18 17 16 15 28 pin sop (eiaj, 8.4mm) 28 pin soic (jedec, 0.300o) 28 1 15 14 2 3 4 5 6 7 17 16 8 9 19 18 10 11 23 22 21 20 27 26 25 24 12 13 db11 r2 r3 r1 minv db1 agnd a in av dd v refb v reft av dd agnd db10 db6 clk db3 db2 db9 db8 db7 aperture agnd db5 db4 oe db0 av dd db10 db6 clk db3 db2 db9 db8 db7 aperture agnd db5 db4 oe av dd db11 r2 r3 r1 minv db1 agnd a in av dd v refb v reft av dd agnd db0 see packaging section for package dimensions pin out definitions 1 db11 data output bit 11 (msb) 2 agnd analog ground 3a in analog input 4av dd analog positive supply 5 r2 ref. resistor ladder tap (1/2 v ref ) 6 r3 ref. resistor ladder tap (3/4 v ref ) 7 r1 ref. resistor ladder tap (1/4 v ref ) 8v refb negative reference 9v reft positive reference 10 av dd analog positive supply 11 agnd analog ground 12 minv invert msb (active high) 13 db0 data output bit 0 (lsb) 14 db1 data output bit 1 pin no. name description 15 db2 data output bit 2 16 db3 data output bit 3 17 db4 data output bit 4 18 db5 data output bit 5 19 av dd digital positive supply 20 agnd digital negative supply 21 aperture delayed clock, indicates sample point 22 oe output enable (active low) 23 clk clock 24 db6 data output bit 6 25 db7 data output bit 7 26 db8 data output bit 8 27 db9 data output bit 9 28 db10 data output bit 10 pin no. name description
xrd87l94 3 rev. 1.00 electrical characteristics table unless otherwise specified: av dd = dv dd = 3.3 v, fs = 1 mhz (50% duty cycle), v ref(+) = 3.0 v, v ref() = agnd, ta = 25 c 25 c parameter symbol min typ max units test conditions/comments key features resolution 12 bits sampling rate fs 1 mhz accuracy 1 differential non-linearity dnl + 1 lsb integral non-linearity inl + 2.5 lsb best fit line (max inl min inl)/2 zero scale error ezs +10 lsb full scale error efs 10 lsb reference voltages positive ref. voltage v ref(+) 1.5 av dd v functional negative ref. voltage v ref() agnd v differential ref. voltage 3 v ref 1.5 av dd v ladder resistance r l 550 w analog input input bandwidth (3 db) 4 bw 3 mhz input voltage range v in v ref() v ref(+) v p-p input capacitance sample 5 c in 50 pf input capacitance convert 5 8pf aperture delay from clock t ap 55 ns aperture delay from aperture t ap 0 ns aperture pin load 5 pf. signal measured at 50% point. digital inputs logical a1o voltage v ih 2.5 v logical a0o voltage v il 0.5 v leakage currents 6 i in v in =dgnd to dv dd clk, oe , minv 10 m a input capacitance 5 pf clock timing clock period t s 0.4 1 m s functional rise & fall time 7 t r , t f 15 ns functional ahigho time t pwh 500 ns functional alowo time t pwl 500 ns functional duty cycle 50 % digital outputs c out =15 pf logical a1o voltage v oh v dd -0.5 v i load = 1 ma logical a0o voltage v ol 0.5 v i load = 1 ma 3-state leakage i oz 1 m av out =dgnd to dv dd data enable delay t den 60 ns data 3-state delay t dhz 60 ns data valid delay t dv 115 ns oe = 0 data invalid delay t di 115 ns oe = 0
xrd87l94 4 rev. 1.00 electrical characteristics table (cont'd) parameter symbol min typ max units test conditions/comments power supplies 8 (tmin to tmax) operating voltage (av dd , dv dd )v dd 3.3 v current (av dd + dv dd )i dd 12 ma ac parameters signal noise ratio (n+d) snr 60 db f in = 100 khz 25 c notes 1 tester measures code transitions by dithering the voltage of the analog input (v in ). the difference between the measured and the ideal code width (v ref /4096) is the dnl error. the inl error is the maximum distance (in lsbs) from the best fit line to any transition voltage. accuracy is a function of the sampling rate (fs). 2 guaranteed. not tested. 3 specified values guarantee functionality. refer to other parameters for accuracy. 4 3 db bandwidth is a measure of performance of the a/d input stage (s/h + amplifier). refer to other parameters for accuracy within the specified bandwidth. 5 switched capacitor analog input requires driver with low output resistance. 6 all inputs have diodes to dv dd and dgnd. input(s) oe and minv have internal pull down(s). input dc currents will not exceed specified limits for any input voltage between dgnd and dv dd . 7 condition to meet aperture delay specifications (t ap , t aj ). actual rise/fall time can be less stringent with no loss of accuracy. 8 agnd & dgnd pins are connected through the silicon substrate. specifications are subject to change without notice absolute maximum ratings (t a = +25 c unless otherwise noted) 1, 2, 3 v dd to gnd 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ref(+) & v ref() v dd +0.5 to gnd 0.5 v . . . . . . . . . v in v dd +0.5 to gnd 0.5 v . . . . . . . . . . . . . . . . . . . . . all inputs v dd +0.5 to gnd 0.5 v . . . . . . . . . . . . . . . . all outputs v dd +0.5 to gnd 0.5 v . . . . . . . . . . . . . . storage temperature 65 to +150 c . . . . . . . . . . . . . . lead temperature (soldering 10 seconds) +300 c . . . . . . . . . . . . . . . . . . package power dissipation rating @ 75 c pdip, soic 1050mw . . . . . . . . . . . . . . . . . . . . . . . . . derates above 75 c 14mw/ c . . . . . . . . . . . . . . . . . notes: 1 stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation at or above this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2 any input pin which can see a value outside the absolute maximum ratings should be protected by schottky diode clamps (hp5082-2835) from input pin to the supplies. all inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100ma for less than 100 m s. 3 v dd refers to av dd and dv dd . gnd refers to agnd and dgnd.
xrd87l94 5 rev. 1.00 clk pipeline delay n + 1 n + 2 n 3 n 2 n 1 data (db0-db11) high impedance oe 1/fs t pwh figure 1. timing diagram with oe = 0 t dv = t ap + t den t di = t ap + t dhz figure 2. 3-state timing diagram t dhz t den data (db0-db11) t pwl n n+1 n+2 n+3 n sampling points t ap analog input v in t dv t di clk clk delay aperture 12 12 data tri-state buffer 12 data out oe figure 3. block diagram of the xrd87l94 output aperture
xrd87l94 6 rev. 1.00 overview of the xrd87l94 pins & operation notes oe : output enable (input) this signal controls the 3-state drivers on the digital outputs db0 - db11 as shown in figure 2. during normal operation, oe should be held low so that all outputs are enabled (note: an in- ternal resistor will pull oe to this level if it is not connected). when oe is driven high, db0 - db11 goes into high impedance mode. this control operates asynchronously to the clock and only controls the output drivers. the internal output register will get updated if the clock is running while the outputs are in 3-state mode. the aperture and oe signals are internally combined to enable the output data. if aperture is high, the output data bits are tri-stated, independent of oe . figure 3. shows the circuit used to tri-state the output. this will reduce the errors introduced by digital output coupling during the a in sample time. aperture: aperture delay sync (output) this signal is high when the internal sample/hold function is sampling v in , and goes low when it is in the hold mode (when the adc is comparing the stored input value to the reference lad- der). the value of v in at the high to low transition of aperture is the value that will be digitized. a system can monitor this sig- nal and adjust the clk to accurately synchronize the sampling point to an external event. the aperture and oe signals are in- ternally combined to enable the output data. if aperture is high, the output data bits are tri-stated, independent of oe . this will reduce the errors introduced by digital output coupling during the a in sample time. minv: digital output format (input) this signal controls the format of the digital output data bits db0 db11. normally it is held low so the data is in straight binary format (all 0's when v in = v rb ; all 1's when v in = v rt ). if minv is pulled high then the msb (db11) will be inverted. minv is meant to be a static digital signal. if it is to change during operation, it should only change when the clk is low. changing minv on the wrong phase of the clk will not hurt any- thing, but the effects on the digital outputs will not be seen until the output latch of the output register is enabled. minv has an internal pull down device. db11 3-state driver dq en latch minv dq en latch clk figure 4. minv simplified logic circuit v in analog input this part has a switched capacitor type input circuit. this means that the input impedance changes with the phase of the input clock. v in is sampled at the high to low clock transition. the diagram figure 5. shows an equivalent input circuit. figure 5. equivalent input circuit 50 w + - v rt + v rb v in agnd 50 w 41pf 1.5pf av dd c l c l c l 8pf 2 c l at phase = 1 r1, r2, r3: reference ladder taps these taps connect to every 1/4 point along the reference ladder; r1 is 1/4th up from v rb , r3 is 3/4ths up from v rb (or 1/4th down from v rt ). normally these pins should have 0.1 mi- crofarad capacitors to v ss ; this helps reduce the inl errors by stabilizing the reference ladder voltages. these taps can also be used to alter the transfer curve of the adc. a 4-segment, piecewise linear, custom transfer curve can be designed by connecting voltage sources to these pins. this may be desirable to make the probability of codes for a certain range of v in be enhanced or minimized. sometimes this is referred to as probability density function shaping, or histogram shaping. the internal interconnect resistance from each of the t ap pins to the ladder is less than 3 w .
xrd87l94 7 rev. 1.00 1.6v maximum per tap is recommended for applications above 85 c. up to 3.2v is allowed for applications under 85 c. 4095 3072 2048 1024 0 0.5 v 1 v 2 v 3 v v 1 v 2 v 3 v 4 digital code v in figure 6. a piecewise linear transfer function figure 7. a/d with programmed ladder control for creating a piecewise linear transfer function dac2 dac1 xrd87l94 dac mp7226 dac4 dac3 v rt r3 r2 r1 v rb only the ladder detail shown. v3 v2 v1 v4
xrd87l94 8 rev. 1.00 performance characteristics graph 1. inl graph 2. inl vs. sampling frequency graph 3. dnl graph 4. dnl vs. sampling frequency graph 5. dnl vs. reference voltage graph 1. i dd vs. sampling frequency
xrd87l94 9 rev. 1.00 figure 8. xrd8794ab schematic
xrd87l94 10 rev. 1.00 28 lead plastic dual-in-line (600 mil pdip) symbol min max min max inches a 0.160 0.250 4.06 6.35 a 1 0.015 0.070 0.38 1.78 a 2 0.125 0.195 3.18 4.95 b 0.014 0.024 0.36 0.56 b 1 0.030 0.070 0.76 1.78 c 0.008 0.014 0.20 0.38 d 1.380 1.565 35.05 39.75 e 0.600 0.625 15.24 15.88 e 1 0.485 0.580 12.32 14.73 e 0.100 bsc 2.54 bsc e a 0.600 bsc 15.24 bsc e b 0.600 0.700 15.24 17.78 l 0.115 0.200 2.92 5.08 a 0 15 0 15 millimeters 28 1 15 14 d b 1 a 1 e 1 e a l b seating plane a e c a 2 note: the control dimension is the inch column e b e a
xrd87l94 11 rev. 1.00 symbol min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 b 0.013 0.020 0.33 0.51 c 0.009 0.013 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.050 bsc 1.27 bsc h 0.394 0.419 10.00 10.65 l 0.016 0.050 0.40 1.27 a 0 8 0 8 inches millimeters 28 lead small outline (300 mil jedec soic) e d e h b a l c a 1 seating plane 28 15 14 a note: the control dimension is the millimeter column 1
xrd87l94 12 rev. 1.00 e 28 lead small outline (8.4 mm eiaj sop) a l c d e h b a 1 seating plane 28 1 15 14 a 2 symbol min max min max a 0.098 0.114 2.50 2.90 a 1 0.004 0.012 0.10 0.30 a 2 0.094 0.102 2.40 2.60 b 0.012 0.020 0.30 0.50 c 0.004 0.008 0.10 0.20 d 0.693 0.713 17.60 18.10 e 0.327 0.335 8.30 8.50 e 0.050 bsc 1.27 bsc h 0.453 0.477 11.50 12.10 l 0.028 0.051 0.70 1.30 a 0 10 0 10 inches millimeters a note: the control dimension is the millimeter column
xrd87l94 13 rev. 1.00 notes
xrd87l94 14 rev. 1.00 notes
xrd87l94 15 rev. 1.00 notes
xrd87l94 16 rev. 1.00 notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 1996 exar corporation datasheet march 1996 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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