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dual input network clock generator/synchronizer preliminary technical data ad9549 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features flexible reference inputs input frequencies 8 khz to 750 mhz two reference inputs loss of reference indicators auto and manual holdover modes auto and manual switchover modes smooth a to b phase transition on outputs excellent stability in holdover mode programmable 16+1-bit input divider, r differential hstl clock output output frequencies to 750 mhz low jitter clock doubler for frequencies > 400 mhz single-ended cmos output; frequencies < 50mhz programmable digital loop filter (< 1 hz to ~100 khz) high speed digitally controlled oscillator (dco) core dds with integrated 14 bit dac excellent dynamic performance programmable 16+1-bit feedback divider, s software controlled power-down 64-lead lfcsp package applications network synchronization reference clock jitter cleanup sonet/sdh clocks up to oc-192, including fec stratum 3/3e reference clocks wireless base stations, controllers cable infrastructure data communications general description the ad9549 provides synchronization for many systems including synchronous optical networks (sonet/sdh). the ad9549 generates an output clock, synchronized to one of two external input references. the external references may contain significant time jitter, also specified as phase noise. using a digitally controlled loop and holdover circuitry, the ad9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed. the ad9549 operates over an industrial temperature range, spanning -40c to +85c. figure 1: basic block diagram
ad9549 preliminary technical data rev. prb | page 2 of 71 sample application circuit figure 2: ad9549 + ad9514 precision clock distribution circuit features: input frequencies down to 8 khz. ou tput frequencies up to 400 mhz. programmable loop bandwidth down to < 1 hz automatic redundant clock switchover with user selectable rate of phase adjustment. automatic stratum 2/3/3e clock holdov er, depending on configuration. phase noise (fc=122.3 mhz & 100 hz loop bw): 100 hz offset: -107 dbc/hz. 1 khz offset: -142 dbc/ hz. 100 khz offset: -157 dbc/hz . two zero-delay outputs with programmabl e post-divider and synchronization. two additional outputs (non-zero delay) on ad9549. programmable skew adjustment on one ad9514 output.
preliminary technical data ad9549 rev. prb | page 3 of 71 table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 sample application circuit..............................................................2 dc specifications ..............................................................................5 ac specifications ..............................................................................7 typical performance characteristics ............................................11 absolute maximum ratings ..........................................................14 esd caution ................................................................................14 pin configuration and function descriptions ...........................15 input / output termination recommendations.........................18 theory of operation .......................................................................19 overview ......................................................................................19 pll core (dpllc) .....................................................................20 feedforward divider (divide-by-r).....................................20 feedback divider (divide-by-s) ...........................................20 forward and reverse fec clock scaling ............................21 phase detector.........................................................................21 digital loop filter...................................................................21 direct digital synthesizer ......................................................22 dac output.............................................................................23 phase detector.............................................................................24 coarse phase detector ...........................................................24 fine phase detector................................................................24 phase detector gain matching .............................................24 phase detector pin connections ..........................................25 digital loop filter coefficients ................................................25 closed loop phase offset..........................................................26 lock detection ............................................................................27 phase lock detection.............................................................27 frequency lock detection ....................................................28 reference monitors ....................................................................29 loss of reference ....................................................................29 reference frequency monitor...............................................29 reference switchover .................................................................30 use of line card mode to eliminate runt pulses..............31 holdover ......................................................................................31 holdover control....................................................................31 holdover & reference switchover state machine..............32 reference validation timers .................................................33 holdover operation ...............................................................33 holdover sampler and averager...........................................33 output frequency range control ............................................34 reconstruction filter..................................................................34 use of narrowband filter for high performance...............35 fdbk inputs................................................................................36 reference inputs .........................................................................36 reference clock receiver ......................................................36 sysclk inputs...............................................................................36 functional description ..........................................................36 bipolar edge detector ............................................................37 sysclk pll multiplier ............................................................37 external loop filter (sysclk pll) .......................................38 detail of sysclk differential inputs .....................................38 harmonic spur reduction.........................................................39 output clock drivers & 2x frequency multiplier ..................40 primary 1.8v differential hstl driver..............................40 2x frequency multiplier.........................................................40
ad9549 preliminary technical data rev. prb | page 4 of 71 single-ended cmos output................................................ 40 frequency slew limiter............................................................. 40 frequency estimator.................................................................. 41 status and warnings .................................................................. 42 status pins ............................................................................... 42 reference monitor status ...................................................... 43 default dds output frequency on power-up .................. 43 interrupt request (irq)........................................................ 43 power-on reset.......................................................................... 45 ad9549 power up and programming sequence................... 45 power management........................................................................ 46 3.3v supplies............................................................................... 46 1.8v supplies............................................................................... 46 serial control port.......................................................................... 47 serial control port pin descriptions....................................... 47 operation of serial control port.............................................. 47 framing a communication cycle with csb ...................... 47 communication cycleinstruction plus data ................. 47 write......................................................................................... 47 read ......................................................................................... 48 the instruction word (16 bits)................................................ 48 msb/lsb first transfers ........................................................... 48 i/o register map ............................................................................ 51 types of registers:.................................................................. 58 i/o register description ............................................................... 59 serial port configuration (0000 C 0005)............................. 59 power down and reset ......................................................... 59 system clock........................................................................... 60 digital pll control and dividers........................................ 61 digital pll loop filter.......................................................... 62 free-run (single-tone) mode.............................................. 63 reference selector / holdover .............................................. 63 doubler and output drivers ................................................ 64 monitor.................................................................................... 65 calibration (user accessible trim) ..................................... 68 harmonic spur reduction.................................................... 70 outline dimensions ....................................................................... 71 ordering guide............................................................................... 71
preliminary technical data ad9549 rev. prb | page 5 of 71 dc specifications unless otherwise noted, avdd=1.85%, avdd3=3.35%, dvdd=1.85%, dvdd_i/o=3.35%. table 1. parameter min typ max unit test conditions/comments supply voltage dvdd_i/o (pin 1) 3.135 3.30 3.465 v (with respect to dvss) dvdd (pin 3, 5, 7) 1.71 1.80 1.89 v (with respect to dvss) avdd3 (pin 14, 46, 47, 49) 3.135 3.30 3.465 v (with respect to avss) avdd3 (pin 37) 1.71 3.30 3.465 v (with respect to avss) avdd (pin 11,19, 23-26,29,30,36,42,44,45,53) 1.71 1.80 1.89 v (with respect to avss) supply current i-avdd3 (pin 14) 6 tbd ma refa, refb buffers i-avdd3 (pin 37) tbd ma cmos output clock driver at 3.3v i-avdd3 (pin 46, 47, 49) 25 tbd ma dac output current source i-avdd (pin 36) 8 tbd ma hstl output clock driver i-avdd (pin 42) 10 tbd ma fdbk i-avdd (pin 11) 10 tbd ma sysclk i-avdd (pin 19, 23-26, 29, 30, 44, 45) 170 tbd ma aggregate analog supply i-avdd (pin 53) 35 tbd ma dac power supply i-dvdd (pin 3, 5, 7) 200 tbd ma digital core i-dvdd_i/o (pin 1) 3 tbd ma digital i/o (varies dynamically) logic inputs (except pin 32) pins 56-61, 64, 9, 10, 54, 55, 63 input high voltage (v ih ) 2.0 v input low voltage (v il ) 0.8 v input current (i inh , i inl ) 30 100 a at vin=0v and vin=dvdd_i/o maximum input capacitance (c in ) 3 pf clkmodesel (pin 32) logic input pin 32 only. input high voltage (v ih ) 1.4 v input low voltage (v il ) 0.4 v input current (i inh , i inl ) 30 100 a at vin=0v and vin=dvdd_i/o maximum input capacitance (c in ) 3 pf logic outputs pin 62, & bi-dir. pins 9, 10, 54, 55, 63 output high voltage (v oh ) 2.7 v i oh = 1 ma w/ v oh =dvdd_i/o-0.4v output low voltage (v ol ) 0.4 v i ol = 1ma w/ v ol =0.4v reference inputs pins 12, 13, 15, 16 input capacitance 3 pf input resistance 16 k differential at vbias=avdd3-800mv common mode input voltage 1 v differential operation differential input voltage swing 1 mv differential operation input voltage high (v ih ) v single-ended operation input voltage low (v il ) v single-ended operation input current ma single-ended operation internal bias voltage avdd3- 1600 avdd3- 800 avdd3- 400 mv programmable (see text) fdbk input pins 40, 41 input capacitance 3 pf input resistance 30 k differential common mode input voltage 2 v differential operation differential input voltage swing 2 mv differential operation
ad9549 preliminary technical data rev. prb | page 6 of 71 parameter min typ max unit test conditions/comments system clock input s ys c lk pll b ypassed input capacitance (dc) 1.5 pf single-ended, each pin input impedance (dc) 1 k differential common mode input voltage 3 differential operation differential input voltage swing 3 differential operation input voltage high (v ih ) single-ended operation input voltage low (v il ) single-ended operation input current single-ended operation s ys c lk pll e nabled input capacitance (dc) 3 pf single-ended, each pin input impedance (dc) 2 k differential common mode input voltage 3 differential operation differential input voltage swing 3 differential operation input voltage high (v ih ) single-ended operation input voltage low (v il ) single-ended operation input current single-ended operation c rystal r esonator with s ys c lk pll e nabled motional resistance k clock output drivers hstl o utput d river differential output voltage swing 4 tbd 700 mv both pins ac-coupled using 0.01uf, then 50 to gnd, common mode output voltage 4 tbd 0.9 v continuous output current 7.2 ma cmos o utput d river output voltage high (v oh ) v output voltage low (v ol ) 0.4 v output high current (i oh ) a output low current (i ol ) a total power dissipation all blocks running tbd tbd mw tbd power-down mode tbd tbd mw using either the power down register or pwrdown pin. default with sysclk pll enabled tbd tbd mw after reset or power up with f s =1ghz, s4=0, s1-s3=1, f sysclk =25mhz default with sysclk pll disabled tbd tbd mw after reset or power up with f s =1ghz, s4-s4=1, & sysclk pll powered down. - with digital power down tbd mw - with refa or refb power down tbd mw one reference still powered up. - with hstl clock driver power down tbd mw - with cmos clock driver power down tbd mw - with hstl 2x freq. multiplier power down tbd mw 1 must be 0v relative to avdd3 (pin 14) and 0v relative to avss (pins 33, 43). 2 must be 0v relative to avdd (pin 42) and 0v relative to avss (pins 33, 43). 3 relative to avss (pins 33, 43). 4 must be 0v relative to avdd (pin 36) and 0v relative to avss (pins 33, 43). 5 see power management section for details about power profiles.
preliminary technical data ad9549 rev. prb | page 7 of 71 ac specifications unless otherwise noted: f s =1ghz. dac r set =10k . power supply pins within the range specified in dc specifications. table 2. parameter min typ max unit test conditions/comments reference inputs pins 12, 13, 15, 16 frequency range .008 750 mhz minimum slew rate v/ns minimum pulse width high ps minimum pulse width low ps fdbk input pins 40, 41 input frequency range .008 750 mhz sinusoidal (without degrading phase noise performance) minimum slew rate v/ns minimum differential input level v peak-to-peak (xxxdbm into 50 ) system clock input pins 27, 28 s ys c lk pll b ypassed input frequency range tbd 1000 mhz minimum pulse width high ps minimum pulse width low ps minimum differential input level v peak-to-peak (xxxdbm into 50 ) s ys c lk pll e nabled vco frequency range C low band 700 850 mhz vco frequency range C high band 800 1000 mhz maximum input rate of pfd 100 mhz without bipolar edge detector input frequency range tbd tbd mhz multiplication range 8 66 integer multiples of 2 minimum pulse width high ps minimum pulse width low ps minimum differential input level v peak-to-peak (xxxdbm into 50 ) with bipolar edge detector input frequency range tbd tbd mhz multiplication range 16 132 integer multiples of 4 input duty cycle % minimum differential input level v peak-to-peak (xxxdbm into 50 ) c rystal r esonator with s ys c lk pll e nabled crystal resonator frequency range 10 40+ mhz fundamental mode resonator maximum crystal motional resistance tbd see text for recommendations clock drivers hstl o utput d river toggle rate 20 725 mhz see plot for maximum toggle rate output duty cycle 48 52 % output rise/fall time tbd ps 100 terminated, 5pf load jitter (12 khz-20 mhz) 1.0 ps fin=19.44 mhz, fout=155.52 mhz. 50 mhz system clock input. (see phase noise plots for test conditions.) hstl o utput d river with 2 x m ultiplier output frequency range tbd tbd mhz duty cycle 45 55 %
ad9549 preliminary technical data rev. prb | page 8 of 71 parameter min typ max unit test conditions/comments sub-harmonic spur level - 35 dbc without correction jitter (12 khz-20 mhz) 1.1 ps fin=19.44 mhz, fout=622.08 mhz. 50 mhz system clock input. (see phase noise plots for test conditions.) cmos o utput d river (avdd3/p in 37) @3.3v toggle rate 150 mhz see plot for maximum toggle rate duty cycle 55 60 % with 20pf load and up to 250 mhz output rise/fall time ns with 20pf load jitter (12 khz-20 mhz) fin=25 mhz, fout=50 mhz cmos o utput d river at (avdd3/p in 37) @1.8v toggle rate 50 mhz see plot for maximum toggle rate duty cycle 55 60 % with 20pf load and up to 40 mhz output rise/fall time ns jitter (12 khz-20 mhz) fin=25 mhz, fout=50 mhz holdover frequency accuracy (xtal) xxxmhz, xxxppm crystal resonator at sysclk pins variation over temperature range ppm/ o c variation over supply range ppm/v frequency accuracy (tcxo) tcxo at sysclk pins variation over temperature range 0 ppm/ o c variation over supply range 0 ppm/v output frequency slew limiter slew rate resolution 0.54 111 hz/sec p=2 16 for minimum; p=2 5 for maximum slew rate range 0 3x10 16 hz/sec p=2 16 for minimum; p=2 5 for maximum reference monitors l oss of r eference m onitor operating frequency range 7.63x10 3 167x10 6 hz minimum frequency error for continuous ref present indication -16 ppm f ref = 8 khz minimum frequency error for continuous ref present indication -19 % f ref = 155 mhz maximum frequency error for continuous ref lost indication -32 ppm f ref = 8 khz maximum frequency error for continuous ref lost indication -35 % f ref = 155 mhz r eference q uality m onitor operating frequency range frequency resolution (normalized) 0.001 16 ppm f ref = 8 khz; m=15 for minimum; m=1 for maximum (see text) frequency resolution (normalized) 0.002 44.9 % f ref = 155 mhz; m=15 for minimum; m=1 for maximum (see text) v alidation t imer timing range 32x10 -9 137 s p io = 5 (see text) timing range 65x10 -6 2.8x10 5 s p io = 16 (see text)
preliminary technical data ad9549 rev. prb | page 9 of 71 parameter min typ max unit test conditions/comments dac output characteristics dco frequency range (1 st nyquist zone) 10 450 mhz dpll loop bandwidth sets lower limit output resistance 50 single-ended (each pin internally terminated to avss) output capacitance 5 pf full-scale output current 10 31.7 ma range depends on dac rset resistor gain error tbd tbd %fs output offset 0.6 a voltage compliance range avss ?0.50 +0.5v avss +0.50 outputs not dc shorted to vss wideband sfdr (dc to nyquist): sfdr may be improved by activating harmonic spur suppression (see text) 10mhz analog out tbd dbc 40mhz analog out tbd dbc 80mhz analog out tbd dbc 120mhz analog out tbd dbc 160mhz analog out tbd dbc narrowband sfdr 10 mhz analog out (1 mhz) tbd dbc 40 mhz analog out (1 mhz) tbd dbc 80 mhz analog out (1 mhz) tbd dbc 120 mhz analog out (1 mhz) tbd dbc 160 mhz analog out (1 mhz) tbd dbc digital pll minimum open-loop bandwidth 0.0001 khz dependent on the frequency of refa/b, the dac sample rate, and the p, r, and s divider values maximum open-loop bandwidth 100 khz dependent on the frequency of refa/b, the dac sample rate, and the p, r, and s divider values minimum phase margin 10 degrees dependent on the frequency of refa/b, the dac sample rate, and the p, r, and s divider values (not a hard limit but bounded by 0 ) maximum phase margin 85 degrees dependent on the frequency of refa/b, the dac sample rate, and the p, r, and s divider values (not a hard limit but bounded by 90 ) pfd input frequency range ~0.008 ~24.5 mhz feedforward divider ratio 1 131,070 1,2,..,65,535 or 2,4,..,131,070 feedback divider ratio 1 131,070 1,2,..,65,535 or 2,4,..,131,070 lock detection p hase l ock d etector time threshold programming range 0 2097 s fpfd_gain=200 time threshold resolution 0.488 ps fpfd_gain=200 lock time programming range 32x10 -9 68.7 s in power-of-2 steps unlock time programming range 64x10 -6 16.8 ms in power-of-2 steps f requency l ock d etector normalized frequency threshold programming range 0 0.0021 fpfd_gain=200; normalized to (f ref /r) 2 ; see text for details normalized frequency threshold 5x10 -13 fpfd_gain=200; normalized to (f ref /r) 2 ;
ad9549 preliminary technical data rev. prb | page 10 of 71 parameter min typ max unit test conditions/comments programming resolution see text for details lock time programming range 32x10 -9 68.7 s in power-of-2 steps unlock time programming range 64x10 -6 16.8 ms in power-of-2 steps digital timing specifications time required to enter power down ns time reqd to recover from power down ns s0-4 config setup time during reset ns time s0-4 must be present before falling edge of signal on reset pin. s0-4 config hold time during reset ns time s0-4 must be held after falling edge of signal on reset pin. reset assert to s0-4 high-z time ns time from rising edge of reset to high z on s0-4 configuration pins. reset deassert to s0-4 low-z time ns time from falling edge of reset to low-z on s0-4 configuration pins. cs to sclk setup time tbd ns period of sclk 10 ns tdsu (serial data setup time) tbd ns tdhd (serial data hold time) tbd ns tdv (data valid time) tbd ns propagation delay fdbk to hstl output driver fdbk to hstl output driver with 2x frequency multiplier enabled fdbk to hstl output driver with 2x frequency multiplier enabled fdbk to cmos output driver fdbk through s-divider to cmos output driver
preliminary technical data ad9549 rev. prb | page 11 of 71 typical performance characteristics unless otherwise noted: avdd, avdd3, and dvdd at nominal supply voltage; f s = 1 ghz, dac r set = 10k . -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 0.183 psec plot 1: additive phase noise at hstl output driver. sysclk=1 ghz (sysclk pll bypassed). ref=19.44 mhz., fout=311.04 mhz. dpll loop bw= 1 khz. -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 0.363 psec plot 2: additive phase noise at hstl output driver. sysclk=1 ghz (sysclk pll bypassed). ref=19.44 mhz., fout=622.08 mhz, dpll loop bw= 1 khz. hstl output doubler enabled -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 1.0 psec plot 3: additive phase noise at hs tl output driver. sysclk = 1 ghz (sysclk pll enabled driven by r&s sma100 signal generator at 50 mhz .ref=19.44 mhz., fout=311.04 mhz, dpll loop bw= 1 khz. -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 1.1 psec plot 4: additive phase noise at hstl output driver. sysclk= 1 ghz (sysclk pll enabled and driven by r&s sma100 signal generator at 50 mhz. fin=19.44 mhz., fout=622. 08 mhz, dpll loop bw= 1 khz. system clock doubler enabled. hstl doubler enabled.
ad9549 preliminary technical data rev. prb | page 12 of 71 -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 1.0 psec plot 5: additive phase noise at hs tl output driver. sysclk = 1 ghz. (sysclk pll enabled and driven by r&s sma100 signal generator at 50 mhz.) fin=19.44 mhz, fout=155.52 mhz. system clock doubler enabled. dpll loop bw=1 khz. plot 6: additive phase noise at hstl output driver. sysclk = 500 mhz. sysc lk pll disabled. fin=8 khz, fout= 155.52 mhz. dpll loop bw= 400 hz. -150 -140 -130 -120 -110 -100 -90 -80 -70 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 1e+08 frequency offset (hz) phase noise (dbc/hz) rms jitter (12khz-20 mhz): 1.28 psec plot 7: additive phase noise at hs tl output driver. sysclk = 1 ghz. (sysclk pll enabled and driven by a 25 mhz fox crystal oscillator.) fin=19.44 mhz, fout=155.52 mhz. dpll loop bw=1 khz. plot 8: additive phase noise at cmos output driver. sysclk= 500 mhz. sysclk pll disabled. fin=10.24 mhz, fout=10.24 mhz. dpll loop bw=1 khz
preliminary technical data ad9549 rev. prb | page 13 of 71 plot 9: sfdr vs fout at sysclk = 1ghz with and w/o recon filter. fcut = fout * 1.2 450 mv 500 mv 550 mv 600 mv 650 mv 0 mhz 200 mhz 400 mhz 600 mhz 800 mhz nom skew 25oc 1.8v supply slow skew 90oc 1.7v supply plot 10: hstl output driver peak-peak amplitude vs. toggle rate (100 ohms across differential pair,) 0.0 v 0.5 v 1.0 v 1.5 v 2.0 v 2.5 v 0 mhz 20 mhz 40 mhz 60 mhz 80 mhz 100 mhz nom skew 25oc 1.8v supply (20pf) slow skew 90oc 1.7v supply (20pf) plot 11: cmos output driver peak-peak amplitude vs. toggle rate (avdd3 = 1.8 v) with 20 pf load 0.0 v 0.5 v 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 0 mhz 50 mhz 100 mhz 150 mhz 200 mhz 250 mhz nom skew 25oc 3.3v supply (20pf) slow skew 90oc 3.0v supply (20pf) plot 12: cmos output driver amplitude vs. toggle rate (avdd3 = 3.3 v) with 20 pf load. plot 13: 12khz-20mhz rms jitter vs system clock pll frequency. fin=19.44 mhz. fout=155.52 mhz. plot 14: system clock sub-harmoni c spur level for typical system clock pll conditions.
ad9549 preliminary technical data rev. prb | page 14 of 71 absolute maximum ratings table 1. parameter rating analog supply voltage (avdd) 2 v digital supply voltage (dvdd) 2 v digital i/o supply voltage (dvdd_i/0) 3.6 v dac supply voltage (dac_vdd) 3.6 v maximum digital input voltage ?0.5 v to d vdd _i/o + 0.5 v storage temperature ?65c to +150c operating temperature range ?40c to +85c lead temperature range (soldering 10 sec) 300c junction temperature 150c thermal resistance 1 ( ja ) 26c/w typ. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 the exposed pad on bottom of package must be soldered to ground in order to achieve the specif ied thermal performance. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulates on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad9549 rev. prb | page 15 of 71 pin configuration and fu nction descriptions avdd dvdd_i/o dvss dvdd s1 s2 refa_in pfd_vrb pfd_rset pfd_vrt dvss dvdd dvss dvdd dvss refa_inb avdd3 refb_in refb_inb avdd n/c n/c avdd avdd avdd avdd sysclk sysclkb avdd avdd loop_filter clkmodesel dac_rset avdd3 avdd avdd3 avss avdd fdbk_in n/c fdbk_inb avss out_cmos avdd3 avdd avss out outb sclk sdo sdio io_update csb reset pwrdown refselect holdover s3 s4 avdd avss avdd3 iout ioutb figure 3: 64-lead lfcsp pin configuration table 2: pin function descriptions pin no. input/ output pin type mnemonic description 1 i power dvdd_i/o i/o digital supply 2, 4, 6, 8 i power dvss digital ground: connect to ground 3, 5, 7 i power dvdd digital supply 9, 10, 54, 55 i/o 3.3v cmos s1, s2, s3, s4 configurable i/o pins: these pins are conf igured under program control (see status and warnings on page 42., and do not have internal pull-up/pull-down resistors. 11, 19, 23- 26, 29, 30, 36, 42, 45, 53 i power avdd analog supply: connect to a nominal 1.8v supply
ad9549 preliminary technical data rev. prb | page 16 of 71 12 i diff input refa_in frequency/phase reference a input. this intern ally biased input is typically ac-coupled, and when configured as such, can accept any differential signal, whose single-ended swing is between 0.4 and 3.3v. if dc-coupled, lvpecl or cmos input is preferred. 13 i diff input refa_inb complementary frequency/phase reference a input: complementary signal to the input provided on pin 12. if using a single-e nded, dc-coupled cmos signal into refa_in, bypass this pin to ground with a 0.01uf capacitor. 14, 37, 46, 47, 49 i power avdd3 analog supply: connect to a nominal 3.3v supply 15 i diff input refb_in frequency/phase reference b input. this intern ally biased input is typically ac-coupled, and when configured as such, can accept an y differential signal whose single-ended swing is between 0.4 and 3.3v. if dc-coupled, lvpecl or cmos input is preferred. 16 i diff input refb_inb complementary frequency/phase reference b input: complementary signal to the input provided on pin 15. if using a single-ended , dc-coupled cmos signal into refa_in, bypass this pin to ground with a 0.01uf capacitor. 17, 18 n/c no connects: these are excess, unused pins that may be left floating 20, 21 o pfd_vrb, pfd_vrt these pins must be capacitively decoupled. see the phase detector pin connections section for details. 22 o i set res pfd_rset connect a 5k resistor from this pin to ground (see the phase detector pin connections section). 27 i diff input sysclk system clock input. can be lvpecl or cr ystal input, depending on clkmodesel pin. single-ended 1.8v cmos is also ok, but can introduce a spur caused by an input duty cycle that is not 50%. 28 i diff input sysclkb complementary system clock: complementary signal to the input provided on pin 27. 31 o loop_filter system clock multiplier loop filter: when using the frequency multiplier to drive the system clock, an external loop filter must be constructed and attached to this pin. this pin is pulled high when the system clock pll is bypassed, and can be left floating in this mode. put a hyperlink here. 32 i 1.8v cmos clkmodesel clock mode select. set to gnd when connecting a crystal to the system clock input (pins 27 and 28). pull up to 1.8v when using either an oscillator or external clock source. (see the sysclk inputs section for details on the use of this pin). 33, 39, 43, 52 i gnd avss analog ground: connect to ground. 34 o 1.8v hstl outb complementary hstl output: see spec table and the output drivers and multiplier section, under sub heading prima ry (differential) driver, for details. 35 o 1.8v hstl out hstl output: see spec table and the outp ut drivers and multiplier section, under sub heading primary (differential) driver, for details. 38 o 3.3v cmos out_cmos cmos output: see specificat ion table and the clock drivers section 40 i diff input fdbk_inb complementary feedback input: in standard operating mode, this pin is connected to the filtered ioutb output . this internally bi ased input is typically ac-coupled, and when configured as such, can accept any differential signal whose single-ended swing is at least 400 mv. 41 i diff input fdbk_in feedback input: in standard operating mode , this pin is connected to the filtered iout output 48 o dac_rset dac output current setting resistor. connect a resistor from this pin to gnd . see the dac output section. 50 o iout dac output: this signal should be filt ered and sent back on ch ip through fdbk_in input 51 o ioutb complimentary dac output: this signal should be filtered and sent back on chip through fdbk_inb input 56 i/o 3.3v cmos refselect reference select input: in manual mode, the refselect pin operates as a high impedance input pin, while in automatic mode, it operates as a low impedance output pin. logic 0 (low) indicates/selects refa. logic 1 (high) indicates/selects refb. there is no internal pull-up/pull-down resistor on this pin.
preliminary technical data ad9549 rev. prb | page 17 of 71 57 i/o 3.3v cmos holdover holdover: (active high) in manual holdover mode, this pin is used to force the ad9549 into holdover mode. in automatic holdover mo de, it indicates holdover status. there is no internal pull-up/pull-down resistor on this pin. 58 i 3.3v cmos pwrdown power down: when this active high pin is asserted, the device becomes inactive and enters the full power down state. this pin has an internal 50kohm pull-down resistor. 59 i 3.3v cmos reset chip reset: when this active high pin is as serted, the chip goes into reset. note: upon power up, a 10 us reset pulse is internally generated when the power supplies reach a threshold and stabilize. this pin has an internal 50kohm pull-down resistor. 60 i 3.3v cmos io_update i/o update: a logic transition from 0 to 1 on this pin transfers data from the i/o port registers to the control registers (see the write subsection of the general operation of serial control port section). this pin has an internal 50kohm pull-down resistor. 61 i 3.3v cmos csb chip select: active low. when programming a device, this pin must be held low. in systems where more than one ad9549 is pr esent, this pin enables individual programming of each ad9549. this pin has an internal 100kohm pull-up resistor. 62 o 3.3v cmos sdo serial data output: when the de vice is in three wire mode, data is read on this pin. there is no internal pull-up/pull-down resistor on this pin. 63 i/o 3.3v cmos sdio serial data input/output: when the device is in three-wire mode, data is written via this pin. in 2 wire mode, data reads and writes both occur on this pin. there is no internal pull-up/pull-down resistor on this pin. 64 o 3.3v cmos sclk serial programming clock: data clock for se rial programming. this pin has an internal 50kohm pull-down resistor.
ad9549 preliminary technical data rev. prb | page 18 of 71 input / output termination recommendations 0.01 uf 100 0.01 uf ad9549 1.8v hstl output downstream device (high-z) figure 4: ac-coupled hstl output driver (recommended) 50 ad9549 1.8v hstl output 50 downstream device (high-z) + avdd/2 - figure 5: dc-coupled hstl output driver 0.01 uf 100 (opt.) 0.01 uf ad9549 self-biasing ref input figure 6: reference input. 0.1 uf 100 0.1 uf ad9549 self-biasing fdbk input figure 7: fdbk input.
preliminary technical data ad9549 rev. prb | page 19 of 71 theory of operation figure 8: detailed block diagram overview the ad9549 provides a clocking output which is directly related in phase and frequency to the selected (active) reference (ref_a or ref_b), but having a phase noise spectrum primarily governed by the syst em clock. a wide band of reference frequencies is supported. jitter existent on the active reference is greatly reduced by a programmable digital filter in the digital phase locked loop (p ll), which is the core of this product. the ad9549 supports both manual and automatic holdover. while in holdover , the ad9549 will continue to provide an output as long as the system clock is maintained. the frequency of the output during holdover is an average of the steady state output freque ncy prior to holdover. also offered are manual and automatic switchover modes for changing between the two references should one become suspect or lost. a digitally controlled oscillator (dco) is implemented using a direct digital synthesizer (dds) with an integrated output dac, clocke d by the system clock. a bypassable pll based frequency mu ltiplier is present enabling use of an inexpensive, low frequency source for the system clock. for best jitter performance, the system clock pll should be bypassed, and a low-noise high-frequency system clock should be provided directly. sampling theory sets an upper bound for the dds output frequency at 50% of f s (where f s is the dac sample rate), but a practical limitation of 40% of f s is generally recommended to allow for the selectivity of the required off-chip reconstruction filter. the output signal from the reconstruction filter is fe d back to the ad9549, both to complete the pll, and to be processed through the output circuitry. the output circuitry includes hstl and cmos output buffers, as well as a frequency doubler, for designs that need to provide frequencies abov e the nyquist level of the dds. the individual functional blocks are described in the following sections. dds/dac freq tuning word holdover control logic digital interface pfd s r 2x hstl clk_out cmos clk_out input ref monitor ref_cntrl lock detect s1-s4 ref_a ref_b ref_select sys_clk freq est. digital pll core sysclk port external analog low-pass filter slew limit prog. digital loop filter low noise clock multiplier amp fdbk irq & status logic ool&lor holdover
ad9549 preliminary technical data rev. prb | page 20 of 71 pll core (dpllc) the digital phase locked loop core (dpllc) includes the frequency estimation block and the digital phase lock control block driving the dds. the start of the dpllc signal ch ain is the reference signal, f r , which appears on ref a or ref b inputs. the frequency of this signal can be divided by an integer factor of r via the feedforward divider. the output of the feedforward divider is routed to the phase/frequency detector (pfd). therefore, the frequency at the input to the pfd is given by r f pfd r f = . the pfd outputs a time series of digital words that are routed to the digital loop filter. the di gital filter implementation offers many advantages: the filter resp onse is determined by numeric coefficients rather th an discrete component values. there is no aging of components and therefore, no drift of component value over time. there is no ther mal noise in the loop filter, and there is no control node leakage current (which causes reference feed through in a traditional analog pll). the output of the loop filter is a time series of digital words. these words are applied to the frequency tuning input of a dds to steer the dco frequency. the dds provides an analog output signal via an integrated dac, effectively mimicking the operation of an analog vco. the dpllc can be programmed to operate in conjunction with an internal frequency estimator to help decrease the time required to achieve lock. wh en the frequency estimator is employed, frequency acquisition is accomplished in a two-step process: step 1: an estimate is made of the frequency of f pfd . the phase- lock control loop is essentially inoperative during the frequency estimation process. once a freq uency estimate is made, it is delivered to the dds so that its output frequency is approximately equal to f pfd multiplied by s (the modulus of the feedback divider). step 2: the phase-lock control loop becomes active and acts as a servo to acquire and hold phase lock with the reference signal. as mentioned in step 1) above, the dpllc includes a feedback divider that allows the dco to operate at an integer multiple (s) of f pfd . this establishes a nominal dco frequency (f dds ) given by: () r r s dds f f = . figure 9: ad9549 digital pll block diagram feedforward divider (divide-by-r) the feedforward divider is an integer divider allowing frequency prescaling of the ref source input signal while maintaining the desired low jitter performance of the ad9549. the feedforward divider is a programmable modulus divider with very low jitter injection. the divider is capable of handling input frequencies as high as 750 mhz. the divider depth is 16- bits cascaded with an additional divide-by-two. the divider therefore is capable of integer division from 1 to 65,535 (index of 1) or 2 to 131,070 (index of 2). the divider is programmed via the i/o register map to trigger on either the rising (default) or falling edge of the ref source input signal. there is a lower bound on the value of r imposed by the phase- frequency detector within the dpllc which has a maximum operating frequency of f pfd[max] as explained in the fine phase detector section. the r divider /2 bit must be set when ref_a or ref_b is greater than 400 mhz. the user must also ensure that r is chosen so that it satisfies the inequality: r ceil (f r / f pfd[max] ) the upper bound is: r floor(f r /8 khz) where the ceil (x) function yields the nearest integer x. for example, if f r =155 mhz and f pfd[max] =24.5 mhz, then ceil (155/24.5) = 7, so r must be > 7. feedback divider (divide-by-s) the feedback divider is an integer divider allowing frequency multiplication of the ref signal that appears at the input of the phase detector. it is capable of handling frequencies well above the nyquist limit of the dds. the divider depth is 16-bits cascaded with an additional divide-by-two. the divider is therefore capable of integer division from 1 to 65,535 (index of 1) or 2 to 131,070 (index of 2). the divider is programmed via
preliminary technical data ad9549 rev. prb | page 21 of 71 the i/o register map to trigger on either the rising (default) or falling edge of the feedback signal. the feedback divider must be programmed within certain boundaries. the s divider /2 bit must be set when fdbk_in is greater than 400 mhz. the upper boundary on the feedback divider is the lesser of the maximum programmable value of s and the maximum practical output frequency of the dds (~ 40%f s ). two formulae are given: s max1 for a feedback divider index of 1 and s max2 for an index of 2: ( ) 65535 , min % 40 1 max r s f r f s = or [ ] 131070 , min % 40 2 max r s f r f s = where r is the modulus of the feedforward divider, f s is the dac sample rate, and f r is the input reference frequency. the dco has a minimum frequency, f dcomin (see dac output characteristics section of ac specification table). this imposes a lower bound, s min , on the feedback divider value, as well. ( ) ( ) 1 , max min min r dco f f r s = note: reduced dco frequencies result in worse jitter performance (a consequence of the reduced slew rate of the sinusoid generated by the dds). forward and reverse fec clock scaling the feedforward (divide-by-r) and feedback divider (divide- by-s) enable fec clock scaling. for instance, to multiply the incoming signal by 255/237, set the s- divider to 255, and the r-divider to 237. one should be careful to abide by the limitations on the r- and s-dividers, and make sure the phase detector input frequency is within specified limits. phase detector the phase detector is composed of two detectors: a coarse phase detector and a fine phase detector. the two detectors operate in parallel. both detectors measure the duration ( t) of the pulses generated by a conventional 3-state phase/frequency detector. together, the fine and coarse phase detectors produce a digital word that is a time-to-digital conversion of the separation between the edge transitions of the pre-scaled reference signal and the feedback signal. if the fine phase detector is able to produce a valid result, then this result alone serves as the phase error measurement. if the fine phase detector is either in an overflow or underflow condition, the phase error measurement uses the coarse phase detector instead. digital loop filter the digital loop filter integrates and low-pass filters the digital phase error values delivered by the phase detector. the loop filter response mimics that of a 2 nd order, r-c network used to filter the output of a typical phase detector and charge pump combination as shown in the diagram below. phase/ frequency detector charge pump c1 r2 c2 loop filter vco clk figure 10: typical analog pll block diagram the building blocks implemented on the ad9549, however, are digital. a time-to-digital converter that produces digital values proportional to the edge timing error between the clk and feedback signals replaces the phase-frequency detector and charge pump. a digital filter that processes the edge timing error samples from the time-to-digital converter replaces the loop filter. a dds replaces the vco, which produces a frequency that is linearly related to the digital value provided by the loop filter. this is shown in figure 11 on page 22 with some additional detail. the samples provided by the time-to-digital converter are delivered to the loop filter at a sample rate equal to the clk frequency (i.e., f r /r). the loop filter is intended to oversample the time-to-digital converter output at a rate determined by the "p"-divider. the value of p is programmable via the i/o register map. it is stored as a 5-bit number, p io . the value of p io is related to p by the equation: p = 2 p io (where 5 p io 16) hence, the "p"-divider can provid e divide ratios between 32 and 65536 in power-of-2 steps. with a dac sample rate of 1ghz the loop filter sample rate can range from as low as 15.26khz to a maximum of 31.25mhz. coupled to the loop filter is a cascaded comb-integrator (cci) fi lter that provides a sample rate translation between the loop filter sample rate (f s /p) and the dds sample rate, f s . the choice of p is important because it controls both the response of the cci filter and the sample rate of the loop filter. in order to understand the method for determining a useful
ad9549 preliminary technical data rev. prb | page 22 of 71 value for p, it is first necessary to examine the transfer function of the cci filter: [ ] 2 ) 1 ( 1 ) ( j p j e p e cci h ? ? ? ? = or () 0 0 , , 1 ) ( ) cos( 1 ) cos( 1 1 2 > = = ? ? p p cci h to evaluate the response in terms of absolute frequency, make the substitution: s f f 2 = (where f s is the dac sample rate and f is the frequency at which h cci is to be evaluated) analysis of this function reveals that the cci magnitude response follows a low pass characteristic that consists of a series of p lobes. the lobes are bounded by null points occurring at frequency multiples of f s /p. the peak of each successive lobe is lower that its predecessor over the frequency range between dc and ?f s . for frequencies greater than ?f s , the response is a reflection about the vertical at ?f s . furthermore, the first lobe (which appears between dc and f s /p) exhibits a monotonically decreasing response. that is, the magnitude is unity at dc and it steadily decreases with frequency until it vanishes at the first null point (f s /p). the null points imply the existence of transmission zeros placed at finite frequencies. while transmission zeros placed at infinity yield minimal phase delay, zeros placed closer to dc result in increased phase delay. hence, the position of the first null point has a significant impact on the phase delay introduced by the cci filter. this is an important consideration, because excessive phase delay negatively impacts the overall closed loop response. as a rule of thumb, choose a value for p so that the frequency of the first null point (f s /p) is the greater of: 80 times the desired loop bandwidth, or 1.5 times the frequency of clk (f r /r) the value of p thus calculated (p max ) is the largest usable value in practice. since p is programmed as p io , it is necessary to define p max in terms of p io , so that p iomax may be determined. the condition, p io p iomax , ensures that the impact of the phase delay of the cci filter on the phase margin of the loop will not exceed 5. p iomax may be expressed as: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ref s loop s iomax f f floor f f floor p 3 2 log , 80 log , 16 min , 5 max 2 2 with a properly chosen value for p, the closed-loop response of the digital pll is primarily determined by the response of the digital loop filter. flexibility in controlling the loop filter response translates directly into flexibility in the range of applications satisfied by the architecture of the ad9549. the ad9549 evaluation software automatically sets the value of the p divider based on the users input criteria. therefore, the formulas are provided here mainly to assist in understanding how the part works. direct digital synthesizer one of the primary building blocks of the digital pll is a direct digital synthesizer (dds). the dds behaves like a sinusoidal signal generator. the frequency of the sinusoid generated by the dds is determined by a frequency tuning word (ftw), which is a digital (i.e., numeric) value. unlike an analog sinusoidal generator, a dds uses digital building blocks and operates as a sampled system. thus, it requires a sampling clock (f s ) that serves as the dds's fundamental timing source. the accumulator behaves as a modulo-2 48 counter with a programmable step size (ftw). a block diagram of the dds is shown below. f s 48 48 19 48 frequency tuning word (ftw) angle to amplitude conversion 14 16 19 phase offset i-set dac- dac+ dac (14-bit) q d 48-bit accumulator figure 11: dds block diagram
preliminary technical data ad9549 rev. prb | page 23 of 71 the input to the dds is a 48-bit ftw that provides the accumulator with a seed value. on each cycle of f s , the accumulator adds the value of the ftw to the running total of its output. for example, given an ftw=5, the accumulator would count by 5's, incrementing on each f s cycle. over time, the accumulator will reach the upper end of its capacity (2 48 in this case). at which point it rolls over, retaining the excess. the average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. the average rollover rate of the accumulator is given by the formula below, and establishes the output frequency (f dds ) of the dds. ( ) s ftw dds f f 48 2 = solving this equation for ftw yields: ? ? ? ? ? ? ? ? ? ? ? ? ? ? = s dds f f round ftw 48 2 for example, given that f s =1ghz and f dds =19.44mhz, then ftw=5,471,873,547,255 (04fa05143bf7h). the relative phase of the sinusoid can be controlled numerically, as well. this is accomplished using the phase offset input to the dds (a programmable 16-bit value ( phase ); see the i/o register map). the resulting phase offset, ? (radians), is given by: ( ) 16 2 2 phase = the dds can be operated in either open loop or closed loop mode, via the close loop bit in the dpll register. there are two open loop modes: single tone and holdover. in single tone mode, the dds behaves like a frequency synthesizer, and uses the value stored in the ftw0 register to determine its output frequency. alternatively, the ftw and phase values can be determined by the device itself using the frequency estimator. because single tone mode ignores the reference inputs, it is very useful for generating test signals to aid in debugging. single tone mode must be activated manually via register programming. in holdover mode, the ad9549 uses past tuning words when the loop was closed to determine its output frequency. therefore, the loop must have been successfully closed in order for holdover mode to work. switching in and out of holdover mode can be either automatic or manual, depending on register settings. typically, the ad9549 operates in closed loop mode. in closed loop mode, the ftw values come from the output of the digital loop filter and vary with time. the dds frequency is steered in a manner similar to a conventional vco-based pll. note: in "closed loop" mode, th e dds phase offset capability is inoperative. dac output the output of the digital core of the dds is a time series of numbers representing a sinusoidal waveform. this series is translated to an analog signal by means of a digital-to-analog converter (dac). the dac outputs its signal to two pins driven by a balanced current source architecture (see dac output diagram below). the peak output current derives from the combination of two factors. the first is a reference current (i dac_ref ) established at the dac_rset pin and the second is a scale factor programmed into the i/o register map. avdd3 current switch array current switch array i fs switch control i fs /2 i fs /2 iout ioutb 50 avss 52 49 code i fs /2 + i code i fs /2 - i code 50 50 51 figure 12: dac output pins
ad9549 preliminary technical data rev. prb | page 24 of 71 the value of i dac_ref is set by connecting a resistor (r dac_ref ) between the dac_rset pin and ground. the dac_rset pin is internally connected to a virtual voltage reference of 1.2v nominal, so the reference current can be calculated by: ref dac r ref dac i _ 2 . 1 _ = note: the recommended value of i dac_ref is 120 a, which leads to a recommended value of r dac_ref of 10k . the scale factor consists of a 10-bit binary number (fsc) programmed into the dac fs current register in the i/o register map. the full-scale dac output current (i dac_fs ) is then given by: () 1024 192 _ _ 72 fsc ref dac fs dac i i ? + = using the recommended value of r dac_ref the full-scale dac output current can be set with 10-bit granularity over a range of approximately 8.6ma to 31.7ma. 20 ma is the default value. phase detector coarse phase detector the coarse phase detector uses the dac sample rate (f s ) to determine the edge timing deviation between the ref signal and the feedback signal generated by the dds. hence, f s sets the timing resolution of the coarse phase detector. at the recommended rate of f s =1ghz, the coarse phase detector spans a range of over 131 s (sufficient to accommodate ref signal frequencies as low as 8 khz). the phase gain of the coarse phase detector is controlled via the i/o registers by means of two numeric entries. the first is a 3- bit power-of-2 scale factor, pds. the second is a 6-bit linear scale factor, pdg. ( ) () pdg r gain phase pds f f cpd r s 6 2 + = fine phase detector the fine phase detector operates on a divided down version of f s as its sampling time base. the sample rate of the fine phase detector is set using a 4-bit word (pfd_div) in the i/o register map and is given by: () div pfd f s rate sample detector phase fine _ 4 = the default value of pfd_div is 5, so for f s =1ghz, the default sample rate of the fine phase detector is 50mhz. the upper bound on the maximum allowable input frequency to the phase detector (f pfd[max] ) is 49% of the sample rate, or: () div pfd f pfd s f _ 8 [max] = therefore, f pfd[max] is 25mhz in the example above. the fine phase detector uses a proprietary technique to determine the phase deviation between the ref signal and feedback signal. the phase gain of the fine phase detector is controlled by an 8- bit scale factor (fpfd_gain) in the i/o register map. the nominal (default) value of fpfd_gain is 200, and establishes the phase gain as: ( ) () r f gain fpfd r fpd phasegain _ 10 2 7 10 = phase detector gain matching although the fine and coarse phase detectors use different means to make a timing measurement, it is essential that both have equivalent phase gain. without proper gain matching the closed-loop dynamics of the system cannot be properly controlled. hence, the goal is to make phasegain cpd = phasegain fpd . this leads to: ( ) ( ) gain fpfd pdg f pds s _ 10 2 2 7 10 6 = + which simplifies to: ( ) s f gain fpfd pds pdg _ 10 16 7 2 ? = typically, fpfd_gain is established first and then pdg and pds are calculated. the proper choice for pds is given by: ( ) [ ] s f gain fpfd round pds 2 _ 10 2 7 log = the final value of pds must satisfy 0 pds 7. the proper choice for pdg is calculated using this equation: ( ) s pds f gain fpfd round pdg 4 7 2 _ 10 ? = the final value of pdg must satisfy 0 pdg 63. for example, let f s =700mhz and fpfd_gain=200, then pds=1 and pdg=23. note that the ad9549 evaluation software will calculate register values that have the phase detector gains already matched.
preliminary technical data ad9549 rev. prb | page 25 of 71 phase detector pin connections there are three pins associated with the phase detector that must be connected to external components. the diagram below shows the recommended component values and their connections. pfd_vrb pfd_vrt pfd_rset 20 21 22 0.1 f 10 f 0.1 f0.1 f 4k99 ad9549 figure 13: phase detector pin connections digital loop filter coefficients in order to provide the desired flexibility, the loop filter has been designed with three programmable coefficients ( , and ). the coefficients along with p (where p=2 pio ) completely defines the response of the filter, which is given by: ( ) ) 1 ( ) 2 ( ) 1 ( 2 ) ( + + ? ? + ? ? + = j j j e e e loopfilter h to evaluate the response in terms of absolute frequency substitute: s f pf 2 = where p is the divide ratio of the "p"-divider, f s is the dac sample rate, and f is the frequency at which the function is to be evaluated. the loop filter coefficients are determined by the ad9549 evaluation software accord ing to three parameters: : desired closed-loop phase margin (0 < < /2 rad) f loop : desired open-loop bandwidth (hz) f dds : desired output frequency of the dds (hz) note that f dds can also be expressed as f dds = f r (s/r). the three coefficients are calculated according to parameters via the equations below: ) tan( 4 c pf ? = ( ) f 2 1 = ( ) ) ( _ 10 2 7 38 f f f c dds gain fpfd ? = where ) sin( 1 1 ) ( + = f , s loop f f c f = , and fpfd_gain is the value of the gain scale factor for the fine phase detector as programmed into the i/o register map. note: the range of loop filter coefficients is limited as follows: 0 < < 2 23 (~8.3910 6 ) -0.125 < < 0 -0.125 < < 0 the above constraints on and constrain the closed-loop phase margin such that both and will assume negative values. even though and are limited to negative quantities, the values as programmed are positive. the negative sign is assumed internally. note: the closed-loop phase margin is limited to the range of 0 < < 90 because and are negative. the three coefficients are implemented as digital elements, necessitating quantized values. determination of the programmed coefficient values in this context follows. the quantized coefficient is composed of three factors, where 0 , 1 and 2 are the programmed values for the coefficient: ( ) ( )( ) 2 1 0 2 2 2048 ? = quantized the boundary values for each are 0 0 4095, 0 1 22, and 0 2 7. the optimal values of 0 , 1 and 2 are: () { } [ ] 4095 2048 2 1 log , 22 min , 0 max ceil = () () { } [ ] 11 log , 7 min , 0 max 1 4095 2 2 ? + = floor ( ) { } [ ] 11 0 1 2 2 , 4095 min , 0 max + ? ? = round
ad9549 preliminary technical data rev. prb | page 26 of 71 the magnitude of the quantized coefficient is composed of two factors, where 0 and 1 are the programmed values for the coefficient: () () ( ) 15 0 1 2 + ? = quantized the boundary values for each are 0 0 4095 and 0 1 7. the optimal values of 0 and 1 are: ( ) ( ) { } [ ] 15 log , 7 min , 0 max 4095 2 1 ? = floor ( ) { } [ ] 15 0 1 2 , 4095 min , 0 max + ? = round the magnitude of the quantized coefficient is composed of two factors: () () ( ) 15 0 1 2 + ? = quantized where 0 and 1 are the programmed values for the coefficient, the boundary values for each are 0 0 4095 and 0 1 7. the optimal values of 0 and 1 are: ( ) ( ) { } [ ] 15 log , 7 min , 0 max 4095 2 1 ? = floor ( ) { } [ ] 15 0 1 2 , 4095 min , 0 max + ? = round the min (), max (), floor (), ceil () and round () functions are defined as follows. the function, min (x 1 , x 2 , x n ), chooses the smallest value in the list of arguments. the function, max (x 1 , x 2 , x n ), chooses the largest value in the list of arguments. the function, ceil (x), increases x to the next higher integer if x is not an integer, otherwise x is unchanged. the function, floor(x), reduces x to the next lower integer if x is not an integer, otherwise x is unchanged. the function, round (x), rounds x to the nearest integer. to demonstrate the wide programmable range of the loop filter bandwidth, consider the following design example. the system clock frequency (f s ) is 1ghz, the input reference frequency (f r ) is 19.44mhz, the dds output frequency (f dds ) is 155.52mhz, and the required phase margin ( ) is 45. f r is within the nominal bandwidth of the phase detector (25mhz), and f dds /f r , is an integer (8), so the prescalar is not required. we can therefore use r=1 and s=8 for the feedforward and feedback dividers, respectively. note: if f dds /f r is a non- integer, then r and s must be chosen such that s/r= f dds /f r with s and r both constrained to integer values. for example, if f r =10mhz and f dds =155.52mhz, then the optimal choice for s and r is 1944 and 125, respectively. the open loop bandwidth range under the defined conditions spans 9.5hz to 257.5khz . the wide dynamic range of the loop filter coefficients allows for programming of any open loop bandwidth within this range under these conditions. the resulting closed loop bandwidth range under the same conditions is approximately 12hz to 359khz . the resulting loop filter coefficients for the upper loop bandwidth along with the necessary programming values are shown below. = 4322509.4784981 0 = 3393 (d41h) 0 = 2111 (83fh) 1 = 0 (0h) 1 = 22 (16h) = -0.12499215775201 2 = 0 (0h) 0 = 4095 (fffh) = -0.10354689386232 1 = 0 (0h) the resulting loop filter coefficients for the lower loop bandwidth along with the necessary programming values are shown below. = 0.005883404361345 0 = 16 (10h) 0 = 1542 (606h) 1 = 7 (7h) 1 = 0 (00h) = -0.00000461136116 2 = 7 (7h) 0 = 19 (13h) = -0.000003820176667 1 = 7 (7h) the ad9549 evaluation software generates these coefficients automatically based on the users desired loop characteristics. closed loop phase offset the ad9549 provides for limited control over the phase offset between the reference input signal and the output signal by adding a constant phase offset value to the output of the phase detector. an adder is included at the output of the phase detector as shown in the figure below to support this. the value of the constant (pll offset ) is set via the pll offset register. phase detector loop filter phase offset value clk feedback to cci filter figure 14: input phase offset adder
preliminary technical data ad9549 rev. prb | page 27 of 71 pll offset is a function of the phase detector gain and the desired amount of timing offset ( t offset ). it is given by: ( ) gain fpfd t pll offset offset _ 10 2 7 10 = note: fpfd_gain is described in the fine phase detector section. for example, suppose that fpfd_gain=200, f clk =3mhz, and 1 of phase offset is desired. first, we must find the value of t offset , which is: () ps t t mhz clk offset 9 . 925 3 1 360 1 360 deg = = = having determined t offset , we have: ( ) 1896 200 10 2 9 . 925 7 10 = ? ? = ps pll offset the result has been rounded because pll offset is restricted to integer values. note: the pll offset value is programmed as a 14-bit, twos- complement number. however, the user must ensure that the magnitude is constrained to 12 bits, such that: -2 11 pll offset < +2 11 the above constraint yields a timing adjustment range of 1ns. this ensures that the phase offset remains within the bounds of the fine phase detector. lock detection phase lock detection during the phase locking process, the output of the phase detector tends toward a value of zero, which indicates perfect alignment of the phase detector input signals. as the control loop works to maintain the alignment of the phase detector input signals, the output of the phase detector wanders around zero. the phase lock detector tracks the absolute value of the digital samples generated by the phase detector. these samples are compared to the phase lock detect threshold value programmed in the i/o register map. a false state at the output of the comparator indicates the absolute value of a sample exceeds the value in the threshold register. a true state at the output of the comparator indicates alignment of the phase detector input signals to the degree specified by the lock detection threshold. digital comparator phase lock detect absolute value p-divider clock phase detector samples control logic lock timer unlock timer x y i/o registers 3 5 close loop reset phase lock detect threshold figure 15: phase lock detector block diagram the phase lock detect threshold value (pldt) is a 32-bit number stored in the i/o register map: ( ) gain fpfd t round pldt _ 10 2 7 10 ? ? ? = where t is the maximum allowable timing error between the signals at the input to the phase detector and the value of fpfd_gain is as described in the fine phase detector section. for example, suppose that f r /r=3mhz, fpfd_gain=200, and the maximum timing deviation is given as 1. this yields a t value of: ( ) () 6 10 3 360 1 360 360 1 ? ? = = ? ? = r f r r t r t o o the resulting phase lock detect threshold is: () 1896 10 3 360 200 10 2 6 7 10 = ? ? ? ? ? ? ? ? ? ? ? = round pldt hence, 1896 (00000768h) is the value th at must be stored in the phase lock detect threshold register. the "phase lock detect" signal is generated once the control logic observes that the output of the comparator has been in the true state for 2 x periods of the p-divider clock (see the digital loop filter section for a description of the p-divider). once the phase lock detect signal is asserted, it remains asserted until cleared by an "unlock" event or by a device reset. the duration of the lock detection process is programmable via the phase lock watchdog timer register. the interval is controlled by a 5-bit number, x (0 x 20). the absolute duration of the phase lock detect interval is: s x f p lock t 2 =
ad9549 preliminary technical data rev. prb | page 28 of 71 hysteresis in the phase lock de tection process is controlled by specifying the minimum duration that qualifies as an unlock event. an unlock event is declared when the control logic observes that the output of th e comparator has been in the false state for 2 y+1 periods of the p-divider clock (provided that the phase lock detect signal has been asserted). detection of an unlock event clears the phase lo ck detect signal, and the phase lock detection process is automatically restarted. the time required to declare an unlock event is programmable via the phase unlock watchdog timer register. the interval is controlled by a 3-bit number, y (0 y 7). the absolute duration of the unlock detection interval is: s y f p unlock t 1 2 + = figure 16 below shows the basic timing relationship between the reference signal at the input to the phase detector, the phase error magnitude, the output of the comparator, and the output of the phase lock detector. the example shown here assumes that x=3 and y=1. f r /r f s /p phase error magnitude samples threshold 0 threshold comparator lock timer (x=3) unlock timer (y=1) 8 4 8 locked figure 16: lock/unlock detection timing frequency lock detection frequency lock detection is similar to phase lock detection, with the exception that the difference between successive phase samples is the source of information. a running difference of the phase samples serves as a digital approximation to the time- derivative of the phase samples, which is analogous to frequency. digital comparator absolute value p-divider clock phase detector samples control logic lock timer unlock timer x y i/o registers 3 5 close loop reset differencer frequency lock detect frequency lock detect threshold figure 17: frequency lock detection the formula for the frequency lock detect threshold value (fldt) is: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 2 7 10 _ 10 2 r f r gain fpfd f round fldt where f r is the frequency of the active reference, r is the value of the reference prescaler, and f is the maximum frequency deviation of f r that is considered to indicate a frequency locked condition ( f 0). for example, suppose that f r =3mhz, r=5, fpfd_gain=200, and a frequenc y lock threshold of 1% is specified. then the frequency lock detect threshold value is: () 667 , 170 10 3 5 200 10 2 10 3 % 1 2 6 7 10 6 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = round fldt hence, 170667 (00029aabh) is the value that should be stored in the frequency lock detect threshold register. the duration of the frequency lock/unlock detection process is controlled in exactly the same way as the phase lock/unlock
preliminary technical data ad9549 rev. prb | page 29 of 71 detection process in the previous section. however, different control registers are used: the frequency lock/ unlock watchdog timer registers. reference monitors loss of reference the ad9549 can set an alert when one or both of the reference signals are not present. each of the two reference inputs (refa, refb) has a dedicated lor (loss of reference) circuit enabled via the i/o register map. dete ction of an lor condition sets the appropriate lor bit in both a status register and an irq register in the i/o register map. the lor state is also internally available to the multi- purpose "status" pins (s1:4) of the ad9549. by setting the approp riate bit in the i/o register map, the user can assign a status pin to each of the lor flags. this provides a means to control external hardware based on the state of the lor flags directly. the lor circuits are internal watchdog timers with a programmable period. the period of the timer is set via the i/o register map so that its period is longer than that of the monitored reference signal. the rising edge of the reference signal continuously resets the watchdog timer. if the timer reaches a full count, this indicates that the reference was either lost or its period was longer th an the timer period. lor does not differentiate between these. the period for each of the lor timers is controlled by a 16-bit word in the i/o register map. the period of the timer clock (t clk ) is 2/f s . therefore, the period of the watchdog timer (t wd ) is: t wd = (2/f s )n where n is the value of the 16-bit word stored in the i/o register map for the appropriate lor circuit. choose the value of n so that the watchdog period is greater than the input reference period, expressed mathematically as: ( ) r s f f floor n 2 > where f r is the frequency of the input reference. the value of n results in establishing two frequencies. one for which the lor signal will never be triggered (f present ), and one for which the lor signal will always be active (f lost ). between these frequencies the lor signal will intermittently toggle between states. the values of the two frequency bounds are: () 1 2 2 + = = n f lost n f present s s f f note that when n is chosen to be ( ) 1 2 + r s f f floor , the lor circuit is capable of indicating an lor condition in little more than a single input reference period. for example, if f s =1ghz and f r =2.048mhz, then the smallest useable n value is: () ( ) 245 1 6 9 10 048 . 2 2 10 = + = floor n min which yields values for f present and f lost as: 520 , 032 , 2 816 , 048 , 2 = = lost present f and f note: n should be chosen su fficiently large to account for any acceptable deviation in the period of the input reference signal. notice that the value of n is inversely proportional to the reference frequency, meaning t hat as the reference frequency goes up, the precision for adjusting the threshold goes down. proper operation of the lor circuit requires that n be no less than 3. therefore, the highest reference frequency for which the lor circuit will function properly is given by: f lor_max = f s /6. reference frequency monitor the ad9549 can set an alert when ever one or both of the reference inputs drift in frequency beyond user-specified limits. each of the two references has a dedicated out of limits (ool) circuit enabled/disabled via the i/o register map. detection of an ool condition sets the appropriate ool bit in both a status register and an irq register in the i/o register map. the user can also assign a status pin (s1-s4) to each of the ool flags by setting the appropriate bit in the i/o register map. this provides a means to control external hardware based on the state of the ool flags directly. each reference monitor contains three main building blocks: a programmable reference divider, a 32-bit counter, and a 32-bit digital comparator. figure 18: reference monitor
ad9549 preliminary technical data rev. prb | page 30 of 71 four values are needed to calculate the correct values of the reference monitor: the system clock frequency, f s (usually 1 ghz), the reference input frequency, f r (in hz), the error bound, e (1%=0.01), and the monitor window size (w). the monitor window size is the difference between the maximum and minimum number of counts accumulated between adjacent edges of the reference input. if this window is too small, random variations will cause the ool detector to indicate incorrectly that a reference is out of limits. however, the time required to determine if the reference frequency is valid increases with window size. a window size of at least 20 is a good starting point. the four input values mentioned above are used to calculate the ool divider (d) and ool nominal value (n), which in turn are used to calculate the ool upper limit (u), and ool lower limit (l) according to the following formulas: )) * * 4 , 65535 min( , 1 max( ? ? ? ? ? ? ? ? = e w f f ceil d s r 4 * d f f n s r = ) ( ) ( w floor n floor l ? = ) ( ) ( w floor n ceil u + = the timing accuracy is dependent on two factors. the first is the inherent accuracy of f s , since it serves as the time base for the reference monitor. as such, the accuracy of the reference monitor can be no better than the accuracy of f s . second, the value of w, which must be sufficiently large so that the timer resolves the deviation between a nominal value of f r and a value that is out of limits. as an example, let f r =10mhz, =1.0%, f s =1ghz, and w=20. the limits are then: lower limit = 1980 upper limit = 2020 now let =0.01%, then the limits are: lower limit = 199980 upper limit = 200020 notice that the number of counts (and time) required to make this measurement has increased 100x. reference switchover the ad9549 supports dual input reference clocks. reference switchover may be accomplished either automatically or manually by appropriately programming the "autorefsel" bit in the i/o register map. transition to a newly selected reference depends on a number of factors: state of the refselect pin state of the "ref_ab" control register bit state of the "enable ref input override" register bit holdover status a functional diagram of the reference switchover and holdover logic is shown in figure 19. state machine ref sel derived refsel state derived holdover state holdover autohold autorefsel 0 1 0 1 0 1 override refpin refab 0 1 override hldpin hldovr active refsel state active holdover state to reference switching control logic to holdover control logic figure 19: reference switchover and holdover logic in manual mode, the active reference is determined by an externally applied logic level to the refselect pin. in automatic mode, an internal state machine determines which reference is active, and the refselect pin becomes an output indicating which reference the state machine is using. the user may override the active reference chosen by the internal state machine via the "enable ref input override " bit in the i/o register map. the "ref_ab" bit in the i/o register map is then used to select the desired reference. when in override, it is important to note that the refselect pin does not indicate the physical reference selected by the "ref_ab" bit. instead, it indicates the reference that the internal state machine would select if the device were not in the override mode. this
preliminary technical data ad9549 rev. prb | page 31 of 71 allows the user to force a reference switchover by means of the programming registers while monitoring the response of the state machine via the refselect pin. the same type of operation (manual/automatic and override) also applies to the holdover function, as shown in the reference switchover logic diagram. the dashed arrows in the diagram indicate that the state machine output is available to the refselect and holdover pins when in override mode. use of line card mode to eliminate runt pulses when two references are not in exact phase alignment and a transition is made from one to th e other, it is possible that an extra pulse can be generated. this depends on the relative edge placement of the two references and the point in time that a switch over is initiated. to eliminate the "extra pulse" problem, an "enable line card mode" bit is provided in the i/o register map. the line card mode logi c is shown in figure 20 below. when enable line card bit is 0, reference switch over occurs on command without consideration to the relative edge placement of the references. this means that there is the possibility of an extra pulse. however, when this bit is set to 1, the timing of the reference switch over is executed conditionally as shown in figure 21 on page 31. 0 1 0 1 0 1 qd from reference selection logic refa in refb in ref in selected reference enable line-card mode figure 20: reference switchover control logic note that when the line card mode is enabled, the rising edges of the alternate reference are used to clock a latch. the latch holds off the actual transition until the next rising edge of the alternate reference. shown in figure 21 is a timing diagram that demonstrates the difference between reference switchover with the line card mode enabled and disabled. if enabled, when the reference switchover logic is given the command to switch to the alternate reference, an actual transition does not occur until the next rising edge of the altern ate reference. this action eliminates the spurious pulse that can occur when the line card mode is disabled. refa in refb in ref in line card mode disabled ref in 1 1 1 1 2 2 2 3 3 3 3 4 4 4 4 5 from reference selection logic select refa select refb enabled 2 ref selection stalled until next rising edge of refb figure 21: reference switchover timing holdover holdover control holdover functionality provides the user with a means of maintaining the output clock signal even in the absence of a reference signal at the ref a or b input. in holdover mode, the output clock is generated from the sysclk input (via the dds) by directly applying a frequency tuning word to the dds. transfer from normal operatio n to holdover mode may be accomplished either manua lly or automatically by appropriately programming th e "automatic holdover" bit (0=manual, 1=auto). the actual transfer to holdover operation, however, depends on the state of the holdover pin and the state of control re gister bits "enable holdover override" and "holdover on/off". manual holdover is established when the automatic holdover bit is a logic 0 (default). in manual mode, holdover is determined by the state of the holdover pin (0=normal, 1=holdover). the holdover pi n is configured as a high impedance (>100k ) input pin in order to accommodate manual holdover operation. automatic holdover is invoked when the autohold" bit is a logic 1. in automatic mode, the holdover pin is configured as a low impedance output with its logic st ate indicating the holdover state as determined by the internal state machine (0=normal, 1=holdover). in automatic holdover operatio n the user may override the internal state machine by prog ramming the "override hldpin" bit to a logic 1 and the "hldovr" bit to the desired state (0=normal, 1=holdover). however, the holdover pin does
ad9549 preliminary technical data rev. prb | page 32 of 71 not indicate the "forced" holdover state in the override condition, but continues to indicate the holdover state as chosen by the internal state machine (even though the state machine choice is overridden). this allows the user to force a holdover state by means of th e programming registers while monitoring the response of the state machine via the holdover pin. a diagram of the reference switchover and holdover logic is shown in figure 19 on page 30. note: the default state for the reference switchover bits is autohold=0, override hl dpin=0, and hldovr=0. holdover & reference switchover state machine the interplay between the input reference signals and holdover is in figure 22. the various cont rol signals and the four states are shown. states 1 or 2 are in effect when the device is not in the holdover condition, while states 3 & 4 are in effect when the holdover condition is active. when ref a is selected as the "active" reference, then states 1 or 3 are in effect. when ref b is selected as the "active" reference, then states 2 or 4 are in effect. a transition between states depends on the reference switchover and holdover control re gister settings, the logic state of the refselect and holdover pins, and the occurrence of certain events (e.g., a reference failure). the state machine and its relation ship to control register and external pin stimuli are shown below. the state machine generates a "derived" reference selection and holdover state. the actual control signal sent to the reference switchover logic and the holdover logic, however, depends on the control signals applied to the muxes. the "dashed" path leading to the refselect and holdover pins is active when the "auto" mode is selected for referenc e selection and/or holdover assertion. figure 22: holdover state diagram abbreviation key ovrdrefpin: override ref sel pin ovrdhldpin: override holdover pin autorefsel: automatic reference select autorcov: automatic holdover recovery autohold: automatic holdover entry || logical or & logical and % logical not refa: reference a selected refb: reference b selected holdover: holdover state faila: reference a failed failb: reference b failed valida: reference a validated validb: reference b validated figure 23: holdover state diagram abbreviation key
preliminary technical data ad9549 rev. prb | page 33 of 71 reference validation timers each of the two reference inputs has a dedicated validation timer. the status of these timers is used by the holdover state machine as part of the decision making process for reverting to a previously faulty reference. for example, suppose that a reference fails (i.e., an lor or ool condition is in effect) and that the device is programmed to revert automatically to a valid reference when it recovers. when a reference returns to normal operation, the lor and ool conditions will no longer be true. however, the state machine is not immediately notified of the clearing of the lor and ool condition. instead, once both the lor and ool conditions are cleared, the validation timer for that particular reference is started. expiration of the validation time r is an indicati on to the state machine that the reference is now available for selection. however, even though the reference is now flagged as "valid", actual transition to the recovered reference depends on the programmed settings of the vari ous holdover control bits. the validation timers are controlled via the i/o register map. the user should be careful to make sure the validation timer is at least two periods of the reference clock. although there are two independent validation timers, the programmed information is shared among both. the desired time interval is controlled via a 5-bit word (t) such that 0 t 31 (default is t=0). the duration of the validation timers is given by: ( ) 1 2 1 0 ? = + t recover t t where t 0 is the sample rate of the digital loop filter, whose period is: s p f t io 2 0 = (see the digital loop filter section) holdover operation when the holdover condition is asserted, the dds output frequency is no longer controlled by the phase lock feedback loop. instead, a static frequency tuning word (ftw) is applied to the dds to hold it at a spec ified frequency. the source of the static ftw depends on the status of the appropriate control register bits. during normal operation, the averager & sampler monitors and accumulates up to 65000 ftw values as they are generated, and upon en tering holdover, the holdover state machine can use the averaged tuning word, or the last valid tuning word. holdover mode is exited in a similar manner that it is entered. if manual holdover control is used, then when the holdover pin is de-asserted, the phase detector starts comparing the holdover signal with the reference input signal, and will start to adjust the phase/frequency using the holdover signal as its starting point. the behavior of the holdover state machine when it is in automatically exiting holdover mode is very similar. the primary difference is that reference monitor is continuously monitoring both reference inputs and as soon as one becomes valid, it automatically switches to that input. the output frequency in holdover mode depends on the frequency of the sysclk input source and the value of the frequency tuning word applied to the dds. therefore, the stability of the output signal is completely dependent on the stability of the sysclk source (and the sysclk pll multiplier, if enabled). note: it is very important to power down an unused reference input to avoid chattering on that input. also, the reference validation timer must be set to at least one full cycle of the signal coming out of the reference divider. holdover sampler and averager if activated via the i/o register map, the hsa continuously monitors the data generated by the digital loop filter in the background. it should be noted that the loop filter data is a time sequence of frequency adjustments ( f) to the dds. the output of the hsa is routed to a read-only register in the i/o register map and to the holdover control logic. the first of these destinations (the read-only register) serves as a "trace buffer" that may be read by the user and the data processed externally. the second destination (the holdover control logic) uses the output of the hsa to "peg" the dds at a specific frequency upon entry into the holdover state. hence, the dds will assume a frequency specified by the last value generated by the hsa just prior to entering the holdover state. the state of the output mux is established by programming the i/o register map. the default state is such that the f values pass through the hsa unaltered. in this mode, the output sample rate is f s /p, the same as the sample rate of the digital loop filter. note: p is the divide ratio of the "p"-divider (see digital loop filter on page 21) and f s is the dac sample rate. alternatively, the mux can be set to select the averaging path. in this mode, a "block average" is performed on a sequence of
ad9549 preliminary technical data rev. prb | page 34 of 71 samples. the length of the sequence is determined by programming the value of y (a 4-bit number stored in the i/o register map), and has a value of 2 y+1 . in the "averaging" mode, the output sample rate is given by f s / (p?2 y+1 ). when the number of f samples specified by y has been collected, the averaged result is delivered to a 2-stage pipeline. the last stage of the pipeline contains the value that will be delivered to the holdover control logic when a transition into the holdover state occurs. the pipeline is a guarantee that the averaged f value delivered to the holdover control logic has not been interrupted by the transition into the holdover state. the pipeline provides an inherent delay of t = p?2 y+1 /f s . hence, the dds "hold" frequency is the average as it appeared t to 2 t seconds prior to entering the holdover state. note that the user has some control over the duration of t because it is dependent on the programmed value of y. output frequency range control under normal operating conditions, its output frequency is dynamically changing in response to the output of the digital loop filter. the loop filter ca n steer the dds to any frequency between dc and f s /2 (with 48-bit resolution). however, the user is given the option of placing limits on the tuning range of the dds via two 48-bit registers in the i/o register map: ftw upper limit and ftw lower limit . if the tuning word input exceeds the upper or lower fr equency limit boundaries, the tuning word is clipped to the appropriate value. the default setting for these registers is f s /2 and dc, respectively. it may be desirable to limit the output range of the dds to a narrow band of frequencies (for example, to achieve better jitter performance in conjunction with a band pass filter). see use of narrowband filter for high performance on page 35 for more information about this feature. loop filter dds/dac s phase detector external reconstruction filter ref in r frequency limiter loop filter dds/dac s phase detector external reconstruction filter ref in r low pass band pass figure 24: application of the frequency limiter reconstruction filter the origin of the output cloc k signal produced by the ad9549 is the combined dds and dac. the dac output signal appears as a sinusoid sampled at f s . the frequency of the sinusoid is determined by the frequency tuning word (ftw) that appears at the input to the dds. the dac output is typically passed through an extern al reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. the signal is then brought back on-chip to be converted to a square wave that is routed internally to the output clock dr iver or the 2x dll multiplier. since the dac constitutes a sampled system, its output must be filtered so that the analog wave form accurately represents the digital samples supplied to the dac input. the unfiltered dac output contains the desired base band signal, which extends from dc to the nyquist frequency (f s /2). it also contains images of the base band signal that theoretically extend to infinity. notice that the odd images (shown in figure 25 below) are mirror images of the base band signal. furthermore, the entire dac outp ut spectrum is affected by a sin(x)/x response, which is ca used by the "sample and hold" nature of the dac output signal.
preliminary technical data ad9549 rev. prb | page 35 of 71 magnitude (db) f f s 2f s f s /2 3f s /2 5f s /2 -100 0 -20 -40 -60 -80 sin(x)/x envelope image 0image 1image 2image 3image 4 primary signal base band spurs filter response figure 25: dac spectrum vs. re construction filter response the response of the reconstructi on filter should preserve the base band signal (image 0), whil e completely rejecting all other images. however, a practical filter implementation will typically exhibit a relatively fl at pass band that covers the desired output frequency plus 20%, roll off as steeply as possible, and then maintain si gnificant (though not complete) rejection of the remaining images. plot 15: dac output without reconstruction filter. f out =155.52 mhz. sysclk=25 mhz. sysclk pll = x40. spur reduction disabled. dpll loop closed. freq span for plot: 500 mhz. plot 16: filtered dac output using 7 th order elliptical with fc=186 mhz. same conditions as previous plot. since the dac output signal serves as the feedback signal for the digital pll, the design of the reconstruction filter can have a significant impact on the over all jitter performance. hence, good filter design and implementation techniques are important for obtaining the best possible jitter results. use of narrowband filter for high performance a distinct advantage of the ad9549 architecture is its ability to constrain the frequency output range of the dds. this allows the user to employ a narrow band reconstruction filter instead of the low pass response shown ab ove resulting in less jitter on the output. for example, suppose that the nominal output frequency of the dds is 150mhz. one might then choose a 5mhz narrow band filter center ed at 150mhz. by using the ad9549's dds frequency limiting feature, the user could constrain the output frequenc y to 150mhz 4.9mhz (which allows for a 100khz margin at the pass band edges). this will ensure that a feedback signal is always present for the digital pll. such a design would be extremely difficult to implement with conventional pll architectures.
ad9549 preliminary technical data rev. prb | page 36 of 71 fdbk inputs the fdbk pins serve as the input to the feedback path of the digital pll. typically, these pins are used to receive the signal generated by the dds after it has been band-limited by the external reconstruction filter. a diagram of the fdbk input pins is provided here, which includes some of the internal components used to bias the input circuitry. note that the fdbk input pins are internally biased to a dc level of ~1v. care should be taken to ensure that any external connections do not disturb the dc bias, as this may significantly degrade performance. to s-divider and clock output section vss 15k 15k ~2pf ~1v vss ~1pf ~1pf fdbk_in fdbk_inb + figure 26: differential fdbk inputs reference inputs reference clock receiver the reference clock receiver is the point at which the user supplies the input clock signal that the synchronizer will synthesize into an output clock. the clock receiver circuit is able to handle a relatively broad range of input levels as well as frequencies from 8 khz up to 750 mhz. the following is a diagram of the refa/b input pins, which includes some of the internal components used to bias the input circuitry. note that the ref input pins are internally biased by a dc source, v b . care should be taken to ensure that any external connections do not disturb the dc bias, as this may significantly degrade performance. to reference monitor and switching logic vss 8k 8k ~1pf ~1pf refa_in refa_inb (or refb_in) (or refb_inb) gnd 1pf v b vdd + figure 27: reference inputs note: support for redundant reference clocks is achieved by using the two reference clock receivers (refa & refb). in order to accommodate a variety of input signal conditions the value of v b is programmable via a pair of bits in the i/o register map. table 3 below gives the value of v b for the bit pattern in register 040f. reference bias level r040f[1:0] v b 00 (default) avdd3-800mv 01 avdd3-400mv 10 avdd3-1600mv 11 avdd3-1200mv table 3: setting of input bias voltage (v b ) sysclk inputs functional description the sysclk pins are where an exte rnal timebase is connected to the ad9549 for generating the inte rnal high frequency system clock (f s ). the sysclk inputs can be operated in one of three modes: 1) sysclk pll bypassed, 2) sysclk pll enabled with input signal generated externally, or 3) cr ystal resonator with sysclk pll enabled. a functional diagram of the system clock generator is shown in figure 28 on page 37.
preliminary technical data ad9549 rev. prb | page 37 of 71 figure 28: system clock generator block diagram the sysclk pll multiplier path is enabled by a logic 0 (default) in the pd sysclk pll location of the i/o register map. the sysclk pll multiplier can be driven from the sysclk input pins by one of two means depending on the logic level applied to the 1.8v cmos clkmodesel pin. when clkmodesel=0, a crystal can be connected directly across the sysclk pins. when clkmodesel=1, the maintaining amp is disabled, and an external frequency source (oscilla tor, signal generator, etc.) can be connected directly to the sysclk input pins. note that clkmodesel=1 does not disable the system clock pll. when the sysclk pll multiplier path is disabled, the ad9549 must be driven by a high frequenc y signal source (up to 1ghz). the signal thus applied to the sysclk input pins becomes the internal dac sampling clock (f s ) after passing through an internal buffer. bipolar edge detector the sysclk pll multiplier path offers an optional bipolar edge detector (bed). this block acts as a frequency doubler by generating a pulse on each edge of the sysclk input signal. the sysclk pll multiplier locks to the falling edges of this regenerated signal. the impetus for doubling the frequency at the input of the sysclk pll multiplier is that an improvement in overall phase noise performance can sometimes be realized. the main drawback is that the bed output not a rectangular pulse with a constant duty cycle even for a perfectly symmetric sysclk input signal. this results in a sub-harmonic appearing at the same frequency as the sysclk input signal, and the magnitude of the sub-harmonic can be quite large. when employing the bed care must be taken to ensure that the loop bandwidth of the sysclk pll multiplier will adequately suppress the sub- harmonic. the benefit offered by the bed depends on the magnitude of the sub-harmonic, the loop bandwidth of the sysclk pll multiplier, and the overall phase noise requirements of the specific application. in many applications, the ad9549 clock output is applied to the input of another pll, and the sub- harmonic is often suppressed by the relatively narrow bandwidth of the downstream pll. note: generally, the benefits of the bipolar edge detector are realized for sysclk input frequencies of 25mhz and above. sysclk pll multiplier when the sysclk pll multiplier path is employed, the frequency applied to the sysclk input pins must be limited so as not to exceed the maximum input frequency of the sysclk pll phase detector. a block diagram of the sysclk generator appears in figure 29 below. figure 29: block diagram of the sysclk pll the sysclk pll multiplier has a 1ghz vco at its core. a phase/frequency detector (pfd) and charge pump provide the steering signal to the vco in typical pll fashion. the pfd operates on the falling edge transitions of the input signal, which means that the loop locks on the negative edges of the reference signal. the charge pu mp gain is controlled via the i/o register map by selecting one of three possible constant current sources ranging from 125-375 a in 125 a steps. the center frequency of the vco is also adjustable via the i/o register map and provides high/low gain selection. the feedback path from vco to pfd consists of a fixed divide-by-2 prescaler followed by a programmable divide-by-n block, where 2 n 33. this limits the overall divider range to any even integer from 4 to 66, inclusive. the value of n is programmed via the i/o register map via a 5-bit word that spans a range of 0 to 31, but the internal logic automatically adds a bias of 2 to the value entered, extending the range to 33. care should be taken when choosi ng these values so as to not exceed the maximum input frequency of the sysclk pll phase detector or bipolar edge detector. these values can be found in the ac electrical characteristics section of this datasheet.
ad9549 preliminary technical data rev. prb | page 38 of 71 external loop filter (sysclk pll) the loop bandwidth of the sysclk multiplier pll can be adjusted by means of three external components as shown in the diagram below. the nominal gain of the vco is 800mhz/v. the recommended component values are shown in table 4 below. they establish a loop bandwidth of approximately 1.6mhz with the charge pump current set to 250 a. the default case is n=40, and assumes a 25mhz sysclk input frequency and generates an internal dac sampling frequency (f s ) of 1ghz. figure 30: external loop filter for sysclk pll sysclk multiplier r1 series c1 shunt c2 < 8 390 1 nf 82 pf 10 470 820pf 56 pf 20 1k 390pf 27 pf 40 (default) 2.2k 180 pf 10 pf 60 2.7k 120 pf 5 pf table 4: recommended loop filter values for a nominal 1.5mhz sysclk pll loop bandwidth detail of sysclk differential inputs a diagram of the sysclk input pins is provided here. included are details of the internal comp onents used to bias the input circuitry. these components have a direct effect on the static levels at the sysclk input pins. this information is intended to aid in determining how best to interface to the device for a given application. note that the sysclk pll bypassed and sysclk pll enabled input paths are internally biased to a dc level of ~1v. care should be taken to ensure that any external connections do not disturb the dc bias, as this may significantly degrade performance. generally, it is recommended that the sysclk inputs be ac coupled to the signal source (except when using a crystal resonator). figure 31: differential sysclk inputs
preliminary technical data ad9549 rev. prb | page 39 of 71 harmonic spur reduction the most significant spurious signals produced by the dds are harmonically related to the desired output frequency of the dds. the source of these harmonic spurs can usually be traced to the dac, and the spur level is in the -60dbc range. this ratio represents a level that is about 10 bits below the full-scale output of the dac (10 bits down is 2 -10 , or 1/1024). to reduce such a spur would require combining the original signal with a replica of the spur but offset in phase by 180. this idea is the foundation of the technique used to reduce harmonic spurs in the ad9549. since the dac has 14-bit resolution, a -60dbc spur can be synthesized using only the lower 4 bits of the dac full scale range. that is, the 4 lsbs can create an output level approxi mately 60db below the full scale level of the dac (commensurate with a -60dbc spur). this fact gives rise to a means of digitally reducing harmonic spurs or their aliased images in the dac output spectrum by digitally adding a sinusoid at the input of the dac with similar magnitude as the offending spur but shifted in phase to produce destructive interference. although the worst spurs tend to be harmonic in origin, the fact that the dac is part of a sampled system results in the possibility of some harmonic sp urs to appear in non-harmonic locations in the output spectrum. for example, if the dac is sampled at 1 ghz and generates an output sinusoid of 170 mhz, the 5 th harmonic would normally be at 850 mhz. however, because of the sampling process, this spur appears at 150 mhz, only 20 mhz away from the fundamental. hence, when attempting to reduce dac spurs it is important to know the actual location of the harmonic spur in the dac output spectrum based on the dac samp le rate so that its harmonic number can be reduced. the mechanics of performing harmonic spur reduction is shown in figure below. it essent ially consists of two additional dds cores operating in parallel with the original dds. this enables the user to reduce two different harmonic spurs from the 2 nd to the 15 th with 9 bits of phase offset control ( ) and 8 bits of amplitude control. the dynamic range of the canc ellation signal is further augmented by a gain bit associated with each channel. when this bit is set, the magnitude of the cancellation signal is doubled by employing a 1-bit left-shift of the data. however, the shift operation reduces the granularity of the cancellation signal magnitude. note: full-scale amplitude of a cancellation spur is approximately -60dbc when the gain bit is a logic 0 and approximately -54dbc when the gain bit is a logic 1. sysclk 48 48 19 48 48-bit frequency tuning word (ftw ) 48-bit accum ulator angle to amplitude conversion dac (14-bit) 14 16 19 dds phase offset i-s et dds- dds+ 0 1 14 2-channel harmonic frequency generator 9 ch1 cancellation phase offset ch1 harmonic number h arm onic spur c ancellation spur c ancellation enable 8 ch1 cancellation magnitude 4 dds ch2 harmonic number 4 9 ch2 cancellation phase offset 8 ch2 cancellation magnitude ch1 ch2 headroom correction dq ch1 gain ch2 gain 0 1 shift 0 1 shift figure 32: spur reduction technique
ad9549 preliminary technical data rev. prb | page 40 of 71 output clock drivers & 2x frequency multiplier there are two output drivers provided by the ad9912. the primary supports differential 1.8v hstl output levels while the secondary supports either 1.8v or 3.3v cmos levels, depending on whether pin 37 is driven at 1.8 or 3.3v. the primary differential driver nominally provides an output voltage with 100 load applied differentially (v dd -v ss =1.8v). the source impedance of the driver is approximately 100 for most of the output clock period; during transition between levels, the source impedance reaches a maximum of about 500 ohms. the driver is designed to support output frequencies of up to and beyond the oc-12 network rate of 622.08mhz. the output clock may also be powered down by a control bit in the i/o register map. primary 1.8v differential hstl driver the dds produces a sinusoidal clock signal that is sampled at the system clock rate. this dds output signal is routed off-chip where it is passed through an analog filter and brought back on- chip for buffering and, if necessary, frequency doubling. where possible, for the best jitter performance, it is recommended that the upconverter be bypassed. the 1.8v hstl output driver should be ac-coupled, with 100 termination at the destination. the driver design has low jitter injection for frequencies in the range of 50 to 750 mhz. please refer to the ac electrical specifications for the exact frequency limits. 2x frequency multiplier the ad9549 may be configured (v ia the i/o register map) with an internal 2x delay locked loop (dll) multiplier at the input of the primary clock dr iver. the extra octave of frequency gain allows the ad 9549 to provide output clock frequencies that exceed the range available from the dds alone. these settings are found in registers 0010 and 0200. the input to the dll consists of the filtered dds output signal after it has been "squared up" by an integrated clock receiver circuit. the dll can accept input frequencies in the range of 200mhz to 400mhz. single-ended cmos output in addition to the high speed differential output clock driver, the ad9549 provides an independent, single-ended output, cmos clock driver. it serves as a relatively low speed (<50mhz) clock source. the origin of the signal generated by the cmos clock driver is determined by the appropriate control bits in the i/o register map. the user may select one of two sources under program control. one source is the signal generated by the dds after it has been externally filtered and brought back on-chip. in this configuration, the cmos clock driver generates the same frequency as appears at the output of the dds. note: in this configuration, the dds output frequency must not exceed 50mhz. the other source is the output of the feedback divider (s- divider). in this configuration, the cmos clock driver generates the same frequency as the input reference after optional prescaling by the r-divider (i.e., f cmos =f r /r) which is inherently limited to a maximum of 25 mhz. frequency slew limiter the ad9549 offers frequency slew limiting capability enabling users to specify the maximum rate of frequency change that appears at the output. the function is programmable via the i/o register map. program control a bit to enable/disable the function (default condition is disable ) and a register that sets the desired slew rate. the frequency slew limiter is located between the digital loop filter and the cci filter as shown in the diagram below. figure 33: frequency slew limiter
preliminary technical data ad9549 rev. prb | page 41 of 71 the frequency slew limiter sets a boundary on the rate of change of the output frequency of the dds. the frequency slew limiting constant, k slew , is a 48-bit value stored in the i/o register map. the value of the constant is determined by: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = + t f f round k s p slew io 2 48 2 where p io is the value stored in the i/o register map for the "p"-divider, f s is the dac sample rate, and f/ t is the desired frequency slew rate limitation. for example, suppose that f s =1ghz, p io =9 and f/ t=5khz/second, then: () () 721 10 5 3 10 2 2 9 9 48 = ? ? ? ? ? ? ? ? ? ? ? ? ? = + round k slew the resulting slew rate can be calculated as: ? ? ? ? ? ? ? ? = + io p s slew f k t f 48 2 2 the above example yields: f/ t=5.003khz/s frequency estimator the ad9549 has a frequency estimation function that will automatically set the dds output frequency so that the feedback frequency (f dds /s) and the prescaled reference frequency (f ref_in /r) are matched within an error tolerance ( 0 ). its primary purpose is to allow the pll to quickly lock when the reference frequency is not known. the error tolerance is defined as a fractional error and is controlled by a 16-bit programmable value (k) via the i/o register map. the precision of any frequency measurement is dependent on two factors: the timing resolution of the measurement device ( t) the duration of the measurement (t meas ) the frequency estimator uses f s as its measurement reference, so t=1/f s (i.e., t=1ns for a 1ghz dac sample rate). the duration of the measurement is controlled by k, which establishes a measurement interval that is k cycles of the measured signal such that t meas =kr/f ref_in . the frequency estimator uses a 17-bit counter to accumulate the number t periods within the measurement interval. the finite capacity of the counter puts an upper limit on the duration of the measurement, which is constrained to t max =2 17 /f s . if f s =1ghz, then this equates to ~131 s. the fact that the measurement time is bounded by t max means there is a limit to the largest value of k (k max ) that can be used without causing the counter to overflow. the value of k max is given by: ( ) 65535 floor k max = where r s f r f = r is the modulus of the feedforward divider and f r is the input reference frequency. the measurement error ( ) associated with the frequency estimator depends on the choice of the measurement interval parameter (k). these are related by: () 1 1 ? = ? k floor k with a specified fractional error ( 0 ), only those values of k for which 0 result in a frequency estimate that meets the requirements. a plot of versus k (for a given ) takes on the general form shown below. k 1 0 1 2 16 bounded by envelope 0 k 0 k 1 k hi k lo < 0 for all k > k 1 > 0 for all k < k 0 < 0 for some k (k 0 < k < k 1 ) figure 34: frequency estimator vs. k an iterative technique is necessary to determine the exact values of k 0 and k 1 . however, a closed form exists for a conservative estimate of k 0 (k lo ) and k 1 (k hi ): ( ) [ ] 0 1 1 1 + = ceil k lo ( ) [ ] 0 1 2 1 + = ceil k hi
ad9549 preliminary technical data rev. prb | page 42 of 71 as an example, consider the system conditions specified below: f s = 400mhz f ref_in = 155.52mhz r = 8 0 =0.00005 (i.e., 50ppm) these conditions yield k max =3185, which is the largest k value that can be programmed without causing the frequency estimator counter to overflow. with k=k max we find that t meas =163.84 s and =30.2ppm. k max will generally (but not always) yield the smallest value of , but this comes at the cost of the largest measurement time (t meas ). if the measurement time must be reduced, then k hi can be used instead of k max . this yields: k hi =1945, t meas =100.05 s, and =39.4ppm. the measurement time can be further reduced (though marginally) by using k 1 instead of k hi . k 1 is found by solving the 0 inequality iteratively. to do so, start with k=k hi and decrement k successively while evaluating the inequality for each value of k. stop the process the first time that the inequality is no longer satisfied and add 1 to the value of k thus obtained. the result is the value of k 1 . for the above example, k 1 =1912, t meas =98.35 s, and =39.8ppm. if a further reduction of the measurement time is necessary, then k 0 can be used. k 0 is found in a manner similar to k 1 . start with k=k lo and increment k successively while evaluating the inequality for each value of k. stop the process the first time that the inequality is satisfied. the result is the value of k 0 . for the above example, k 0 =1005, t meas =51.70 s and =49.0ppm. status and warnings status pins four pins (s1 C s4) are reserved for providing device status information to the external environment. these four pins are individually programmable (via the serial i/o port) as an or'd combination of six possible status indications. each pin has a dedicated group of control register bits that determine which internal status flags are used to provide an indication on a particular pin (as shown in the diagram below). internal status flags refa lor refa ool refa invalid refb lor refb ool refb invalid phase lock detect frequency lock detect irq 0 1 0 1 0 1 status pin control register (1 of 4) refab lor phase lock refab ool irq refab invalid refab frequency lock status pin (1 of 4) ref lor ref ool ref invalid phase lock freq. lock irq figure 35: status pin control
preliminary technical data ad9549 rev. prb | page 43 of 71 reference monitor status in the case of reference monitoring status information, a pin can be programmed for either re fa or refb, but not both. in addition, the or'd output conf iguration allows the user to combine multiple status flags into a single status indication. for example, if both the lor a nd ool control register bits are true, then the status pin associated with that particular control register will give an indication if either the lor or ool status flag is asserted for the selected reference (a or b). default dds output frequency on power-up the four status pins (s1-s4) provide a completely separate function at power-up. they can be used to define the output frequency of the dds at power-up even though the i/o registers have not yet been programmed. this is made possible because the status pins are designed with bi-directional drivers. at power-up, internal logic initiates a reset pulse of about 10 ns. during this time, s1-s4 briefly function as input pins, and can be driven externally. any logic levels thus applied are transferred to a 4-bit register on the falling edge of the internally initiated pulse. the falling edge of the pulse also returns s1-s4 to their normal function as output pins. the same behavior occurs when the reset pin is asserted manually. setting up s1-s4 for default dds start-up is accomplished by connecting a resistor to each pin (either pull-up or pull-down) to produce the desired bit pattern, yielding 16 possible states that are used both to address an internal 8x16 rom and to select the sysclk mode (see table 5). the rom contains eight 16-bit dds frequency tuning words (ftws), one of which is selected by the state of the s1-s3 pins. the selected ftw is transferred to the ftw0 register in the i/o register map without the need for an "i/o_update". this ensures that the dds generates the selected frequency even if the i/o registers have not been programmed. the state of the s4 pin selects whether the internal system cloc k is generated by means of the internal sysclk pll multiplier or not (see the sysclk input section for details). the dds output frequency listed in table 5 assumes that the internal dac sampling frequency (f s ) is 1ghz. these frequencies scale 1:1 with f s , meaning that other startup frequencies are available by va rying the sysclk frequency. at startup, the internal frequency multiplier defaults to 40x when the xtal/pll mode is selected via the status pins. note: when using this mode, the digital pll loop is still open, and the ad9549 is acting as a frequency synthesizer. the frequency dividers and dpll loop filter must still be programmed prior to closing the loop. status pin s4 s3 s2 s1 sysclk input mode output frequency in mhz 0 0 0 0 xtal/pll 0 0 0 0 1 xtal /pll 38.87939 0 0 1 0 xtal /pll 51.83411 0 0 1 1 xtal /pll 61.43188 0 1 0 0 xtal /pll 77.75879 0 1 0 1 xtal /pll 92.14783 0 1 1 0 xtal /pll 122.87903 0 1 1 1 xtal /pll 155.51758 1 0 0 0 direct 0 1 0 0 1 direct 38.87939 1 0 1 0 direct 51.83411 1 0 1 1 direct 61.43188 1 1 0 0 direct 77.75879 1 1 0 1 direct 92.14783 1 1 1 0 direct 122.87903 1 1 1 1 direct 155.51758 table 5: default power-up frequency options for 1 ghz system clock interrupt request (irq) any one of the four status pins (s1-s4) may be programmed as an irq pin. if a status pin is programmed as an irq pin, then the state of the internal irq flag appears on that pin. an irq flag is internally generated based on the change of state of any one of the internal status flags. the individual status flags are routed to a read-only i/o register (status register) so that the user may interrogate the status of any of these flags at any time. furthermore, each status flag is monitored for a change in state. in some cases, only a change of state in one direction is necessary (e.g., the frequency estimate done flag), but in most
ad9549 preliminary technical data rev. prb | page 44 of 71 cases, the status flags are moni tored for a change of state in either direction (see the diagram below). whether or not a particular state change is allowed to generate an irq is dependent on the state of the bits in the irq mask register. the user programs the mask to enable those events, which are to constitute cause for an irq. if an unmasked event occurs, it will trigger the irq latch and the irq flag will be asserted (active high). the st ate of the irq flag is made available externally via one of the programmable status pins (see the status pins section of this document). the automatic assertion of the irq flag causes the contents of the status register to be transferred to the irq register. the user can then read the irq register any time after the indication of an irq event (i.e., assertion of the irq flag). by noting the bits in the irq register that is set, the cause of the irq event can be determined. once the irq register has been read, the user must set the irq reset bit in the appropriate control register via the serial i/o port. this restores the irq flag to its default state, clears the irq status register, and resets the edge detection logic that monitors the status flags in preparation for the next state change. status flags status register edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect edge detect irq mask register irq reg. irq reset figure 36: interrupt request logic
preliminary technical data ad9549 rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. power-on reset on initial power-up, the ad9549 internally generates a 75ns reset pulse. the pulse is initiated when both of the following two conditions are met: the 3.3v supply is greater than 2.35 0.1v the 1.8v supply is greater than 1.4 0.05v less than 1 ns after reset goes high, the s1-s4 configuration pins go high impedance, and remain high impedance until reset is deactivated. this allows strapping and configuration during reset. because of this reset sequence, power supply sequencing isnt critical. ad9549 power up and programming sequence the following sequence should be followed when initializing the ad9549: 1. apply power. the ad9549 will perform an internal reset. 2. important: make sure the desired configuration registers have single tone mode(r0100[5]) set, and lock loop (r0100[0]) cleared. if the lock loop bit is set on initial loading, the ad9549 will attempt to lock the loop before it has been configured. 3. once the registered are loaded, the ool (out of limits) and lor (loss of reference) can be monitored to insure that a valid reference signal is present on refa or refb. 4. if a valid reference is present, register 0100 can be reprogrammed to clear single tone mode and lock the loop. 5. automatic holdover mode can now be used to make the ad9549 immune to any disturbance on the reference inputs. the following sequence should be followed when changing frequencies the ad9549: 1. open the loop and enter single tone mode via register 0100. 2. enter the new register settings. 3. write 1e to register 0012. 4. once the registered are loaded, the ool (out of limits) and lor (loss of reference) can be monitored to insure that a valid reference signal is present on refa or refb. 5. if a valid reference is present, register 0100 can be reprogrammed to clear single tone mode and lock the loop. 6. automatic holdover mode can now be used to make the ad9549 immune to any disturbance on the reference inputs. notes: attempting to lock the loop without a valid reference can put the ad9549 into a state that requires a reset. automatic holdover mode is not available unless the loop has been successfully closed. if the user desires to open and close the loop manually, we recommend writing 1e to register 0012 prior to reclosing the loop.
ad9549 preliminary technical data rev. prb | page 46 of 71 power management the ad9549 features multiple power supplies, and their power consumption varies with its configuration. this section covers which power supplies can be grouped together, and how each blocks power consumption varies with frequency. the numbers quoted here are for comparison only. please refer to the spec table for exact numbers. with each group, bypass caps of 1 uf in parallel with a 10 uf should be used. the recommendations here are for typical applications, and an application demanding the highest performance may require additional power supply isolation. 3.3v supplies digital i/o (pin 1) and vddx_ref (pin 14): these two 3.3v supplies can be grouped together. the power consumption on pin 1 varies dynamically with serial port activity. noise from the serial port that couples into the reference input should be filtered by the digital pll. avdd3 (pin 37): this is the cmos driver supply. if the cmos driver will be used, this supply should be isolated from other 3.3v supplies to avoid a spur at the output frequency. the power consumption is a function of the output frequency and loading of this pin. if this supply will not be used, this supply can be tied to other 3.3v supplies, and its consumption will be less than 5 ma. avdd3 (pins 46,47,49): these are 3.3v dac power supplies that typically consume about 25ma. at a minimum, a ferrite bead should be used to isolate these from other 3.3v supplies, with a separate regulator being ideal. 1.8v supplies digital core (pins 3,5,7): these pins can be grouped together. their current consumption increases from about 160ma at a system clock of 700 mhz to about 220ma a system clock of 1 ghz. there is also a slight (~5%) increase as fout increases from 50 mhz to 400 mhz. vdd dac decoder (pin 53): this 1.8v supply consumes about 20 to 40 ma. it is critical that this supply be well isolated from other 1.8v supplies. at a minimum, a ferrite bead should be used for isolation, with a separate regulator being ideal. avdd (pins 11, 19, 23, 24, 36, 42, 45): these pins may be grouped together and should be isolated from other 1.8v supplies. at a minimum, a ferrite bead should be used for isolation, with a separate regulator being ideal. avdd (pin 25, 26, 29, 30): these pins may be grouped together and should be isolated from other 1.8v supplies. at a minimum, a ferrite bead should be used for isolation, with a separate regulator being ideal.
preliminary technical data ad9549 rev. prb | page 47 of 71 serial control port the ad9549 serial control port is a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. single or multiple byte transfers are supported, as well as msb first or lsb first transfer fo rmats. the ad9549 serial control port can be configured for a single bidirectional i/o pin (sdio only) or for two unidirectional i/o pins (sdio/sdo). serial control port pin descriptions sclk (serial clock) is the serial shift clock. this pin is an input. sclk is used to synchronize serial control port reads and writes. write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. this pin is internally pulled down by a 30 k resistor to ground. sdio (serial data input/output) is a dual-purpose pin and acts as input only or input/output. the ad9549 defaults to bidirectional pins for i/o. alternatively, sdio can be used as a unidirectional i/o pin by writing to the sdo active register at 00h<7> = 1b. in this case, sdio is the input, and sdo is the output. sdo (serial data out) is used only in the unidirectional i/o mode (00h<7> = 1) as a separate output pin for reading back data. bidirectional i/o mode (using sdio as both input and output) is active by default and (i.e. sdo enable register at 00h<7> = 0). csb (chip select bar) is an active low control that gates the read and write cycles. when csb is high, sdo and sdio are in a high impedance state. this pin is internally pulled up by a 100 k resistor to 3.3v. it shou ld not be left floating. see the operation of serial control port section on the use of the csb in a communication cycle. sclk (pin 64) sdio (pin 63) sdo (pin 62) csb (pin 61) ad9549 serial control port figure 37: serial control port operation of serial control port framing a communication cycle with csb a communications cycle (a write or a read operation) is gated by the csb line. csb must be brought low to initiate a communication cycle. csb stall high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (w1:w0 must be set to 00, 01, or 10, see table 6 below). in these modes, csb can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte. csb can go high on byte boundaries only and can go high during either part (instruction or data) of the transfer. during this period, the serial control port state machine enters a wait state until all data has been sent. if the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing th e remaining transfer or by returning the csb low for at least one complete sclk cycle (but less than eight sclk cycl es). raising the csb on a non- byte boundary terminates the se rial transfer and flushes the buffer. in the streaming mode (w1:w0 = 11b), any number of data bytes can be transferred in a co ntinuous stream. the register address is automatically incremented or decremented (see the msb/lsb first transfers section). csb must be raised at the end of the last byte to be transf erred, thereby ending the stream mode. communication cycleinstruction plus data there are two parts to a co mmunication cycle with the ad9549. the first writes a 16-bi t instruction word into the ad9549, coincident with the firs t 16 sclk rising edges. the instruction word provides the ad9549 serial control port with information regarding the data transfer, which is the second part of the communication cycle. the instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data tran sfer, and the starting register address for the first byte of the data transfer. write if the instruction word is for a write operation (i15 = 0b), the second part is the transfer of da ta into the serial control port buffer of the ad9549. the length of the transfer (1, 2, 3 bytes, or streaming mode) is indicate d by 2 bits (w1:w0) in the instruction byte. the length of the transfer indicated by (w1:w0) does not include the two-byte instruction. csb can be raised after each sequence of 8 bits to stall the bus (except after the last byte, where it en ds the cycle). when the bus is stalled, the serial transfer resume s when csb is lowered. stalling on non-byte boundaries resets the serial control port.
ad9549 preliminary technical data rev. prb | page 48 of 71 there are three types of registers on the ad9549: buffered, live, and read-only. buffered (also refe rred to as mirrored) registers require an io_update to transfer the new values from a temporary buffer on the chip to the actual register, and are marked with an m in the column labeled type of the register map. toggling the io_u pdate pin or writing a 1 to the register update bit (r05h<0>) will cause the update to occur. since any number of bytes of data can be changed before issuing an update command, the update simultaneously enables all register changes since any prev ious update. live registers do not require io_update and update immediately after being written. read-only registers ignore write commands, and are marked ro in the type colu mn of the register map. the type column of the register map may also have an ac, which indicates that the register is auto-clearing. read if the instruction word is for a read operation (i15 = 1b), the next n 8 sclk cycles clock out the data from the address specified in the instruction word, where n is 1,2,3,4 as determined by w1:w0. in this case, 4 is used for streaming mode where 4 or more words are transferred per read. the data read back is valid on th e falling edge of sclk. the default mode of the ad9549 serial control port is bidirectional mode, and the data read back appears on the sdio pin. it is possible to set the ad9549 to unidirectional mode by writing the sdo enable register at 00h<7> = 0b, and in that mode, the requested data appears on the sdo pin. by default, a read request reads the register value that is currently in use by the ad9549. however, setting r04h<0>=1 will cause the buffered registers to be read instead. the buffered registers are the ones that will take effect during the next io_update. s clk sdio sdo csb update registers toggle io_update pin serial control port register buffers ad9549 core control registers figure 38: relationship between se rial control port register buffers and control registers of the ad9549 the ad9549 uses addresses 00h to 509h. although the ad9549 serial control port a llows both 8-bit and 16-bit instructions, the 8-bit instructio n mode provides access to five address bits (a4 to a0) only, which restricts its use to the address space 00h to 01f. th e ad9549 defaults to 16-bit instruction mode on power-up, and the 8-bit instruction mode is not supported. the instruction word (16 bits) the msb of the instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, w1:w0, indicate the length of the transfer in bytes. the final 13 bits are the address (a12:a0) at which to begin the read or write operation. for a write, the instruction word is followed by the number of bytes of data indicated by bits w1:w0, which is interpreted according to table 6. a12:a0 : these 13 bits select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. the ad9549 uses all of the 13-bit address space. for multi-byte transfers, this address is the starting byte address. w1 w0 bytes to transfer (excluding the two-byte instruction) 0 0 1 0 1 2 1 0 3 1 1 streaming mode table 6: byte transfer count msb/lsb first transfers the ad9549 instruction word and byte data may be msb first or lsb first. the default for the ad9549 is msb first. the lsb first mode may be set by writin g 1b to register 00h<6>, and requires that an i/o update be executed. immediately after the lsb, first bit is set, all serial control port operations are changed to lsb first order. when msb first mode is active, the instruction and data bytes must be written from msb to lsb. multi-byte data transfers in msb first format start with an instruction byte that includes the register address of the most si gnificant data byte. subsequent data bytes must follow in order from high address to low address. in msb first mode, the serial control port internal address generator decrements for each data byte of the multi- byte transfer cycle.
preliminary technical data ad9549 rev. prb | page 49 of 71 when lsb_first = 1b (lsb first), the instruction and data bytes must be written from lsb to msb. multi-byte data transfers in lsb first format start with an instruction byte that includes the register address of the least si gnificant data byte followed by multiple data bytes. the serial control port internal byte address generator increments for each byte of the multi-byte transfer cycle. the ad9549 serial control port register address decrements from the register address just written toward 0000h for multi- byte i/o operations if the msb firs t mode is active (default). if the lsb first mode is active, the serial control port register address increments from the addr ess just written toward 1fffh for multi-byte i/o operations. unused addresses are not skipped during multi-byte i/o operations. the user should write the default value to a reserved register, and should only write zeros to unmapped registers. note: it is more efficient to issue a new write command than writing the default value to more than two consecutive reserved (or unmapped) registers. msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 7: serial control port, 16- bit instruction word, msb first 05046-019 csb sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data figure 39: serial control port writems b first, 16-bit instruction, 2 bytes data 05046-020 csb sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 40: serial control port readmsb first, 16-bit instruction, 4 bytes data 05046-021 t s don't care don't care w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 d4 d3 d2 d1 d0 don't care don't care r/w t ds t dh t hi t lo t clk t h csb sclk sdio figure 41: serial control port write: msb first, 16-bit instruction, timing measurements
ad9549 preliminary technical data rev. prb | page 50 of 71 05046-022 data bit n? 1 data bit n csb sclk sdio sdo t dv figure 42: timing diagram for se rial control port register read 05046-023 csb sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1 d0 r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 figure 43: serial control port writels b first, 16-bit instruction, 2 bytes data 05046-040 csb sclk sdio t hi t lo t clk t s t ds t dh t h bi n bi n + 1 figure 44: serial control port timingwrite parameter description t ds setup time between data and rising edge of sclk t dh hold time between data and rising edge of sclk t clk period of the clock t s setup time between csb and sclk t h hold time between csb and sclk t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state table 8: definitions of terms used serial control port timing diagrams
preliminary technical data ad9549 rev. prb | page 51 of 71 i/o register map table 9 addr (hex) type name (short description) d7 d6 d5 d4 d3 d2 d1 d0 default (hex) 0000 serial port configuration and part identification 0000 serial config sdo active lsb first (buffered) soft rst long inst. 18 0001 reserved 00 0002 ro 02 0003 ro part id part id 09 0004 read buffer reg 00 0005 ac serial options register update 00 0010 power down and reset 0010 power down / enable pd hstl driver enable cmos driver enable output doubler pd sysclk pll pd refa pd refb full pd digital pd 00 0011 reserved 00 0012 m, ac history reset irq reset fpfd reset cpfd reset lf reset cci reset dds reset 00 0013 m reset pd fund dds s div2 reset r div2 reset s div reset r div reset 00 0020 system clock 0020 n-divider n divider [4:0] 12 0021 reserved 00 0022 pll parameters vco auto range 2x refer- ence vco range charge pump current [1:0] 04 0023 pfd divider pfd divider [3:0] (relationship between sysclk and pfd clock) 05 0100 dpll 0100 m pll control single tone mode disable freq. estimator enable freq slew limiter loop polarity close loop 30 0101 00 0102 r divider [15:0] 00 0103 r-divider falling edge triggered r divider /2 00
ad9549 preliminary technical data rev. prb | page 52 of 71 0104 00 0105 s divider [15:0] 00 0106 s-divider falling edge triggered s divider /2 00 0107 m p-divider p divider[4:0] 05 0108 m alpha-0 [7:0] 00 0109 m alpha-0 [11:8] 00 010a m alpha-1 [4:0] 00 010b m alpha-2 [2:0] 00 010c m beta-0 [7:0] 00 010d m beta-0 [11:8] 00 010e m beta-1 [2:0] 00 010f m gamma-0 [7:0] 00 0110 m gamma-0 [11:8] 00 0111 m gamma-1 [2:0] 00 0112 00 0113 00 0114 loop coefficient s 00 0115 ro n/a 0116 ro n/a 0117 ro n/a 0118 ro n/a 0119 ro n/a 011a ro ftw estimate ftw estimate [47:0] (read-only) n/a
preliminary technical data ad9549 rev. prb | page 53 of 71 011b m 00 011c m 00 011d m 00 011e m 00 011f m 00 0120 m ftw lower limit [47:0] 00 0121 m ff 0122 m ff 0123 m ff 0124 m ff 0125 m ff 0126 m ftw limits ftw upper limit [47:0] 7f 0127 m 00 0128 m 00 0129 m 00 012a m 00 012b m 00 012c m slew limit frequency slew limit [47:0] 00 012d 00 012e 00 012f 00 0130 reserved 00
ad9549 preliminary technical data rev. prb | page 54 of 71 01a0 free-run mode 01a0 00 01a1 00 01a2 00 01a3 00 01a4 00 01a5 reserved 00 01a6 m 00 01a7 m 00 01a8 m 00 01a9 m 00 01aa m start-up cond. 01ab m ftw0 (open loop frequency tuning word) ftw0 [47:0] start-up cond. 01ac- 01ad m phase (open loop only) dds phase word [15:0] 00 01c0 reference selector / holdover 01c0 m automatic control holdover mode automatic selector automatic recover automatic holdover 00 01c1 m override enable line-card mode enable ref input override ref_ab enable holdover override holdover on/off 00 01c2 averaging window ftw windowed average size [3:0] 00 01c3 reference validation validation timer [4:0] 00 0200 doubler and output drivers 0200 hstl driver opol (polarity) hstl output doubler 05 0201 cmos driver cmos mux 00
preliminary technical data ad9549 rev. prb | page 55 of 71 0300 monitor 0300 ro pfd freq too high pfd freq too low freq. est. done ref selected free run ph. lock detected freq. lock detected n/a 0301 ro status refa valid refa lor refa ool refb valid refb lor refb ool n/a 0302 ro pfd freq too high pfd freq too low freq. est. done ref selected free run ph. lock detected freq. lock detected 00 0303 ro irq status refa valid refa lor refa ool refb valid refb lor refb ool 00 0304 ref. changed leave free run enter free run 00 0305 freq est done phase unlock phase lock freq. unlock freq. lock 00 0306 refa valid !refa valid refa lor !refa lor refa ool !refa ool 00 0307 irq mask refb valid !refb valid refb lor !refb lor refb ool !refb ool 00 0308 s1 pin config ref? ref? lor ref? ool ref? not valid phase lock freq. lock irq 60 0309 s2 pin config ref? ref? lor ref? ool ref? not valid phase lock freq. lock irq e0 030a s3 pin config ref? ref? lor ref? ool ref? not valid phase lock freq. lock irq 08 030b s4 pin config ref? ref? lor ref? ool ref? not valid phase lock freq. lock irq 01 030c control enable refa lor enable refa ool enable refb lor enable refb ool enable phase lock det. enable freq. lock detector a2 030e ro n/a 030f ro n/a 0310 ro n/a 0311 ro n/a 0312 ro n/a 0313 ro hftw average or instantaneous ftw [47:0] (read-only) (an io_update is required to refresh these registers.) n/a 0314 m ff 0315 m 00 0316 m 00 0317 m phase lock phase lock threshold [31:0] 00
ad9549 preliminary technical data rev. prb | page 56 of 71 0318 m phase unlock watchdog timer [2:0] phase lock watchdog timer [4:0] ff 0319 m 00 031a m 00 031b m 00 031c m frequency lock threshold [31:0] 00 031d m frequency lock frequency unlock watchdog timer [2:0] frequency lock watchdog timer [4:0] ff 031e m ff 031f m refa lor divider [15:0] ff 0320 m ff 0321 m loss of reference refb lor divider [15:0] ff 0322 m 00 0323 m refa ool divider [15:0] 00 0324 m ff 0325 m ff 0326 m ff 0327 m refa ool upper limit [31:0] ff 0328 m 00 0329 m 00 032a m 00 032b m refa ool lower limit [31:0] 00 032c m 00 032d m refb ool divider [15:0] 00 032e m ff 032f m ff 0330 m reference out of limits refb ool upper limit [31:0] ff
preliminary technical data ad9549 rev. prb | page 57 of 71 0331 m ff 0332 m 00 0333 m 00 0334 m 00 0335 m refb ool lower limit [31:0] 00 0400 calibration (user accessible trim) 0400 00 0401 k divider k divider [15:0] 00 0402 m cpfd gain scale [2:0] 00 0403 m cpfd gain cpfd gain [5:0] 20 0404 fpfd gain fpfd gain [7:0] c8 0405 00 0406 00 0407 00 0408 reserved 00 0409 m dpll phase offset [7:0] 00 040a m pfd offset dpll phase offset [13:8] 00 040b dac full-scale current [7:0] ff 040c dac fs current dac full-scale current [9:8] 01 040d reserved 00 040e reserved 10 040f ref bias level dc input level [1:0] 00 0410 reserved 00
ad9549 preliminary technical data rev. prb | page 58 of 71 0500 harmonic spur reduction 0500 m hsr-a enable gain spur a harmonic [3:0] 00 0501 m spur a magnitude [7:0] 00 0502 m 00 0503 m spur a phase [7:0] 00 0504 m spur a spur a phase [8] 00 0505 m hsr-b enable gain spur b harmonic [3:0] 00 0506 m spur b magnitude [7:0] 00 0507 m 00 0508 m spur b phase [7:0] 00 0509 m spur b spur b phase [8] 00 types of registers: m: mirrored (also called buffered). this type of register needs an io_update for the new value to take effect.) ro: read-only ac: auto-clear
preliminary technical data ad9549 rev. prb | page 59 of 71 i/o register description serial port configuration (0000 C 0005) 0000; serial configuration; bits d4 C d7 are mirror image of d0 C d3 [0] sdo active: enables sdo pin 1=sdo pin enabled (fou r-wire serial port mode.) 0= three-wire mode. [1] lsb first: sets bit order for serial port. 1=lsb first. 0=msb first. io_update must occur in order to take effect. [2] soft reset: resets register map except for register 0000. setting this bit forces a soft reset, meaning that s1-s4 are not tri- stated, nor is their state read when this bit is cleared. the 9549 will assume the values of s1-s4 that were present during the last hard reset. this bit is not self-clearing, and all other registers will be restored to their default values after a soft reset. [3] long instruction: read-only: this part only supports long instructions. 0001; reserved 0002 - 0003; part id (read-only) 0004; serial options [0] read buffer register: for buffered registers, serial port re ad-back reads from actual (active) registers instead of the buf fer. 1= reads the buffered values that will take effect during the next io_update. 0= reads values that are currently in effect. 0005; serial options; self clearing [0] register update: software access to the register update pin function. writing a 1 to this bit is identical to performing an io_update. power down and reset 0010; power down and enables; power up default is defined by start-up pins. [0] digital pd; remove clock from most of digital section; leave serial port usable. in contrast to full pd, setting this bit does not de-bias inputs, allowing for quick wake-up. [1] full pd; setting this bit is identical to activating the pd pin, and puts all blocks (except serial port) into power down m ode. sysclk is turned off. [2] pd refb; power down reference clock b input (and related circuits) [3] pd refa; power down reference clock a input (and related circuits) [4] pd system clock pll: system clock multiplier is powered down. 1= system clock multiplier powered down. [5] enable output doubler; power up output clock generator do ubler. output doubler must still be enabled in register 0200. [6] enable cmos driver: power up cmos output driver. 1= cmos driver on. [7] pd hstl driver: power down hstl output driver. 1 = hstl driver powered down. 0011; reserved
ad9549 preliminary technical data rev. prb | page 60 of 71 0012; reset; auto clear; to reset the entire chip, the user may also use the (non-self clearing) soft reset bit in register 0000. except for irq reset, the user normally would not need to use these. however, if the user attempts to lock the loop for the fir st time when no signal is present, the user should write a 1 to bits 0-4 of this register prior to attempting to lock the loop aga in. [0] dds (direct digital synthesis) reset [1] cci (cascaded comb integrator) reset [2] lf (loop filter) reset [3] cpfd (coarse phase frequency detector) reset [4] fpfd (fine phase frequency detector) reset [5] irq reset: clear irq signal and irq status monitor [6] unused [7] history reset: setting this bit clears the ftw monitor and pipeline. 0013; reset (continued); not auto clear. [0] r divider reset: synchronous (to r divide r prescaler output) reset for integer divider [1] s divider reset: synchronous (to s divider prescaler output) reset for integer divider [2] r div2 reset: asynchronous reset for r prescaler [3] s div2 reset: asynchronous reset for s prescalar [7] pd fund dds: setting this bit powers down the dds fundamental output, but not the spurs. it is used during tuning of the spur killer circuit. system clock 0020; n divider [4:0] n divider: these bits set the feedback divider for system clock pll. there is a fixed /2 preceding this block, as well a s a an offset of 2 added to this value. therefore, setting this register to 00000 translates to an overall feedback divider ratio o f 4. see figure 29: block diagram of the sysclk pll on page 37. 0021; reserved 0022; pll parameters [1:0] charge pump current: 00: 250 ua , 01: 375 ua, 10: off, 11: 125 ua [2] vco range: select low range or high range vco. 0= low range (700 to 800 mhz). 1= high range (850 to 1000 mhz). for system clock settings in between 800-850 mhz, use the vco auto range (bit 7) to set the correct vco range automatically. [3] 2x reference: enables a frequency doubler prior to the sysclk pll and can be useful in reducing jitter induced by the syscl k pll. see figure 28: system clock generator block diagram, page 37. [4:6] reserved [7] vco auto range: automatic vco range selection. enabling this bit allows bit 2 of this register to be set automatically.
preliminary technical data ad9549 rev. prb | page 61 of 71 0023; pfd divider [3:0] divide ratio for pfd clock from system clock. this is typically varied only in cases where the designer wishes to run the dpll phase detector fast while sysclk is run relatively slowly. the ratio is equal to pfd divider * 4. for a 1 ghz system clock , the adc runs at 1 ghz / 20 = 50 mhz, and the dpll phase detector runs at half this speed , which in this case is 25 mhz). digital pll control and dividers 0100; pll control [0] close loop: setting this bit closes the loop. if bit 4 of this register is cleared, then the frequency estimator will be us ed. if this bit is cleared and the loop is opened, the user should reset the cci and lf bits of register 0012 prior to closing the loop aga in. [1] loop polarity: this bit reverses the polarity of the loop response. [2] unused [3] enable frequency slew limiter: this bit enables the frequency slew limiter that controls how fast the tuning word can change, and is useful for avoiding runt and stretched pulses during clock switchover and holdover transitions. these values are set in registers 0127-012c. see frequency slew limiter on page 40. [4] disable frequency estimator. the frequency estimator is no rmally not used, but is useful when the input frequency is unknown, or needs to be qualified. this estimate appears in registers 115-11a. the frequency estimator is not needed when ftw0 (register 01a6-01ab) is programmed. see frequency estimator on page 41. [5] single tone mode: setting this bit allows the 9549 to output a tone open loop using ftw0 as dds tuning word. this bit must be cleared when bit 0 (close loop) is set. this is very useful in debugging when the signal coming into the ad9549 is questionable or nonexistent. [7:6] reserved 0101 C 0102; r divider (dpll feedforward divider) [15:0] feedforward divider (also called th e reference divider) of the dpll. divide ratio: 1 C 65536. see feedforward divider (divide-by-r) on page 20. if the desired feedfeedforward ratio is greater than 65536, or if the reference input signal on ref_ a or ref_b is greater than 400 mhz, then bit 0, r103 must be set. 0103; r divider (continued) [0] divide by 2: setting this bit enables an additional /2 pre-scalar, effectively doubling the range of the feedforward divide r. if the desired feedfeedforward ratio is greater than 65536, or if th e reference input signal on ref_a or ref_b is greater than 400 mhz, then this bit must be set. [6:1] unused [7] falling edge triggered: setting this bit inverts the reference clock before r divider. 0104 C 0105; s divider (dpll feedback divider) [15:0] feedback divider: divide ratio: 1 C 65536. if the desired feedback ratio is gr eater than 65536, or if the feedback signa l on fdbk_in is greater than 400 mhz, then bit 0, r106 must be set.
ad9549 preliminary technical data rev. prb | page 62 of 71 0106; s divider (continued) [0] divide by 2: setting this bit enables an additional /2 pre- scalar. see feedback divider (div ide-by-s) on page 20. if the desired feedback ratio is greate r than 65536, or if the feedback signal on fdbk_i n is greater than 400 mhz, then this bit must be set. an example of this case is when the pll is locking to an image of the dac output that is above the nyquist frequency. [6:1] unused [7] falling edge triggered: setting this bit inverts the reference clock before the s divider. digital pll loop filter 0107; p divider [4:0] divide ratio: controls the ratio of dac sample rate to loop filter sample rate. see digital loop filter on page 21. loop filter sample rate = dac sample rate / 2^(divide rati o[4:0]). for the default case of 1 ghz dac sample rate, and p divider [4:0] of 5, the loop filter sample rate is 31.25 mhz. note: the dac sample rate is the same as system clock. 0108 C 0109; loop coefficients (see digital loop filter coefficients on page 25.) (note : the ad9549 evaluation software will derive these values.) [11:0] alpha-0: linear coefficient for alpha coefficient 010a; loop coefficients (continued) [4:0] alpha-1: power of 2 multiplier for alpha coefficient 010b; loop coefficients (continued) [3:0] alpha-2: power of 2 divider for alpha coefficient 010c C 010d; loop coefficients (continued) [11:0] beta-0: linear coefficient for beta coefficient 010e; loop coefficients (continued) [2:0] beta-1: power of 2 divider for beta coefficient 010f C 0110; loop coefficients (continued) [11:0] gamma-0: linear coefficient for gamma coefficient 0111; loop coefficients (continued) [2:0] gamma -1: power of 2 divider for gamma coefficient 0112 C 0114; reserved 0115 C 011a; ftw estimate (read-only) [47:0] ftw estimate: this is frequency estimate from frequency estimator circuit, and is informational only. its useful for verifying the input reference frequency. see frequency estimator on page 41 for a description. 011b C 0120; ftw lower limit [47:0] ftw lower limit: lowest dds tuning word in closed loop mode. this feature is recommended when a bandpass reconstruction filter is used. see output frequency range control on page 34.
preliminary technical data ad9549 rev. prb | page 63 of 71 0121 C 0126; ftw upper limit [47:0] ftw upper limit: highest dds tuning word in closed loop mode. this feature is recommended when a bandpass reconstruction filter is used. see output frequency range control on page 34. 0127 C 012c; frequency slew limit [47:0] frequency slew limit: see frequency slew limiter on page 40. 012d C 0130; reserved free-run (single-tone) mode 01a0 C 01a5; reserved 01a6 C 01ab; ftw0 [47:0] ftw0: ftw (frequency tuning word) for dds when loop is not closed (see register 0100 bit 0) also used as the initial frequency estimate when the estimator is disabled (see register 0100 bit 4) note: the power up default is defined by startup pins s1-s4. see default dds output frequency on power-up on page 43. 01ac C 01ad; phase [15:0] dds phase word: allows user to vary the phase of the dds output. active only when loop is not closed. reference selector / holdover 01c0; automatic control [0] automatic holdover: setting this bit permits state-machine to enter holdover (free-run) mode. [1] automatic recover: setting this bit permits state-machine to leave holdover mode. [2] automatic selector: setting this bit permits state-machine to switch the active reference clock input. [3] reserved [4] holdover mode: this bit determines which frequency tuning word (ftw) is used in holdover mode. 0: use last ftw at time of holdover. 1: use averaged ftw at time of holdover, which is the recommended setting. the number of averages used is set in register 01c2. 01c1; override [0] holdover on/off: this bit controls the status of holdover when bit 1 of this register is set. [1] enable holdover override: setting this bit disables automatic holdover, and allows user to enter/exit holdover manually via bit 0 (see above). setting this bit overrides the holdover pin. [2] ref_ab: this bit selects the input when bit 3 of this register is set. 0 equals ref_a. [3] enable ref input override: setting this bit disables automatic reference switchover, and allows user to switch references manually via bit 2 of this register. setting this bit overrides the refselect pin. [4] enable line-card mode: enables line-card mode of reference switch mux, which eliminates the possibility of a runt pulse during switchover. see use of line card mode to eliminate runt pulses on page 31.
ad9549 preliminary technical data rev. prb | page 64 of 71 01c2; averaging window [3:0] ftw windowed average size: this register sets the number of ftws (frequency tuning words) that are used for calculating the average ftw. bit 4 in register 01c0 enables this feature. an average size of at least 32000 is recommended for most applications. the number of averages equals 2 (ftw windowed average size [3:0]) . these samples are taken at the rate of (fs / 2^p io ). 01c3; reference validation [4:0] validation timer: the value in this register sets the time required to validate a reference after a lor or ool event befo re the reference can be used as the dpll reference. this circuit uses the digital loop filter clock (see register 0107). validation time = loop filter clock period * 2 (validation timer[4:0] +1) -1. assuming power-on defaults, the recovery time varies from 32 ns (00000) to 137 sec (11111). if longer validation times are re quired, the user can make the p divider larger. the user sho uld be careful to set the validation timer to at least two periods of the ool evaluation period. the ool evaluation period is is th e period of reference input clock times the ool divider (r0322-0323). [6:5] unused doubler and output drivers 0200; hstl driver [2:0] hstl output doubler: 01: doubler disabled. 00: doubler enabled. [3:2] unused [4] opol: output polarity: setting this bit inverts the hstl driver output polarity. 0201; cmos driver [0] user mux control: this bit allows the user to select whether the cmos driver output is divided by the s divider. 0: s divider input sent to cmos driver. 1: s divider output sent to cmos driver. see figure 8: detailed block diagram on page 19.
preliminary technical data ad9549 rev. prb | page 65 of 71 monitor 0300; status: this register contains the status of the chip. this register is read-only and live update. [0] frequency lock detect: this flag indicates that the frequency lock detect circuit has detected frequency lock. this feature compares the absolute value of the difference of two consecutive phase detector edges against a programmable threshold. because of this, frequency lock detect is more rigorous than phase lock detect, and it is possible to have phase lock detect without frequency lock detect. [1] phase lock detect: this flag indicates that the phase lock detect circuit has detected phase lock. the amount of phase adjustment is compared against a programmable threshold. note: this bit may be set in single tone and holdover modes, and should be ignored in these cases. [2] free run: dpll is in holdover mode (free-run) [3] reference selected: 0: reference a is active. 1: reference b is active. [4] frequency estimator done: true when the frequency estimator circuit has successfully estimated the input frequency. see frequency estimator on page 41. [5] pfd frequency too low: this flag indicates that the frequency estimator failed and detected too low of a pfd frequency. this bit is only relevant if the user is relying on the frequency estimator to determine the input frequency. [6] pfd frequency too high: this flag indicates that the frequency estimator failed and detected too high of a pfd frequency. this bit is only relevant if the user is relying on the frequency estimator to determine the input frequency. [7] unused 0301; status (continued): this register contains the status of the chip. this register is read-only and live update. [0] refb ool: the ool (out of limits) circuit has determined that reference b is out of limits. [1] refb lor: a lor (loss of reference) has occurred on reference b. [2] refb valid: the reference validation circuit has successfully determined that reference b is valid. [3] unused [4] refa ool: the ool (out of limits) circuit has determined that reference a is out of limits. [5] refa lor: a lor (loss of reference) has occurred on reference a. [6] refa valid: the reference validation circuit has successfully determined that reference a is valid. [7] unused 0302 C 0303; irq status; these registers contain the chip status (registers 0300 C 0301) at the time of irq. these bits are cleared with an irq reset (see register 0012, bit 5). 0304; irq mask [0] enter free run: trigger irq when dpll enters free-running (holdover) mode. [1] leave free run: trigger irq when dpll leaves free-running (holdover) mode [2] reference changed: trigger irq when active reference clock selection changes [7:3] unused
ad9549 preliminary technical data rev. prb | page 66 of 71 0305; irq mask (continued) [0] frequency lock: trigger irq on rising edge of frequency lock signal [1] frequency unlock: trigger irq on falling edge of frequency lock signal [2] phase lock: trigger irq on rising edge of phase lock signal [3] phase unlock: trigger irq on falling edge of phase lock signal [4] frequency estimator done: trigger irq when the frequency estimator is done 0306; irq mask (continued) [0] !refa ool: trigger irq on falling edge of reference as ool [1] refa ool: trigger irq on rising edge of reference as ool [2] !refa lor: trigger irq on falling edge of reference as lor [3] refa lor: trigger irq on rising edge of reference as lor [4] !refa valid: trigger irq on falling edge of reference as valid [5] refa valid: trigger irq on rising edge of reference as valid [7:6] unused 0307; irq mask (continued) [0] !refb ool: trigger irq on falling edge of reference bs ool [1] refb ool: trigger irq on rising edge of reference bs ool [2] !refb lor: trigger irq on falling edge of reference bs lor [3] refb lor: trigger irq on rising edge of reference bs lor [4] !refb valid: trigger irq on falling edge of reference bs valid [5] refb valid: trigger irq on rising edge of reference bs valid [7:6] unused
preliminary technical data ad9549 rev. prb | page 67 of 71 0308; s1 pin configuration (see status and warnings on page 42.) note: the choice of input for a given pin must be all ref a or all ref b, and not a combination thereof. [0] irq: select irq signal for output on this pin [1] reserved [2] frequency lock: select frequency lock signal for output on this pin [3] phase lock: select phase lock signal for output on this pin [4] ref? not valid: select either refa (0) or refb (1) not valid signal for output on this pin [5] ref? ool: select either refa (0) or refb (1) ool signal for output on this pin [6] ref?: lor: select either refa (0) or refb (1) lor signal for output on this pin [7] ref?: choose either refa (0) or refb (1) for use with bits 4 C 6 0309; s2 pin configuration: same as re gister 0308, except applies to pin s2 030a; s3 pin configuration: same as re gister 0308, except applies to pin s3 030b; s4 pin configuration: same as re gister 0308, except applies to pin s4 030c; control [0] enable frequency lock detector. register 0319 must be set up to use this. see frequency lock detection on page 28. [1] enable phase lock detector: register 0314h-0318h must be se t up to use this. see phase lock detection on page 27. [3:2] unused [4] enable refb ool: the refb ool limits are set up in registers 032c to 0335. [5] enable refb lor: the refa lor limits are set up in registers 0320 to 0321. [6] enable refa ool: the refb ool limits are set up in registers 0322 to 032b. [7] enable refa lor: the refb lor limits are set up in registers 031e to 031f. 030d; unused 030e C 0313; hftw; read-only [47:0] average or instantaneous ftw: this read-only register is the output of ftw monitor. average or instantaneous is determined by holdover mode (see bit 4, register 01c0). these registers must be manually refreshed by issuing an io_update. 0314 C 0317; phase lock [31:0] phase lock threshold: see phase lock detection on page 27. 0318; phase lock (continued) [7:5] phase unlock watchdog timer : see phase lock detection on page 27. [4:0] phase lock watchdog timer : see phase lock detection on page 27.
ad9549 preliminary technical data rev. prb | page 68 of 71 0319 C 031c; frequency lock [31:0] frequency lock threshold: see frequency lock detection on page 28. 031d; frequency lock (continued) [7:5] frequency unlock watchdog timer: see frequency lock detection on page 28. [4:0] frequency lock watchdog timer: see frequency lock detection on page 28. 031e C 031f; loss of reference [15:0] refa lor divider: see loss of reference on page 29. 0320 C 0321; loss of reference (continued) [15:0] refb lor divider: see loss of reference on page 29. 0322 C 0323; reference out of limits (ool) [15:0] refa ool divider: see reference frequency monitor on page 29. r0322 is the lsb, and r0323 is the msb. 0324 C 0327; reference ool (continued) [31:0] refa ool upper limit: see reference frequency monitor on page 29. 0328 C 032b; reference ool (continued) [31:0] refa ool lower limit: see reference frequency monitor on page 29. 032c C 032d; reference ool (continued) [15:0] refb ool divider: see reference frequency monitor on page 29. r032c is the lsb, and r032d is the msb. 032e C 0331; reference ool (continued) [31:0] refb ool upper limit: see reference frequency monitor on page 29. 0332 C 0335; reference ool (continued) [31:0] refb ool lower limit: see reference frequency monitor on page 29. calibration (user accessible trim) 0400 C 0401; k divider [15:0] k divider: the k divider alters precision of frequency estimator circuit. see frequency estimator on page 41. 0402; cpfd gain [2:0] cpfd gain scale: this register is the coarse phase frequency power of 2 multiplier (pds). see phase detector on page 24. note that the correct value for this register will be calculated by filter design software provided with the evaluati on board. 0403; cpfd gain (continued) [5:0] cpfd gain: this register is the coarse phase frequency linear multiplier (pdg). see phase detector on page 24. note that the correct value for this register will be calculated by filter design software provided with the evaluation board.
preliminary technical data ad9549 rev. prb | page 69 of 71 0404; fpfd gain [7:0] fpfd gain: this register is the fine phase frequency dete ctor linear multiplier (alters charge-pump current). see fine phase detector on page 24. note that the correct value for this register will be calculated by filter design software provided with the evaluation board. 0405 C 0408; unused 0409 C 040a; pfd offset [13:0] dpll phase offset: this register controls the static time offset of the pfd (phase frequency detector) in closed-loop mode. it has no effect when the dpll is open. 040b; dac full-scale current: [7:0] dac full-scale current: dac full-scale current [7:0]. see dac output on page 23. 040c; dac full-scale current [1:0] dac full-scale current: dac full-s cale current [9:8]. see register 040b. 040d C 040e; unused 040f; reference bias level [1:0] dc input level for vddx @ 3.3 v: this register sets the dc bias level for the reference inputs. the value should be chose n such that vih is as close as possible to (but not exceeding) 3.3v. 00: vdd3 C 800 mv 01: vdd3 C 400 mv 10: vdd3 C 1.6 v 11: vdd3 C 1.2 v [7:2] reserved 0410; unused
ad9549 preliminary technical data rev. prb | page 70 of 71 harmonic spur reduction 0500; spur a: see harmonic spur reduction on page 70. [3:0] spur a harmonic 1 C 15 [5:4] unused [6] amplitude gain x2 [7] harmonic spur reduction a enable (hsr-a enable) 0501 C 0502; spur a (continued) [7:0] spur a magnitude: linear multiplier for spur a magnitude 0503 C 0504; spur a (continued) [8:0] spur a phase: linear offset for spur a phase 0505; spur b [3:0] spur b harmonic: 1 C 15 [5:4] unused [6] amplitude gain x2 [7] harmonic spur reduction b enable (hsr-b enable) 0506 C 0507; spur b (continued) [7:0] spur b magnitude: linear multiplier for spur b magnitude 0508 C 0509; spur b (continued) [8:0] spur b phase: linear offset for spur b phase
preliminary technical data ad9549 outline dimensions pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.45 0.40 0.35 0.50 bsc 0.20ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max 4.85 4.70 sq * 4.55 seating plane pin 1 indicato r exposed pad (bottom view) 0.30 0.25 0.18 a 64-lead lead frame chip scale package [lfcsp] 9 x 9 mm body (cp-64-1) dimensions shown in millimeters * compliant to jedec standards mo-220-vmmd except for exposed pad dimension figure 45: outline dimensions ordering guide model temperature range package description package option ad9549bcpz 1 (when released) -40 to +85 64-lead lfcsp AD9549XCPZ 1 (prototypes) -40 to +85 64-lead lfcsp 1 z = pb-free part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr06744-0-5/07(prb)

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