1 ? fn6279.0 isl97536 monolithic 1a step-down regulator with low quiescent current the isl97536 is a synchronous, integrated fet 1a step-down regulator with internal compensation. it operates with an input voltage range from 2.5v to 6v, which accommodates supplies of 3.3v , 5v, or a li-ion battery source. the output can be externally set from 0.8v to v in with a resistive divider. the isl97536 features pwm control with a 1.4mhz typical switching frequency. the typical no load quiescent current is only 500a. additional features include a 100ms power-on- reset output, <1a shutdown current, short-circuit protection, and over-temperature protection. the isl97536 is available in the 10 ld msop package, making the entire converter occupy less than 0.15in 2 of pcb area with components on one side only. the 10 ld msop package is specified for operation over the full -40c to +85c temperature range. features ? less than 0.15in 2 footprint for the complete 1a converter ? components on one side of pcb ? max height 1.1mm msop10 ? 100ms power-on-reset output (por) ? internally-compensated voltage mode controller ? up to 95% efficiency ? <1a shutdown current ? 500a quiescent current ? hiccup mode overcurrent and over-temperature protection ? pb-free plus anneal available (rohs compliant) applications ? pda and pocket pc computers ? bar code readers ? cellular phones ? portable test equipment ? li-ion battery powered devices ? small form factor (sfp) modules pinout and typical a pplication diagram isl97536 (10 ld msop) top view ordering information part number part marking tape & reel package pkg. dwg. # ISL97536IUZ (note) 7536z - 10 ld msop (pb-free) mdp0043 ISL97536IUZ-tk (note) 7536z 13? (1k pcs) 10 ld msop (pb-free) mdp0043 ISL97536IUZ-t (note) 7536z 13? (2.5k pcs) 10 ld msop (pb-free) mdp0043 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. * v o = 0.8v * (1 + r 1 /r 2 ) 1 2 3 4 10 9 8 7 5 6 sgnd fb vdd rsi vin en lx por pgnd vo 1.8h v o (1.8v@600ma) c 1 por r 1 * r 2 * 124k ? 100k ? en rsi 100k ? c 2 v s (2.5v-6v) 100k ? r 4 r 5 10f 10f l 1 r 6 100k ? 0.1f r 3 100 ? c 3 c 4 470pf data sheet october 5, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6279.0 october 5, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute m aximum ratings (t a = +25c) thermal information v in , v dd , pg to sgnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v lx to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (v in + +0.3v) sync, en, v o , fb to sgnd . . . . . . . . . . . . . -0.3v to (v in + +0.3v) pgnd to sgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a thermal resistance (typical, note 1) ja (c/w) msop10 package . . . . . . . . . . . . . . . . . . . . . . . . . . 130 operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications v dd = v in = v en = 3.3v, c1 = c2 = 10f, l = 1.8h, v o = 1.8v (as shown in typical application diagram), t a = -40c to +85c unless otherwise specified. parameter description conditions min typ max unit dc characteristics v fb feedback input voltage 790 800 810 mv i fb feedback input current 250 na v in , v dd input voltage 2.5 6 v v in,off minimum voltage for shutdown v in falling, t a = +25c only 2 2.2 v v in,on maximum voltage for start-up v in rising, t a = +25c only 2.2 2.4 v i dd supply current v in = v dd = 5v 400 500 a en = 0, v in = v dd = 5v 0.1 3 a r ds(on)-pmos pmos fet resistance v dd = 5v, t a = +25c 70 m ? r ds(on)-nmos nmos fet resistance v dd = 5v, t a = +25c 45 m ? i lmax current limit 1.5 a t ot,off over-temperature threshold t rising 145 c t ot,on over-temperature hysteresis t falling 130 c i en , i rsi en, rsi current v en , v rsi = 0v and 3.3v -1 1 a v en1 , v rsi1 en, rsi rising threshold v dd = 3.3v 2.4 v v en2 , v rsi2 en, rsi falling threshold v dd = 3.3v 0.8 v v por minimum v fb for por, wrt targeted v fb value v fb rising 95 % v fb falling 86 % v olpor por voltage drop i sink = 3.3ma 35 70 mv ac characteristics f pwm pwm switching frequency 1.25 1.4 1.6 mhz t rsi minimum rsi pulse width guaranteed by design 25 50 ns t ss soft-start time 650 s t por power on reset delay time 80 100 120 ms isl97536
3 fn6279.0 october 5, 2006 block diagram pin descriptions pin number pin name pin function 1 sgnd negative supply for the controller stage 2 pgnd negative supply for the power stage 3 lx inductor drive pin; high current digital output with average voltage equal to the regulator output voltage 4 vin positive supply for the power stage 5 vdd power supply for the controller stage 6 rsi resets por timer 7 en enable 8 por power on reset open drain output 9 vo output voltage sense 10 fb voltage feedback input; connected to an external resistor divider between v o and sgnd for variable output - + - + - + - + - + control logic pfm on-time control pwm compen- sation ramp genera- tor under- voltage lockout por clock soft- start bandgap reference temperature sense + ? v in lx pgnd por v o fb en v dd sgnd 10pf 5m 124k 100k 10f 5v en pwm comparator pwm comparator synchronous rectifier n-driver p-driver current sense inductor short 1.8h 10f 100k por 1.8v 0 to 1a 100 ? 0.1f 470pf c4 rsi isl97536
4 fn6279.0 october 5, 2006 performance curves and waveforms all waveforms are taken at v in = 3.3v, v o = 1.8v, i o = 600ma with component values shown on page 1 at room ambient temperature, unless otherwise noted. figure 1. efficiency vs i o at 5v v in figure 2. efficiency vs i o at 3.3v figure 3. load regulation vs i o at 5v v in figure 4. load regulation vs i o at 3.3v v in figure 5. line regulation vs v in figure 6. no load quiescent current 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 i o (ma) effeciency (%) v o = 1.2v v o = 1.8v v o = 2.5v v o = 3.3v 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 i o (ma) effeciency (%) v o = 1.2v v o = 1.8v v o = 2.5v -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 200.2 400.2 600.2 800.2 1000.2 1200.2 i o (ma) load regulation (%) v o = 1.2v v o = 1.8v v o = 2.5v v o = 3.3v -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0 200 400 600 800 1000 1200 i o (ma) load regulation (%) v o = 1.2v v o = 1.8v v o = 2.5v -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 v in (v) line regulation (%) v o = 1.2v v o = 1.8v 23456 0 2 4 6 8 10 12 2.5 3 3.5 44.55 v s (v) i s (ma) isl97536
5 fn6279.0 october 5, 2006 figure 7. start-up at i o = 600ma figure 8. pwm steady-state operation (i o = 600ma) figure 9. external synchronization to 2mhz figure 10. external synchronization to 12mhz figure 11. load transient response (22ma to 600ma) figure 12. load transient response (30ma to 600ma) performance curves and waveforms (continued) all waveforms are taken at v in = 3.3v, v o = 1.8v, i o = 600ma with component values shown on page 1 at room ambient temperature, unless otherwise noted. v out v in i in 0.5s/div lx (2v/div) i l (0.5a/div) ? v o (10mv/div) sync (2v/div) lx (2v/div) 0.2s/div i l (0.5a/div) 20ns/div sync (2v/div) lx (2v/div) i l (0.5a/div) 100s/div i o (200ma/div) ? v o (100mv/div) 50s/div i o (200ma/div) ? v o (100mv/div) isl97536
6 fn6279.0 october 5, 2006 figure 13. efficiency vs i o figure 14. load regulation figure 15. line regulation @ 500ma figure 16. overcurrent shutdown figure 17. overcurrent hiccup mode performance curves and waveforms (continued) all waveforms are taken at v in = 3.3v, v o = 1.8v, i o = 600ma with component values shown on page 1 at room ambient temperature, unless otherwise noted. 0 200 400 600 800 1k 1.2k i o (ma) 100 80 60 40 20 0 efficiency (%) 12mhz 1.4mhz 5mhz 0 200 400 600 800 1k 1.2k i o (ma) 1 0.6 0.2 0 -0.2 -0.6 v o changes (%) 5mhz 12mhz 1.4mhz 0 200 400 600 800 1k 1.2k v in (v) 0.5 0.3 0.1 -0.1 -0.3 -0.5 v o changes (%) 5mhz 12mhz 1.4mhz pg i l v o pg i l v o isl97536
7 fn6279.0 october 5, 2006 applications information product description the isl97536 is a synchronous, integrated fet 1a step-down regulator which operates from an input of 2.5v to 6v. the output voltage is user-adjustable with a pair of external resistors. the internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 1a dc:dc converter. pwm operation in pwm switching mode, the p-channel mosfet and n-channel mosfet always operate complementary. when the p-channel mosfet is on and the n-channel mosfet off, the inductor current increases linearly. the input energy is transferred to the output and also stored in the inductor. when the p-channel mosfet is off and the n-channel mosfet on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. hence, the average current through the inductor is the output current. since the inductor and the output capacitor act as a low pass filter, the duty cycle ra tio is approximately equal to v o divided by v in . the output lc filter has a second order effect. to maintain the stability of the converter, the overall controller must be compensated. this is done with the fixed internally compensated error amplifier and the pwm compensator. because the compensations are fixed, the values of input and output capacitors are 10f to 40f ceramic and inductor is 1.5h to 2.2h. start-up and shutdown when the en pin is tied to v in , and v in reaches approximately 2.4v, the regulator begins to switch. the inductor current limit is gradually increased to ensure proper soft-start operation. when the en pin is connected to a logic low, the isl97536 is in the shutdown mode. all the control circuitry and both mosfets are off, and v out falls to zero. in this mode, the total input current is less than 1a. when the en reaches logic hi, the regulator repeats the start-up procedure, including the soft-start function. current limit and short-circuit protection the current limit is set at about 1.5a for the pmos. when a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop as load demand increases. when the output voltage drops 30mv below the reference voltage, the converter will shutdown for a period of time, approximated by equation 1, and then restart. if the overcurrent condition still exists , it will repeat the shutdown- wait-restart event. this is called a ?hiccup? event. the average power dissipation is reduced, thereby reducing the likelihood of damage current and thermal conditions in the ic. thermal shutdown once the junction reaches about 145c, the regulator shuts down. both the p-channel and the n-channel mosfets turn off. the output voltage will drop to zero. with the output mosfets turned off, the regulator will cool down. once the junction temperature drops to ab out 130c, the regulator will perform a normal restart. thermal performance the isl97536 is available in a fused-lead msop10. compared with regular msop10 package, the fused-lead package provides lower thermal resistance. the ja is +100c/w on a 4-layer board and +125c/w on 2-layer board. maximizing the copper area around the pins will further improve the thermal performance. rsi/por function when powering up, the open-collector power-on-reset output holds low for about 100ms after v o reaches the preset voltage. when the active-hi reset signal rsi is issued, por goes to low immediately and holds for the same period of time after rsi comes back to low. the output voltage is unaffected. (please refer to the timing diagram). when the function is not used, connect rsi to ground and leave open the pull-up resister r 4 at por pin. the por output also serves as a 100ms delayed power good signal when the pull-up resister r 4 is installed. the rsi pin needs to be directly (or indirectly through a resister r 6 ) connected to ground for this to function properly. output voltage selection users can set the output voltage of the variable version with a resister divider, which can be chosen based on the following formula: thiccup 700 v in ? 3 --------------------------- - 216 + ?? ?? (eq. 1) 100ms min 25ns 100ms por rsi v o figure 18. rsi and por timing diagram v o 0.8 1 r 2 r 1 ------ - + ?? ?? ?? = (eq. 2) isl97536
8 fn6279.0 october 5, 2006 component selection because of the fixed internal compensation, the component choice is relatively narrow. for a regulator with fixed output voltage, only two capacitors and one inductor are required. capacitors must be chosen in the range of 10f to 40f, multilayer ceramic capacitors with x5r or x7r rating for both the input and output capacitors, and inductors in the range of 1.5h to 2.2h. the rms current present at the input capacitor is decided by the following formula: this is about half of the output current i o for all the v o . this input capacitor must be able to handle this current. the inductor peak-to-peak ripple current is given as: l is the inductance f s the switching frequency (nominally 1.4mhz) the inductor must be able to handle i o for the rms load current, and to assure that the inductor is reliable, it must handle the 2a surge current that can occur during a current limit condition. in addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor c 4 (refer to the typical applicat ion diagram). the phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. as a general rule of thumb, c 4 should be sized to start the phase- lead at a frequency of ~2.5khz. the zero will always appear at lower frequency than the pole and follow the equation below: over a normal range of r 2 (~10-100k), c 4 will range from ~470-4700pf. the pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of r 1 and r 2 , which is solely determined by the desired output set point. the equation below shows the pole frequency relationship: layout considerations the layout is very important for the converter to function properly. the following pc layout guidelines should be followed: 1. separate the power ground ( ) and signal ground ( ); connect them only at one point right at the pins 2. place the input capacitor as close to v in and pgnd pins as possible 3. make the following pc traces as small as possible: - from lx pin to l - from c o to pgnd 4. if used, connect the trace from the fb pin to r 1 and r 2 as close as possible 5. maximize the copper area around the pgnd pin 6. place several via holes under the chip to additional ground plane to improve heat dissipation the demo board is a good example of layout based on this outline. please refer to the isl97536 application brief. i inrms v o v in v o ? () v in ----------------------------------------------- i o = (eq. 3) ? i il v in ( v o ) v o ? lv in f s -------------------------------------------- = (eq. 4) f z 1 2 r 2 c 4 ---------------------- = (eq. 5) f p 1 2 r 1 r 2 () c 4 --------------------------------------- = (eq. 6) isl97536
9 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6279.0 october 5, 2006 isl97536 mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3 3 gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol msop8 msop10 tolerance notes a1.101.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c0.180.18 0.05 - d 3.00 3.00 0.10 1, 3 e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. c 6/99 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
|
