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? 2012 microchip technology inc. ds25135a-page 1 features ? single voltage read and write operations - 2.3-3.6v ? serial interface architecture - spi compatible: mode 0 and mode 3 ? high speed clock frequency - 80 mhz (2.7-3.6v operation) - 50 mhz (2.3-2.7v operation) ? superior reliability - endurance: 100,000 cycles (typical) - greater than 100 years data retention ? low power consumption: - active read current: 10 ma (typical) - standby current: 5 a (typical) ? flexible erase capability - uniform 4 kbyte sectors - uniform 32 kbyte overlay blocks - uniform 64 kbyte overlay blocks ? fast erase and byte-program: - chip-erase time: 35 ms (typical) - sector-/block-erase time: 18 ms (typical) - byte-program time: 7 s (typical) ? auto address increment (aai) programming - decrease total chip programming time over byte-program operations ? end-of-write detection - software polling the busy bit in status register - busy status readout on so pin in aai mode ? hold pin (hold#) - suspends a serial sequence to the memory without deselecting the device ? write protection (wp#) - enables/disables the lock-down function of the status register ? software write protection - write protection through block-protection bits in status register ? temperature range - commercial: 0c to +70c ? packages available - 8-lead soic (150 mils) - 8-contact wson (6mm x 5mm) - 8-contact uson (3mm x 2mm) ? all non-pb (lead-free) devices are rohs compliant product description the 25 series serial flash family features a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ulti- mately lowers total system costs. the sst25pf020b devices are enhanced with improved operating fre- quency and even lower power consumption. sst25pf020b spi serial flash memories are manu- factured with proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst25pf020b devices significantly improve per- formance and reliability, while lowering power con- sumption. the devices write (p rogram or erase) with a single power supply of 2.3-3.6v for sst25pf020b. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or pro- gram operation is less than alternative flash memory technologies. the sst25pf020b device is offered in 8-lead soic (150 mils), 8-contact wson (6mm x 5mm), and 8-con- tact uson (3mm x 2mm) packages. see figure 2-1 for pin assignments. sst25pf020b 2 mbit 2.3-3.6v spi serial flash
sst25pf020b ds25135a-page 2 ? 2012 microchip technology inc. 1.0 functional block diagram figure 1-1: functional block diagram 25135 b1.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface
? 2012 microchip technology inc. ds25135a-page 3 sst25pf020b 2.0 pin description figure 2-1: pin assignments table 2-1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addr esses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. outputs flash busy status during aai programming when reconfigured as ry/by# pin. see ?hardware end-of-write detection? on page 11 for details. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. hold# hold to temporarily stop serial communicat ion with spi flash memory without resetting the device. v dd power supply to provide power supply voltage: 2.3-3.6v for sst25pf020b v ss ground 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd hold# sck si top view 25135 08-soic s2a p1.0 8-lead soic 1 2 3 4 8 7 6 5 ce# so wp# v ss top view v dd hold# sck si 25135 08-wson qa p2.0 8-contact wson 1 2 3 4 8 7 6 5 ce# so wp# v ss top vie w v dd hold# sck si 25135 08-uson q3a p1.0 8-contact uson
sst25pf020b ds25135a-page 4 ? 2012 microchip technology inc. 3.0 memory organization the sst25pf020b superflash memory array is orga- nized in uniform 4 kbyte erasable sectors with 32 kbyte overlay blocks and 64 kbyte overlay erasable blocks. 4.0 device operation the sst25pf020b is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), se rial data output (so), and serial clock (sck). the sst25pf020b supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 4-1 , is the state of the sck signal when the bus master is in standby mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sam- pled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 4-1: spi protocol 4.1 hold operation the hold# pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signal?s rising edge coincides with the sck active low state. if the falling edge of the hold# signal does not coin- cide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reaches the active low state. see figure 4-2 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven high during a hold condition, the device returns to standby mode. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 4-2 for hold timing. figure 4-2: hold condition waveform 25135 spiprot.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb active hold active hold active 25135 holdcond.0 sck hold#
? 2012 microchip technology inc. ds25135a-page 5 sst25pf020b 4.2 write protection sst25pf020b provides software write protection. the write protect pin (wp#) enables or disables the lock- down function of the status register. the block-protec- tion bits (bp1, bp0, and bpl) in the status register, and the top/bottom sector protection status bits (tsp and bsp) in status register 1, provide write protection to the memory array and the status register. see table 4- 4 for the block-protection description. 4.2.1 write protect pin (wp#) the write protect (wp#) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp# is driven low, t he execution of the write- status-register (wrsr) instruction is determined by the value of the bpl bit (see table 4-1 ). when wp# is high, the lock-down function of the bpl bit is disabled. 4.3 status register the software status register provides status on whether the flash memory array is available for any read or write operation, w hether the device is write enabled, and the state of t he memory write protection. during an internal erase or program operation, the sta- tus register may be read only to determine the comple- tion of an operation in progress. table 4-2 describes the function of each bit in t he software status register. table 4-1: conditions to execute write- status-register (wrsr) instruction wp# bpl execute wrsr instruction l1 not allowed l0 allowed hx allowed table 4-2: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicates current level of block write protection (see table 4-4 ) 1r / w 3 bp1 indicates current level of block write protection (see table 4-4 ) 1r / w 4:5 res reserved for future use 0n / a 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp1, bp0 are read-only bits 0 = bp1, bp0 are read/writable 0r / w
sst25pf020b ds25135a-page 6 ? 2012 microchip technology inc. 4.4 software status register 1 the software status register 1 is an additional register that contains top sector and bottom sector protection bits. these register bits are read/writable and determine the lock and unlock status of the top and bottom sectors. table 4-3 describes the function of each bit in the software status register 1. 4.4.1 busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. 4.4.2 write enable latch (wel) the write-enable-latch bit indicates the status of the internal memory write enable latch. if the write- enable-latch bit is set to ?1 ?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/erase) commands. the write-enable-latch bit is automatically reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? byte-program inst ruction completion ? auto address increment (aai) programming is completed or reached its highest unprotected memory address ? sector-erase inst ruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-status-register instruction completion 4.4.3 auto address increment (aai) the auto address increment programming-status bit provides status on whether the device is in aai pro- gramming mode or byte-program mode. the default at power up is byte-program mode. 4.4.4 block protection (bp1, bp0) the block-protection (bp1, bp0) bits define the size of the memory area, as defined in table 4-4 , to be software protected against any memory write (program or erase) operation. the write-status -register (wrsr) instruc- tion is used to program the bp1 and bp0 bits as long as wp# is high or the block-pr otect-lock (bpl) bit is 0. chip-erase can only be exec uted if block-protection bits are all 0. after power-up, bp1 and bp0 are set to 1. table 4-3: software status register 1 bit name function default at power-up read/write 0:1 res reserved for future use 0n / a 2 tsp top sector protection status 1 = indicates highest sector is write locked 0 = indicates highest sector is write accessible 0r / w 3 bsp bottom sector protection status 1 = indicates lowest se ctor is write locked 0 = indicates lowest sector is write accessible 0r / w 4:7 res reserved for future use 0n / a table 4-4: software status register block protection for sst25pf020b 1 1. x = don?t care (reserved) default is ?0? protection level status register bit 2 2. default at power-up for bp1 and bp0 is ?11?. (all blocks protected) protected memory address bp1 bp0 2 mbit 00 0 n o n e 1 (1/4 memory array) 0 1 030000h-03ffffh 1 (1/2 memory array) 1 0 020000h-03ffffh 1 (full memory array) 1 1 000000h-03ffffh
? 2012 microchip technology inc. ds25135a-page 7 sst25pf020b 4.4.5 block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp1, and bp0 bits of the status register and bsp and tsp of status register 1. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power- up, the bpl bit is reset to 0. 4.4.6 top-sector protection/ bottom-secto r protection the top-sector protection (tsp) and bottom-sector protection (bsp) bits independently indicate whether the highest and lowest sector locations are write locked or write accessible. when tsp or bsp is set to ?1?, the respective sector is write locked; when set to ?0? the respective sector is wr ite accessible. if tsp or bsp is set to '1' and if the top or bottom sector is within the boundary of the target addr ess range of the program or erase instruction, the init iated instruction (byte-pro- gram, aai-word program, sector-erase, block-erase, and chip-erase) will not be executed. upon power-up, the tsp and bsp bits are auto matically reset to ?0?.
sst25pf020b ds25135a-page 8 ? 2012 microchip technology inc. 4.5 instructions instructions are used to read, write (erase and pro- gram), and configure the sst25pf020b. the instruc- tion bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any byte-program, auto address increment (aai) program- ming, sector-erase, block-erase, write-status-regis- ter, or chip-erase instructions, the write-enable (wren) instruction must be executed first. the com- plete list of instructions is provided in table 4-5 . all instructions are synchronized off a high to low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most si gnificant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status- register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. instruction com- mands (op code), addresses, and data are all input from the most significant bit (msb) first. table 4-5: device operation instructions instruction descript ion op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most signi ficant bit of each density can be v il or v ih . dummy cycle(s) data cycle(s) read read memory 0000 0011b (03h) 301 to high-speed read read memory at higher speed 0000 1011b (0bh) 311 to 4 kbyte sector- erase 3 3. 4kbyte sector erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 300 32 kbyte block- erase 4 4. 32kbyte block erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. erase 32 kbyte block of memory array 0101 0010b (52h) 300 64 kbyte block- erase 5 5. 64kbyte block erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. erase 64 kbyte block of memory array 1101 1000b (d8h) 300 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 byte-program to program one data byte 0000 0010b (02h) 301 aai-word-program 6 6. to continue programming to the next sequential address location, enter the 8-bit command, adh, followed by 2 bytes of data to be programmed. data byte 0 will be programmed into the initial address [a 23 -a 1 ] with a 0 =0, data byte 1 will be pro- grammed into the initial address [a 23 -a 1 ] with a 0 =1. auto address increment program- ming 1010 1101b (adh) 302 to rdsr 7 7. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. read-status-register 0000 0101b (05h) 001 to rdsr1 read-status-register 1 0011 0101b (35h) 001 to ewsr enable-write-status-register 0101b 0000b (50h) 000 wrsr write-status-register 0000 0001b (01h) 0 0 1 or 2 wren write-enable 0000 0110b (06h) 000 wrdi write-disable 0000 0100b (04h) 000 rdid 8 8. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufacturer?s id and device id output stream is continuous until terminated by a low-to-high transition on ce#. read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to jedec-id jedec id read 1001 1111b (9fh) 003 to ebsy enable so to output ry/by# status during aai programming 0111 0000b (70h) 000 dbsy disable so to output ry/by# status during aai programming 1000 0000b (80h) 000
? 2012 microchip technology inc. ds25135a-page 9 sst25pf020b 4.5.1 read (33/25 mhz) the read instruction, 03h, supports up to 33 mhz (2.7- 3.6v operation) or 25 mhz (2.3-2.7v operation) read. the device outputs the data st arting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wr ap-around) of the address space. once the data from address location 3ffffh has been read, the next output will be from address location 000000h. the read instruction is initiated by executing an 8-bit command, 03h, followed by address bits [a 23 -a 0 ]. ce# must remain active low for the duration of the read cycle. see figure 4-3 for the read sequence. figure 4-3: read sequence 4.5.2 high-speed-r ead (80/50 mhz) the high-speed-read instruction, supporting up to 80 mhz (2.7-3.6v operation) or 50 mhz (2.3-2.7v opera- tion) read, is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 4-4 for the high- speed-read sequence. following a dummy cycle, the high-speed-read instruction outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wr ap-around) of the address space. once the data from address location 3fffh has been read, the next output will be from address location 00000h. figure 4-4: high-speed-read sequence 25135 readseq.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out 25135 hsrdseq.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb msb msb mode 0 mode 3 d out d out d out d out 80 71 72 d out note: x = dummy byte: 8 clocks input dummy cycle (v il or v ih )
sst25pf020b ds25135a-page 10 ? 2012 microchip technology inc. 4.5.3 byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a pro- gram operation. a byte-program instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be execut ed. ce# must remain active low for the duration of the byte-program instruction. the byte-program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 - a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte- program operation. see figure 4-5 for the byte-pro- gram sequence. figure 4-5: byte-program sequence 4.5.4 auto address increment (aai) word-program the aai program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total programming time when multiple bytes or entire memory array is to be progr ammed. an aai word pro- gram instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) when initiating an aai word program operation. while within aai word program- ming sequence, only the following instructions are valid: for software end-of -write detection?aai word (adh), wrdi (04h), and rdsr (05h); for hardware end-of-write detection?aai word (adh) and wrdi (04h). there are three options to determine the com- pletion of each aai word program cycle: hardware detection by reading the serial output, software detec- tion by polling the busy bit in the software status reg- ister, or wait t bp. refer to?end-of-write detection? for details. prior to any write operation, the write-enable (wren) instruction must be executed. initiate the aai word program instruction by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two bytes of data are input sequentially, each one from msb (bit 7) to lsb (bit 0). the first byte of data (d0) is programmed into the initial address [a 23 - a 1 ] with a 0 =0, the second byte of data (d1) is pro- grammed into the initial address [a 23 -a 1 ] with a 0 =1. ce# must be driven high before executing the aai word program instructi on. check the busy status before entering the next valid command. once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed, fol- lowed by the next two, and so on. when programming the last desired word, or the high- est unprotected memory address, check the busy sta- tus using either the hardware or software (rdsr instruction) method to check for program completion. once programming is complete, use the applicable method to terminate aai. if the device is in software end-of-write detection mode, execute the write-dis- able (wrdi) instruction, 04h. if the device is in aai hardware end-of-write detection mode, execute the write-disable (wrdi) instruction, 04h, followed by the 8-bit dbsy command, 80h. there is no wrap mode during aai programming once the highest unprotected memory address is reached. see figures 4-8 and 4-9 for the aai word programming sequence. 4.5.5 end-of-write detection there are three methods to determine completion of a program cycle during aai word programming: hard- ware detection by reading the serial output, software detection by polling the busy bit in the software status register, or wait t bp. the hardware end-of-write detection method is described in the section below. 25135 byteprog.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb
? 2012 microchip technology inc. ds25135a-page 11 sst25pf020b 4.5.6 hardware end-of-write detection the hardware end-of-write detection method elimi- nates the overhead of polling the busy bit in the soft- ware status register during an aai word program operation. the 8-bit command, 70h, configures the serial output (so) pin to indicate flash busy status during aai word programming. (see figure 4-6 ) the 8- bit command, 70h, must be executed prior to initiating an aai word-program instruction. once an internal programming operation begins, asserting ce# will immediately drive the status of the internal flash status on the so pin. a ?0? indicates the device is busy and a ?1? indicates the device is r eady for the next instruction. de-asserting ce# will return the so pin to tri-state. while in aai and hardware end-of-write detection mode, the only valid instructions are aai word (adh) and wrdi (04h). to exit aai hardware end-of-write detection, first exe- cute wrdi instruction, 04h, to reset the write-enable- latch bit (wel=0) and aai bit. then execute the 8-bit dbsy command, 80h, to disabl e ry/by# status during the aai command. see figures 4-7 and 4-8 . figure 4-6: enable so as hardware ry/by# during aai programming figure 4-7: disable so as hardware ry/by# during aai programming ce# so si sck 01234567 70 high impedance mode 0 mode 3 25135 enableso.0 msb ce# so si sck 01234567 80 high impedance mode 0 mode 3 25135 disableso.0 msb
sst25pf020b ds25135a-page 12 ? 2012 microchip technology inc. figure 4-8: auto address increment ( aai) word-program sequence with hardware end-of-write detection figure 4-9: auto address increment ( aai) word-program sequence with software end-of-write detection ce# si sck so 25135 aai.hw.3 check for flash busy status to load next valid 1 command load aai command, address, 2 bytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming 0 aaa ad d0 ad mode 3 mode 0 d1 d2 d3 7 wren ebsy 0 7 078 32 47 15 16 23 24 31 0 4039 7 8 15 16 23 d out wrdi followed by dbsy to exit aai mode wrdi rdsr 70 1 5 7 8 0 dbsy 70 ce# cont. si cont. sck cont. so cont. last 2 data bytes ad d n-1 d n 7 8 15 16 23 0 check for flash busy status to load next valid 1 command 078 32 47 15 16 23 24 31 0 4039 7 8 15 16 23 7 8 15 16 23 70 15 78 00 ce# si sck so d out mode 3 mode 0 25135 aai.sw.2 note: 1. valid commands during aai programming: aai command, rdsr command, or wrdi command wait t bp or poll software status register to load next valid 1 command last 2 data bytes wrdi to exit aai mode load aai command, address, 2 bytes data aaa ad d0 ad d1 d2 d3 ad d n-1 d n wrdi rdsr
? 2012 microchip technology inc. ds25135a-page 13 sst25pf020b 4.5.7 4-kbyte sector-erase the sector-erase instructio n clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms =most sig- nificant address) are us ed to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self-timed se ctor-erase cycle. see figure 4-10 for the sector-erase sequence. figure 4-10: sector-erase sequence 4.5.8 32-kbyte and 64-kbyte block- erase the 32-kbyte block-erase instruction clears all bits in the selected 32 kbyte bl ock to ffh. a block-erase instruction applied to a protected memory area will be ignored. the 64-kbyte block-erase instruction clears all bits in the selected 64 kbyte bl ock to ffh. a block-erase instruction applied to a pr otected memory area will be ignored. prior to any writ e operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the 32-kbyte block-erase instruction is initiated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most sig- nificant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before th e instruction is executed. the 64-kbyte block-erase instruction is initiated by executing an 8-bit command d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the inst ruction is executed. the user may poll the busy bit in the software status register or wait t be for the completion of the internal self-timed 32- kbyte block-erase or 64-kbyte block-erase cycles. see figures 4-11 and 4-12 for the 32-kbyte block- erase and 64-kbyte block-erase sequences. figure 4-11: 32-kbyte block-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 25135 secerase.0 msb msb ce# so si sck addr 012345678 addr addr 52 high impedance 15 16 23 24 31 mode 0 mode 3 25135 32kbkler.0 msb msb
sst25pf020b ds25135a-page 14 ? 2012 microchip technology inc. figure 4-12: 64-kbyte block-erase sequence 4.5.9 chip-erase the chip-erase instruction clears all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write oper- ation, the write-enable (wren) instruction must be exe- cuted. ce# must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 4-13 for the chip-erase sequence. figure 4-13: chip-erase sequence 4.5.10 read-status-register (rdsr) the read-status-register (rdsr) instruction allows reading of the status regist er. the status register may be read at any time even during a write (program/ erase) operation. when a write operation is in prog- ress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read-status-register is continuous with ongoing clock cycles until it is termi- nated by a low to high transition of the ce#. see figure 4-14 for the rdsr instruction sequence. ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 25135 63kblker.0 msb msb ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 25135 cher.0 msb
? 2012 microchip technology inc. ds25135a-page 15 sst25pf020b figure 4-14: read-status-register (rdsr) sequence 4.5.11 read-status- register (rdsr1) the read-status-register 1 (rdsr1) instruction allows reading of the status register 1. ce# must be driven low before the rdsr in struction is entered and remain low until the status data is read. read-status- register 1 is continuous wi th ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 4-15 for the rdsr instruction sequence. figure 4-15: read-status-register 1 (rdsr1) sequence 4.5.12 write-enable (wren) the write-enable (wren) in struction sets the write- enable-latch bit in the status register to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) opera- tion. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruc- tion; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. figure 4-16: write en able (wren) sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25135 rdsrseq.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25135 rdsr1seq.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 35 mode 0 high impedance status register out msb msb ce# so si sck 01234567 06 high impedance mode 0 mode 3 25135 wren.0 msb
sst25pf020b ds25135a-page 16 ? 2012 microchip technology inc. 4.5.13 write-disable (wrdi) the write-disable (wrdi) inst ruction resets the write- enable-latch bit and aai bit to 0 disabling any new write operations from occurring. the wrdi instruction will not terminate any programming operation in prog- ress. any program operation in progress may continue up to t bp after executing the wrdi instruction. ce# must be driven high before the wrdi instruction is exe- cuted. figure 4-17: write di sable (wrdi) sequence 4.5.14 enable-write-status- register (ewsr) the enable-write-status-regi ster (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write- status-register instruction must be executed immedi- ately after the execution of the enable-write-status- register instruction. this two-step instruction sequence of the ewsr instruction followed by the wrsr instruction works like sdp (software data pro- tection) command structur e which prevents any acci- dental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high bef ore the ewsr instruction is executed. 4.5.15 write-status-register (wrsr) the write-status-register in struction writes new val- ues to the bp1, bp0, and bpl bits of the status register. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wr sr instruction is executed. see figure 4-18 for ewsr or wren and wrsr for byte-data input sequences. executing the write-status-r egister instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, and bp1 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruct ion, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0, bp1, and bp2 bits at the same time. see table 4-1 for a summary description of wp# and bpl functions. figure 4-18: enable-write-status-registe r (ewsr) or write-enable (wren) and write-status-register (wrsr) byte-data input sequence ce# so si sck 01234567 04 high impedance mode 0 mode 3 25135 wrdi.0 msb 25135 ewsr.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
? 2012 microchip technology inc. ds25135a-page 17 sst25pf020b the write-status-register instruction also writes new values to the status register 1. to write values to sta- tus register 1, the wrsr sequence needs a word- data input?the first byte bei ng the status register bits, followed by the second byte status register 1 bits. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 4-19 for ewsr or wren and wrsr instruction word-data input sequences. executing the write-status-r egister instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status registers, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, bp1, tsp, and bsp bits in the status register can all be changed. as long as bpl bit is set to 0 or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wr sr instruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bpl, bp0, bp1, tsp, and bsp bits at the same time. see table 4-1 for a summary descrip- tion of wp# and bpl functions. figure 4-19: enable-write-status-registe r (ewsr) or write-enable (wren) and write-status-register (wrsr) word-data input sequence the wrsr instruction can either execute a byte-data or a word-data input. extra data/clock input, or within byte-/word-data input, will not be executed. the reason for the byte support is for backward compatibility to products where wrsr instruction sequence is fol- lowed by only a byte-data. 25135 ewsr1.0 mode 3 high impedance mode 0 status register 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 01234567 0123456789101112131415 status register 1 76543210 msb 16 17 18 19 20 21 22 23
sst25pf020b ds25135a-page 18 ? 2012 microchip technology inc. 4.5.16 jedec read-id the jedec read-id instruction identifies the device as sst25pf020b and the manufacturer as microchip. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, bfh, is output from the device. after that, a 16-bit device id is shifted out on the so pin. byte 1, bfh, identifies the manufac- turer as microchip. byte 2, 25h, identifies the memory type as spi serial flash. byte 3, 8ch, identifies the device as sst25pf020b. the instruction sequence is shown in figure 4-20 . the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. figure 4-20: jedec read-id sequence 25 8c 25135 jedecid.1 ce# so si sck 012345678 high impedance 15 1614 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 9f 19 20 21 22 23 24 25 26 27 table 4-6: jedec read-id data device id manufacturer?s id memory type memory capacity byte1 byte 2 byte 3 bfh 25h 8ch
? 2012 microchip technology inc. ds25135a-page 19 sst25pf020b 4.5.17 read-id (rdid) the read-id instruction (rdid) identifies the devices as sst25pf020b and manufacturer as microchip. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 - a 0 ]. following the read-id instruction, the manufac- turer?s id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manufacturer?s and device id out- put data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. refer to tables 4-6 and 4-7 for device identification data. figure 4-21: read-id sequence 25135 rdid.0 ce# so si sck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. device id = 8ch for sst25pf020b 1. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb table 4-7: product identification address data manufacturer?s id 00000h bfh device id sst25pf020b 00001h 8ch
sst25pf020b ds25135a-page 20 ? 2012 microchip technology inc. 5.0 electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. table 5-1: operating range range ambient temp v dd commercial 0c to +70c 2.3-3.6v table 5-2: ac conditions of test 1 1. see figures 5-6 and 5-7 input rise/fall time output load 5ns c l = 30 pf table 5-3: dc operating characteristics symbol parameter limits test conditions min max units i ddr read current 12 ma ce#=0.1 v dd /0.9 v dd @33 mhz, so=open i ddr3 read current 20 ma ce#=0.1 v dd /0.9 v dd @80 mhz, so=open i ddw program and erase current 30 ma ce#=v dd i sb standby current 20 a ce#=v dd , v in =v dd or v ss i li input leakage current 1a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.7 v v dd =v dd min v ih input high voltage 0.7 v dd v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v ol2 output low voltage 0.4 v i ol =1.6 ma, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min
? 2012 microchip technology inc. ds25135a-page 21 sst25pf020b table 5-4: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. table 5-5: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 table 5-6: ac operating c haracteristics , 2.3-2.7v symbol parameter 25 mhz 50 mhz units minmaxminmax f clk 1 1. maximum clock frequency for read instruction, 03h, is 25 mhz serial clock frequency 25 50 mhz t sckh serial clock high time 18 9 ns t sckl serial clock low time 18 9 ns t sckr serial clock rise time (slew rate) 0.1 0.1 v/ns t sckf serial clock fall time (slew rate) 0.1 0.1 v/ns t ces 2 2. relative to sck ce# active setup time 55ns t ceh 2 ce# active hold time 55ns t chs 2 ce# not active setup time 55ns t chh 2 ce# not active hold time 55ns t cph ce# high time 50 50 ns t chz ce# high to high-z output 77ns t clz sck low to low-z output 00ns t ds data in setup time 22ns t dh data in hold time 44ns t hls hold# low setup time 55ns t hhs hold# high setup time 55ns t hlh hold# low hold time 55ns t hhh hold# high hold time 55ns t hz hold# low to high-z output 77ns t lz hold# high to low-z output 77ns t oh output hold from sck change 00ns t v output valid from sck 12 8 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 50 50 ms t bp byte-program 10 10 s
sst25pf020b ds25135a-page 22 ? 2012 microchip technology inc. figure 5-1: serial input timing diagram table 5-7: ac operating c haracteristics , 2.7-3.6v symbol parameter 33 mhz 80 mhz units min max min max f clk 1 1. maximum clock frequency for read instruction, 03h, is 33 mhz serial clock frequency 33 80 mhz t sckh serial clock high time 13 6 ns t sckl serial clock low time 13 6 ns t sckr 2 2. maximum rise and fall time may be limited by t sckh and t sckl requirements serial clock rise time (slew rate) 0.1 0.1 v/ns t sckf serial clock fall time (slew rate) 0.1 0.1 v/ns t ces 3 3. relative to sck. ce# active setup time 55ns t ceh 3 ce# active hold time 55ns t chs 3 ce# not active setup time 55ns t chh 3 ce# not active hold time 55ns t cph ce# high time 50 50 ns t chz ce# high to high-z output 15 7 ns t clz sck low to low-z output 00ns t ds data in setup time 22ns t dh data in hold time 44ns t hls hold# low setup time 55ns t hhs hold# high setup time 55ns t hlh hold# low hold time 55ns t hhh hold# high hold time 55ns t hz hold# low to high-z output 77ns t lz hold# high to low-z output 77ns t oh output hold from sck change 00ns t v output valid from sck 10 6 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 50 50 ms t bp byte-program 10 10 s high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 25135 serin.0
? 2012 microchip technology inc. ds25135a-page 23 sst25pf020b figure 5-2: serial output timing diagram figure 5-3: hold timing diagram 25135 serout.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb t hz t lz t hhh t hls t hlh t hhs 25135 hold.0 hold# ce# sck so si
sst25pf020b ds25135a-page 24 ? 2012 microchip technology inc. 5.1 power-up specifications all functionalities and dc sp ecifications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v - 3.0v in less than 300 ms). see table 5-8 and figure 5-4 for more information. figure 5-4: power-up timing diagram table 5-8: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change t hat could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s table 5-9: recommended power-up/-down limits symbol parameter limits conditions min max units t pf v dd falling time 1100ms/v t pr v dd rising time 0.033 100 ms/v t off v dd off time 100 ms v off v dd off level 0.3 v 0v (recommended) time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. commands may not be accepted or properly interpreted by the device. 25135 pwrup.0
? 2012 microchip technology inc. ds25135a-page 25 sst25pf020b figure 5-5: recommended power-up/-down waveform figure 5-6: ac input/output reference waveforms figure 5-7: a test load example 25135 f28.1 t off gnd v off v dd 25135 ioref.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 25135 tstld.0 to tester to dut c l
sst25pf020b ds25135a-page 26 ? 2012 microchip technology inc. 6.0 product iden tification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. part no. xx xxx package endurance/ device device: sst25pf020b = 2 mbit, 2.3-3.6v, serial peripheral inter- face flash memory operating frequency: 80 = 80 mhz endurance: 4 = 10,000 cycles temperature: c = 0c to +70c package: qae = wson (6mm x 5mm), 8-contact sae = soic (150 mil), 8-lead q3ae = uson(3mm x 2mm), 8-contact tape and reel flag: t = tape and reel valid combinations: SST25PF020B-80-4C-QAE SST25PF020B-80-4C-QAE-t sst25pf020b-80-4c-sae sst25pf020b-80-4c-sae-t sst25pf020b-80-4c-q3ae sst25pf020b-80-4c-q3ae-t xx operating temperature x tape/reel indicator frequency
? 2012 microchip technology inc. ds25135a-page 27 sst25pf020b 7.0 packaging diagrams figure 7-1: 8-lead small outline integrated ci rcuit (soic) 150mil body width (5mm x 6mm) package code: sa 08-soic-5x6-sa-8 n ote: 1. complies with jedec pub lication 95 ms-012 aa dimensions, altho u gh some dimensions may b e more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maxim um allo w ab le mold flash is 0.15 mm at the package ends and 0.25 mm betw een leads. top view side view end view 5.0 4.8 6.20 5.80 4.00 3.80 pin #1 identifier 0.51 0.33 1.27 bsc 0.25 0.10 1.75 1.35 7 4 places 0.25 0.19 1.27 0.40 45 7 4 places 0 8 1mm
sst25pf020b ds25135a-page 28 ? 2012 microchip technology inc. figure 7-2: 8-contact very-very-th in small outline no-lead (wson) package code: qa note: 1. all linear dimensions are in millimeters (max/min). 2. untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. the external paddle is electrically connected to the die back-side and possibly to certain v ss leads. this paddle can be soldered to the pc board; it is suggested to connect this paddle to the v ss of the unit. connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. 8-wson-5x6-qa-9.0 4.0 1.27 bsc pin #1 0.48 0.35 0.076 3.4 5.00 0.10 6.00 0.10 0.05 max 0.70 0.50 0.80 0.70 0.80 0.70 pin #1 corner top view bottom view cross sectio n side view 1mm 0.2
? 2012 microchip technology inc. ds25135a-page 29 sst25pf020b figure 7-3: 8-contact ultra-thin small outline no-lead (uson) package code: q3a 1mm 0.60 0.45 0.08 pin # 1 3.00 0.10 pin #1 (laser engra v ed see note 2) 2.00 0.10 0.5 bsc 0.2 0.25 0.05 8-uson-2x2-q3a-1.1 0.05 max see notes 3 &4 1.60 n ote: 1. similar to jedec jep95 mo-252 v ariant u2030d, tho ugh n umb er of contacts and some dimensions may b e different. 2. the topside pin #1 indicator is laser engra v ed; its approximate shape and location is as sho w n. 3. from the bottom vie w , the pin #1 indicator may be either a cur v ed indent or a 45-degree chamfer. 4. untoleranced dimensions are nominal target dimensions. 5. all linear dimensions are in millimeters (max/min). 6. lead-frame nominal thickness 0.127mm or 0.15mm (s upplier-dependent). 2.45 0.40 0.05 0.35 0.05 0.15 max
sst25pf020b ds25135a-page 30 ? 2012 microchip technology inc. table 7-1: revision history revision description date a ? initial release of spec nov 2012
? 2012 microchip technology inc. ds25135a-page 31 sst25pf020b the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2012 microchip technology inc. ds25135a-page 32 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-678-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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