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never stop thinking. data sheet, rev 1.11, nov. 2005 communications adm6993/x adm6993/x hdlc to fast ethernet converter
edition 2005-11-28 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
template: template_a4_3.0.fm / 3 / 2005-03-10 trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, convergate?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? and visio ? are registered trademarks of microsoft corporation, linux ? of linus torvalds, and framemaker ? of adobe systems incorporated. adm6993/x adm6993/x hdlc to fast ethernet converter revision history: 2005-11-28, rev 1.11 previous version: page/date subjects (major change s since last revision) 2003-07-02 rev. 1.0: first release of adm6993 2003-10-13 rev. 1.1: added sections 4.3&4.4 2005-08-15 changed to the new infineo format 2005-09-09 rev. 1.11: when changed to the new infineon format 2005-11-28 minor change. included green package information
data sheet 4 rev 1.11, 2005-11-28 adm6993/x table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 data lengths conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin type and buffer type abbreviation s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 port 2 mii/rmii/gpsi/hdlc interfaces comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 3 function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 10/100m phy block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 auto negotiation and speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 auto negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2 speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 switch functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.2 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3 address recognition and packet forwardi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.4 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.5 buffers and queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.6 back off algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.7 inter-packet gap (ipg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.8 illegal frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.9 half duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.10 full duplex flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.11 broadcast storm filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.12 auto tp mdix function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 converter functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1 fault propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.2 redundant link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.3 loop-back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.4 snooping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.5 fiber_sd led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 serial management interface (smi) register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.1 preamble suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.2 read eeprom register via smi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.5.3 write eeprom register via sm i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6 hdlc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.1 hdlc frame receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.6.2 hdlc frame transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7.1 write eeprom register via eeprom interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table of contents
data sheet 5 rev 1.11, 2005-11-28 adm6993/x table of contents 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 eeprom register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.1 eeprom register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 default value of smi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 smi register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.1 smi register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.1 dc characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 ac characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
data sheet 6 rev 1.11, 2005-11-28 adm6993/x list of figures figure 1 adm6993/x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 adm6993/x pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 smi read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4 smi write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 6 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 7 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 8 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 9 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 10 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 11 reduce mii timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 13 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 14 hdlc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 15 smi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 16 128 pqfp packaging for adm6993/x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 list of figures
data sheet 7 rev 1.11, 2005-11-28 adm6993/x list of tables table 1 data lengths conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 adm6993/xabbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4 port 0/1 twisted pair interface (8 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5 port 2 (mii/rmii/gpsi) interface (17 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6 port 1 alternative mii port interface (17 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7 led interface (13 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8 eeprom interface (4 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9 configuration interface (28 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10 ground/power interface (27 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11 miscellaneous (14 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12 port 2 mii/rmii/gpsi/hdl c interfaces comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13 speed configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14 port rising/falling threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15 drop scheme for each queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16 smi read/write command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17 eeprom register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 21 registers clock domainsregisters clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22 other filter regsiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23 other tag port rule 0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24 other tag port rule 1 regsiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25 default value of smi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 26 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 27 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 28 register access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 29 registers clock domainsregisters clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 30 other per port counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 31 electrical absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 32 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 33 dc electrical characteri stics for 3.3 v operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 34 power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 35 eeprom interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 36 10base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 37 10base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 38 100base-tx mii input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 39 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40 100base-tx mii output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41 gpsi (7-wire) input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 42 gpsi (7-wire) output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 43 hdlc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 44 smi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 list of tables
adm6993/x product overview data sheet 8 rev 1.11, 2005-11-28 1 product overview features and the block diagram. 1.1 overview the adm6993/x is a single chip integrating two 10/1 00 mbps mdix tx/fx transceivers, a three-port 10/100m ethernet l2 switch controller, and features converter mode to meet demanding applications, including fiber-to- ethernet media converters, 2/3 port ethernet switches, voip gateways, and nat routers. the adm6993x is the environmentally friendly ?green? package version. the adm6993/x supports priority features on port-bas e priority, vlan tag priority and ip tos precedence checking at individual ports. this is done through a small low-cost micro controller to initialize or on-the-fly to configure. the priority of packets can be tagged base d on tcp port number for the multi-media application. the 2 nd mac interface could be selected as tp/fx or mii/rmii/gpsi to connect with bridge devices for different media. the 3 rd mac interface could be selected as mii/rmii/ gpsi/hdlc to connect with routing devices, and bridge devices for different media. the dedicated hd lc channel supports rate from 64kbps to 50mbps. on the media side of port0/1, the adm6993/x supports auto mdix 10base-t/100base-tx and 100base-fx as specified by the ieee 802.3 committee through uses of digital circuitry and high speed a/d. adm6993/x supports serial management interface (smi) for a small low-cost micro controller to initialize or configure. it also provides port status for remo te agent monitor and smart counter for port statistics. 1.2 features main features: ? 3-port10/100m switch integrated with a 2-port phy (10/100tx and 100fx) and 3 rd mac port as gpsi/mii/rmii/hdlc. ? provides tx<-->fx converter mode s with faulted propagatio n and redundant capab ility by using of two adm6993/x. ? short latency on the converter mode. ? built-in data buffer 6kx64bit sram. ? up to 2k mac unicast addresses with a 4-way associative hashing table. ? mac address learning table with aging function. ? two queues per port for qos purposes. ? port-base, 802.1p and tcp/ip tos priority. ? store & forward architecture. ? 802.3x flow control for full duplex and back-pres sure for half duplex in case the buffer is full. ? supports auto-negotiation. ? packet lengths up to 1536 bytes. ? broadcast storming filter. ? port-base vlan/tag-base vlan. ? 16 entries of packet classification and marking or filt ering for tcp/udp port numbering, ip protocol id and ethernet type. ? serial management interface for low-end cpus. ? provides port status for remote agent monitoring . ? provides smart counters for port statistics reporting. ? 128 pqfp packaging with 2.5 v/3.3 v power supply.
data sheet 9 rev 1.11, 2005-11-28 adm6993/x product overview 1.3 block diagram figure 1 adm6993/x block diagram 1.4 data lengths conventions table 1 data lengths conventions qword 64 bits dword 32 bits word 16 bits byte 8 bits nibble 4 bits port1 mac port2 mac port0 mac dma learn dma learn dma learn packet buffer address filtering buffer management switch fabric link list link list buffer mac address buffer eeprom interface smi interface led display rcv clkgen rstgen cenctrl mux port1 tx/fx phy port0 tx/fx phy mux mii rmii gpsi hdlc mii rmii gpsi
adm6993/x interface de scription data sheet 10 rev 1.11, 2005-11-28 2 interface description this chapter describes pin diagram , pin type and buffer type abbreviations, and pin descriptions. 2.1 pin diagram figure 2 adm6993/x pin assignment lpt_dis chip_dis cas_dis lpbk_p0 lpbk_p1 lpbk_p2 p2linkf p2spdten p2dphalf p2col p2crs vcc2ik p2txclk gndik p2txen p2txd0 p2txd1 p2txd2 p2txd3 p1rxd3 p1rxd2 p1rxd1 p1rxd0 vcc3o ck25mo gndo nc nc nc nc nc nc nc nc p0_mdi xoven scan_en scan_md led_link1 led_full0 led_full1 led_lpbk nc int_n eedo eedi vcc2ik vcc2ik eesk eecs gndik sdc sdio p0_andis p0_rechalf p0_rec10 p0_fcdis ftpr_mode0 ftpr_mode1 p1_andis p1_rechalf p1_rec10 p1_fcdis rc xi xo bypass_pause ledmode2 nc vccpll gndpll control vref gndbias rtx vccbias vcca2(2.5) txp0 txn0 gnda rxp0 rxn0 vccad(3.3) rxn1 rxp1 gnda txn1 txp1 vcca2(2.5) gndik p1txd3 p1txd2 p1txd1 p1txd0 vcc2ik p1txclk p1txen p1rxdv p1rxclk test p2_fcdis gndik p2rxclk p2rxdv p2rxd0 p2rxd1 p2rxd2 p2rxd3 gndik gndik p1col p1crs lnkact0/led_data0 lnkact1/led_data1 vcc2ik vcc2ik p1linkf gndo gndo p1spdten p1dphalf ldspd0 ldspd1/led_fiber_sd dupcol0/led_col0 dupcol1/led_col1 vcc3o vcc3o led_link0 adm6993 ?? ?? ?? ?? ?? ?? ?? ?? ? ? ?? ? ?? ? ? ? ?? ?? ?? ? ? ? ? ?? ? ?? ? ? ? ? ? ?? ?? ?? ? ?? ?? ?? ?? ?? ? ? ? ?? ? ? ? ? ? ? ? ??? ??? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ?? ?? ? ? ? ? ? ? ?? ??? ??? ??? ?? ?? ?? ??? ?? ??? ??? ??? ??? ??? ?? ??? ??? ?? ??? ?? ?? ?? ??? ??? ?? ???
data sheet 11 rev 1.11, 2005-11-28 adm6993/x interface de scription 2.2 pin type and buffer type abbreviations standardized abbreviations: table 2 adm6993/xabbreviations for pin type abbreviations description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. ao output. analog levels. ai/o input or output. analog levels. pwr power gnd ground mcl must be connected to low (jedec standard) mch must be connected to high (jedec standard) nu not usable (jedec standard) nc not connected (jedec standard) table 3 abbreviations for buffer type abbreviations description z high impedance pu1 pull up, 10 k pd1 pull down, 10 k pd2 pull down, 20 k ts tristate capability: the corres ponding pin has 3 operationa l states: low, high and high- impedance. od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to shar e as a wire-or. an external pull-up is required to sustain the inactive state until another agent drives it, and must be provid ed by the central resource. oc open collector pp push-pull. the corresponding pin has 2 operational states: active-low and active-high (identical to output with no type attribute). od/pp open-drain or push-pull. the corresponding pin can be configured either as an output with the od attribute or as an output with the pp attribute. st schmitt-trigger characteristics ttl ttl characteristics
adm6993/x interface de scription data sheet 12 rev 1.11, 2005-11-28 2.3 pin descriptions adm6993/x pins are categorized into one of the following groups: ? port 0/1 twisted pair interface, 8 pins ? port 2 (mii/rmii/gpsi) interface, 17 pins ? port 1 alternative mii port interface, 17 pins ? led interface, 13 pins ? eeprom interface, 4 pins ? configuration interface, 28 pins ? ground/power interface, 27 pins ? miscellaneous, 14 pins note: if not specified, all signals default to digital signals. table 4 port 0/1 twisted pair interface (8 pins) pin or ball no. name pin type buffer type function 40 txp_0 ao twisted pair transmit output positive. 50 txp_1 ao 41 txn_0 ao twisted pair transmit output negative. 49 txn_1 ao 43 rxp_0 ai twisted pair receive input positive. 47 rxp_1 ai 44 rxn_0 ai twisted pair receive input negative. 46 rxn_1 ai table 5 port 2 (mii/rmii/gpsi) interface (17 pins) pin or ball no. name pin type buffer type function 87 p2txd0 i/o ttl, pd, 8ma port 2 mii transmit data bit 0 synchronous to the rising edge of txclk. fxmode0 fxmode0 during power on reset, value will be latched by adm6993/x at the rising e dge of resetl as bit 0 of fxmode. 86 p2txd1 i/o ttl, pd, 8ma port 2 mii transmit data bit 1 synchronous to the rising edge of txclk. fxmode1 fxmode1 during power on reset, value will be latched by adm6993/x at the rising e dge of resetl as bit 1 of fxmode. fxmode [1:0] interface 00 b , both port0 & port1 are tp port 01 b , port0 is tp port and port1 is fx port 10 b , port0 is tp port and port1 is fx port (converter mode) 11 b , both port0 & port1 are fx port
data sheet 13 rev 1.11, 2005-11-28 adm6993/x interface de scription 85 p2txd2 i/o ttl, pd, 8ma port 2 mii transmit data bit 2 synchronous to the rising edge of txclk. p2busmd0 p2busmd0 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as p2busmd0. 84 p2txd3 i/o pd, 8ma port 2 mii transmit data bit 3 p2busmd1 p2busmd1 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as p2busmd1. busmd[1:0] interface 00 b , mii(default) 01 b , rmii 10 b , gpsi 11 b , hdlc 88 p2txen i/o pd, 8ma port 2 mii transmit enable synchronous to the rising edge of txclk disbp disbp. disable back pressure 0 b , enable back-pressure(default) 1 b , disable back-pressure 108 p2rxd_3 i ttl, pd port 2 mii receive data bit 3 ~ 0 107 p2rxd_2 106 p2rxd_1 105 p2rxd_0 104 p2rxdv i ttl, pd port 2 mii receive data valid 93 p2col i ttl, pd port 2 mii collision input 92 p2crs i ttl, pd port 2 mii carrier sense 103 p2rxclk i ttl, pd port 2 mii receive clock input 90 p2txclk i ttl, pd port 2 mii transmit clock input 96 p2linkf i ttl, pu p2linkf this pin will be used to inpu t the link stat us of port2 1 b , link fail 95 p2spdten i ttl, pd p2spdten this pin will be used as po rt 2 speed status input 1 b , 10m 94 p2dphalf i ttl, pd p2dphalf this pin will be used as port 2 duplex status input 1 b , half duplex table 5 port 2 (mii/rmii/g psi) interface (17 pins) (cont?d) pin or ball no. name pin type buffer type function
adm6993/x interface de scription data sheet 14 rev 1.11, 2005-11-28 table 6 port 1 alternative mii po rt interface (17 pins) pin or ball no. name pin type buffer type function 56 p1txd0/chipid _0 i/o ttl, pd, 8ma port 1 mii transmit data bit 0/chip id bit 0 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as chipid_0.this pin will become p1rxd0 if p1busmd[1:0] is 11. synchrono us to the rising edge of txclk. 55 p1txd1/chipid _1 i/o ttl, pd, 8ma port 1 mii transmit data bit 1/chip id bit 1 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as chipid_1.this pin will become p1rxd1 if p1busmd[1:0] is 11. synchrono us to the rising edge of txclk. 54 p1txd2/p1bus md0 i/o ttl, pu, 8ma port 1 mii transmit data bit 2/ port 1 bus mode bit 0 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as p1busmd0.this pin will become p1rxd2 if p1busmd[1:0] is 11. synchrono us to the rising edge of txclk. p1busmd[1:0] interface 00 b , mii (power down tx phy) 01 b , rmii (power down tx phy) 10 b , gpsi (power down tx phy) 11 b , tp/fx (default) 53 p1txd3/p1bus md1 i/o ttl, pu, 8ma port 1 mii transmit data bit 3/ port 1 bus mode bit 1 during power on reset, value will be latched by adm6993/x at the rising edge of resetl as p1busmd1.this pin will become p1rxd3 if p1busmd[1:0] is 11. synchrono us to the rising edge of txclk. p1busmd[1:0] interface 00 b , mii (power down tx phy) 01 b , rmii (power down tx phy) 10 b , gpsi (power down tx phy) 11 b , tp/fx (default) 59 p1txen o ttl, pd, 8ma port 1 mii transmit enable this pin will become p1rxdv if p1busmd[1:0] is 11. synchronous to the rising edge of txclk idle_mode idel_mode during power on reset, value will be latched by adm6993/x at the rising edge of resetl as hdlc idle frame control mode. idle_mode idle pattern 0 b , ff h (default) 1 b , 7e h
data sheet 15 rev 1.11, 2005-11-28 adm6993/x interface de scription 83 p1rxd_3 i ttl, pd port 1 mii receive data bit 3 ~ 0 these pins will become p1txd[3: 0] if p1busmd[1:0] is 11 82 p1rxd_2 81 p1rxd_1 80 p1rxd_0 60 p1rxdv i ttl, pd port 1 mii receive data valid this pin will become p1txen if p1busmd[1:0] is 11 111 p1col i/o ttl, pd port 1 mii collision input this pin will become p1col if p1busmd[1:0] is 11 and becomes an output pin 112 p1crs i/o ttl, pd port 1 mii carrier sense this pin will become p1crs if p1busmd[1:0] is 11 and becomes an output pin 61 p1rxclk i/o ttl, pd port 1 mii receive clock input this pin will become p1crs if p1busmd[1:0] is 11 and becomes an output pin 58 p1txclk i/o ttl, pd port 1 mii transmit clock input this pin will become p1crs if p1busmd[1:0] is 11 and becomes an output pin. 117 p1linkf i ttl, pu port 1 link fail status this pin will be used to input th e link status of port1 if port1 is not connected to internal phy 1 b , link fail 120 p1spdten i ttl, pd port 1 speed status this pin will be used as port 1 speed status input if port1 is not connected to internal phy 1 b , 10m 121 p1dphalf i ttl, pd port 1 duplex status this pin will be used as port 2 duplex status input if port1 is not connected to internal phy 1 b , half duplex table 6 port 1 alternative mii port interface (17 pins) (cont?d) pin or ball no. name pin type buffer type function
adm6993/x interface de scription data sheet 16 rev 1.11, 2005-11-28 table 7 led interface (13 pins) pin or ball no. name pin type buffer type function 113 lnkact_0 i/o ttl pd 8ma port0 link & active led/link led. if ledmode_0 is 1, this pin indicates both link status and rx/tx activity. when link status is link_up, lnkact_0 will be turned on. while port0 is receiving /transmitting data, lnkact_0 will be off for 100ms and then on for 100ms. if ledmode_0 is 0, this pin only indicates rx/tx activity. led_data_0 port0 led data ledmode_0 led mode for link/act led of port0. during power on reset, value will be latched by adm6993/x at the rising edge of r esetl as ledmode_0. 114 lnkact_1 i/o ttl pd 8ma port1 link & active led/link led. if ledmode_2 is 1, this pin indicates both link status and rx/tx activity. when link status is link_up, lnkact_1 will be turned on. while port1 is receiving /transmitting data, lnkact_1 will be off for 100ms and then on for 100ms. if ledmode_2 is 0, this pin only indicates rx/tx activity. led_data_1 port1 led data ledmode_1 led mode duplex/col led of port0 & port1. during power on reset, value will be latched by adm6993/x at the rising edge of r esetl as ledmode_1. if ledmode_1 is 1, dupcol[1:0] will display both duplex condition and collision status. if ledmode_1 is 0, only co llision status will be displayed. 30 ledmode_2 i ttl pd led mode for link/act led of port1 0 b , act 1 b , link/act 124 dupcol_0 i/o ttl pd 8ma port0 duplex led if ledmode_1 is 1, this pin indicates both duplex condition and collision status. when full_dupl ex, this pin will be turned on for port0. when half_duplex and no collision occurs, this pin will be turned off. when half_duplex and a collision occurs, this pin will be off fo r 100ms and then on for 100ms. if ledmode_1 is 0, this pin in dicates collision status. when in half_duplex and a collision occurs, this pin will be off for 100ms and turn on for 100ms. led_col_0 port0 collision led dis_learn disable address learning. during power on reset, value will be latched by adm6993/x at the rising edge of resetl as dis_ learn. if dis_learn is 1, mac address learning will be disabled.
data sheet 17 rev 1.11, 2005-11-28 adm6993/x interface de scription 125 dupcol_1 /led_col_1 i/o ttl pu 8ma port1 duplex if ledmode_1 is 1, this pin indicates both duplex condition and collision status. when full_dupl ex, this pin will be turned on for port1. when half_duplex and no collision occurs, this pin will be turned off. when half_duplex and a collision occurs, this pin will be off for 100ms and then on for 100ms. if ledmode_1 is 0, this pin in dicates collision status. when half_duplex and a collision occurs, this pin will be off for 100ms and turn on for 100ms. 122 ldspd_0 i/o ttl pu 8ma port0 speed led used to indicate speed status of port0. when operating in 100mbps this pin is turned on, and when operating in 10mbps this pin is off. rdnt_en enable redundant capability during power on reset, value will be latched by adm6993/x at the rising edge of resetl as rdnt_en. if rdnt_en is 0, ?redundant? capability will be disabled. for ts1000 application this pin should have a value of 0. 123 ldspd_1 i/o ttl pu 8ma port1 speed led used to indicate speed status of port1. when operating in 100mbps this pin is turned on, and when operating in 10mbps this pin is off. led_fiber_sd led_fiber_sd used to indicate signal status of port1 when adm6993/x is operating in converter mode. snp_en enable snooping mode during power on reset, value will be latched by adm6993/x at the rising edge of resetl as snp_en. if snp_en is 0, ?snooping? capability will be disabled. 1 led_link_1 o ttl 8ma port[1:0] link led these pins indicate link status. when link status is link_up, these pins will be turned on for relevant port. 128 led_link_0 3 led_full_1 o ttl 8ma port[1:0] full duplex led these pins indicate current duplex condition of port0. when full_duplex, these pins will be turned on for relevant port. when half_duplex these pins will be turned off for relevant port. 2 led_full_0 4 led_lpbk o ttl 8ma loop back test led while performing loop back test this pin is turned on. table 7 led interface (13 pins) (cont?d) pin or ball no. name pin type buffer type function
adm6993/x interface de scription data sheet 18 rev 1.11, 2005-11-28 table 8 eeprom interface (4 pins) pin or ball no. name pin type buffer type function 7 eedo i ttl pu eeprom data output serial data input fr om eeprom. this pin is internal pull-up. 12 eecs i/o pd 4ma eeprom chip select this pin is active high chip enabled for eeprom. when resetl is low, it will be tristate. 11 eeck i/o ttl pu 4ma serial clock this pin is the eeprom clock source. when resetl is low, it will be tristate. this pin is internal pull-up. 8 eedi i/o ttl pu 4ma eeprom serial data input this pin is the output for serial data transfer. when resetl is low, it will be tristate. table 9 configuration interface (28 pins) pin or ball no. name pin type buffer type function 16 p0_andis i ttl pd auto-negotiation disable for port0 0 b e , enable 1 b d , disable 17 p0_rechalf i ttl pd recommend half duplex communication for port0 0 b f , full 1 b h , half 18 p0_rec10 i ttl pd recommend 10m for port0 0 b 100 , 100m 1 b 10 , 10m 19 p0_fcdis i ttl pd flow control disable for port0 0 b e , enable 1 b d , disable 22 p1_andis i ttl pd auto-negotiation disable for port1 0 b e , enable 1 b d , disable 23 p1_rechalf i ttl pd recommend half duplex communication for port1 0 b f , full 1 b h , half 24 p1_rec10 i ttl pd recommend 10m for port1 0 b 100 , 100m 1 b 10 , 10m 25 p1_fcdis i ttl pd flow control disable for port1 0 b e , enable 1 b d , disable 63 p2_fcdis i ttl pd flow control disable for port2 0 b e , enable 1 b d , disable
data sheet 19 rev 1.11, 2005-11-28 adm6993/x interface de scription 67 xoven i ttl pd auto-mdix enable. 0 b d , disable 1 b e , enable 68 p0_mdi i ttl pu mdi/mdix control for port0 this setting will be igno re if enable auto-mdix. 0 b mdix , mdix 1 b mdi , mdi 21, 20 ftpr_mode[1: 0 i ttl pd fault propagation mode 00 b r , reserved 01 b fx , fx fail -> utp fail, ut p fail -> fx transmit fefi 10 b r , reserved 11 b d , disable 99 lpbk_p0 i ttl pd enable loop back test for port0 0 b d , disable 1 b e , enable 98 lpbk_p1 i ttl pd enable loop back test for port1 0 b d , disable 1 b e , enable 97 lpbk_p2 i ttl pd enable loop back test for port2 0 b d , disable 1 b e , enable 101 chip_dis i ttl pd chip disable 0 b d , disable 1 b e , enable 100 cas_dis o ttl 4ma disable cascaded chip 0 b d , disable 1 b e , enable 102 lpt_dis i ttl pd link pass through disable 0 b e , enable 1 b d , disable 29 bypass_paus e i ttl pd bypass frame the destination address is reserved ieee mac address 0 b d , disable 1 b e , enable table 10 ground/power interface (27 pins) pin or ball no. name pin type buffer type function 42, 48 gndtr gnd, a ground used by ad receiver/transmitter block. 39, 51 vcca2 pwr, a 2.5 v used for analogue block 45 vccad pwr, a 3.3 v used for tx line driver table 9 configuration interface (28 pins) (cont?d) pin or ball no. name pin type buffer type function
adm6993/x interface de scription data sheet 20 rev 1.11, 2005-11-28 36 gndbias gnd, a ground used by digital substrate 38 vccbias pwr, a 3.3 v used for bios block 33 gndpll gnd, a ground used by pll 32 vccpll pwr, a 2.5 v used for pll 13, 52, 64, 89, 109, 110 gndik gnd, d ground used by digital core and pre-driver 9, 10, 57, 91, 115, 116 vccik pwr, d 2.5 v used for digital core and pre-driver 77, 118, 119 gndo gnd, d ground used by digital pad 79, 126, 127 vcc3o pwr, d 3.3 v used for digital pad. table 11 miscellaneous (14 pins) pin or ball no. name pin type buffer type function 6 int o ttl od 4ma interrupt this pin will be used to interrupt external management device. this is a low active and open drain pin. 15 sdio i/o ttl pu 8ma serial management data this pin is in/out to phy. wh en resetl is low, this pin will be tristate. 14 sdc i ttl 8ma serial manageme nt data clock 78 cko25m o ttl pu 8ma 50m output for rmii and 25m clock output for others 34 control ao fet control signal the pin is used to control fet for 3.3 v to 2.5 v regulator. 37 rtx a tx resistor 35 vref a analog power failure detected 26 rc i ttl st rc input for power on reset adm6993/x sample pin rc as resetl with the clock input from pin xi. 27 xi ai 25m crystal input 25m crystal input. variation is limited to +/- 50ppm. table 10 ground/power interface (27 pins) (cont?d) pin or ball no. name pin type buffer type function
data sheet 21 rev 1.11, 2005-11-28 adm6993/x interface de scription 2.4 port 2 mii/rm ii/gpsi/hdlc interfaces comparison adm6993/x doesn't provide mdc/mdio to access external phy, but provides pxlinkf, pxspdten, and pxdphalf to update mac status from external phy link/speed/dup lex led pin.pxlinkf, input = 1 b means unlink, 0 b means link.pxspdten, input = 1 b means 10mbps, 0 b means 100mbps.pxdphalf, input = 1 b means half duplex, 0 b means full duplex. 28 xo ao 25m crystal output when connected to oscillator, th is pin should left unconnected. 5, 31, 62, 65, 66, 69, 70, 71, 72, 73, 74, 75, 76 nc no connection table 12 port 2 mii/rmii/gpsi/hdl c interfaces comparison pin no. mii rmii gpsi hdlc 87 p2txd0(o) p2txd0(o) p2txd0(o) p2txd0(o) 86 p2txd1(o) p2txd1(o) 85 p2txd2(o) 84 p2txd3(o) 88 p2txen(o) p2txen(o) p2txe(o) no support p2txer(o) 90 p2txclk(i) p2rxclk(i) p2rxclk(i) 105 p2rxd0(i) p2rxd0(i) p2rxd0(i) p2rxd0(i) 106 p2rxd1(i) p2rxd1(i) 107 p2rxd2(i) 108 p2rxd3(i) 104 p2rxdv(i) p2crs_dv(i) p2rxe/crs(i) no support p2rxer(i) p2rxer(i) 93 p2col(i) p2col(i) 92 p2crs(i) 103 p2rxclk(i) p2refclk(i) p2rxclk(i) p2rxclk(i) port status 96 p2linkf(i) p2linkf(i) p2linkf(i) p2linkf(i)=?0? 95 p2spdten(i) p2spdten(i) p2spdten(i) 94 p2dphalf(i) p2dphalf(i) p2dphalf(i) table 11 miscellaneous (14 pins) (cont?d) pin or ball no. name pin type buffer type function
adm6993/x function description data sheet 22 rev 1.11, 2005-11-28 3 function description the adm6993/x integrates a two 100base-x physical la yer device (phy), two complete 10base-t modules, a 3- port 10/100 switch controller and memo ry into a single chip for both 10 mbps and 100 mbps ethernet switch operations. it also supports 100base-fx operation through ex ternal fiber-optic transceivers. the device is capable of operating in either full-duplex or half-duplex mode in both 10 mbps and 100 mbps operations. operation modes can be selected by hardware configuration pins, soft ware settings of management registers, or determined by the on-chip auto negotiation logic. the adm6993/x consists of four major blocks: ? 10/100m phy block ? switch controller block ? built-in 6kx64 ssram 3.1 10/100m phy block the 100base-x section of the device im plements the following functional blocks: ? 100base-x physical coding sub-layer (pcs) ? 100base-x physical medium attachment (pma) ? 100base-x physical medium dependent (pmd) the 10base-t section of the device implements the following functional blocks: ? 10base-t physical layer signaling (pls) ? 10base-t physical medium attachment (pma) the 100base-x and 10base-t sections share the following functional blocks: ? clock synthesizer module ? mii registers ? ieee 802.3u auto negotiation the interfaces used for the communication between th e phy block and the switch core is a mii interface. an auto mdix function is supported. this function can be enabled/disabled by using the hardware pin. a digital approach for the integrated phy of the adm6993/x has been adopted.
data sheet 23 rev 1.11, 2005-11-28 adm6993/x function description 3.2 auto negotiation a nd speed configuration 3.2.1 auto negotiation the auto negotiation function provides a mechanism fo r exchanging configuration information between two ends of a link segment and automatically selecting the highes t performance mode of operat ions supported by both devices. fast link pulse (flp) bu rsts provide the signa ling used to communicate auto negotiation abilities between two devices at each end of a link segment. for further detail regarding auto negotiation, refer to clause 28 of the ieee 802.3u specification. the adm6993/x supports four different ethernet protocols, so the inclusion of auto negotiation ensures that the highest perfor mance protocol will be selected ba sed on the ability of the link partner. the auto negotiation function within the adm6993/x can be co ntrolled either by internal register access or by the use of configuration pins. if disabled, auto negotiation will not occur until software enables bit 12 in mii register 0. if auto negotiatio n is enabled, the negotiation process will commence immediately. when auto negotiation is enabled, the adm6993/x transmits the abilities programme d into the auto negotiation advertisement register at address 04 h via flp bursts. any combination of 10 mbps, 100 mbps, half duplex, and full duplex modes may be selected. auto negotiation cont rols the exchange of config uration information. upon successfully auto negotiating, the abilities reported by the link partner are stored in the auto negotiat ion link partner ability register at address 05 h . the contents of the ?auto negotiation link partner ability re gister? are used to automatically configure the highest performance protocol between the local and far-end nodes. software can determine which mode has been configured by auto negotiation, by comparing the contents of register 04 h and 05 h and then selecting the technology whose bit is set in both registers of highest priority relative to the following list: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register at address 0 h controls the enabling, disabling and restarting of the auto negotiation function. when auto negotiati on is disabled, the speed selection bi t (bit 13) controls switching between 10 mbps or 100 mbps operation, while the duplex mode bi t (bit 8) controls switching between full duplex operation and half duplex operation. the speed selection and duple x mode bits have no effect on the mode of operations when the auto negotiation enable bit (bit 12) is set. the basic mode status register at address 1 h indicates the set of available abilitie s for technology types (bit 15 to bit 11), auto negotiation ability (bit 3) , and extended register capab ility (bit 0). these bits ar e hardwired to indicate the full functionality of the adm6993/x. the bmsr also provides status on: ? whether auto negotiation is complete (bit 5) ? whether the link partner is advertising th at a remote fault has occurred (bit 4) ? whether a valid link has been established (bit 2) the auto negotiation advertis ement register at address 4 h indicates the auto negotiati on abilities to be advertised by the adm6993/x. all available abilitie s are transmitted by default, but writin g to this register or configuring external pins can suppress any ability. the auto negotiation link partner ability register at address 05 h indicates the abilities of the link partner as indicated by auto negotiation communica tion. the contents of this register are considered valid when the auto negotiation complete bit (bit 5, register address 1 h ) is set. 3.2.2 speed configuration the twelve sets of four pins listed in table 13 configure the speed capability of each channel of the adm6993/x. the logic states of these pins are latched into the advertisement register (register address 4 h ) for auto negotiation
adm6993/x function description data sheet 24 rev 1.11, 2005-11-28 purpose. these pins are also used for evaluating the default value in the base mode control register (register 0 h ) according to table 13 . in order to make these pins with the same read/write priority as software, they should be programmed to 11111111 b in case a user wishes to update the advertisement register through software. 3.3 switch functional description the adm6993/x uses a ?store & forward? switching approach for the following reason: store & forward switches allow switching between diff erent speed media (e.g. 10basex and 100basex). such switches require the large elastic bu ffer especially bridging between a serv er on a 100mbps network and clients on a 10mbps segment. store & forward switches improve overall network performance by acting as a ?network cache? store & forward switches prevent the forwarding of corr upted packets by the frame check sequence (fcs) before forwarding to the destination port. 3.3.1 basic operation the adm6993/x receives incoming packets from one of its ports, searches in the address table for the destination mac address and then forwards the packet to the other port within the same vlan group, if appropriate. if the destination address is not found in the address table, the adm6993/x treats the packet as a broadcast packet and forwards the packet to the other ports which in the same vlan group. table 13 speed configuration advertis e all capabilit y advertis e single capabili ty paralle l detect follow ieee std. auto negoti- ation (pin & eeprom) speed (pin & eeprom ) duplex (pin & eeprom ) auto negot iation advertise capability parallel detect capability 10 0f 10 0h 10 f 10 h 10 0f 10 0h 10 f 10 h 1 0 0 1 x x 1 1 1 1 1 1 0 1 0 1 0 1 1 x x 1 1 1 1 1 0 1 0 1 1 1 0 1 x x 1 1 0 0 0 1 0 0 0 1 1 1 1 x x 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 x 1 1 0 1 0 1 0 1 0 1 0 1 0 1 x 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 x x 1 0 0 1 0 0 0 1 0 0 0 1 x x x 0 1 1 0 1 ? ? ? ? ? ? ? x x x 0 1 0 0 ? 1 ? ? ? ? ? ? x x x 0 0 1 0 ? ? 1 ? ? ? ? ? x x x 0 0 0 0 ? ? ? 1 ? ? ? ?
data sheet 25 rev 1.11, 2005-11-28 adm6993/x function description the adm6993/x automatically learns the port number of attached network devices by examining the source mac address of all incoming packets at wire speed. if the sour ce address is not found in the address table, the device adds it to the table. 3.3.2 address learning the adm6993/x uses a hash algorithm to learn the mac address and can learn up to 2k mac addresses. address is stored in the address table. the adm6993/x searches for the source address (sa) of an incoming packet in the address table and acts as below: if the sa was not found in the address table (a new address), the adm6993/x waits until the end of the packet (non-error packet) and updates the address table. if the sa was found in the address table, then aging value of each corresponding entry will be reset to 0. when the da is pause command, then the learning pr ocess will be disabled au tomatically by adm6993/x. 3.3.3 address recognition and packet forwarding the adm6993/x forwards the incoming packets between bri dged ports according to the destination address (da) as below. all the packet forwarding will check vlan first. a forwarding port mu st be within the same vlan as the source port. 1. if the da is an unicast address and the address was found in the ad dress table, the adm6993/x will check the port number and acts as follows: a) if the port number is equal to the port on which the packet was received, the packet is discarded. b) if the port number is different, th e packet is forwarded across the bridge. 2. if the da is an unicast address and the address wa s not found, the adm6993/x treats it as a multicast packet and forwards across the bridge. 3. if the da is a multicast address, the packet is forwarded across the bridge. 4. if the da is pause command (0 1-80-c2-00-00-01), then this pa cket will be dropped by adm6993/x. adm6993/x can issue and learn pause command. 5. adm6993/x will forward by de faulted or filtering out th e packet with da of (01-80-c 2-00-00-00), discarding the packet with da of (01-80-c2-00-00-01), filtering out th e packet with da of (01-80-c2-00-00-02 ~ 01-80-c2-00- 00-0f), and forwarding the packet with da of (01- 80-c2-00-00-10 ~ 01 -80-c2-00-00-ff) de cided by eeprom reg.7 h . 3.3.4 address aging address aging is supported for topology changes such as an address moving from one port to the other. when this happens, the ad m6993/x internally has a 300 seconds timer will aged out (remove) th e address from the address table. aging function can be enabled/disabled by user. normally, dis abling aging function is for security purpose. 3.3.5 buffers and queues the adm6993/x incorporates transmitted queues and the receiving buffer area for the three ethernet ports. the receiving buffers as well as the transmitted queues are located within the adm69 93/x along with the switch fabric. the buffers are divided into 192 blocks of 256 bytes each. the queues of each port are managed according to each port's read/write pointer. 3.3.6 back off algorithm the adm6993/x implements the truncated exponential ba ck off algorithm compliant to the ieee802.3 csma/cd standard. adm6993/x will restart the back off algorith m by choosing 0-9 collision c ounts. the adm6993/x resets the collision counter after 16 consecutive retransmit trials.
adm6993/x function description data sheet 26 rev 1.11, 2005-11-28 3.3.7 inter-packet gap (ipg) ipg is the idle time between any two successive packets from the same port. the typical number is 96-bits time. the value is 9.6 s for 10mbps ethernet, and 960ns for 100mbps fast ethernet. adm6993/x provides the option of a 92-bit gap in eeprom to prevent packet lost when flow control is turned off and clock p.p.m. value differs. 3.3.8 illegal frames the adm6993/x will discard all illegal frames such as runt packet (less than 64 bytes), oversize packet (greater than 1518 or 1522 bytes) and bad crc. dribbling packing with good crc value will accept by adm6993/x. in case of bypass mode enabled, adm6993/x will support tagg ed up to 1522bytes, and unta gged packets up to 1518 bytes. in case of non-by pass mode, adm6993/x will su pport tagged packets up to 1522 bytes, and untagged packets up to 1518 bytes. 3.3.9 half duplex flow control back pressure function is supported for half-duplex oper ation. when the adm6993/x c annot allocate a receiving buffer for an incoming packe t (buffer full), the device will tr ansmit a jam pattern on the por t, thus forcing a collision. back pressure is enabled by the bpen set during rese t asserting. an infineon-ad mtek co ltd proprietary algorithm is implemented inside the adm6993/x to prevent back pressure function causing hub partitioned under heavy traffic environment and reduce the packet lo st rate to increase the whole system performance. 3.3.10 full duplex flow control when full duplex port runs out of its receiving buffer, a pause packet co mmand will be issued by adm6993/x to notice the packet sender to pause the transmission. this frame based flow control is totally compliant to ieee 802.3x. adm6993/x can issue or receive pause packet. 3.3.11 broadcast storm filter if broadcast storming filter is enable, the broadcast packet s over the rising threshold within 50 ms will be discarded by the threshold setti ng. see eeprom reg.5 h . broadcast storm mode after initial: time interval: 50 ms the max. packet number = 7490 in 100base, 749 in 10base table 14 port rising/falling threshold per port rising threshold 00 01 10 11 all 100tx disable 10% 20% 40% not all 100tx disable 1% 2% 4% per port falling threshold 00 01 10 11 all 100tx disable 5% 10% 20% not all 100tx disable 0.5% 1% 2%
data sheet 27 rev 1.11, 2005-11-28 adm6993/x function description 3.3.12 auto tp mdix function at normal application which switch conn ect to nic card is by one by one tp cable. if switch connects other device such as another switch must by two way. first one is cr oss over tp cable. second way is to use extra rj45 which crossover internal tx+- and rx+- signal. by second way customers can use one by one cable to connect two switch devices. all these efforts need extra cost and are not good solutions. adm6993 /x provides auto mdix function which can adjust tx+- and rx+- at correct pi n. users can use one by one cable between adm6993/x and other device either switches or nics. 3.4 converter functional description 3.4.1 fault propagation the adm6993/x media converter incorpor ates a fault propagation feature, wh ich allows indirect sensing of a fiber link loss via the 10/100base-tx utp connection. whenever the adm6993/x media converter detects a link loss condition on the receive fiber (fiber lnk off) , it disables its utp link pulse so that a link loss condition will be sensed on th e utp port to which the ad m6993/x media converter is connected. th is link loss can then be sensed and reported by a network management agent in the remote utp port's host equipment. this feature will affect the adm6993/x utp lnk led. the adm6993/x media converter also incorporates a far en d fault feature, which allows the stations on both ends of a pairs of fibers to be informed when there is a problem with one of th e fibers. without far end fault, it is impossible for a fiber interface to detect a problem that affects only its transmitting fiber. when far end fault is su pported and e nabled, a loss of received signal (link) will cause th e transmitter to generate a far end fault pattern in order to inform the device at the far end of the fiber pair that a fault has occurred. unless fiber link loss occurred, if the ut p port link failed, the adm6993/x media converter will also generate a far end fault pattern in order to inform the device at the fa r end of the fiber pair that a fault has occurred. 3.4.2 redundant link the adm6993/x media converter incorporates a redundant link feature, which allows designing a cost-effective redundant tx fx media converter to provide a more reliable fiber link. at converter mode (fxmode[1:0]=10 and rdnt_en=1), pin cas_dis of primary adm6993/x connects to pin chip_dis of secondary adm6993/x. ? while fx port works well, pin c as_dis will output ?1? to disable 2 nd adm6993/x ? while fx fiber link loss or the remote fault detection happens, pin cas_dis will ou tput ?0? to enable 2 nd adm6993/x. ? while adm6993/x disable, tx port will become hi-z state. table 15 drop scheme for each queue drop scheme for each queue discard mode utilization 00 01 10 11 00 0% 0% 0% 0% 01 0% 0% 25% 50% 11 0% 25% 50% 75%
adm6993/x function description data sheet 28 rev 1.11, 2005-11-28 3.4.3 loop-back mode the adm6993/x media converter incorporates a loop-bac k mode, which allows users or isp to diagnose the local or the remote network equipment. the loop-back is used to check the operation of the switch and ensure the device's connection on the media side. ? while lpbk_p0=1, the received data fr om port 1/port 2 will be routed thro ugh the receiving path back to the transmitting path on port 0 mii interface (between switch core and embedded port 0 phy). ? while lpbk_p1=1, the received data fr om port 0/port 2 will be routed thro ugh the receiving path back to the transmitting path on port 1 mii interface (between switch core and embedded port 1 phy). ? while lpbk_p2=1, the received data fr om port 0/port 1 will be routed thro ugh the receiving path back to the transmitting path on port 2 mii interface. note: the address learning, packet filter, crc check, le ngth check and loop-back function are not performed in snooping mode. 3.4.4 snooping mode the adm6993/x media converter incorporates a snoopi ng mode, which allows packets perform cut-through between tx<-->fx while both tx and fx ports operat e on 100m full mode. on snoo ping mode, the packets will not enter the switch core to perform store and forward mechanisms. ? while snp_en=1, the adm6993/x tx fx media conver ter will act tx<-->fx bridge while both tx and fx ports operate on 100m mode. ? while snp_en=0, the adm6993/x tx fx media converter will fo rce all packets to enter the switch core to perform store and forward mechanisms. 3.4.5 fiber_sd led the adm6993/x media converter provides a fiber_sd le d on original ldspd_1 pin. fiber_sd is used to indicate the signal status of the fiber port. 3.5 serial management interf ace (smi) register access the smi consists of two pins, management data clock (sdc) and management data input/output (sdio). the adm6993/x is designed to support an sdc frequency up to 25 mhz. the sdio line is bi-directional and may be shared with other devices. the sdio pin requires a 1.5 k ? pull-up which, during idle and turn ar ound periods, will pull sdio to a logic ?1? state. adm6993/x requires a single initialization sequenc e of 35 bits of preamble following power-up/hardware reset. the first 35 bits are preamble c onsisting of 35 contiguous logic ?1?bits on sdio and 35 corresponding cycles on sdc. following preamble, the start-of-frame field is indicated by a <01> pattern. the next field signals the operation code (op): <10> indicates read from management register operation, and <01> indicates write to management register operation. the next field is manageme nt register address. it is 10 bits wide and the most significant bit is transferred first. table 16 smi read/write command format operation preamble sfd op chipid[1:0] unused register address ta data read 35?1?s 01 10 2 bits 000 5 bits address z0 32 bits data read write 35?1?s 01 01 2 bits 000 5 bits address 10 32 bits data write
data sheet 29 rev 1.11, 2005-11-28 adm6993/x function description during read operation, a 2-bit turn around (ta) time s pacing between the register addr ess field and data field is provided for the sdio to avoid contention. following t he turnaround time, a 32-bit data stream is read from or written into the management registers of the adm6993/x. figure 3 smi read operation figure 4 smi write operation 3.5.1 preamble suppression the smi of adm6993/x supports a preamble suppression mode. if the station management entity (i.e. mac or other management controller) determines that all device s which are connected to the same sdc/sdio in the system support preamble suppression, then the station ma nagement entity needs not generate preamble for each management transaction. the adm6993/x requires a single initialization sequence of 35 bits of preamble following power-up /hardware reset. this requirement is generally met by pullin g-up the resistor of sdio. while the adm6993/x will respond to management accesses without preamble, a minimum of one idle bit between management transactions is required. when adm6993/x detects that there is address match, then it will enable read/write capab ility for external access. when an address is mismatched, then adm6993/x will tri- state the sdio pin. 3.5.2 read eeprom regi ster via smi register the following 2 steps are for reading the data of eeprom register via smi interface. write the address of the desired eeprom regi ster and read command to smi register 04 h ex. <35?1?s><01><01><00000><00100><10>< 000 0000000 000001 0000000000000000 > cmd address data read adm6993/x internal eeprom mapping reg.1 h . read smi register 04. the data of desired eeprom register will be in bit [15:0]. ex. <35?1?s><01><10><00000><00100>< 000 0000000 000000 1000001000001111 > cmd address data get adm6993/x internal eeprom mapping reg.1 h . value 820f. sdc sdio (sta) sdio (ad2109) z 0 1 1 0 0 0 0 0 0 0 0 0 0 0 z 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (read) register address (5'h0 in this example) ta register data (32'h13000000 in this example) ~ ~ smi read operation unused id[1:0] sdc sdio (sta) z 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 z preamble start opcode (write) register address (5'h0 in this example) ta register data (32'h13000000 in this example) 0 ~ ~ smi write operation unused id[1:0]
adm6993/x function description data sheet 30 rev 1.11, 2005-11-28 3.5.3 write eeprom regi ster via smi register to write data into desired eeprom register, write the addr ess of the eeprom register. ex. <35?1?s><01><01><00000><00100><10>< 001 0000000 000001 1000001000001111 > cmd address data write adm6993/x internal eeprom mapping reg.1 h . with value 820f. 3.6 hdlc controller the adm6993/x has an interface to hdlc. the main functi on is to forward ethernet packet from local lan to wan. 3.6.1 hdlc frame receiver a received packet consists of an opening flag, data byte s, a 16-bit crc, and a clos ing flag. the received cycle starts with the detection of data after the opening flag in the packet. after a flag is detected, the hdlc checks the data bit stream for minimum (less then 62 bytes includ ing crc-16) and maximum (more than 1534 bytes including crc-16) packet lengths, ze ro deletion, abort characte rs, and idle characters. hdlc controller will remove crc- 16 2 byte in the received packet before writing to buffer. clocking the hdlc controller receiver gets data from hdlc_rxd at the positive edge of hdlc_rxclk. flag detection the hdlc supports the following received flag (01111110) sequence: multiple flags between packets (.......0111111001111110......) a flag shared as the closing and opening flags between two packets (......data crc 0 1111110 data......) a shared zero between flags (......011111101111110......) all incoming flags are ignored and discarded by the hdlc. the first bit received, which is not a part of the flag character, signifies the start of the packet. if a flag is re ceived during a packet, it indicates the end of the packet. the crc is checked (the last two by tes of the packet ), and a decision is gene rated to forw ard or not. zero deletion each bit received between the opening and closing fl ag is checked for zero bit insertion. a zero that follows five contiguous ones is discarded from the incomi ng bit stream. hdlc is defined this feature to avoid the occurrence of flags in user data field. cyclic redundancy check (crc) the frame check sequence (fcs) consists of 16 bits immediately preceding the closing flag. the 16-bit fcs detects data errors th rough the use of a cycle redundancy check (crc) code. the crc is generated from the incoming data and compared ag ainst the received crc (remainder), carried in the fcs field of the packet. if the comparison does not match beca use of a bit error or burst error, the hdlc discards the packet by flushing the memory buffer regions, and wait s for the next packet to be received. the crc check polynomials are as follows: crc-16: x 16 +x 12 +x 5 +1 3.6.2 hdlc frame transmitter a transmitted packet consists of an opening flag, data byte s, 16-bit crc, and a closing flag. the transmitter timing is asynchronous in relation ship with the receive timing. clocking the hdlc controller transmitter send data to hdlc_txd at the positive edge of external hdlc_txclk. flag generation the hdlc controller generates either (01 111110) or multiple fl ags (011111100 1111110...), depending on the packet data present in the buffer stored by lan interface.
data sheet 31 rev 1.11, 2005-11-28 adm6993/x function description zero insertion the data in the packet read from the buffer is checked for the number of contiguous ones prior to the transmission. a zero is inserted into the transmi tted bit stream after five contiguous ones are detected, excluding flags or abort characters. by this, hdlc can avoid the confusion between flag and data, which has the same value with flag. cyclic redundancy ch eck (crc) generation the frame check sequence (fcs) consists of 16 bits immediately preceding the cl osing flag. the 16-bit fcs detects data errors through the use of a cycle redundancy check (crc) code. when all user data is transmitted, the calculated valu e is transmitted after the last data byte, and encloses the frame with a closing flag. the crc check polynomials are as follows: crc-16: x 16 +x 12 +x 5 +1 3.7 reset operation the adm6993/x can be reset either by hardware or software. a hardware reset is accomplished by applying a negative pulse, with the duration of at least 100 ms to the rc pin of the adm6993/x during normal operation to guarantee internal ssram is reset well. hardware reset operation samples the pins and initializes a ll registers to their default values. this process includes re-evaluation of all hardware configurable registers. a hardware reset affects all embedded phys in the device. software reset can reset all embedded phy and it does not latch the external pins nor reset the registers to their respective default value. this can be achieved by writing ff to eeprom reg.3f h . logic levels on several i/o pins are detected during a hardware reset to determine the initial functionality of adm6993/x. some of these pins are used as output ports after reset operation. care must be taken to ensure that the configuration setup will not interf ere with normal operations. dedicated configuration pins can be tied to vcc or ground directly. configuration pins multiple xed with logic level output functions should be either weakly pulled up or weakly pulled down through external resistors. 3.7.1 write eeprom regist er via eeprom interface to write data into desired eeprom register via eeprom interface: if external eeprom 93c46 or 93c66 exists, any write programming instructions a fter ewen instruction be executed can be updated effe ctively on eeprom content and adm6993/x internal mapping register on the same time. if no external eeprom exists, eecs/eeck/eedi must be kept tri-state at least 100ms after hardware reset. any write programming instructions after ewen instruction be executed can be updated effectively on adm6993/x internal mapping register. please notice that adm6993/x can only identify 93c66-programming instructions if no external eeprom.
adm6993/x registers description data sheet 32 rev 1.11, 2005-11-28 4 registers description this chapter describes de scriptions of eeprom re gisters and smi registers. 4.1 eeprom registers table 17 eeprom register map register bit 15-8 bit 7-0 default value 00 h signature 4154 h 01 h port 0 configuration 820f h 02 h port 1 configuration 820f h 03 h port 2 configuration 820f h 04 h tos priority map low vlan priority map low f0f0 h 05 h miscellaneous configuration 0 c0 06 h miscellaneous configuration 1 82e8 h 07 h miscellaneous configuration 2 1480 08 h port 2 to port map port 1 to port map port 0 to port map 777 h 09 h filter control register 1 filter control register 0 0 h 0a h filter control register 3 filter control register 2 0 h 0b h filter control register 5 filter control register 4 0 h 0c h filter control register 7 filter control register 6 0 h 0d h filter control register 9 filter control register 8 0 h 0e h filter control register 11 filter control register 10 0 h 0f h filter control register 13 filter control register 12 0 h 10 h filter control register 15 filter control register 14 0 h 11 h filter type register 0 0 h 12 h filter type register 1 0 h 13 h filter register 0 0 h 14 h filter register 1 0 h 15 h filter register 2 0 h 16 h filter register 3 0 h 17 h filter register 4 0 h 18 h filter register 5 0 h 19 h filter register 6 0 h 1a h filter register 7 0 h 1b h filter register 8 0 h 1c h filter register 9 0 h 1d h filter register 10 0 h 1e h filter register 11 0 h 1f h filter register 12 0 h 20 h filter register 13 0 h 21 h filter register 14 0 h
data sheet 33 rev 1.11, 2005-11-28 adm6993/x registers description 22 h filter register 15 0 h 23 h pvid and pcid mask of port 0 1 h 24 h pvid and pcid mask of port 0 0 h 25 h pvid and pcid mask of port 1 1 h 26 h pvid and pcid mask of port 1 0 h 27 h pvid and pcid mask of port 2 1 h 28 h pvid and pcid mask of port 2 0 h 29 h tag rule 0 f000 h 2a h tag rule 0 00ff h 2b h tag rule 1 f000 h 2c h tag rule 1 00ff h 2d h tag rule 2 f000 h 2e h tag rule 2 00ff h 2f h tag rule 3 f000 h 30 h tag rule 3 00ff h 31 h tag rule 4 f000 h 32 h tag rule 4 00ff h 33 h tag rule 5 f000 h 34 h tag rule 5 00ff h 35 h tag rule 6 f000 h 36 h tag rule 6 00ff h 37 h tag rule 7 f000 h 38 h tag rule 7 00ff h 39 h miscellaneous configuration 2 0000 h 3a h vendor code[15:0] 0000 h 3b h model number [7:0] vendor code [23:16] 0000 h 3c h vendor code[23:8] 0000 h table 17 eeprom register map (cont?d) register bit 15-8 bit 7-0 default value
adm6993/x registers description data sheet 34 rev 1.11, 2005-11-28 4.2 eeprom regist er descriptions table 18 registers address space module base address end address note eeprom 00 h 3c h table 19 registers overview register short name register long name offset address page number sr signature register 00 h 36 pcr_0 port configuration register 0 01 h 36 pcr_1 port configuration register 1 02 h 37 pcr_2 port configuration register 2 03 h 38 vlan_tos_pmr vlan(tos) priority map register 04 h 39 mc_0 miscellaneous configuration 0 05 h 40 mcr_1 miscellaneous configur ation register 1 06 h 41 mcr_2 miscellaneous configur ation register 2 07 h 42 pbvlan_mr port base vlan port map register 08 h 42 pcfc_1_0 packet filter control register 1 and 0 09 h 44 tftr_0 filter type register 0 11 h 45 tftr_1 filter type register 1 12 h 45 fr_0 filter register 0 13 h 46 fr_1 filter register 1 14 h 46 fr_2 filter register 2 15 h 46 fr_3 filter register 3 16 h 46 fr_4 filter register 4 17 h 46 fr_5 filter register 5 18 h 46 fr_6 filter register 6 19 h 46 fr_7 filter register 7 1a h 46 fr_8 filter register 8 1b h 46 fr_9 filter register 9 1c h 47 fr_10 filter register 10 1d h 47 fr_11 filter register 11 1e h 47 fr_12 filter register 12 1f h 47 fr_13 filter register 13 20 h 47 fr_14 filter register 14 21 h 47 fr_15 filter register 15 22 h 47 pb_id_0_0 port base vlan id and mask 0 of port 0 23 h 48 pb_id_1_0 port base vlan id and mask 1 of port 0 24 h 48 pb_id_0_1 port base vlan id and mask 0 of port 1 25 h 49 pb_id_1_1 port base vlan id and mask 1 of port 1 26 h 49 pb_id_0_2 port base vlan id and mask 0 of port 2 27 h 50 pb_id_1_2 port base vlan id and mask 1 of port 2 28 h 50
data sheet 35 rev 1.11, 2005-11-28 adm6993/x registers description the register is addressed wordwise. tpr_0_0 tag port rule 0 register 0 29 h 51 tpr_1_0 tag port rule 1 register 0 2a h 51 tpr_0_1 tag port rule 0 register 1 2b h 51 tpr_1_1 tag port rule 1 register 1 2c h 52 tpr_0_2 tag port rule 0 register 2 2d h 51 tpr_1_2 tag port rule 1 register 2 2e h 52 tpr_0_3 tag port rule 0 register 3 2f h 51 tpr_1_3 tag port rule 1 register 3 30 h 52 tpr_0_4 tag port rule 0 register 4 31 h 51 tpr_1_4 tag port rule 1 register 4 32 h 52 tpr_0_5 tag port rule 0 register 5 33 h 51 tpr_1_5 tag port rule 1 register 5 34 h 52 tpr_0_6 tag port rule 0 register 6 35 h 51 tpr_1_6 tag port rule 1 register 6 36 h 52 tpr_0_7 tag port rule 0 register 7 37 h 51 tpr_1_7 tag port rule 1 register 7 38 h 52 mcr_3 miscellaneous configur ation register 3 39 h 52 mcr_4 miscellaneous configuration 4 3a h 54 mcr_5 miscellaneous configur ation register 5 3b h 54 mcr_6 miscellaneous configur ation register 6 3c h 54 table 20 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) table 19 registers overview (cont?d) register short name register long name offset address page number
adm6993/x registers description data sheet 36 rev 1.11, 2005-11-28 4.2.1 eeprom register format signature register port configuration register 0 interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the in put signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the in put signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interr upt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be clea red due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 21 registers clock domainsregisters clock domains clock short name description sr offset reset value signature register 00 h 4154 h field bits type description signature 15:0 ro signature 4154 h sig , default (at) table 20 register access types (cont?d) mode symbol description hw description sw ur 6ljqdwxuh
data sheet 37 rev 1.11, 2005-11-28 adm6993/x registers description port configuration register 1 pcr_0 offset reset value port configuration register 0 01 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac anpd 9 rw port 0 auto-negotiation para llel detect follow ieee802.3 0 b b , both 1 b h , half only (default) ansc 8 rw port 0 auto-negotiation advertise single capability 0 b e , expand(default) 1 b s , single pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability uz %0 uz /70 uz $13' uz $16& uz 3%3 uz 35 uz '; uz 63 uz $1( uz )&
adm6993/x registers description data sheet 38 rev 1.11, 2005-11-28 port configuration register 2 pcr_1 offset reset value port configuration register 1 02 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac anpd 9 rw port 1 auto-negotiation para llel detect follow ieee802.3 0 b b , both 1 b h , half only (default) ansc 8 rw port 1 auto-negotiation advertise single capability 0 b e , expand(default) 1 b s , single pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability uz %0 uz /70 uz $13' uz $16& uz 3%3 uz 35 uz '; uz 63 uz $1( uz )&
data sheet 39 rev 1.11, 2005-11-28 adm6993/x registers description vlan(tos) priority map register pcr_2 offset reset value port configuration register 2 03 h 820f h field bits type description bm 15 rw bypass mode(tx packets same as rx) 1 b e , enable ltm 14:10 rw limit total mac 00000 b , disable others b , maximum total mac hm 9 rw hdlc mode 0 b , by-pass pre/sfd 1 b , remove pre/sfd(default) hcm 8 rw hdlc crc mode 0 b , 16 bits crc(default) 1 b , 32 bits crc pbp 7 rw port-base priority pr 6:4 rw priority rule/000 000 b , port base priority 001 b , [tcp,tos,tag] 010 b , [tcp,tag,tos] 011 b , [tag,tcp,tos] 100 b , [tos,tag] 101 b , [tag,tos] dx 3 rw duplex this bit is unused if corresponding po rt is not connected to internal phy 0 b hd , half duplex 1 b fd , full duplex (default) sp 2 rw speed this bit is unused if corresponding po rt is not connected to internal phy 0 b 10m , 10base-t 1 b 100m , 100tx ane 1 rw auto negotiation enable this bit is unused if corresponding po rt is not connected to internal phy 0 b d , disable auto-negotiation 1 b e , enable auto-negotiation. (default) fc 0 rw 802.3x flow control command ability uz %0 uz /70 "" +0 "" +&0 uz 3%3 uz 35 uz '; uz 63 uz $1( uz )&
adm6993/x registers description data sheet 40 rev 1.11, 2005-11-28 note: 0 b : low priority queue. q0; 1 b : high priority queue. q1. the weight rati o is 1:n. the default is q0 for un-tag and none ip frame. miscellaneous configuration 0 vlan_tos_pmr offset reset value vlan(tos) priority map register 04 h f0f0 h field bits type description ip7 15 rw priority of the packet which the precedence field of ip header is 7 ip6 14 rw priority of the packet which the precedence field of ip header is 6 ip5 13 rw priority of the packet which the precedence field of ip header is 5 ip4 12 rw priority of the packet which the precedence field of ip header is 4 ip3 11 rw priority of the packet which the precedence field of ip header is 3 ip2 10 rw priority of the packet which the precedence field of ip header is 2 ip1 9 rw priority of the packet which the precedence field of ip header is 1 ip0 8 rw priority of the packet which the precedence field of ip header is 0 tag7 7 rw priority of the packet which th e priority field of tag is 7 tag6 6 rw priority of the packet which th e priority field of tag is 6 tag5 5 rw priority of the packet which th e priority field of tag is 5 tag4 4 rw priority of the packet which th e priority field of tag is 4 tag3 3 rw priority of the packet which th e priority field of tag is 3 tag2 2 rw priority of the packet which th e priority field of tag is 2 tag1 1 rw priority of the packet which th e priority field of tag is 1 tag0 0 rw priority of the packet which th e priority field of tag is 0 mc_0 offset reset value miscellaneous configuration 0 05 h c0 h uz ,3 uz ,3 uz ,3 uz ,3 uz ,3 uz ,3 uz ,3 uz ,3 uz 7$* uz 7$* uz 7$* uz 7$* uz 7$* uz 7$* uz 7$* uz 7$* uz '0 uz 9/$1 uz 3/ uz 345 "" 0$' "" 6& uz ,3* "" (&& "" '%2 uz %6( uz %67
data sheet 41 rev 1.11, 2005-11-28 adm6993/x registers description miscellaneous configuration register 1 field bits type description dm 15:12 rw discard mode (drop scheme for each queue) vlan 11 rw enable replace vlan id 0 &1 by pvid pl 10 rw packet length 0 b , 1536 1 b , 1518 pqr 9:8 rw priority queue ratio 00 b , 1:2 01 b , 1:4 10 b , 1:8 11 b , 1:16 mad 7 rw disable mcc_average 1 b d , disable mcc average sc 6 rw swclk(switch rxclk to txclk for 7-wire) ipg 5 rw ipg leveling 0 b , 96bt(default) 1 b , 92bt ecc 4 rw xcrc 0 b xcrcchk , enable crc check dbo 3 rw disable back-off 1 b d , disable back-off bse 2 rw broadcast storming enable bst 1:0 rw broadcast storming threshold[1:0] mcr_1 offset reset value miscellaneous configuration register 1 06 h 82e8 h field bits type description res 15:11 ro reserved et 10 rw enable tenlmt 1 b e , enable cdp 9 rw check the destination port is in the same vlan group 1 b e , enable res 8:3 ro reserved dffe 2 rw disfefi(disable far end fault/0) ur 5hv uz (7 uz &'3 ur 5hv uz '))( uz '3 uz $'
adm6993/x registers description data sheet 42 rev 1.11, 2005-11-28 miscellaneous configuration register2 note: 1. learning mode: 00 b : group 0(default), 01 b : group 1, 1x b : according to bit 0 of received vid(bit 0 is used to set the learning group of untag packet 2. packet filtering mode: 00 b : forward, 01 b : discard, 10 b : forward the packet to cpu po rt(defined in bit [7:6] of register 07 h ). if this packet is received from cpu port, this packet will be forward to the vlan group. 11 b : forward the packet to cpu port. if this packet is received from cpu po rt, this packet will be discard. port base vlan port map register dp 1 rw discard packet after 16th collision 0 b d , don?t discard ad 0 rw aging disable 0 b e , enable aging mcr_2 offset reset value miscellaneous configuration register 2 07 h 1480 h field bits type description pfm1 15:14 rw packet filtering mode for received da= 01 80 c2 00 00 10 ~ 01 80 c2 00 00 ff pfm2 13:12 rw packet filtering mode for received da= 01 80 c2 00 00 02 ~ 01 80 c2 00 00 0f pfm3 11:10 rw packet filtering mode for received da= 01 80 c2 00 00 01 and opcode!= pause pfm4 9:8 rw packet filtering mode for received da= 01 80 c2 00 00 00 cpn 7:6 rw cpu port number lm2 5:4 rw learning mode of port 2 lm1 3:2 rw learning mode of port 1 lm0 1:0 rw learning mode of port 0 pbvlan_mr offset reset value port base vlan port map register 08 h 777 h field bits type description uz 3)0 uz 3)0 uz 3)0 uz 3)0 uz &31 uz /0 uz /0 uz /0
data sheet 43 rev 1.11, 2005-11-28 adm6993/x registers description field bits type description led 15 rw put off leds of utp port 0 b , always put off leds of utp port when utp link down 1 b , leds of utp port show dipsw setting when auto-negotiation disable and link down res 14:13 ro reserved lp 12 rw link partner 0 b , if auto-negotiation enable, follow speed and duplex setting to negotiate with link partner. 1 b , if auto-negotiation enable, alwa ys advertise full capability to its link partner. res 11 ro reserved pm2 10:8 rw port 2 to port map res 7 ro reserved pm1 6:4 rw port 1 to port map res 3 ro reserved pm0 2:0 rw port 0 to port map uz /(' ur 5hv uz /3 ur 5hv uz 30 ur 5hv uz 30 ur 5hv uz 30
adm6993/x registers description data sheet 44 rev 1.11, 2005-11-28 packet filter control registers 1 and 0 note: op code bit[4:3] 00 b : priority. priority is defined in op code bit[2:0] ; 01 b : discard. op code bit[2:0] is reserved and should keep always 0; 1x b : reserved. pcfc_1_0 offset reset value packet filter control register 1 and 0 09 h 0000 h field bits type description apr2 15 rw apply to port 2 rx 0 b dna , do not apply 1 b apl , apply apr1 14 rw apply to port 1 rx 0 b dna , do not apply 1 b apl , apply apr0 13 rw apply to port 0 rx 0 b dna , do not apply 1 b apl , apply op14 12:8 rw op code for filter defined in register 14 h (16 h , 18 h , 1a h , 1c h , 1e h , 20 h , 22 h ) apr2 7 rw apply to port 2 rx 0 b dna , do not apply 1 b apl , apply apr1 6 rw apply to port 1 rx 0 b dna , do not apply 1 b apl , apply apr0 5 rw apply to port 0 rx 0 b dna , do not apply 1 b apl , apply op13 4:0 rw op code for filter which defined in register 13 h (15 h , 17 h , 19 h , 1b h , 1d h , 1f h , 21 h ) uz $35 uz $35 uz $35 uz 23 uz $35 uz $35 uz $35 uz 23
data sheet 45 rev 1.11, 2005-11-28 adm6993/x registers description filter type register 0 note: 00 b : tcp/udp port number; 01 b : ip protocol id; 10 b : ethernet type; 11 b : reserved filter type register 1 tftr_0 offset reset value filter type register 0 11 h 0000 h field bits type description tf_7 15:14 rw type of filter 7 tf_6 13:12 rw type of filter 6 tf_5 11:10 rw type of filter 5 tf_4 9:8 rw type of filter 4 tf_3 7:6 rw type of filter 3 tf_2 5:4 rw type of filter 2 tf_1 3:2 rw type of filter 1 tf_0 1:0 rw type of filter 0 tftr_1 offset reset value filter type register 1 12 h 0000 h field bits type description tf_15 15:14 rw type of filter 15 tf_14 13:12 rw type of filter 14 uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b uz 7)b
adm6993/x registers description data sheet 46 rev 1.11, 2005-11-28 note: 00 b : tcp/udp port number; 01 b : ip protocol id; 10 b : ethernet type; 11 b : reserved filter register 0 other filter registers have the same structure and characteristics as filter register 0 ; the offset addresses are listed in table 22 . tf_13 11:10 rw type of filter 13 tf_12 9:8 rw type of filter 12 tf_11 7:6 rw type of filter 11 tf_10 5:4 rw type of filter 10 tf_9 3:2 rw type of filter 9 tf_8 1:0 rw type of filter 8 fr_0 offset reset value filter register 0 13 h 0000 h field bits type description filter 15:0 rw filter table 22 other filter regsiters register short name register long name offset address page number fr_1 filter register 1 14 h fr_2 filter register 2 15 h fr_3 filter register 3 16 h fr_4 filter register 4 17 h fr_5 filter register 5 18 h fr_6 filter register 6 19 h fr_7 filter register 7 1a h fr_8 filter register 8 1b h field bits type description uz )lowhu
data sheet 47 rev 1.11, 2005-11-28 adm6993/x registers description fr_9 filter register 9 1c h fr_10 filter register 10 1d h fr_11 filter register 11 1e h fr_12 filter register 12 1f h fr_13 filter register 13 20 h fr_14 filter register 14 21 h fr_15 filter register 15 22 h table 22 other filter regsiters (cont?d) register short name register long name offset address page number
adm6993/x registers description data sheet 48 rev 1.11, 2005-11-28 port base vlan id and mask 0 of port 0 port base vlan id and mask 1 of port 0 note: if (tag packet) then tag = {tagin[15:12], (( tagin[11:0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_0 offset reset value port base vlan id and mask 0 of port 0 23 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_0 offset reset value port base vlan id and mask 1 of port 0 24 h 0000 h field bits type description pvid 7:0 rw pvid mask[11:4] uz '35, uz 39,' 5hv uz 39,'
data sheet 49 rev 1.11, 2005-11-28 adm6993/x registers description port base vlan id and mask 0 of port 1 port base vlan id and mask 1 of port 1 note: if (tag packet) then tag = {tagin[15:12], (( tagin[11:0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_1 offset reset value port base vlan id and mask 0 of port 1 25 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_1 offset reset value port base vlan id and mask 1 of port 1 26 h 0000 h field bits type description pvid 7:0 rw pvid mask[11:4] uz '35, uz 39,' 5hv uz 39,'
adm6993/x registers description data sheet 50 rev 1.11, 2005-11-28 port base vlan id and mask 0 of port 2 port base vlan id and mask 1 of port 2 note: if (tag packet) then tag = {tagin[15:12], (( tagin[11:0] & ~mask) | (pvid & mask))} if (untag packet) then tag = {pkt_prt[2:0], 0 b , pvid} pb_id_0_2 offset reset value port base vlan id and mask 0 of port 2 27 h 0001 h field bits type description dpri 15:12 rw pvid mask[3:0] default priority pvid 11:0 rw pvid port base vlan id pb_id_1_2 offset reset value port base vlan id and mask 1 of port 2 28 h 0000 h field bits type description pvid 7:0 rw pvid mask[11:4] uz '35, uz 39,' 5hv uz 39,'
data sheet 51 rev 1.11, 2005-11-28 adm6993/x registers description tag port rule 0 register 0 other tag port rule 0 registers have the same structure and characteristics as tag port rule 0 register 0 ; the offset addresses are listed in table 23 . tag port rule 1 register 0 tpr_0_0 offset reset value tag port rule 0 register 0 29 h f000 h field bits type description rm 15:12 rw rule mask[3:0] rule 11:0 rw rule table 23 other tag port rule 0 registers register short name register long name offset address page number tpr_0_1 tag port rule 0 register 1 2b h tpr_0_2 tag port rule 0 register 2 2d h tpr_0_3 tag port rule 0 register 3 2f h tpr_0_4 tag port rule 0 register 4 31 h tpr_0_5 tag port rule 0 register 5 33 h tpr_0_6 tag port rule 0 register 6 35 h tpr_0_7 tag port rule 0 register 7 37 h tpr_1_0 offset reset value tag port rule 1 register 0 2a h 00ff h field bits type description par 11:9 rw port to apply the rule er 8 rw exclude rule "" 50 "" 5xoh 5hv "" 3$5 "" (5 "" 50
adm6993/x registers description data sheet 52 rev 1.11, 2005-11-28 other tag port rule 1 registers have the same structure and characteristics as tag port rule 1 register 0 ; the offset addresses are listed in table 24 . miscellaneous configuration register 3 rm 7:0 rw rule mask[11:4] table 24 other tag port rule 1 regsiters register short name register long name offset address page number tpr_1_1 tag port rule 1 register 1 2c h tpr_1_2 tag port rule 1 register 2 2e h tpr_1_3 tag port rule 1 register 3 30 h tpr_1_4 tag port rule 1 register 4 32 h tpr_1_5 tag port rule 1 register 5 34 h tpr_1_6 tag port rule 1 register 6 36 h tpr_1_7 tag port rule 1 register 7 38 h mcr_3 offset reset value miscellaneous configuration register 3 39 h 0000 h field bits type description res 15:14 ro reserved clc 13 rw check of the length of crs 0 b , enable the checking of the length of crs (default) 1 b , disable the checking of the length of crs rl 12 rw redundant link 0 b , enable redundant link in converter mode(default) 1 b , disable redundant link fp 11 rw fault propagation 0 b , enable fault propagation in converter mode(default) 1 b , disable fault propagation 100s 10 rw 100m snooping 0 b , enable 100m snooping in converter mode(default) 1 b , disable snooping ap_p 9:7 rw all packet/pppoe 0 b , all packet 1 b , pppoe only field bits type description ur 5hv uz &/& uz 5/ uz )3 uz 6 uz $3b3 uz //% uz 31b9 uz 7$*
data sheet 53 rev 1.11, 2005-11-28 adm6993/x registers description llb 6:4 rw local loop-back for port2/port1/port0 0 b , normal operation(default) 1 b , local loop-back for port2/port1/port0 pn_v 3 rw port number/vlan id base grouping 0 b , port number base grouping(default) 1 b , received vlan id base grouping tag 2:0 rw vlan tag 0 b , recognize vlan tag automatically(default) 1 b , disable field bits type description
adm6993/x registers description data sheet 54 rev 1.11, 2005-11-28 miscellaneous configuration register 4 miscellaneous configuration register 5 miscellaneous configuration register 6 mcr_4 offset reset value miscellaneous configuration 4 3a h 0000 h field bits type description res 15:0 ro reserved mcr_5 offset reset value miscellaneous configuration register 5 3b h 0000 h field bits type description res 15:0 ro reserved mcr_6 offset reset value miscellaneous configuration register 6 3c h 0000 h field bits type description res 15:0 ro reserved ur 5hv ur 5hv ur 5hv
data sheet 55 rev 1.11, 2005-11-28 adm6993/x registers description 4.3 default value of smi register note: any write activity to counter register will reset the counter and the overflow flag of this counter. table 25 default value of smi register register bit 31-0 mode default 00 h chip identifier ro 21143 h 01 h hardware settings ro pin 02 h interrupt register lh/roc 0 h 03 h port status ro real time status 04 h eeprom register file access control rw 0 h 05 h port control register rw 0 h 06 h over flow flag lh/roc 0 h 07 h p0 receive packets rw 0 h 08 h p0 reveive byte count rw 0 h 09 h p0 transmit packets rw 0 h 0a h p0 transmit byte count rw 0 h 0b h p0 error count rw 0 h 0c h p0 collision count rw 0 h 0d h p1 receive packets rw 0 h 0e h p1 reveive byte count rw 0 h 0f h p1 transmit packets rw 0 h 10 h p1 transmit byte count rw 0 h 11 h p1 error count rw 0 h 12 h p1 collision count rw 0 h 13 h p2 receive packets rw 0 h 14 h p2 reveive byte count rw 0 h 15 h p2 transmit packets rw 0 h 16 h p2 transmit byte count rw 0 h 17 h p2 error count rw 0 h 18 h p2 collision count rw 0 h 19 h per port counter reset wr
adm6993/x registers description data sheet 56 rev 1.11, 2005-11-28 4.4 smi register descriptions the register is addressed wordwise. table 26 registers address space module base address end address note smi 00 h 19 h table 27 registers overview register short name register long name offset address page number ci chip identifier 00 h 57 hss hardware se tting status 01 h 58 interrupt interrupt register 02 h 58 psr port status register 03 h 60 eeprom_fac eeprom register file access control 04 h 62 pcr port control register 05 h 62 overflow_flag overflow flag 06 h 63 perportcounter0 per port counter 0 07 h 64 perportcounter1 per port counter register 1 08 h 65 perportcounter2 per port counter register 2 09 h 65 perportcounter3 per port counter register 3 10 h 65 perportcounter4 per port counter register 4 11 h 65 perportcounter5 per port counter register 5 12 h 65 perportcounter6 per port counter register 6 13 h 65 perportcounter7 per port counter register 7 14 h 65 perportcounter8 per port counter register 8 15 h 65 perportcounter9 per port counter register 9 16 h 65 perportcounterreset per port counter reset 19 h 65 table 28 register access types mode symbol description hw description sw read/write rw register is used as input for the hw register is read and writable by sw read r register is written by hw (register between input and output -> one cycle delay) value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= target for development.) read only ro register is set by hw (register between input and output -> one cycle delay) sw can only read this register read virtual rv physically, there is no new register, the input of the signal is connected directly to the address multiplexer. sw can only read this register latch high, self clearing lhsc latch high signal at high level, clear on read sw can read the register
data sheet 57 rev 1.11, 2005-11-28 adm6993/x registers description 4.4.1 smi register format chip identifier latch low, self clearing llsc latch high signal at low-level, clear on read sw can read the register latch high, mask clearing lhmk latch high signal at high level, register cleared with written mask sw can read the register, with write mask the register can be cleared (1 clears) latch low, mask clearing llmk latch high signal at low-level, register cleared on read sw can read the register, with write mask the register can be cleared (1 clears) interrupt high, self clearing ihsc differentiate the input signal (low- >high) register cleared on read sw can read the register interrupt low, self clearing ilsc differentiate the in put signal (high- >low) register cleared on read sw can read the register interrupt high, mask clearing ihmk differentiate the in put signal (high- >low) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt low, mask clearing ilmk differentiate the input signal (low- >high) register cleared with written mask sw can read the register, with write mask the register can be cleared interrupt enable register ien enables the interr upt source for interrupt generation sw can read and write this register latch_on_reset lor rw register, value is latched after first clock cycle after reset register is read and writable by sw read/write self clearing rwsc register is used as input for the hw, the register will be clea red due to a hw mechanism. writing to the register generates a strobe signal for the hw (1 pdi clock cycle) register is read and writable by sw. table 29 registers clock domainsregisters clock domains clock short name description ci offset reset value chip identifier 00 h 21143 h field bits type description pc 31:4 ro project code table 28 register access types (cont?d) mode symbol description hw description sw ur 3& ur 5&
adm6993/x registers description data sheet 58 rev 1.11, 2005-11-28 hardware setting status interrupt register rc 3:0 ro revision code hss offset reset value hardware setting status 01 h pin h field bits type description bm2 28:27 ro bus mode of port 2 bm1 26:25 ro bus mode of port 1 fm 24:23 ro fiber mode led1 22 ro ledmode 1 led0 21 ro ledmode 0 dbp 20 ro disable back preasure dma 19 ro disable mac a ddress learning idm 18 ro idle mode es 17 ro enable snooping eop 16 ro enable oam processor er 15 ro enable redundant fpm 14:13 ro fault propagation mode lpt 12 ro disable link pass through eac 11 ro enable auto-crossover p0mm 10 ro p0 mdi/mdix dfc 9:7 ro disable flow control ran 6:5 ro recommend auto-negotiation ability for tp port rs10 4:3 ro recommend speed 10 for tp port rdh 2:1 ro recommend duplex half for tp/fx port cd 0 ro chip dis interrupt offset reset value interrupt register 02 h 0000 0000 h field bits type description 5hv ur %0 ur %0 ur )0 ur /( ' ur /( ' ur '% 3 ur '0 $ ur ,g 0 ur (6 ur (2 3 ur (5 ur )30 ur /3 7 ur ($ & ur 3 00 ur ')& ur 5$1 ur 56 ur 5'+ ur &'
data sheet 59 rev 1.11, 2005-11-28 adm6993/x registers description field bits type description co 18 lh/roc counter overflow 0 b , normal 1 b , any counter defined in register 7 h ~18 h overflow rce2 17 lh/roc port 2 receive crc error packet 0 b , normal 1 b , reveive crc error packet rce1 16 lh/roc port 1 receive crc error packet 0 b , normal 1 b , reveive crc error packet rce0 15 lh/roc port 0 receive crc error packet 0 b , normal 1 b , reveive crc error packet bf2 14 lh/roc port 2 buffer full 0 b , normal 1 b , buffer full bf1 13 lh/roc port 1 buffer full 0 b , normal 1 b , buffer full bf0 12 lh/roc port 0 buffer full 0 b , normal 1 b , buffer full fca2 11 lh/roc port 2 flow control ability change 0 b , normal 1 b , status change dc2 10 lh/roc port 2 duplex change 0 b , normal 1 b , status change sc2 9 lh/roc port 2 speed change 0 b , normal 1 b , status change lsc2 8 lh/roc port 2 link status change 0 b , normal 1 b , status change fca1 7 lh/roc port 1 flow control ability change 0 b , normal 1 b , status change dc1 6 lh/roc port 1 duplex change 0 b , normal 1 b , status change 5hv okfru &2 okfru 5& ( okfru 5& ( okfru 5& ( okfru %) okfru %) okfru %) okfru )& $ okfru '& okfru 6& okfru /6 & okfru )& $ okfru '& okfru 6& okfru /6 & okfru )& $ okfru '& okfru 6& okf r /6 &
adm6993/x registers description data sheet 60 rev 1.11, 2005-11-28 port status register sc1 5 lh/roc port 1 speed change 0 b , normal 1 b , status change lsc1 4 lh/roc port 1 link status change 0 b , normal 1 b , status change fca0 3 lh/roc port 0 flow control ability change 0 b , normal 1 b , status change dc0 2 lh/roc port 0 duplex change 0 b , normal 1 b , status change sc0 1 lh/roc port 0 speed change 0 b , normal 1 b , status change lsc0 0 lh/roc port 0 link status change 0 b , normal 1 b , status change psr offset reset value port status register 03 h real time status h field bits type description cbl1 20:19 ro cbbrk_length of p1 00 b , 0~60m 01 b , 60~90m 10 b , 90~130m 11 b , 130~170m cb1 18 ro cbbrk of p1 0 b , normal 1 b , cable broken cbl0 17:16 ro cbbrk_length of p0 00 b , 0~60m 01 b , 60~90m 10 b , 90~130m 11 b , 130~170m field bits type description 5hv ur &%/ ur &% ur &%/ ur &% ur %) ur %) ur %) ur )& ur 'x s ur 6s h ur /6 ur )& ur 'x s ur 6s h ur /6 ur )& ur 'x s ur 6s h ur /6
data sheet 61 rev 1.11, 2005-11-28 adm6993/x registers description cb0 15 ro cbbrk of p0 0 b , normal 1 b , cable broken bf2 14 ro buffer full status of port 2 0 b , normal 1 b , buffer full bf1 13 ro buffer full status of port 1 0 b , normal 1 b , buffer full bf0 12 ro buffer full status of port 0 0 b , normal 1 b , buffer full fc2 11 ro flow control of port 2 0 b , disable 1 b , enable dup2 10 ro duplex of port 2 0 b , half duplex 1 b , full duplex spe2 9 ro speed of port 2 0 b , 10m 1 b , 100m ls2 8 ro link status of port 2 0 b , link down 1 b , link up fc1 7 ro flow control of port 1 0 b , disable 1 b , enable dup1 6 ro duplex of port 1 0 b , half duplex 1 b , full duplex spe1 5 ro speed of port 1 0 b , 10m 1 b , 100m ls1 4 ro link status of port 1 0 b , link down 1 b , link up fc0 3 ro flow control of port 0 0 b , disable 1 b , enable dup0 2 ro duplex of port 0 0 b , half duplex 1 b , full duplex spe0 1 ro speed of port 0 0 b , 10m 1 b , 100m field bits type description
adm6993/x registers description data sheet 62 rev 1.11, 2005-11-28 eeprom register file access control port control register ls0 0 ro link status of port 0 0 b , link down 1 b , link up eeprom_fac offset reset value eeprom register file access control 04 h 0000 0000 h field bits type description cmm 31:29 rw command 000 b , read 001 b , write others b , reserved res 28:22 rw reserved should be always 0000000 b add 21:16 rw address 00 h ~3f h data 15:0 rw data pcr offset reset value port control register 05 h 00000 h field bits type description stp2 16:15 rw stp state of port 2 0x b , forwarding 10 b , learning 11 b , blocking & listening field bits type description uz &00 uz 5hv uz $gg uz 'dwd uz 673 uz 673 uz 673 uz (b uz '35 uz %& uz 3' uz %& uz 3' uz %& uz 3'
data sheet 63 rev 1.11, 2005-11-28 adm6993/x registers description overflow flag stp1 14:13 rw stp state of port 1 0x b , forwarding 10 b , learning 11 b , blocking & listening stp0 12:11 rw stp state of port 0 0x b , forwarding 10 b , learning 11 b , blocking & listening e9_6 10 rw enable bit[9:6] 0 b , disable 1 b , enable dpr 9:6 rw destination of the packet received from cpu port bit [8:6] : bit[6] is for p0, bi t[7] is for p1 and bit[8] is for p2. if the bit is set to 1, the packet received from cpu port defined in eeprom register 7 h bit [7:6] will be forward to the corresponding port.bit [9]: if the total number of 1 in bit [8 :6] is greater than 1, this bit should set to 1 too. bc2 5 rw p2 bandwidth control on/off 0 b , normal 1 b , force p2 issue pause packet fo r full duplex and back pressure for half duplex p2d 4 rw p2 disable 0 b , normal 1 b , p2 disable rece iving/transmitting bc1 3 rw p1 bandwidth control on/off 0 b , normal 1 b , force p1 issue pause packet fo r full duplex and back pressure for half duplex p1d 2 rw p1 disable 0 b , normal 1 b , p1 disable rece iving/transmitting bc0 1 rw p0 bandwidth control on/off 0 b , normal 1 b , force p0 issue pause packet fo r full duplex and back pressure for half duplex p0d 0 rw p0 disable 0 b , normal 1 b , p0 disable rece iving/transmitting overflow_flag offset reset value overflow flag 06 h 00000 h field bits type description
adm6993/x registers description data sheet 64 rev 1.11, 2005-11-28 per port counter 0 field bits type description cc2 17 lh/roc p2 collision count 1 b , p2 collision count ec2 16 lh/roc p2 error count 1 b , p2 error count tbc2 15 lh/roc p2 transmit byte count 1 b , p2 transmit byte count tp2 14 lh/roc p2 transmit packets 1 b , p2 transmit packets rbc2 13 lh/roc p2 receive byte count 1 b , p2 receive byte count rp2 12 lh/roc p2 receive packets 1 b , p2 receive packets cc1 11 lh/roc p1 collision count 1 b , p1 collision count ec1 10 lh/roc p1 error count 1 b , p1 error count tbc1 9 lh/roc p1 transmit byte count 1 b , p1 transmit byte count tp1 8 lh/roc p1 transmit packets 1 b , p1 transmit packets rbc1 7 lh/roc p1 receive byte count 1 b , p1 receive byte count rp1 6 lh/roc p1 receive packets 1 b , p1 receive packets cc0 5 lh/roc p0 collision count 1 b , p0 collision count ec0 4 lh/roc p0 error count 1 b , p0 error count tbc0 3 lh/roc p0 transmit byte count 1 b , p0 transmit byte count tp0 2 lh/roc p0 transmit packets 1 b , p0 transmit packets rbc0 1 lh/roc p0 receive byte count 1 b , p0 receive byte count rp0 0 lh/roc p0 receive packets 1 b , p0 receive packets 5hv okfru && okfru (& okfru 7% & okfru 73 okfru 5% & okfru 53 okfru && okfru (& okfru 7% & okfru 73 okfru 5% & okfru 53 okfru && okfru (& okfru 7% & okfru 73 okfru 5% & okf r 53
data sheet 65 rev 1.11, 2005-11-28 adm6993/x registers description other per port counter registers have th e same structure and characteristics as per port counter 0 ; the offset addresses are listed in table 30 . per port counter reset perportcounter0 offset reset value per port counter 0 07 h 0000 0000 h field bits type description counter 31:0 rw counter table 30 other per port counter registers register short name register long name offset address page number perportcounter1 per port counter register 1 08 h perportcounter2 per port counter register 2 09 h perportcounter3 per port counter register 3 10 h perportcounter4 per port counter register 4 11 h perportcounter5 per port counter register 5 12 h perportcounter6 per port counter register 6 13 h perportcounter7 per port counter register 7 14 h perportcounter8 per port counter register 8 15 h perportcounter9 per port counter register 9 16 h perportcounterreset offset reset value per port counter reset 19 h ?? h field bits type description cr2 2 wr counter reset of port2 1 b , reset all counter of port 2 uz &rxqwhu 5hv zu &5 zu &5 zu &5
adm6993/x registers description data sheet 66 rev 1.11, 2005-11-28 cr1 1 wr counter reset of port1 1 b , reset all counter of port 1 cr0 0 wr counter reset of port0 1 b , reset all counter of port 0 field bits type description
data sheet 67 rev 1.11, 2005-11-28 adm6993/x electrical specification 5 electrical specification dc and ac. 5.1 dc characterization 5.2 ac characterization power on reset timing, eeprom interface timing, 10ba se-tx mii timing, 100base-tx mii timing, reduce mii timing, gpsi(7-wire) timing, hdlc timing, and smi timing. table 31 electrical absolute maximum rating parameter symbol values unit note / test condition min. typ. max. power supply v cc -0.3 2.7 v input voltage v in -0.3 v cc + 0.3 v output voltage vout -0.3 v cc + 0.3 v storage temperature tstg -55 155 c power dissipation pd 990 mw esd rating esd 2 kv table 32 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. power supply 1) 1) vcc3o. vccbias vcc 3.135 3.3 3.465 v input voltage vin 0 - vcc v junction operating temperature tj 0 25 115 c table 33 dc electrical characteristics for 3.3 v operation 1) 1) under vcc = 3.0 v~ 3.6 v, tj = c ~ 115 c parameter symbol values unit note / test condition min. typ. max. input low voltage vil 0.8 v ttl input high voltage vih 2.0 v ttl output low voltage vol 0.4 v ttl output high voltage voh 2.4 v ttl input pull_up/down resistance ri 50 k ? vil = 0 v or vih = vcc
adm6993/x electrical specification data sheet 68 rev 1.11, 2005-11-28 power on reset timing figure 5 power on reset timing eeprom interface timing figure 6 eeprom interface timing table 34 power on reset timing parameter symbol values unit note / test condition min. typ. max. rst low period t rst 100 ms ttl start of idle pulse width t conf 100 ns ttl table 35 eeprom interface timing parameter symbol values unit note / test condition min. typ. max. eesk period t esk 5120 ns eesk low period t eskl 2550 2570 ns eesk high period t eskh 2550 2570 ns eedi to eesk rising setup time t erds 10 ns tconf trst trst 0us 50us 100us 150us rst * a ll configuration pin s terdh terds tewdd tesk tesk teskl teskl teskh teskh 0us 10us 20us 30us eecs eesk eedo eedi
data sheet 69 rev 1.11, 2005-11-28 adm6993/x electrical specification 10base-tx mii input timing 10base-tx input timing conditions figure 7 10base-tx mii input timing 10base-tx mii output timing 10base-tx mii output timing conditions eedi to eesk rising hold time t erdh 10 ns eesk falling to eedo output delay time t ewdd 20 ns table 36 10base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck 400 ns mii_rxclk low period t ckl 160 240 ns mii_rxclk high period t ckh 160 240 ns mii_crs rising to mii_rxdv rising t csva 0 10 ns mii_rxclk rising to mii_rxd, mii_rxdv, mii_crs output delay t rxod 200 ns table 35 eeprom interface timing (cont?d) parameter symbol values unit note / test condition min. typ. max. tcsva trxod tck tc k l tc k l tck h tck tck h 0ns 1000ns 2000ns mii_rxclk mii_rxdv mii_rxd mii_crs
adm6993/x electrical specification data sheet 70 rev 1.11, 2005-11-28 figure 8 10base-tx mii output timing 100base-tx mii input timing 100base tx mii inpu t timing conditions figure 9 100base-tx mii input timing table 37 10base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck 400 ns mii_txclk low period t ckl 160 240 ns mii_txclk high period t ckh 160 240 ns mii_txd, mii_txen to mii_txclk rising setup time t txs 10 ns mii_txd, mii_txen to mii_txclk rising hold time t txh 10 ns tthx ttxs tck tckl tckl tckh tck tckh 0ns 500ns 1000ns 1500ns 2000ns 2500 n mii_txclk mii_txen mii_txd tcsva trxod tckl tck tckl tckh tckh tck 0ns 100ns 200ns mii_rxclk mii_rxdv mii_rxd mii_crs
data sheet 71 rev 1.11, 2005-11-28 adm6993/x electrical specification 100base-tx mii output timing 100base-tx mii outp ut timing conditions figure 10 100base-tx mii output timing reduce mii timing reduce mii timing conditions table 38 100base-tx mii input timing parameter symbol values unit note / test condition min. typ. max. mii_rxclk period t ck 40 ns mii_rxclk low period t ckl 16 24 ns mii_rxclk high period t ckh 16 24 ns mii_crs rising to mii_rxdv rising t csva 0 10 ns mii_rxclk rising to mii_rxd, mii_rxdv, mii_crs output delay t rxod 20 30 ns table 39 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. mii_txclk period t ck 40 ns mii_txclk low period t ckl 16 24 ns mii_txclk high period t ckh 16 24 ns mii_txd, mii_txen to mii_txclk rising setup time t txs 10 ns mii_txd, mii_txen to mii_txclk rising hold time t txh 10 ns ttxh ttxs tckl tck tckl tckh tckh tck 0ns 50ns 100ns 150ns 200ns 250ns mii_txclk mii_txen mii_txd
adm6993/x electrical specification data sheet 72 rev 1.11, 2005-11-28 figure 11 reduce mii timing gpsi (7-wire) input timing gpsi (7-wire) input timing conditions table 40 100base-tx mii output timing parameter symbol values unit note / test condition min. typ. max. rmii_refclk period t ck 20 ns rmii_refclk low period t ckl 10 ns rmii_refclk high period t ckh 10 ns txen, txd to refclk rising setup time t txs 4 ns txe, txd to refclk rising hold time t txh 2 ns csrdv, rxd to refclk rising setup time t rxs 4 ns crsdv, rxd to refclk rising hold time t rxh 2 ns ttxh ttxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_t xen txd[1:0] trxh trxs tck tckl tckl tckh tck tckh 0ns 50ns 100ns refclk rmii_crsdv rxd[1:0]
data sheet 73 rev 1.11, 2005-11-28 adm6993/x electrical specification figure 12 gpsi (7-wire) input timing gpsi (7-wire) output timing gpsi (7-wire) output timing conditions figure 13 gpsi (7-wire) output timing table 41 gpsi (7-wire) input timing parameter symbol values unit note / test condition min. typ. max. gpsi_rxclk period t ck 100 ns gpsi_rxclk low period t ckl 40 60 ns gpsi_rxclk high period t ckh 40 60 ns gpsi_rxclk rising to gpsi_crs/gpsi_col output delay t od 50 70 ns tod tck tckl tckl tckh tck tckh 0ns 250ns 500ns gpsi_rxclk gpsi_rxd gpsi_crs/col ttxh ttxs tck tckl tckl tckh tck tckh 0ns 250ns 500ns gpsi_txclk gpsi_txd gpsi_txen
adm6993/x electrical specification data sheet 74 rev 1.11, 2005-11-28 hdlc timing figure 14 hdlc timing table 42 gpsi (7-wire) output timing parameter symbol values unit note / test condition min. typ. max. gpsi_txclk period t ck 100 ns gpsi_txclk low period t ckl 40 60 ns gpsi_ t xclk high period t ckh 40 60 ns gpsi_txd, gpsi_txen to gpsi_txclk rising setup time t txs 10 ns gpsi_txd, gpsi_txen to gpsi_txclk rising hold time t txh 10 ns table 43 hdlc timing parameter symbol values unit note / test condition min. typ. max. hdlc_refclk period t ck 20 ns hdlc_refclk low period t ckl 10 ns 0 1 1 1 1 1 1 0 bit 0 bi t1 bit 2 bit 3 bit 4 ttxh ttxs tck tckl tckl tckh tck tckh 0ns 100ns 200ns hdlc_t xclk hdlc_t xd 0 1 1 1 1 1 1 0 bit 0 bi t1 bit 2 bit 3 bit 4 trxh trxs tck tckl tckl tckh tck tckh 0ns 100ns 200ns hdlc_rxclk hdlc_rxd
data sheet 75 rev 1.11, 2005-11-28 adm6993/x electrical specification smi timing figure 15 smi timing hdlc_refclk high period t ckh 10 ns txd to txclk rising setup time t txs 0 ns txd to txclk rising hold time t txh 5 ns rxd to rxclk rising setup time t rxs 0 ns rxd to rxclk rising hold time t rxh 5 ns table 44 smi timing parameter symbol values unit note / test condition min. typ. max. sdc period t ck 20 ns sdc low period t ckl 10 ns sdc high period t ckh 10 ns sdio to sdc rising setup time on read/write cycle t sds 4 ns sdio to sdc rising hold time on read/write cycle t sdh 2 ns table 43 hdlc timing (cont?d) parameter symbol values unit note / test condition min. typ. max. tsdh tsds tsdc tsdcl tsdcl tsdch tsdc tsdch 0ns 25ns 50ns 75ns 100ns sdc sdio
adm6993/x packaging data sheet 76 rev 1.11, 2005-11-28 6 packaging 128 pqfp packaging for adm6993/x figure 16 128 pqfp packaging for adm6993/x 18.5 mm 20.0 +/- 0.1 mm 23.2 +/- 0.2 mm 3.4 mm max 12.5 mm 14.0 +/- 0.1 mm 17.2 +/- 0.2 mm 0.5 mm
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