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rev. 0.1 11/10 copyright ? 2010 by silicon laboratories si5351a/b/c this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5351a/b/c i 2 c-p rogrammable a ny -f requency cmos c lock g enerator + vcxo features applications description the si5351 is an i 2 c configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, vcxos, phase-locked loops (pl), and fanout buffers in cost-sensitive applications. based on a pll/vcxo + high resolution multisynth fractional divider architecture, the si5351 can generate any frequency up to 133 mhz on each of its outputs with 0 ppm error. three versions of the si5351 are available to meet a wide variety of applications. the si5351a generates up to 8 free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. the si5351b adds an internal vcxo and provides the flexibility to replace both free- running clocks and synchronous clocks. the si5351b eliminates the need for higher cost, custom pullable crystals while providing reliable operation over a wide tuning range. the si5351c offers the same flexibility but synchronizes to an external reference clock (clkin). functional block diagram ? generates up to 8 non-integer frequencies from 8 khz to 133 mhz ? i 2 c user definable configuration ? exact frequency synthesis at each output (0 ppm error) ? highly linear vcxo ? optional clock input (clkin) ? low output period jitter: 100 ps pp ? configurable spread spectrum selectable at each output ? operates from a low-cost, fixed frequency crystal: 25 or 27 mhz ? glitchless frequency changes ? separate voltage supply pins: ?? core vdd: 2.5 v or 3.3 v ?? output vddo: 2.5 v or 3.3 v ? excellent psrr eliminates external power supply filtering ? very low power consumption ? adjustable output-output delay ? available in 3 packages types: ?? 10-msop: 3 outputs ?? 24-qsop: 8 outputs ?? 20-qfn (4x4 mm): 8 outputs ? hdtv, dvd/blu-ray, set-top box ? audio/video equipment, gaming ? printers, scanners, projectors ? residential gateways ? networking/communication ? servers, storage si5351a multi synth n n = 2 or 7 i 2 c ssen oeb multi synth 0 multi synth 1 si5351b pll vc vcxo i 2 c ssen oeb multi synth 0 multi synth 1 multi synth 2 multi synth 3 multi synth 4 multi synth 5 multi synth 6 multi synth 7 si5351c plla clkin pllb i 2 c intr oeb multi synth 0 multi synth 1 multi synth 2 multi synth 3 multi synth 4 multi synth 5 multi synth 6 multi synth 7 xa xb osc xa xb osc pllb plla xa xb osc ordering information: see page 41 10-msop 24-qsop 20-qfn
si5351a/b/c 2 rev. 0.1
si5351a/b/c rev. 0.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2. synthesis stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3. output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.4. spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5. control pins (oeb, ssen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. configuring the si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5. si5351 application exam ples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1. replacing crystals and cr ystal oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2. replacing crystals, cr ystal oscillators, and vcxos . . . . . . . . . . . . . . . . . . . . . . . .14 5.3. replacing crystals, cr ystal oscillators, and plls . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. external component recomme ndations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1. power supply decoupling/filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2. power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3. external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4. external crystal load c apacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5. unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 9. detailed block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 10. pin descriptions (10-pin msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11. si5351a pin descriptions (20-pin qfn, 24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . 35 12. si5351b pin descriptions (20-pin qfn, 24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . 36 13. si5351c pin descriptions (20-pin qfn, 24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . 37 14. package outline (24-pin qsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15. package outline (20-pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16. package outline (10-pin msop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
si5351a/b/c 4 rev. 0.1 1. electrical specifications table 1. recommended operating conditions (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit ambient temperature t a ?402585c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v output buffer voltage v ddox 2.25 2.5 2.75 v 2.97 3.3 3.63 v notes: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. vdd and vddox can be operated at independent voltages. power supply sequencing for vdd and vddox requires that both voltage rails are powered at the same time. table 2. absolute maximum ratings parameter symbol test condition value unit dc supply voltage v dd_max ?0.5 to 3.8 v input voltage v in_clkin clkin, scl, sda ?0.5 to 3.8 v v in_vc vc ?0.5 to (vdd+0.3) v v in_xa/b pins xa, xb ?0.5 to 1.3 v v storage temperature range t stg ?55 to 150 c operating junction temperature t jct ?55 to 150 c note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
si5351a/b/c rev. 0.1 5 table 3. dc characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit core supply current i dd enabled 3 outputs ? 20 26 ma enabled 8 outputs ? 25 38 ma power down (pdn = v dd )? 50 ? a output buffer supply current i ddox c l =5pf ? 2.5 4 ma input current i clkin clkin, sda, scl vin < 3.6 v ??10 a i vc vc ? ? 30 a table 4. ac characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85c) parameter symbol test condition min typ max unit power-up time t rdy from v dd =v ddmin to valid out- put clock, c l =15pf, f clkn >1mhz ?110ms output enable time t oe from oeb assertion to valid clock output, c l =15pf, f clkn >1mhz ??10 s output phase offset p step ? 357 ? ps/step spread spectrum frequency deviation ss dev down spread ?0.1 ? ?2.5 % center spread 0.1 ? 1.5 % spread spectrum modulation rate ss mod 30 31.5 33 khz vcxo specifications (si5351b only) vcxo control voltage range vc 0 v dd /2 v dd v vcxo gain (configurable) kv vc = 10?90% of v dd , v dd = 3.3 v 30 ? 250 ppm/v vcxo control voltage linearity kvl vc = 10?90% of v dd ?5 ? +5 % vcxo pull range (configu- rable) pr v dd = 3.3 v* 40 0 330 ppm vcxo modulation bandwidth ? 10 ? khz vcxo period jitter ? 60 110 ps vcxo cycle-cycle jitter ? 50 95 ps pk- pk vcxo rms phase jitter ? 8.5 18.5 ps rms pll input frequency range f clkin 10 ? 100 mhz *note: contact silicon labs for 2.5 v vcxo operation.
si5351a/b/c 6 rev. 0.1 table 5. thermal characteristics parameter symbol test cond ition package value unit thermal resistance junction to ambient ? ja still air 10-msop 131 c/w 24-qsop 80 c/w 20-qfn 51 c/w thermal resistance junction to case ? jc still air 10-msop 43 c/w 24-qsop 31 c/w 20-qfn 16 c/w table 6. input characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units clkin input low voltage v il ?0.1 ? 0.3 x v dd v clkin input high voltage v ih 0.7 x v dd ?3.63 v table 7. output characteristics (v dd = 2.5 v 10%, or 3.3 v 10%, t a =?40 to 85c) parameter symbol test condition min typ max units frequency range f clk 0.008 ? 133 mhz load capacitance c l ?515pf duty cycle dc measured at v dd /2, f clk =50mhz 45 50 55 % rise/fall time t r 20%?80%, c l = 5 pf 0.6 1 1.3 ns t f 0.6 1 1.3 ns output high voltage v oh c l =5pf v dd ? 0.6 ? ? v output low voltage v ol ??0.6v period jitter j per measured over 10k cycles ? 35 100 ps pk period jitter vcxo j per_vcxo ?60110ps pk cycle-to-cycle jitter j cc measured over 10k cycles ? 30 90 ps pk-pk cycle-to-cycle jitter vcxo j cc_vcxo ? 50 95 ps pk-pk rms phase jitter j rms 12 khz?20 mhz ? 3.5 11 ps rms rms phase jitter vcxo j rms_vcxo ? 8.5 18.5 ps rms
si5351a/b/c rev. 0.1 7 table 8. crystal requirements 1,2 parameter symbol min typ max unit crystal frequency f xtal 25 ? 27 mhz load capacitance c l 6?12pf equivalent series resistance r esr ??150 ? crystal max drive level d l ??100w notes: 1. crystals which require load capacitances of 6, 8, or 10 pf should use the device?s internal load capacitance for optimum performance. see register 183 bits 7:6. a crystal with a 12 pf lo ad capacitance requirement should use a combination of the internal 10 pf load capacitors in addition to external 2 pf load capacitors. 2. refer to ?an551: crystal selection guide? for more details. table 9. i 2 c specifications (scl,sda) 1 parameter symbol test condition standard mode 100 kbps fast mode 400 kbps unit min max min max low level input voltage v ili2c ?0.5 0.3 x v ddi2 c ?0.5 0.3 x v ddi2c 2 v high level input voltage v ihi2c 0.7 x v ddi2 c 3.63 0.7 x v ddi2c 2 3.63 v hysteresis of schmitt trigger inputs v hys ?? 0.1 ?v low level out- put voltage (open drain or open collector) at 3 ma sink current v oli2c 2 v ddi2c 2 = 2.5/3.3 v 0 0.4 0 0.4 v v ddi2c 2 = 1.8 v ? ? 0 0.2 x v ddi2c v input current i ii2c ?10 10 ?10 10 a capacitance for each i/o pin c ii2c v in = ?0.1 to v ddi2c ?4 ? 4pf i 2 c bus time- out t to timeout enabled 25 35 25 35 ms notes: 1. refer to nxp?s um10204 i 2 c-bus specification and user manual, revision 03, for further details: www.nxp.com/acrobat_download/ usermanuals/um10204_3.pdf. 2. only i 2 c pullup voltages (vddi2c) of 2. 25 to 3.63 v are supported.
si5351a/b/c 8 rev. 0.1 2. functional description the si5351 is a versatile i 2 c programmable clock generator that is ideally suited for replacing crystals, crystal oscillators, vcxos, plls, and buffers. a block diagram sho wing the general architecture of the si5351 is shown in figure 1. the device consists of an input sta ge, two synthesis stages, and an output stage. the input stage accepts an external crystal (xtal), a clock input (clkin), or a control voltage input (vc) depending on the version of the device (a/b/c). the first stage of synthesis multiplies the input frequencies to an high-frequency intermediate clock, while the second stage of synthesis uses high resolu tion multisynth fractional dividers to generate the desired output frequencies. additional integer division is provided at the output stage for generating output frequencies as low as 8 khz. crosspoint switches at each of the syn thesis stages allows total flexibility in routing any of t he inputs to any of the outputs. because of this high resolution and flexible synthes is architecture, the si5351 is capable of generating synchronous or free-running non-integer related clock fre quencies at each of its out puts, enabling one device to synthesize clocks for multiple clock domains in a design. figure 1. si5351 block diagram 2.1. input stage 2.1.1. crystal inputs (xa, xb) the si5351 uses a fixed-frequency stan dard at-cut crystal as a reference to the internal oscillator. the output of the oscillator can be used to provid e a free-running reference to one or both of the pl ls for generating asynchronous clocks. th e output frequency of the osc illator will operate at the crysta l frequency, either 25 mhz or 27 mhz. the crystal is also used as a reference to the vcxo to help maintain its frequency accuracy. internal load capacitors (c l ) are provided to eliminate the need for exte rnal components when connecting a crystal to the si5351. options for internal load capacitors are 6, 8, or 10 pf. crystals with alternate load capacitance requirements are supported using additional external load capacitors as shown in figure 2. refer to application note an551 for crystal recommendations. figure 2. external xtal with optional load capacitors input stage synthesis stage 1 pll b (vcxo) pll a (ssc) vc vcxo xa xb osc xtal clkin div <30 mhz 600-800 mhz 600-800 mhz 391 khz ? 133 mhz multi synth 0 multi synth 1 multi synth 2 multi synth 3 multi synth 4 multi synth 5 multi synth 6 multi synth 7 synthesis stage 2 r0 r1 r2 r3 r4 r5 r6 r7 output stage clk0 clk1 vddoa clk2 clk3 vddob clk4 clk5 vddoc clk6 clk7 vddod 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 8 khz ? 133 mhz * 10-100 mhz 25 or 27 mhz kv xa xb selectable internal load capacitors 6 pf, 8 pf, 10 pf c l c l c l optional additional external load capacitors c l
si5351a/b/c rev. 0.1 9 2.1.2. external clock input (clkin) the external clock input is used as a clock reference for the plls when generating synchronous clock outputs. clkin can accept any frequency from 10 to 100 mhz. a di vider at the input stage limits the pll input frequency to 30 mhz. 2.1.3. voltage control input (vc) the internal vcxo generates a center frequency in the ra nge of 600 mhz to 800 mhz that is controlled (pulled) by the voltage applied at the vc input pin. the unique design of the vcxo eliminates the need for an external pullable crystal. only a standard, low-cost, fixed-frequency (25 mhz or 27 mhz) at-cut crystal is required. the tuning range of the vcxo is config urable from 10ppm to 1000ppm to satisfy a wide variety of applications. key advantages of the vcxo design in the si5351 include high linearity, a wide operating range (linear from 10 to 90% of vdd), and reliable startup and operation. 2.2. synthesis stages the si5351 uses two stages of synthesis to generate its final output clocks. th e first stage uses plls to multiply the lower frequency input references to a high-frequency intermediate clock in the range of 600 - 800 mhz. the second stage uses high-resolution multisynth fractional di viders to generate frequencies in the range of ~391 khz to 100 mhz. it is also possible to generate two frequenc ies up to 133 mhz on two or more of the outputs. a crosspoint switch at the input of the first stage allows each of the plls to lock to the clkin or the xtal input. this allows each of the plls to lock to a different s ource for generating independent free-running and synchronous clocks. alternatively, both pl ls could lock to the same source. the cro sspoint switch at th e input of the second stage allows any of the multisynth dividers to connect to plla or pllb. this flexible synthesis archit ecture allows any of the outputs to generate synchronous or non-sync hronous clocks, with spread spectrum or without spread spectrum, and with the flexibility of generating non-integer related clock frequencies at each output. since the vcxo already generat es a high-frequency intermediate clock, it is fed directly into the second stage of synthesis. the multisynth high-resolution dividers synthe size the vcxo center frequency to any frequency in the range of ~391 khz to 133 mhz. the center frequency is then controlled (or pulled) by the vc input. an interesting feature of the si5351 is that the vcxo output can be routed to more than one multisynth divider. this creates a vcxo with multiple output frequencies contro lled from one vc input as shown in figure 3. figure 3. using the si5351 as a multi-output vcxo 2.3. output stage an additional level of division (r) is available at the output stage for generating clocks as low as 8 khz. all output drivers generate cmos level outputs with separate output voltage supply pins (vddox) allowing a different voltage signal level (3.3v or 2.5v) at each of the four 2-output banks. clk0 vc multi synth 2 clk1 clk2 additional multisynths can be ?linked? to the vcxo to generate additional clock frequencies xa xb osc vcxo multi synth 1 multi synth 0 control voltage fixed frequency crystal (non-pullable) the clock frequency generated from clk0 is controlled by the vc input r2 r1 r0
si5351a/b/c 10 rev. 0.1 2.4. spread spectrum spread spectrum can be enabled on any of the clock output s that use plla as its reference. spread spectrum is useful for reducing electromagnetic interference (emi). e nabling spread spectrum on an output clock modulates its frequency, which effectively reduces the overall amplitude of its radiated energy. up to ?15 db reduction in emi is possible. note that spread spectrum is not availabl e on clocks synchronized to pllb or to the vcxo. the si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise between system performance and emi compliance. the amount of spread is configurable with the following: ? down spread: ?0.5 to ?2.5% modulation amplitude ? center spread: 0.1 to 1.5% modulation amplitude figure 4. available spread spectrum profiles 2.5. control pins (oeb, ssen) the si5351 offers control pins for enabling/disabling clock outputs and spread spectrum. 2.5.1. output enable (oeb) the output enable pin allows enabling or disabling outputs clocks. output clocks are enabled when the oeb pin is held low, and disabled when pulled high. when disabled, the output state is configurable as disabled high, disabled low, or disabled in high-impedance. the output enable control circuitry ensures glitchless operati on by starting the output clock cycle on the first leading edge after oeb is asserted (oeb = low). when oeb is rele ased (oeb = high), the clock is allowed to complete its full clock cycle before going into a disabled state. the operation of the output enable pin is shown in figure 5. figure 5. glitchless output enable/disable 2.5.2. spread spectr um enable (ssen)?si53 51a and si 5351b only this control pin allows disa bling the spread spectrum feature for all outputs that were configured with spread spectrum enabled. hold ssen low to disable spread spectrum. the ssen pin provides a convenient method of evaluating the effect of using spread spectrum clocks during emi compliance testing. f c reduced amplitude and emi down spread spread amount - 0.1% to - 2.5% f c reduced amplitude and emi center spread spread amount +/- 0.1% to +/- 1.5% f c no spread spectrum center frequency amplitude clock continues until cycle is complete clkx oebx clock starts on the first leading edge
si5351a/b/c rev. 0.1 11 3. i 2 c interface many of the functions and features of the si5351 are controlled by reading and writing to the ram space using the i 2 c interface. the following is a list of the common features that are controllable through the i 2 c interface. a summary of register function s is shown in section 7. ? read status indicators ?? loss of signal (los) for the clkin input ?? loss of lock (lol) for plla and pllb ? configuration of multiplication and divider values for the plls, multisynth dividers ? configuration of the spread spectrum profile (down or center spread, modulation percentage) ? control of the cross point switch selection for each of the plls and multisynth dividers ? set output clock options ?? enable/disable for each clock output ?? invert/non-invert for each clock output ?? output divider values (2 n , n=1.. 7) ?? output state when disabled (stop hi, stop low, hi-z) ?? output phase offset the i 2 c interface operates in slave mode with 7-bit address ing and can operate in standard-mode (100 kbps) or fast-mode (400 kbps) and supports burst data transfer with auto address increments. the i 2 c bus consists of a bidirectional serial data line (sda ) and a serial clock input (scl) as shown in figure 6. both the sda and scl pins must be connected to the vdd supply via an external pull-up as recommended by the i 2 c specification. figure 6. i 2 c and control signals the 7-bit device (slave) address of t he si5351 consist of a 6-bit fixed addres s plus a user selectable lsb bit as shown in figure 7. the lsb bit is selectable as 0 or 1 us ing the optional a0 pin which is useful for applications that require more than one si5351 on a single i 2 c bus. figure 7. si5351 i 2 c slave address data is transferred msb first in 8-bit words as specified by the i 2 c specification. a write command consists of a 7- bit device (slave) address + a write bit, an 8-bit register ad dress, and 8 bits of data as shown in figure 8. a write burst operation is also shown where every additional data word is written using to an auto-incremented address. scl vdd sda i 2 c bus intr a0 i 2 c address select: pull-up to vdd (a0 = 1) pull-down to gnd (a0 = 0) si5351 > 1k > 1k slave address 1 1 0 0 0 0 0/1 a0 0 1 2 3 4 5 6
si5351a/b/c 12 rev. 0.1 figure 8. i 2 c write operation a read operation is performed in two stages. a data writ e is used to set the register address, then a data read is performed to retrieve the data from the set address. a read burst operation is also supported. this is shown in figure 9. figure 9. i 2 c read operation ac and dc electrical specifications for the scl and sda pins are shown in table 9. the timing specifications and timing diagram for the i 2 c bus is compatible with the i 2 c-bus standard. sda timeout is supported for compatibility with smbus interfaces. 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high) s ? start condition p ? stop condition from slave to master from master to slave write operation ? single byte s 0 a reg addr [7:0] slv addr [6:0] a data [7:0] p a write operation - burst (auto address increment) reg addr +1 s 0 a reg addr [7:0] slv addr [6:0] a data [7:0] a data [7:0] p a 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high) s ? start condition p ? stop condition from slave to master from master to slave read operation ? single byte s 0 a reg addr [7:0] slv addr [6:0] a p read operation - burst (auto address increment) reg addr +1 s 1 a slv addr [6:0] data [7:0] p n s 0 a reg addr [7:0] slv addr [6:0] a p s 1 a slv addr [6:0] data [7:0] a p n data [7:0]
si5351a/b/c rev. 0.1 13 4. configuring the si5351 the si5351 is a highly flexible clock generator which is entirely conf igurable through its i 2 c interface. the device?s default configuration is stored in non-volatile memory (nvm) as shown in figure 10. the nvm is a one time programmable memory (otp) which can store a custom user co nfiguration at power-up. this is a useful feature for applications that need a clock present at power- up (e.g., for providing a clock to a processor). figure 10. si5351 memory configuration during a power cycle the contents of the nvm are copied into random access memory (ram), which sets the device configuration that will be us ed during normal operation. any change s to the device c onfiguration after power-up are made by reading and writing to registers in the ram space through the i 2 c interface. a detailed register map is shown in section 9. a development kit supports field programming which allows writing a custom configur ation directly to the nvm. since nvm is an otp memory, it can only be written once . the default configuration is always re-configurable by writing to ram through the i 2 c interface after power up. 5. si5351 application examples the si5351 is a versatile clock generator which serves a wide variety of applications. the following examples show how it can be used to replace crystals, crystal oscillators, vcxos, and plls. 5.1. replacing crystals and crystal oscillators using an inexpensive external crystal, the si5351a can generate up to 8 different free-running clock frequencies for replacing crystals and crystal oscilla tors. a 3 output version packaged in a small 10-mso p is also available for applications that require fewer clocks. an example is shown in figure 11. figure 11. using the si5351a to replace multiple crystals, crystal oscillators, and plls power-up i 2 c ram nvm (otp) default config 48 mhz usb controller 28.322 mhz 125 mhz video/audio processor 74.25/1.001 mhz 24.576 mhz osc xa xb clk0 clk1 clk2 clk3 clk4 clk5 pll multi synth 0 multi synth 1 multi synth 2 74.25 mhz 27 mhz si5351a multi synth 3 multi synth 4 multi synth 5 multi synth 7 hdmi port ethernet phy multi synth 6 22.5792 mhz clk6 33.3333 mhz clk7 cpu
si5351a/b/c 14 rev. 0.1 5.2. replacing crystals, cr ystal oscillators, and vcxos the si5351b combines free-running clock generation and a vcxo in a single packag e for cost sensitive video applications. an example is shown in figure 12. figure 12. using the si5351b to replace crystals, crystal oscillators, vcxos, and plls 5.3. replacing crystals, cr ystal oscillators, and plls the si5350c generates synchronous clocks for applications that require a fully integrated pll instead of a vcxo. because of its dual pll architecture, the si5351c is capable of generating both synchronous and free-running clocks. an example is shown in figure 13. figure 13. using the si5351c to replace crystals, crystal oscillators, and plls ethernet phy usb controller hdmi port 28.322 mhz 48 mhz 125 mhz video/audio processor 74.25/1.001 mhz 24.576 mhz osc xa xb clk0 clk1 clk2 clk3 clk4 clk5 pll vcxo multi synth 0 multi synth 1 multi synth 2 74.25 mhz vc 27 mhz si5351b multi synth 3 multi synth 4 multi synth 5 free-running clocks synchronous clocks note: f bw = 10 khz ethernet phy usb controller hdmi port 28.322 mhz 48 mhz 125 mhz video/audio processor 74.25/1.001 mhz 24.576 mhz osc xa xb clk0 clk1 clk2 clk3 clk4 clk5 pll pll multi synth 0 multi synth 1 multi synth 2 74.25 mhz clkin 25 mhz si5351c multi synth 3 multi synth 4 multi synth 5 54 mhz free-running clocks synchronous clocks
si5351a/b/c rev. 0.1 15 6. external compon ent recommendations the si5351 is a self-contained clock generator that requi res very few external components. the following general guidelines are recommended to ensure optimum perform ance. refer to application note an554 for additional layout recommendations. 6.1. power supply decoupling/filtering the si5351 has built-in power supply filt ering circuitry to help minimize the nu mber of external components. all that is recommended is one 0.1 f decoupling capacitor per power supply pin. this capacitor should be mounted as close to the vdd and vddox pins as possible without using vias. 6.2. power supply sequencing the vdd and vddox (i.e., vddo0, v ddo1, vddo2, vddo3) power supply pins have been separated to allow flexibility in output signal levels. it is important th at power is applied to al l supply pins (vdd, vddox) simultaneously. unused vddox pins should be tied to vdd. 6.3. external crystal the external crystal should be mounted as close to th e pins as possible using short pcb traces. the xa and xb traces should be kept away from other high-speed signal traces. see ?an5 51: crystal selection guide? for more details. 6.4. external crystal load capacitors the si5351 provides the option of using internal and external crystal load capacitors. if external load capacitors are used, they should be placed as clos e to the xa/xb pads as possible. see ?an554: layout recommendations? for more details. 6.5. unused pins unused voltage control pin should be tied to gnd. unused clkin pin should be tied to gnd. unused xa/xb pins should be tied to gnd. unused output pins (clk0?clk7) should be left floating. unused vddox pins should be tied to vdd.
si5351a/b/c 16 rev. 0.1 7. register map summary the following is a summary of the register map used to read status, control, and configure the si5351. register 7 6 5 4 3 2 1 0 0 sys_init lol_b lol_a los revid[1:0] 1 syscal_ stky los_b_ stky lol_a_ stky los_ stky 2 syscal_ mask los_b_ mask lol_a _ mask los_ mask 3 clk7_en clk6_en clk5_en clk4_en clk3_en clk2_en clk1_en clk0_en 4?8 reservedt 9 oeb_clk7 oeb_clk6 oeb_clk5 oeb_clk4 oeb_clk3 oeb_clk2 oeb_clk1 oeb_clk0 10?14 reserved 15 0 0 0 0 pllb_src plla_src 0 0 16 clk0_pdn ms0_int ms0_src clk0_inv 17 clk1_pdn ms1_int ms1_src clk1_inv 18 clk2_pdn ms2_int ms2_src clk2_inv 19 clk3_pdn ms3_int ms3_src clk3_inv 20 clk4_pdn ms4_int ms4_src clk4_inv 21 clk5_pdn ms5_int ms5_src clk5_inv 22 clk6_pdn ms6_int ms6_src clk6_inv 23 clk7_pdn ms7_int ms6_src clk7_inv 24 clk3_dis_state clk2_dis_state clk1_dis_state clk0_dis_state 25 clk7_dis_state clk6_dis_state clk5_dis_state clk4_dis_state 26?172 pll, multisynth, and output clock delay offset configuration registers. use clockbuilder desktop software to determine these register values. 173?176 reserved 177 pllb_rst plla_rst 178?182 reserved 183 xtal_cl 184?255 reserved
si5351a/b/c rev. 0.1 17 8. register descriptions reset value = 0000 0000 register 0. interrupt status sticky bitd7d6d5d4d3d2d1d0 name sys_init lol_b lol_a los revid[1:0] type rrrrrrrr bit name function 7sys_init system initialization status. during power up the device copies the content of the nvm into ram and performs a system initialization. the device is not operational until initializ ation is complete. it is not recom- mended to read or write registers in ram through the i 2 c interface until initialization is com- plete. an interrupt will be triggered (intr pin = 1, si5351c only) during the system initialization period. 0: system initialization is complete. device is ready. 1: device is in syst em initialization mode. 6lol_b pllb loss of lock status. si5351a/c only. pllb will operate in a locked st ate when it has a valid reference from clkin or xtal. a loss of lock will occur if the frequ ency of the reference cl ock forces the pll to operate outside of its lock range as specified in table 4, or if the reference clock fails to meet the minimum requirements of a va lid input signal as specified in table 6. an interrupt will be triggered (intr pin = 1, si5351c) during a lol condition. 0: pll b is locked. 1: pll b is unlocked. when the device is in th is state it will trigger an interrupt causing the intr pin to go high (si5351c only). 5lol_a pll a loss of lock status. pll a will operate in a locked state when it has a valid reference from clkin or xtal. a loss of lock will occur if the frequency of the reference clock forces the pll to oper ate outside of its lock range as specified in table 4, or if the reference cl ock fails to meet the minimum requirements of a valid input si gnal as specified in table 6 . an interrupt will be triggered (intr pin = 1, si5351c only) during a lol condition. 0: pll a is operating normally. 1: pll a is unlocked. when the device is in th is state it will trigger an interrupt causing the intr pin to go high (si5351c only). 4los clkin loss of signal (si5351c only). a loss of signal status indicates if the refere nce clock fails to meet the minimum requirements of a valid input signal as specified in tabl e 6. an interrupt will be triggered (intr pin = 1, si5351c only) during a los condition. 0: valid clock signal at the clkin pin. 1: loss of signal detected at the clkin pin. 3:2 reserved reserved. leave as default. 1:0 revid[1:0] revision id. device re vision number. set at the factory.
si5351a/b/c 18 rev. 0.1 reset value = 0000 0000 register 1. device status bit d7 d6 d5 d4 d3d2d1d0 name sys_init_stky lol_b_stky lol_a_stky los_stky type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 sys_init_stky system calibration st atus sticky bit. the sys_init_stky bit is trig gered when the sys_init bit (reg ister 0, bit 7) is trig- gered high. it remains high until cleared. writing a 0 to this register bit will cause it to clear. 0: no sys_init interrupt has occurred since it was last cleared. 1: a sys_init interrupt has occurr ed since it was last cleared. 6 lol_b_stky pllb loss of lock status sticky bit. the lol_b_stky bit is triggered when the lol_b bit (register 0, bit 6) is triggered high. it remains high until cl eared. writing a 0 to this register bit will cause it to clear. 0: no pll b interrupt has occurred since it was last cleared. 1: a pll b interrupt has occurred since it was last cleared. 5 lol_a_stky plla loss of lock status sticky bit. the lol_a_stky bit is triggered when the lol_a bit (register 0, bit 5) is triggered high. it remains high until cl eared. writing a 0 to this register bit will cause it to clear. 0: no plla interrupt has occurred since it was last cleared. 1: a plla interrupt has occurred since it was last cleared. 4los_stky clkin loss of signal sticky bit (si5351c only). the los_stky bit is triggered when the los bit (register 0, bit 4) is triggered high. it remains high until cleared. writing a 0 to this register bit will cause it to clear. 0: no los interrupt has occurred since it was last cleared. 1: a los interrupt has occurred since it was last cleared. 3:0 reserved reserved. leave as default.
si5351a/b/c rev. 0.1 19 reset value = 0000 0000 register 2. interrupt status mask bit d7 d6 d5 d4 d3d2d1d0 name sys_init_mask lol_b_mask lol_a_mask los_mask type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 sys_init_mask system initialization status mask. use this mask bit to prevent the intr pin (si5351c only) from going high when sys_init goes high. 0: do not mask t he sys_init interrupt. 1: mask the sys_in it interrupt. 6 lol_b_mask pllb loss of lock status mask. use this mask bit to prevent the intr pin (si5351c only) from going high when lol_b goes high. 0: do not mask the lol_b interrupt. 1: mask the lol_b interrupt. 5 lol_a_mask pll a loss of lock status mask. use this mask bit to prevent the intr pin (si5351c only) from going high when lol_a goes high. 0: do not mask the lol_a interrupt. 1: mask the lol_a interrupt. 4 los_mask clkin loss of signal mask (si5351c only). use this mask bit to prevent the intr pin (si5351c only) from going high when los goes high. 0: do not mask the los interrupt. 1: mask the los interrupt. 3:0 reserved reserved. leave as default.
si5351a/b/c 20 rev. 0.1 reset value = 0000 0000 reset value = 0000 0000 register 3. output enable control bitd7d6d5d4d3d2d1d0 name clk7_en clk6_en clk5_en clk4_en clk3_en clk2_en clk1_en clk0_en type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 clkx_en output enable for clkx. where x = 0, 1, 2, 3, 4, 5, 6, 7 0: enable clkx output. 1: disable clkx output. register 9. oeb pin enable control bitd7d6d5d4d3d2d1d0 name oeb_clk7 oeb_clk6 oeb_clk5 oeb_clk4 oeb_clk3 oeb_clk2 oeb_clk1 oeb_clk0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 oeb_clkx oeb pin enable control of clkx. where x = 0, 1, 2, 3, 4, 5, 6, 7 0: oeb pin controls enable/di sable state of clkx output. 1: oeb pin does not control enabl e/disable state of clkx output.
si5351a/b/c rev. 0.1 21 reset value = 0000 0000 register 15. pll input source bitd7d6d5d4d3d2d1d0 name pllb_src plla_src type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:4 reserved reserved . leave as default. 3 pllb_src input source select for pllb. 0: select the xtal input as the refe rence clock for pllb (si5351a/c only). 1: select the clkin input as the reference clock for pllb (si5351c only). 2 plla_src input source select for plla. 0: select the xtal input as the reference clock for plla. 1: select the clkin input as the reference clock for plla (si5351c only). 1:0 reserved reserved . leave as default.
si5351a/b/c 22 rev. 0.1 reset value = 0000 0000 register 16. clk0 control bitd7d6d5d4d3d2d1d0 name clk0_pdn ms0_int ms0_src clk0_inv clk0_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk0_pdn clock 0 power down. this bit allows powering down the clk0 outp ut driver to conserve power when the out- put is unused. 0: clk0 is powered up. 1: clk0 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk0. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk0. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk0_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk0_src[1:0] output clock 0 input source. these bits determine the input source for clk0. 00: select the xtal as the clock source fo r clk0. this option by -passes both synthesis stages (pll/vcxo & multisynth ) and connects clk0 direct ly to the oscillator which generates an output frequency determined by the xtal frequency. 01: select clkin as the clock source for clk0. this by-passes both synthesis stages (pll/vcxo & multisynth) and connects clk0 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk0. select this op tion when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c rev. 0.1 23 reset value = 0000 0000 register 17. clk1 control bitd7d6d5d4d3d2d1d0 name clk1_pdn ms1_int ms1_src clk1_inv clk1_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk1_pdn clock 0 power down. this bit allows powering down the clk1 outp ut driver to conserve power when the out- put is unused. 0: clk1 is powered up. 1: clk1 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk1. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk1. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk1_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk1_src[1:0] output clock 0 input source. these bits determine the input source for clk1. 00: select the xtal as the clock source for clk1. this option by-passes both synthesis stages (pll/vcxo & multisynth ) and connects clk1 directly to the oscillator which gen- erates an output frequency dete rmined by the xtal frequency. 01: select clkin as the clo ck source for clk1. this by-p asses both synthesis stages (pll/vcxo & multisynth) and connects clk1 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk1 . select this option when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c 24 rev. 0.1 reset value = 0000 0000 register 18. clk2 control bitd7d6d5d4d3d2d1d0 name clk2_pdn ms2_int ms2_src clk2_inv clk2_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk2_pdn clock 0 power down. this bit allows powering down the clk2 outp ut driver to conserve power when the out- put is unused. 0: clk2 is powered up. 1: clk2 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk2. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk2. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk2_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk2_src[1:0] output clock 0 input source. these bits determine the input source for clk2. 00: select the xtal as the clock source for clk2. this option by-passes both synthesis stages (pll/vcxo & multisynth ) and connects clk2 directly to the oscillator which gen- erates an output frequency dete rmined by the xtal frequency. 01: select clkin as the clo ck source for clk2. this by-p asses both synthesis stages (pll/vcxo & multisynth) and connects clk2 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk2 . select this option when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c rev. 0.1 25 reset value = 0000 0000 register 19. clk3 control bitd7d6d5d4d3d2d1d0 name clk3_pdn ms3_int ms3_src clk3_inv clk3_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7clk3_pdn clock 0 power down. this bit allows powering down the clk3 output driver to conserve power when the out- put is unused. 0: clk3 is powered up. 1: clk3 is powered down. 6 ms0_int multisynth 0 integer mode. this bit can be used to fo rce ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk3. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk3. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4clk3_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk3_src[1:0] output clock 0 input source. these bits determine the input source for clk3. 1:0 reserved reserved. leave as default.
si5351a/b/c 26 rev. 0.1 reset value = 0000 0000 register 20. clk4 control bitd7d6d5d4d3d2d1d0 name clk4_pdn ms4_int ms4_src clk4_inv clk4_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk4_pdn clock 0 power down. this bit allows powering down the clk4 output driver to conserve power when the out- put is unused. 0: clk4 is powered up. 1: clk4 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk4. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk4. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk4_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk4_src[1:0] output clock 0 input source. these bits determine the input source for clk4. 00: select the xtal as the clock source for clk4. this option by-passes both synthe- sis stages (pll/vcxo & multisynth) and c onnects clk4 directly to the oscillator which generates an output frequency determined by the xtal frequency. 01: select clkin as the clock source for clk4. this by-passes both synthesis stages (pll/vcxo & multisynth) and connects clk4 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk4. select this op tion when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c rev. 0.1 27 reset value = 0000 0000 register 21. clk5 control bitd7d6d5d4d3d2d1d0 name clk5_pdn ms5_int ms5_src clk5_inv clk5_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk5_pdn clock 0 power down. this bit allows powering down the clk5 output driver to conserve power when the out- put is unused. 0: clk4 is powered up. 1: clk4 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk4. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk5. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk5_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk5_src[1:0] output clock 0 input source. these bits determine the input source for clk5. 00: select the xtal as the clock source for clk5. this option by-passes both synthe- sis stages (pll/vcxo & multisynth) and c onnects clk5 directly to the oscillator which generates an output frequency determined by the xtal frequency. 01: select clkin as the clock source for clk5. this by-passes both synthesis stages (pll/vcxo & multisynth) and connects clk5 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk5. select this op tion when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c 28 rev. 0.1 reset value = 0000 0000 register 22. clk6 control bitd7d6d5d4d3d2d1d0 name clk6_pdn ms6_int ms6_src clk6_inv clk6_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk6_pdn clock 0 power down. this bit allows powering down the clk6 output driver to conserve power when the out- put is unused. 0: clk6 is powered up. 1: clk6 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk6. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk6. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk6_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk6_src[1:0] output clock 0 input source. these bits determine the input source for clk6. 00: select the xtal as the clock source for clk6. this option by-passes both synthe- sis stages (pll/vcxo & multisynth) and c onnects clk6 directly to the oscillator which generates an output frequency determined by the xtal frequency. 01: select clkin as the clock source for clk6. this by-passes both synthesis stages (pll/vcxo & multisynth) and connects clk6 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk6. select this op tion when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c rev. 0.1 29 reset value = 0000 0000 register 23. clk7 control bitd7d6d5d4d3d2d1d0 name clk7_pdn ms7_int ms7_src clk7_inv clk7_src[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 clk7_pdn clock 0 power down. this bit allows powering down the clk7 output driver to conserve power when the out- put is unused. 0: clk7 is powered up. 1: clk7 is powered down. 6ms0_int multisynth 0 integer mode. this bit can be used to force ms0 into integer mode to improve jitter performance. note that the fractional mode is necessary when a delay offset is specified for clk7. 0: ms0 operates in fractional division mode. 1: ms0 operates in integer mode. 5ms0_src multisynth source select for clk7. 0: select plla as the source for multisynth0. 1: select pllb (si5351a/c only) or vcxo (si5351b only) multisynth0. 4 clk7_inv output clock 0 invert. 0: output clock 0 is not inverted. 1: output clock 0 is inverted. 3:2 clk7_src[1:0] output clock 0 input source. these bits determine the input source for clk7. 00: select the xtal as the clock source for clk7. this option by-passes both synthe- sis stages (pll/vcxo & multisynth) and c onnects clk7 directly to the oscillator which generates an output frequency determined by the xtal frequency. 01: select clkin as the clock source for clk7. this by-passes both synthesis stages (pll/vcxo & multisynth) and connects clk7 directly to the clkin input. this essen- tially creates a buffered output of the clkin input. 10: reserved. do not select this option. 11: select multisynth 0 as the source for clk7. select this op tion when using the si5351 to generate free-running or synchronous clocks. 1:0 reserved reserved. leave as default.
si5351a/b/c 30 rev. 0.1 reset value = 0000 0000 reset value = 0000 0000 register 24. clk3?0 disable state bitd7d6d5d4d3d2d1d0 name clk3_dis_state clk2_dis_state clk1_dis_state clk0_dis_state type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 clkx_dis_state clock x disable state. where x = 0, 1, 2, 3. these 2 bits determi ne the state of the clkx output when dis- abled. individual output clocks can be disabled using register output enable con- trol located at address 3. outputs are also disabled using the oeb pin. 00: clkx is set to a low state when disabled. 01: clkx is set to a high state when disabled. 10: clkx is set to a high impedance state when disabled. 11: clkx is never disabled. register 25. clk7?4 disable state bitd7d6d5d4d3d2d1d0 name clk7_dis_state clk6_dis_state clk5_dis_state clk4_dis_state type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 clkx_dis_state clock x disable state. where x = 4, 5, 6, 7. these 2 bits determi ne the state of the clkx output when dis- abled. individual output clocks can be disabled using register output enable con- trol located at address 3. outputs are also disabled using the oeb pin. 00: clkx is set to a low state when disabled. 01: clkx is set to a high state when disabled. 10: clkx is set to a high impedance state when disabled. 11: clkx is never disabled.
si5351a/b/c rev. 0.1 31 reset value = 0000 0000 reset value = 11xx xxxx register 177. pll reset bitd7d6d5d4d3d2d1d0 name pllb_rst plla_rst type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7pllb_rst pllb_reset. writing a 1 to this bit will reset pllb. this is a self clearing bit (si5351a/c only). 6 reserved reserved. leave as default. 5plla_rst plla_reset. writing a 1 to this bit will reset pl la. this is a self clearing bit. 4:0 reserved reserved. leave as default. register 183. crystal internal load capacitance bitd7d6d5d4d3d2d1d0 name xtal_cl[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:6 xtal_cl[1:0] crystal load capacitance selection. these 2 bits determine the internal load capacitance value for the crystal. see "2.1.1. crystal inputs (xa, xb)" on page 8. 00: reserved. do not select this option. 01: internal cl = 6 pf. 10: internal cl = 8 pf. 11: internal cl = 10 pf (default). 5:0 reserved reserved. leave as default.
si5351a/b/c 32 rev. 0.1 9. detailed block diagrams figure 14. block diagrams of 3-output and 8-output si5351a devices pll b pll a sda scl osc xa xb vddo r0 r1 clk0 clk1 r2 clk2 multisynth 0 multisynth 1 multisynth 2 vdd gnd 10-msop si5351a 3-output r0 r1 clk0 clk1 vddoa r2 r3 clk2 clk3 vddob r4 r5 clk4 clk5 vddoc r6 r7 clk6 clk7 vddod multisynth 0 multisynth 1 multisynth 2 multisynth 3 multisynth 4 multisynth 5 multisynth 6 multisynth 7 vdd gnd 20-qfn, 24-qsop scl a0 sda control logic oeb ssen i 2 c interface si5351a 8-output i 2 c interface pll b pll a osc xa xb
si5351a/b/c rev. 0.1 33 figure 15. block diagrams of si5351b and si5351c 8-output devices osc xa xb pll vcxo r0 r1 clk0 clk1 vddoa r2 r3 clk2 clk3 vddob r4 r5 clk4 clk5 vddoc r6 r7 clk6 clk7 vddod multisynth 0 multisynth 1 multisynth 2 multisynth 3 multisynth 4 multisynth 5 multisynth 6 multisynth 7 vc vdd gnd si5351b scl sda control logic oeb ssen i 2 c interface 20-qfn, 24-qsop r0 r1 clk0 clk1 vddoa r2 r3 clk2 clk3 vddob r4 r5 clk4 clk5 vddoc r6 r7 clk6 clk7 vddod multisynth 0 multisynth 1 multisynth 2 multisynth 3 multisynth 4 multisynth 5 multisynth 6 multisynth 7 vdd gnd si5351c pll a pll b xa xb osc clkin scl sda control logic intr oeb i 2 c interface 20-qfn, 24-qsop
si5351a/b/c 34 rev. 0.1 10. pin descriptions (10-pin msop) pin name pin number pin type* function 10-msop xa 2 i input pin for external crystal. xb 3 i input pin for external crystal. clk0 10 o output clock 0. clk1 9 o output clock 1. clk2 6 o output clock 2. scl 4 i serial clock input for the i 2 c bus. this pin must be pulled-up using a pull- up resistor of at least 1 k ? . sda 5 i/o serial data input for the i 2 c bus. this pin must be pulled-up using a pull-up resistor of at least 1 k ? . vdd 1 p core voltage supply pin. vddo 7 p output voltage supply pin for clk0, clk1, and clk2. see "6.2. power supply sequencing" on page 15. gnd 8 p ground. *note: i = input, o = output, p = power si5351a 10-msop top view xa vdd scl xb 2 1 4 3 clk1 clk0 vddo gnd 9 10 7 8 sda 5 clk2 6
si5351a/b/c rev. 0.1 35 11. si5351a pin descriptions (20-pin qfn, 24-pin qsop) table 10: pin name pin number pin type* function 20-qfn 24-qsop xa 1 6 i input pin for external crystal. xb 2 7 i input pin for external crystal. clk0 13 21 o output clock 0. clk1 12 20 o output clock 1. clk2 9 15 o output clock 2. clk3 8 14 o output clock 3. clk4 19 3 o output clock 4. clk5 17 1 o output clock 5. clk6 16 24 o output clock 6. clk7 15 23 o output clock 7. a0 3 9 i i 2 c address bit. scl 4 10 i i 2 c bus serial clock input. pull-up to vdd core with 1 k ?? sda 5 11 i/o i 2 c bus serial data input. pu ll-up to vdd core with 1 k ?? ssen 6 12 i spread spectrum enable. hi gh = enabled, low = disabled. oeb 7 13 i output driver enable. low = enabled, high = disabled. vdd 20 4 p core voltage supply pin. see 6.2. vddoa 11 18 p output voltage supply pin for clk0 and clk1. see 6.2. vddob 10 16 p output voltage supply pin for clk2 and clk3. see 6.2. vddoc 18 2 p output voltage supply pin for clk4 and clk5. see 6.2. vddod 14 22 p output voltage supply pin for clk6 and clk7. see 6.2. gnd center pad 5, 8, 17, 19 p ground. use multip le vias to ensure a solid path to gnd. 1. i = input, o = output, p = power. 2. input pins are not internally pulled up. 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 xa xb a0 scl sda oeb clk3 clk2 vddob ssen si5351a 20-qfn top view gnd pad clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7 2 1 4 3 6 5 8 7 10 9 12 11 23 24 21 22 19 20 17 18 15 16 13 14 si5351a 24-qsop top view clk7 clk6 clk0 vdd0d gnd clk1 gnd vddoa clk2 vdd0b oeb clk3 vddoc clk5 vdd clk4 xa gnd gnd xb scl a0 ssen sda
si5351a/b/c 36 rev. 0.1 12. si5351b pin descriptions (20-pin qfn, 24-pin qsop) pin name pin number pin type* function 20-qfn 24-qsop xa 1 6 i input pin for external crystal xb 2 7 i input pin for external crystal clk0 13 21 o output clock 0 clk1 12 20 o output clock 1 clk2 9 15 o output clock 2 clk3 8 14 o output clock 3 clk4 19 3 o output clock 4 clk5 17 1 o output clock 5 clk6 16 24 o output clock 6 clk7 15 23 o output clock 7 vc 3 9 i vcxo control voltage input scl 4 10 i i 2 c bus serial clock input. pull-up to vdd core with 1 k ?? sda 5 11 i/o i 2 c bus serial data input. pu ll-up to vdd core with 1 k ?? ssen 6 12 i spread spectrum enable. hi gh = enabled, low = disabled. oeb 7 13 i output driver enable. low = enabled, high = disabled. vdd 20 4 p core voltage supply pin vddoa 11 18 p output voltage supply pin for clk0 and clk1. see 6.2 vddob 10 16 p output voltage supply pin for clk2 and clk3. see 6.2 vddoc 18 2 p output voltage supply pin for clk4 and clk5. see 6.2 vddod 14 22 p output voltage supply pin for clk6 and clk7. see 6.2 gnd center pad 5, 8, 17, 19 p ground *note: i = input, o = output, p = power *note: input pins are not internally pulled up. 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 xa xb vc scl sda oeb clk3 clk2 vddob ssen si5351b 20-qfn top view gnd pad clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7 2 1 4 3 6 5 8 7 10 9 12 11 23 24 21 22 19 20 17 18 15 16 13 14 si5351b 24-qsop top view vddoc clk5 vdd clk4 xa gnd gnd xb scl vc ssen sda clk7 clk6 clk0 vdd0d gnd clk1 gnd vddoa clk2 vdd0b oeb clk3
si5351a/b/c rev. 0.1 37 13. si5351c pin descriptions (20-pin qfn, 24-pin qsop) pin name pin number pin type* function 20-qfn 24-qsop xa 1 6 i input pin for external crystal. xb 2 7 i input pin for external crystal. clk0 13 21 o output clock 0. clk1 12 20 o output clock 1. clk2 9 15 o output clock 2. clk3 8 14 o output clock 3. clk4 19 3 o output clock 4. clk5 17 1 o output clock 5. clk6 16 24 o output clock 6. clk7 15 23 o output clock 7. intr 3 9 o interrupt pin. hi gh = interrupt active. scl 4 10 i i 2 c bus serial clock input. pull-up to vdd core with 1 k ?? sda 5 11 i/o i 2 c bus serial data input. pu ll-up to vdd core with 1 k ?? clkin 6 12 i pll clock input. oeb 7 13 i output driver enable. low = enabled, high = disabled. vdd 20 4 p core voltage supply pin vddoa 11 18 p output voltage supply pin for clk0 and clk1. see 6.2 vddob 10 16 p output voltage supply pin for clk2 and clk3. see 6.2 vddoc 18 2 p output voltage supply pin for clk4 and clk5. see 6.2 vddod 14 22 p output voltage supply pin for clk6 and clk7. see 6.2 gnd center pad 5, 8, 17, 19 p ground. *note: i = input, o = output, p = power *note: input pins are not internally pulled up 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 xa xb intr scl sda oeb clk3 clk2 vddob clkin si5351c 20-qfn top view gnd pad clk6 clk5 vddoc clk4 vdd vddoa clk1 clk0 vddod clk7 2 1 4 3 6 5 8 7 10 9 12 11 23 24 21 22 19 20 17 18 15 16 13 14 si5351c 20-qsop top view vddoc clk5 vdd clk4 xa gnd gnd xb scl intr clkin sda clk7 clk6 clk0 vdd0d gnd clk1 gnd vddoa clk2 vdd0b oeb clk3
si5351a/b/c 38 rev. 0.1 14. package out line (24-pin qsop) table 11. 24-qsop package dimensions dimension min nom max a??1.75 a1 0.10 ? 0.25 b 0.19 ? 0.30 c 0.15 ? 0.25 d 8.558.658.75 e 6.00 bsc e1 3.81 3.90 3.99 e 0.635 bsc l 0.40 ? 1.27 l2 0.25 bsc q0?8 aaa 0.10 bbb 0.17 ccc 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components.
si5351a/b/c rev. 0.1 39 15. package out line (20-pin qfn) table 12. package dimensions dimension min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 4.00 bsc d2 2.65 2.70 2.75 e 0.50 bsc e 4.00 bsc e2 2.65 2.70 2.75 l 0.300.400.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.10 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components. ?
si5351a/b/c 40 rev. 0.1 16. package out line (10-pin msop) table 13. 24-qsop package dimensions dimension min nom max a??1.10 a1 0.00 ? 0.15 a2 0.75 0.85 0.95 b 0.17 ? 0.33 c 0.08 ? 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.400.600.80 l2 0.25 bsc q0?8 aaa ? ? 0.20 bbb ? ? 0.25 ccc ? ? 0.10 ddd ? ? 0.08 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec so lid state outline mo-137, variation c 4. recommended card reflow profile is per the jede c/ipc j-std-020 specification for small body components. ?
si5351a/b/c rev. 0.1 41 17. ordering information figure 16. device part numbers a development kit containing clockbuilder desktop software and hardware enable easy field programming of blank si5351 devices for instances when rapi d prototyping is required. note that the si5351 must be field-programmed using the development kit. in addition to field prog ramming, this development kit supports simplified device evaluation of any si5351 device. the orderable part numb ers for the development kits are provided in figure 17. figure 17. development kit part numbers si5351x xx a a = product revision a a = crystal in b = crystal in + vcxo c = crystal in + clkin gt = 10-msop gm = 20-qfn gu = 24-qsop si535x evb xxxxx xxxxx = evb = device and field programming kit 20-qfn 24-qsop
si5351a/b/c 42 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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