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sy89855u precision low power di fferential lvpecl 4:1 mux with 1:2 fanout and internal termination precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com august 2007 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 general description the sy89855u is a 2.5v/3.3v precision, high-speed, 4:1 differential multiplexe r with 100k lvpecl (800mv) compatible outputs, capable of handling clocks up to 2.5ghz and data streams up to 2.5gbps. in addition, a 1:2 fanout buffer provides tw o copies of the selected inputs. the differential input includes micrel?s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (ac- or dc-coupled) as small as 100mv without any level shifting or termination resistor network s in the signal path. the result is a clean, stub-free, low-jitter interface solution. the outputs are 800mv l vpecl, (100k temperature compensated) with fast rise/fall times guaranteed to be less than 180ps. the sy89855u operates from a 2.5v 5% supply or a 3.3v 10% supply and is guaranteed over the full industrial temperature range of ?40c to +85c. for applications that require hi gher performance, consider the sy58029u. the sy89855u is part of micrel?s high- speed, precision edge ? product line. all support documentation can be found on micrel?s web site at www.micrel.com . typical performance precision edge ? features ? select 1 of 4 differential inputs ? provides two copies of the selected input ? low power 260mw (v cc = 2.5v) ? guaranteed ac performance over temperature and voltage: ? dc-to->2.5gbps data rate throughput ? <410ps in-to-q t pd ? <180ps t r / t f times ? ultra low-jitter design: ? <10ps pp total jitter (clock) ? <1ps rms random jitter ? <10ps pp deterministic jitter ? <0.7ps rms crosstalk-induced jitter ? unique, patent-pending input design minimizes crosstalk ? accepts an input signal as low as 100mv ? unique patented input termination and vt pin accepts dc- and ac-coupled inputs (cml, lvpecl, lvds) ? 800mv 100k lvpecl output swing ? power supply 2.5v 5% or 3.3v 10% ? ?40c to +85c temperature range ? available in 32-pin (5mm x 5mm) qfn package applications ? redundant clock and/or data distribution ? all sonet/oc-3 to oc-48 clock/data distribution ? loopback ? all fibre channel applications ? all gige applications markets ? lan/wan communication ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89855u august 2007 2 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 functional block diagram truth table sel1 sel0 q 0 0 in0 input select 0 1 in1 input select 1 0 in2 input select 1 1 in3 input select
micrel, inc. sy89855u august 2007 3 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish sy89855umg qfn-32 industrial sy89855u with pb-free bar-line indicator nipdau pb-free SY89855UMGTR (2) qfn-32 industrial sy89855u with pb-free bar-line indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25oc, dc electricals only. 2. tape and reel. pin configuration 32-pin qfn pin description pin number pin name pin function 1, 4 5, 8 25, 28 29, 32 in0, /in0, in1, /in1, in2, /in2, in3, /in3 differential input: each pair accepts ac- or dc-coupled signals as small as 100mv. each pin of a pair internally terminates to a vt pin through 50 ? . note that these inputs will default to an indeterminate state if left open. if an input is not used, connect one end of the differential pairs to ground through a 1k ? resistor, and leave the other end to vcc through an 825 ? resistor. unused vt and vref-ac pins may also be left floating. please refer to the ?input interface applicatio ns? section for more details. 2, 6 26, 30 vt0, vt1 vt2, vt3 input termination center-tap: ea ch side of the differential input pair terminates to a vt pin. the vt pin provides a center-tap to the termination network for maximum interface flexibility. see ?input interface app lications? section for more details. 15, 18 sel0, sel1 this single-ended ttl/cmos compatible input se lects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. input logic threshold is v cc /2. see ?truth table? for select control. 14, 19 nc not connected. 10, 13, 16 17, 20, 23 vcc positive power supply: bypass with 0.1f||0.01f low esr capacitors placed as close as possible to each vcc pin. 11, 12 21, 22 /q0, q0 /q1, q1 differential outputs: these 100k-compatibl e (internally temperature compensated) lvpecl output pairs are copies of the se lected input. unused output pins may be left floating. see ?output interfac e? for terminating guidelines. 9, 24 gnd, exposed pad ground: ground pins and exposed pad must be connected to the most negative potential of the chip. 3 7 27 31 vref-ac0, vref-ac1, vref-ac2, vref-ac3 reference voltage: this reference output is equivalent to v cc ?1.2v. it is used for ac- coupled inputs. when interfacing to ac input signals, connect vref-ac directly to the vt pin and bypass with a 0.01f low esr capacitor to vcc. see ?input interface applications? section. maximum si nk/source current is 1.5ma.
micrel, inc. sy89855u august 2007 4 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ............................?0.5v to +4.0v input voltage (v in ) ....................................?0.5v to v cc lvpecl output current (i out ) continuous................................................. 50ma surge ....................................................... 100ma termination current source or sink current on v t .................. 100ma input current source or sink current on in, /in.............. 50ma current (v ref-ac ) source or sink current on v ref-ac ............... 2ma lead temperature (solde ring, 20sec .) ...............260c storage temperature (t s ) ................ ?65c to +150c operating ratings (2) supply voltage (v cc ) .....................+2.375v to +2.625v ..................................................... +3.0v to +3.6v ambient temperature (t a )....................?40c to +85c package thermal resistance (3) qfn ( ja ) still-ai r......................................................35c/w 500lfpm ....................................................28c/w qfn ( jb ) junction-to- board.....................................16c/w dc electrical characteristics (4) t a = ?40c to +85c, unless otherwise noted. symbol parameter condition min typ max units v cc power supply voltage v cc = 2.5v v cc = 3.3v 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc power supply current no load, max. v cc . 65 85 ma r in input resistance (in-to-vt) 45 50 55 ? r diff_in differential input resistance (in-to-/in, /in-to-v t ) 90 100 110 ? v ih input high voltage (in, /in) note 5 v cc ? 1.6 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in input voltage swing (in-to-/in) see figure 1a. 0.1 1.7 v v diff_in differential input voltage swing | in - /in | see figure 1b. 0.2 v v t_in maximum input voltage (in-to-v t ) 1.28 v v ref-ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those deta iled in the operational sections of this data sheet. exposure to absolute maximum ra tings conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the devices most negative potential on the pcb . ja and jb values are determined for a 4-layer board in still-air, unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 5. v ih (min) not lower than 1.2v.
micrel, inc. sy89855u august 2007 5 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 lvpecl output dc elec trical characteristics (5) v cc = 2.5v 5% or 3.3v 10%; r l = 50 ? to v cc ?2v; t a = ?40c to +85c, unless otherwise noted. symbol parameter condition min typ max units v oh output high voltage (q, /q) v cc ?1.145 v cc ?0.895 v v ol output low voltage (q, /q) v cc ?1.945 v cc ?1.695 v v out output voltage swing (q, /q) see figure 1a. 400 800 mv v diff-out differential output voltage swing (q, /q) see figure 1b. 800 1600 mv lvttl/cmos dc electri cal characteristics (5) v cc = 2.5v 5% or 3.3v 10%; t a = ?40c to +85c, unless otherwise noted. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current v in = v cc 75 a i il input low current v in = 0.5v ?300 a notes: 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. sy89855u august 2007 6 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = ?40c to + 85c, r l = 50 ? to v cc ?2v, unless otherwise stated. symbol parameter condition min typ max units nrz data 2.5 gbps f max maximum operating frequency clock, v out > 400mv 2.5 ghz v in > 100mv 210 300 410 ps t pd propagation delay in-to-q sel-to-q 100 300 500 ps t pd tempco differential propagation delay temperature coefficient 234 fs/c output-to-output note 7 9 20 ps t skew part-to-part note 8 150 ps data random jitter (rj) note 9 1 ps rms deterministic jitter (dj) note 10 10 ps pp clock cycle-to-cycle jitter note 11 1 ps rms total jitter (tj) note 12 10 ps pp t jitter crosstalk-induced jitter (adjacent channel) note 13 0.7 ps rms t r, t f output rise/fall time (20% to 80% ) at full output swing. 50 100 180 ps notes: 6. high frequency ac electricals are guar anteed by design and characterization. 7. output-to-output skew is measured bet ween outputs under identic al input conditions. 8. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 9. random jitter is measured with a k 28.7 character pattern, measured at micrel, inc. sy89855u august 2007 7 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 2.5v, gnd = 0, v in = 100mv; t a = ?40c to + 85c, r l = 50 ? to v cc ?2v, unless otherwise stated.
micrel, inc. sy89855u august 2007 8 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 functional characteristics v cc = 3.3v 10%; t a = ?40c to + 85c, r l = 50 ? to v cc ?2v, unless otherwise stated.
micrel, inc. sy89855u august 2007 9 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 single-ended and di fferential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing timing diagram in-to-q timing diagram sel-to-q timing diagram
micrel, inc. sy89855u august 2007 10 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 input and output stages figure 2a. simplified differential input stage figure 2b. pecl output stage input interface applications figure 3a. lvpecl interface (dc-coupled) option: may connect vt to v cc figure 3b. lvpecl interface (ac-coupled) figure 3c. cml interface (dc-coupled) figure 3d. cml interface (ac-coupled) figure 3e. lvds interface
micrel, inc. sy89855u august 2007 11 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 output interface applications lvpecl has high input im pedance, very low output (open emitter) impedance, and small signal swing, which result in low emi. l vpecl is ideal for driving 50 ? and 100 ? controlled impedance transmission lines. there are different techniques for terminating lvpecl outputs: parallel termination thevenin- equivalent, parallel termination (3-resistor), and ac- coupled termination. unused output pairs may be left floating; however, single-ended outputs must be terminated or balanced. note: for a 2.5v system, r1 = 250 ? , r2 = 62.5 ? . figure 4a. parallel thevenin-equivalent termination note: 1. for a 2.5v system, rb = 19 ? . figure 4b. parallel termination (3-resistor) note: for a 2.5v system, r = 50 ? . figure 4c. ac-coupled termination note: for a 2.5v system, r1 = 250 ? , r2 = 62.5 ? . figure 4d. parallel thevenin-equivalent termination related product and su pport documentation part number function data sheet link sy58029u ultra precision differential lvpecl 4 :1 mux with 1 :2 fanout internal termination www.micrel.com/product-info/p roducts/sy58029u.shtml. hbw solutions new products and applications www.micrel.com/product-info/products/solutions.shtml
micrel, inc. sy89855u august 2007 12 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 package information 32-pin qfn pcb thermal consideration for 32-pin qfn package (always solder, or equivalent, the exposed pad to the pcb) packages notes: 1. package meets level 2 moisture sensitivity classification. 2. all parts are dry-packed before shipment. 3. exposed pads must be soldered to a ground for proper thermal management.
micrel, inc. sy89855u august 2007 13 m9999-082907-c hbwhelp@micrel.com or (408) 955-1690 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support applianc es, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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