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revision 0.0 october 2002 k1s1616b1m - 1 - u t ram advance document title 1mx16 bit uni-transistor random access memory the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision history revision no. 0.0 remark advanced history initial draft draft date october 17, 2002
revision 0.0 october 2002 k1s1616b1m - 2 - u t ram advance product family product family operating temp. vcc range speed power dissipation pkg type standby (i sb1 , max.) operating (i cc2 , max.) k1s1616b1m-i industrial(-40~85 c) 1.7v~2.2v 70/85ns 60 m a 25ma 48-tbga-6.00x7.00 1m x 16 bit uni-transistor cmos ram general description the k1s1616b1m is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device supports industrial temperature range and 48 ball chip scale package for user flexibility of system design. the device also supports dual chip selection for user interface. features process technology: cmos organization: 1m x16 bit power supply voltage: 1.7v~2.2v three state outputs compatible with low power sram dual chip selection support package type: 48-tbga-6.00x7.00 samsung electronics co., ltd. reserves the right to change products and specifications without notice . pin description 1) reserved for future use. name function name function cs 1,cs2 chip select inputs vcc power oe output enable input vss ground we write enable input ub upper byte(i/o 9 ~ 16 ) a 0 ~a 19 address inputs lb lower byte(i/o 1 ~ 8 ) i/o 1 ~i/o 16 data inputs/outputs dnu do not use 1) 48-tbga: top view(ball down) lb oe a0 a1 a2 cs2 i/o9 ub a3 a4 cs 1 i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vss i/o12 a17 a7 i/o4 vcc vcc i/o13 dnu a16 i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 a19 a12 a13 we i/o8 a18 a8 a9 a10 a11 dnu 1 2 3 4 5 6 a b c d e f g h functional block diagram clk gen. row select i/o 1 ~i/o 8 data cont data cont data cont i/o 9 ~i/o 16 vcc vss precharge circuit. memory array i/o circuit column select we oe ub cs 1 lb control logic cs2 row addresses column addresses
revision 0.0 october 2002 k1s1616b1m - 3 - u t ram advance power up sequence 1. apply power. 2. maintain stable power(vcc min.=1.7v) for a minimum 200 m s with cs 1=high.or cs2=low. 3. issue read operation at least twice. absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c functional description 1. x means don t care.(must be low or high state) cs 1 cs2 oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active product list industrial temperature products(-40~85 c) part name function k1s1616b1m-ei70 K1S1616B1M-EI85 48-tbga-6.00x7.00, 70ns 48-tbga-6.00x7.00, 85ns
revision 0.0 october 2002 k1s1616b1m - 4 - u t ram advance recommended dc operating conditions 1) 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: vcc+1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 1.7v 1.8v 2.2v v ground vss 0 0 0 v input high voltage v ih 1.4 - v cc +0.2 2) v input low voltage v il -0.2 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1=v ih or cs2=v il or oe =v ih or we =v il or lb = ub =v ih , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 1 0.2v, lb 0.2v or/and ub 0.2v, cs2 3 v cc - 0.2v, v in 0.2v or v in 3 v cc - 0.2v - - 5 ma i cc2 cycle time=min, i io =0ma , 100% duty, cs 1=v il, cs2 = v ih lb =v il or/and ub =v il , v in =v ih or v il - - 25 ma output low voltage v ol i ol = 0.1ma - - 0.2 v output high voltage v oh i oh = -0.1ma 1.4 - - v standby current(cmos) i sb1 other inputs=0~vcc 1) cs 1 3 v cc -0.2v , cs2 3 v cc - 0.2v( cs 1 controlled) or 2) 0v cs2 0.2v(cs2 controlled) - - 60 m a
revision 0.0 october 2002 k1s1616b1m - 5 - u t ram advance ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to vcc-0.2v input rising and falling time: 5ns input and output reference voltage: 0.5 x v cc output load (see right): c l =50pf c l 1. including scope and jig capacitance dout ac characteristics (vcc=1.7~2.2v, t a =-40 to 85 c) 1. t wp (min)=70ns for continuous write operation over 50 times.(only in case of we controlled write operation) parameter list symbol speed bins units 70ns 85ns min max min max read read cycle time t rc 70 - 85 - ns address access time t aa - 70 - 85 ns chip select to output t co - 70 - 85 ns output enable to valid output t oe - 35 - 40 ns ub , lb access time t ba - 70 - 85 ns chip select to low-z output t lz 10 - 10 - ns ub , lb enable to low-z output t blz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 ns ub , lb disable to high-z output t bhz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns output hold from address change t oh 5 - 5 - ns write write cycle time t wc 70 - 85 - ns chip select to end of write t cw 60 - 70 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 60 - 70 - ns ub , lb valid to end of write t bw 60 - 70 - ns write pulse width t wp 55 1) - 60 1) - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 25 0 25 ns data to write time overlap t dw 30 - 35 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns
revision 0.0 october 2002 k1s1616b1m - 6 - u t ram advance address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , cs 2 = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. if invalid address signals shorter than min. t rc are continuously repeated for over 4us, the device needs a normal read timing(t rc ) or needs to sustain standby state for min. t rc at least once in every 4us. cs 2
revision 0.0 october 2002 k1s1616b1m - 7 - u t ram advance timing waveform of write cycle(2) ( cs 1 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs 1 cs 2 timing waveform of write cycle(1) ( we controlled) address cs 1 data undefined ub , lb we data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs 2
revision 0.0 october 2002 k1s1616b1m - 8 - u t ram advance address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(4) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs 1 or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs 1 cs 2 timing waveform of write cycle(3) (cs 2 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs 1 cs 2
revision 0.0 october 2002 k1s1616b1m - 9 - u t ram advance 200 m s read operation twice timing waveform of power up(1) ( cs 1 controlled) timing waveform of power up(2) (cs 2 controlled) power up(2) 1. after v cc reaches v cc (min.) following power application, wait 200 m s with cs 2 high and then toggle cs 2 low and commit read operation at least twice. then you get into the normal operation. 2. read operation should be executed after toggling cs 2 pin low. 3. the read operation must satisfy the specified t rc . ? ? ? ? v cc cs 1 cs 2 v cc(min) power up(1) 1. after v cc reaches v cc (min.) following power application, wait 200 m s with cs 1 high and then toggle cs 1 low and commit read operation at least twice. then you get into the normal operation. 2. read operation should be executed after toggling cs 1 pin low. 3. the read operation must satisfy the specified t rc . 200 m s read operation twice ? v cc cs 1 cs 2 v cc(min) ? ? ?
revision 0.0 october 2002 k1s1616b1m - 10 - u t ram advance timing waveform of power up(3) ( cs 1 controlled) power up(3) 1. after v cc reaches v cc (min.) following power application, wait 200 m s and wait another 300 m s with cs 1 high if you don?t want to commit dummy read cycle. after total 500 m s wait, toggle cs 1 low, then you get into the normal mode. timing waveform of power up(4) (cs 2 controlled) power up(4) 1. after v cc reaches v cc (min.) following power application, wait 200 m s and wait another 300 m s with cs 2 low if you don?t want to commit dummy read cycle. after total 500 m s wait, toggle cs 2 high, then you get into the normal mode. ? ? ? ? v cc cs 2 cs 1 v cc(min) 200 m s 300 m s ? ? ? ? ? ? ? ? v cc cs 2 cs 1 v cc(min) 200 m s 300 m s ? ? ? ?
revision 0.0 october 2002 k1s1616b1m - 11 - u t ram advance c 1 / 2 package dimension 6 5 4 3 2 1 a b c d e f g h c b/2 b c 1 b c bottom view top view d e 2 e 1 e c side view 0 . 5 5 / t y p . 0 . 3 5 / t y p . a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 6.90 7.00 7.10 c1 - 5.25 - d 0.40 0.45 0.50 e - 0.90 1.00 e1 - 0.55 - e2 0.30 0.35 0.40 y - - 0.08 b1 #a1 notes. 1. bump counts: 48(8 row x 6 column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are 0.050 unless specified beside figures. 4. typ : typical 5. y is coplanarity: 0.08(max) unit: millimeters 48 tape ball grid array(0.75mm ball pitch)

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