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smsc lan8810/lan8810i revision 1.0 (02-06-13) datasheet datasheet product features lan8810/lan8810i gmii 10/100/1000 ethernet transceiver with hp auto-mdix support highlights ? single-chip ethernet physical layer transceiver (phy) ? compliant with ieee 802.3ab (1000base-t), ieee 802.3u (fast ethernet), and iso 802-3/ieee 802.3 (10base-t) ? hp auto-mdix support in accordance with ieee 802.3ab specification at 10/100/1000 mbps operation ? small footprint 72-pin qfn lead-free rohs compliant package with gmii (10 x 10 x 0.9mm height) ? flexible configurations for led status indicators ? implements reduced power operating modes target applications ? set-top boxes ? networked printers and servers ? test instrumentation ? lan on motherboard ? embedded telecom applications ? video record/playback systems ? cable modems/routers ? dsl modems/routers ? digital video recorders ? ip and video phones ? wireless access points ? digital televisions ? digital media adaptors/servers ? gaming consoles ? poe applications key benefits ? high-performance 10/100/1000 ethernet transceiver ? compliant with ieee 802.3ab (1000base-t) ? compliant with ieee 802.3/802.3u (fast ethernet) ? compliant with iso 802-3/ieee 802.3 (10base-t) ? 10base-t, 100base-tx and 1000base-t support ? loop-back modes ? auto-negotiation (next page support) ? automatic polarity detection and correction ? link status change wake-up detection ? vendor specific register functions ? supports gmii interface ? controlled impedance outputs ? four status led outputs and configurable led modes with support for tricolor operation ? compliant with ieee 802.3-2005 standards ? gmii pins tolerant to 3.6v ? integrated dsp implements adaptive equalizer, echo cancellers, and crosstalk cancellers ? efficient digital baseline wander correction ? power and i/os ? configurable led outputs ? various low power modes ? variable voltage i/o supply (2.5v/3.3v) ? miscellaneous features ? ieee 1149.1 (jtag) boundary scan ? multiple clock options - 25mhz crystal or 125mhz clock ? packaging ? 72-pin qfn (10x10 mm) lead-free rohs compliant package with gmii ? environmental ? commercial temperature range (0c to +70c) ? industrial temperature range (-40c to +85c)
order numbers: lan8810-akze for 72-pin, qfn lead-free rohs compliant package (0 to +70c temp range) LAN8810I-AKZE for 72-pin, qfn lead-free rohs compliant package (-40 to +85c temp range) this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs please contact your smsc sales representative fo r additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 2 smsc lan8810/lan8810i datasheet copyright ? 2013 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. the microchip name and logo, and the microchip logo are registered trademarks of microchip technology incorporated in the u.s.a . and other countries. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 3 revision 1.0 (02-06-13) datasheet table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin description and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 chapter 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 restarting auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 3.1.2 disabling auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.3 parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.4 master/slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.5 manual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.6 half vs. full-duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 hp auto-mdix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.1 required ethernet magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 gmii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 mii isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 serial management interface (smi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.1 hardware reset (nreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.2 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.3 power-down reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7.1 general power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 3.7.2 energy detect power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.7.3 hardware power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.8 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.8.1 hardware configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.8.2 software configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9 miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.9.1 leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.9.2 variable voltage i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.9.3 isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.4 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.5 collision detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.6 link integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9.7 speed optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.9.8 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.9.9 ieee 1149.1 (jta g) boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.9.10 advanced features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.10 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10.1 simplified application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.10.2 power supply & twisted pair inte rface diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 chapter 4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.1 register nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 primary phy registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.1 basic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.2 basic status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 4 smsc lan8810/lan8810i datasheet 4.2.3 phy identifier 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.4 phy identifier 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.5 auto negotiation advertisement regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2.6 auto negotiation link partner ability register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2.7 auto negotiation expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.8 auto negotiation next page tx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.2.9 auto negotiation next page rx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.10 master/slave control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2.11 master/slave status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.12 extended status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.13 link control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.14 10/100 mode control/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.15 10/100 special modes register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.16 extended mode control/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2.17 advanced register address port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.18 advanced register read data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2.19 control / status indications register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.2.20 interrupt source flags register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2.21 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.22 phy special control / status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3 advanced phy registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.1 advanced register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3.2 user status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.3 user status 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.4 receive error-free packets counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.5 receive error-free packets counter mid register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.6 receive error-free packets counter low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.7 crc error counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.8 crc error counter mid register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.9 crc error counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.10 receive error during data counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.11 receive error during idle counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.3.12 transmit packet counter high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.3.13 transmit packet counter mid register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3.14 transmit packet counter low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 5 operational characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1 absolute maximum ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 operating conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.4 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.5 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.5.1 equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.5.2 power sequence timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.5.3 power-on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.5.4 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.5.5 gmii timing (1000base-t). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.5.6 mii timing (100base-tx, 10base-t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.5.7 smi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.5.8 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.6 clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.1 72-qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 5 revision 1.0 (02-06-13) datasheet chapter 7 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 6 smsc lan8810/lan8810i datasheet list of figures figure 1.1 internal block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 1.2 system level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2.1 72-qfn pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3.1 cable connection types: straight-through, cro ssover, semi crossover. . . . . . . . . . . . . . . 23 figure 3.1 mdio timing and frame structure - read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3.2 mdio timing and frame structure - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3.1 simplified application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 3.2 power supply & twisted pair interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 5.1 output equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 5.2 power sequence timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 5.3 power-on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 5.4 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 5.5 gmii transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 5.6 gmii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 5.7 mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 5.8 mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 5.9 smi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 5.10 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 6.1 72-qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 6.2 72-qfn recommended pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 7 revision 1.0 (02-06-13) datasheet list of tables table 2.1 gmii interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2.2 serial management interface (smi) pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2.3 led & configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2.4 ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2.5 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2.6 miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2.7 power pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2.8 72-qfn pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2.9 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.1 master/slave resolution for 1000base-t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 3.2 crs behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3.3 gmii/mii signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3.4 interrupt management table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 3.5 configuration straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 3.6 hardware connection determines configuration pi n value (cpv) . . . . . . . . . . . . . . . . . . . . . 30 table 3.7 smi address configuration with pause=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3.8 smi address configuration with pause=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 3.9 configuring the mode of operation with macclkdis=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3.10 configuring the mode of operation with macclkdis= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3.11 register bits impacted by the mode of operation (m od) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3.12 led mode 1 operation - led_mode[1:0]=01b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 3.13 led mode 2 operation - led_mode[1:0]=10b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 3.14 led mode 3 operation - led_mode[1:0]=11b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 3.15 ieee 1149.1 op codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 4.1 register bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 4.2 phy control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 4.3 advanced register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 5.1 power consumption - 1000base-t linked. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 5.2 power consumption - 100base-tx link ed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 5.3 power consumption - 10base-t linked. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5.4 power consumption - energy detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5.5 power consumption - ha rdware power down (pll enabled) . . . . . . . . . . . . . . . . . . . . . . . . 84 table 5.6 power consumption - hardware power do wn (pll disabled) . . . . . . . . . . . . . . . . . . . . . . . . 85 table 5.7 i/o buffer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 5.8 1000base-t transceive r characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 table 5.9 100base-tx transceiver ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 table 5.10 10base-t transceiver char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 5.11 power sequence timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 5.12 power-on reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 5.13 reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 5.14 gmii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 5.15 gmii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 5.16 mii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 5.17 mii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 5.18 smi timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 5.19 jtag timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 5.20 crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 6.1 72-qfn dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 7.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 8 smsc lan8810/lan8810i datasheet chapter 1 introduction 1.1 general description the smsc lan8810/lan8810i is a low-powe r 10base-t/100base-tx/1000b ase-t gigabit ethernet physical layer (phy) transceiver with variable i/o vo ltage that is fully comp liant with the ieee 802.3 and 802.3ab standards. the lan8810/lan8810i can be configured to comm unicate with an ethernet mac via the standard mii(ieee 802.3u)/gmii(ieee 802.3z) interfaces. it contains a full-duplex transceiver for 1000mbps operation on four pairs of cate gory 5 or better balanced twiste d pair cable. per ieee 802.3-2005 standards, all digital interface pins are tolerant to 3.6v. the lan8810/lan8810i is configurable via hardwar e and software, supporting both ieee 802.3-2005 compliant and vendor-specific register functions via smi. the lan8810/lan8810i implements auto- negotiation to automatically determine the best possible speed and duplex mode of operation. hp auto-mdix support allows the use of di rect connect or cross-over cables. an internal block diagram of the lan8810/lan8810i is shown in figure 1.1 . a typical system-level diagram is shown in figure 1.2 . figure 1.1 internal block diagram lan8810/lan8810i gmii 3 2 1 active hybrid 0 10/100/1000 ethernet 3 2 1 analog rx 0 3 2 1 analog tx 0 3 2 1 dsp 0 3 2 1 spectral shaper 0 digital tx scrambler trellis 4dpam-5 encoders digital rx descrambler viterbi decoder 4dpam-5 decoders 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 physical coding sublayer tap controller leds pll leds jtag 3 2 1 0 3210
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 9 revision 1.0 (02-06-13) datasheet figure 1.2 system level block diagram lan8810/ lan8810i 10/100/1000 ethernet mac led status gmii crystal mdi ethernet magnetics jtag ethernet
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 10 smsc lan8810/lan8810i datasheet chapter 2 pin description and configuration figure 2.1 72-qfn pin a ssignments (top view) vss note: exposed pad (vss) on bottom of package must be connected to ground smsc lan8810/lan8810i 72 pin qfn (top view) tr0n mdc txd1 rxd6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 28 29 30 31 32 33 34 52 51 50 49 48 47 46 45 44 43 42 41 40 39 70 69 68 67 66 65 64 63 62 61 60 59 58 57 vdd12core vddvario rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 vdd12core vddvario xo xi tdo config0 config1 vddvario vdd12core config2 config3 10_led/refclk_sel 100_led/hpd_mode 1000_led act_led vddvario vdd12core gtxclk tr0p vdd12a tr1n tr1p vdd12a vdd12bias vdd12pll tr2n tr2p vdd12a tr3n tr3p txd2 vddvario vdd12core txd3 txd4 txd5 txd6 txd7 macclk/macclk_sel vdd12core vddvario rxclk col 56 55 nreset hpd vdd12a 72 71 irq tdi 38 37 txclk txer 54 53 ethrbias mdio 1 2 tms tck 17 18 rxdv rxd7 19 20 crs rxer 35 36 txen txd0
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 11 revision 1.0 (02-06-13) datasheet table 2.1 gmii interface pins num pins name symbol buffer type description 1 transmit data 0 txd0 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 1 txd1 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 2 txd2 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 3 txd3 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 4 txd4 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 5 txd5 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 6 txd6 vis (pd) the mac transmits data to the phy using this signal. 1 transmit data 7 txd7 vis (pd) the mac transmits data to the phy using this signal. 1 transmit error txer vis (pd) indicates a transmit error condition. note: this input is ignored during 10base-t operation. 1 transmit enable txen vis (pd) indicates the presence of valid data on txd[7:0] 1 transmit clock txclk vo8 used to latch data from the mac into the phy. mii (100base-tx): 25mhz mii (10base-t): 2.5mhz note: for 1000base-t operat ion, gtxclk is used as the transmit clock. txclk is not used in 1000base-t mode. 1 gmii transmit clock gtxclk vis (pd) 125mhz clock used to latch data from the mac into the phy in 1000base-t mode. 1 receive data 0 rxd0 vo6 the phy transfers data to the mac using this signal. 1 receive data 1 rxd1 vo6 the phy transfers data to the mac using this signal. 1 receive data 2 rxd2 vo6 the phy transfers data to the mac using this signal. 1 receive data 3 rxd3 vo6 the phy transfers data to the mac using this signal. 1 receive data 4 rxd4 vo6 the phy transfers data to the mac using this signal. 1 receive data 5 rxd5 vo6 the phy transfers data to the mac using this signal.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 12 smsc lan8810/lan8810i datasheet note 2.1 configuration strap values are latched on hardware reset. config uration straps are identified by an underlined symbol name. signals that function as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.8, "configuration," on page 29 for additional information. 1 receive data 6 rxd6 vo6 the phy transfers data to the mac using this signal. 1 receive data 7 rxd7 vo6 the phy transfers data to the mac using this signal. 1 receive data valid rxdv vo6 indicates that recovered and decoded data is being presented on the receive data pins. 1 receive error rxer vo6 asserted to indicate an error has been detected in the frame presently being transferred from the phy. 1 receive clock rxclk vo6 used to transfer data to the mac. gmii (1000base-t): 125mhz mii (100base-tx): 25mhz mii (10base-t): 2.5mhz 1 collision detect col vo6 asserted to indicate detection of a collision condition. (used in half-duplex mode only) 1 carrier sense crs vo6 indicates detection of carrier. (used in half-duplex mode only) 1 mac transmit clock macclk vo6 125mhz or 25mhz selectable mac clock output as required by clause 40.6.1 .2.5 of the ieee 802.3ab specification. mac clock frequency select configuration strap macclk_sel vis (pd) this configuration strap is used to select the output frequency of macclk. when pulled-up to vddvario, 25mhz is selected. when pulled-down to vss, 125mhz is selected. see note 2.1 for more information on configuration straps. table 2.2 serial management interface (smi) pins num pins name symbol buffer type description 1 smi clock mdc vis (pd) serial management interface clock. 1 smi data input/output mdio vis/vo8 (pu) serial management interface data input/output. table 2.1 gmii interface pins (continued) num pins name symbol buffer type description
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 13 revision 1.0 (02-06-13) datasheet table 2.3 led & configuration pins num pins name symbol buffer type description 1 10base-t link led indicator 10_led vo8 10base-t led link indication. refer to section 3.9.1, "leds," on page 34 for additional information. reference clock freq. select configuration strap refclk_sel vis (pd) this configuration strap is used to select the reference clock frequency. when pulled-up, a 125mhz reference clock is selected. when pulled- down, a 25mhz reference clock is selected. see note 2.2 for more information on configuration straps. 1 100base-tx link led indicator 100_led vo8 100base-tx led link indication. refer to section 3.9.1, "leds," on page 34 for additional information. hardware power down (hpd) mode configuration strap hpd_mode vis (pd) this configuration strap is used to select the hardware power down (hpd) mode. when pulled- up, the pll is not disabled when hpd is asserted. when pulled-down, the pll is disabled when hpd is asserted. refer to section 3.7.3, "hardware power-down," on page 28 for additional information. see note 2.2 for more information on configuration straps. 1 1000base-t link led indicator 1000_led vo8 1000base-t led link indication. refer to section 3.9.1, "leds," on page 34 for additional information. 1 link activity led indicator act_led vo8 link activity led indication. refer to section 3.9.1, "leds," on page 34 for additional information. 1 configuration input 0 config0 vis (pd) this pin sets the phya dd[1:0] bits of the 10/100 special modes register on reset or power-up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[3:0] configuration pins," on page 29 for additional information. 1 configuration input 1 config1 vis (pd) this pin sets the pause bit of the auto negotiation advertisement register and phyadd [2] bit of the 10/100 special modes register on reset or power- up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[ 3:0] configuration pins," on page 29 for additional information. 1 configuration input 2 config2 vis (pd) this pin sets the mod[1:0] bits of the extended mode control/status register on reset or power- up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[ 3:0] configuration pins," on page 29 for additional information. 1 configuration input 3 config3 vis (pd) this pin sets the clk125dis bit and mod[3] bit of the extended mode control/status register on reset or power-up. it must be connected to vss, 100_led, 1000_led, or vddvario. refer to section 3.8.1.2, "config[3:0] configuration pins," on page 29 for additional information.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 14 smsc lan8810/lan8810i datasheet note 2.2 configuration strap values are latched on hardware reset. config uration straps are identified by an underlined symbol name. signals that function as configuration straps must be augmented with an external resistor when connected to a load. refer to section 3.8, "configuration," on page 29 for additional information. table 2.4 ethernet pins num pins name symbol buffer type description 1 ethernet tx/rx positive channel 0 tr0p aio transmit/receive positive channel 0. 1 ethernet tx/rx negative channel 0 tr0n aio transmit/receive negative channel 0. 1 ethernet tx/rx positive channel 1 tr1p aio transmit/receive positive channel 1. 1 ethernet tx/rx negative channel 1 tr1n aio transmit/receive negative channel 1. 1 ethernet tx/rx positive channel 2 tr2p aio transmit/receive positive channel 2. 1 ethernet tx/rx negative channel 2 tr2n aio transmit/receive negative channel 2. 1 ethernet tx/rx positive channel 3 tr3p aio transmit/receive positive channel 3. 1 ethernet tx/rx negative channel 3 tr3n aio transmit/receive negative channel 3. 1 external phy bias resistor ethrbias ai used for the internal bias circuits. connect to an external 8.06k 1.0% resistor to ground.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 15 revision 1.0 (02-06-13) datasheet table 2.5 jtag pins num pins name symbol buffer type description 1 jtag test data out tdo vo8 jtag (ieee 1149.1) data output. 1 jtag test data input tdi vis (pu) jtag (ieee 1149.1) data input. note: when not used, tie this pin to vddvario. 1 jtag test clock tck vis (pd) jtag (ieee 1149.1) test clock. note: when not used, tie this pin to vss. 1 jtag test mode select tms vis (pu) jtag (ieee 1149.1) te st mode select. note: when not used, tie this pin to vddvario. table 2.6 miscellaneous pins num pins name symbol buffer type description 1 crystal input xi iclk external 25 mhz crystal input. note: this pin can also be driven by a single- ended clock oscillator. when this method is used, xo should be left unconnected 1 crystal output xo oclk external 25 mhz crystal output. 1 system reset nreset vis (pu) this active-low pin allows external hardware to reset the device. 1 interrupt request irq vo8 programmable interrupt request. note: when used, this pin requires an external 4.7k pull-up resistor. 1 hardware power down hpd vis (pd) when asserted, this pin places the device into hardware power down (hpd) mode. refer to section 3.7.3, "hardware power-down," on page 28 for additional information.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 16 smsc lan8810/lan8810i datasheet note 2.3 exposed pad on package bottom ( figure 2.1 ). table 2.7 power pins num pins name symbol buffer type description 6 +3.3v/+2.5v i/o power supply input vddvario p +2.5v/+3.3v variable i/o power. refer to section 3.10, "application diagrams," on page 41 and the lan8810/lan8810i reference schematics for connection information. 6 digital core +1.2v power supply input vdd12core p refer to section 3.10, "application diagrams," on page 41 and the lan8810/lan8810i reference schematics for connection information. 4 ethernet +1.2v port power supply input for channels 0-3 vdd12a p refer to section 3.10, "application diagrams," on page 41 and the lan8810/lan8810i reference schematics for connection information. 1 ethernet +1.2v bias power supply input vdd12bias p refer to section 3.10, "application diagrams," on page 41 and the lan8810/lan8810i reference schematics for connection information. 1 ethernet pll +1.2v power supply input vdd12pll p refer to section 3.10, "application diagrams," on page 41 and the lan8810/lan8810i reference schematics for connection information. note 2.3 ground vss p common ground
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 17 revision 1.0 (02-06-13) datasheet table 2.8 72-qfn pin assignments pin num pin name pin num pin name pin num pin name pin num pin name 1 tck 19 rxer 37 txer 55 nreset 2 tms 20 crs 38 txclk 56 hpd 3 tdo 21 col 39 gtxclk 57 tr0n 4 xi 22 rxclk 40 vdd12core 58 tr0p 5 xo 23 vddvario 41 vddvario 59 vdd12a 6 vddvario 24 vdd12core 42 act_led 60 tr1n 7 vdd12core 25 macclk/ macclk_sel 43 1000_led 61 tr1p 8 rxd0 26 txd7 44 100_led/ hpd_mode 62 vdd12a 9 rxd1 27 txd6 45 10_led/ refclk_sel 63 vdd12bias 10 rxd2 28 txd5 46 config3 64 vdd12pll 11 rxd3 29 txd4 47 config2 65 tr2n 12 rxd4 30 txd3 48 vdd12core 66 tr2p 13 rxd5 31 vdd12core 49 vddvario 67 vdd12a 14 vddvario 32 vddvario 50 config1 68 tr3n 15 vdd12core 33 txd2 51 config0 69 tr3p 16 rxd6 34 txd1 52 mdc 70 vdd12a 17 rxd7 35 txd0 53 mdio 71 irq 18 rxdv 36 txen 54 ethrbias 72 tdi exposed pad must be connected to vss
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 18 smsc lan8810/lan8810i datasheet 2.1 buffer types note: the digital signals are not 5v tolerant. refer to section 5.1, "absolute maximum ratings*," on page 82 for additional buffer information. note: sink and source capabilities are dependant on the vddvario voltage. refer to section 5.1, "absolute maximum ratings*," on page 82 for additional information. table 2.9 buffer types buffer type description vis variable voltage schmitt-triggered input vo6 variable voltage output with 6ma sink and 6ma source vo8 variable voltage output with 8ma sink and 8ma source pu 50ua (typical) internal pull-up. unless otherwis e noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50ua (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals ex ternal to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 19 revision 1.0 (02-06-13) datasheet chapter 3 functional description this chapter provides functional descriptions of th e various device features. these features have been categorized into the following sections: ? auto-negotiation ? hp auto-mdix ? gmii interface ? serial management interface (smi) ? interrupt management ? resets ? power-down modes ? configuration ? miscellaneous functions ? application diagrams 3.1 auto-negotiation the purpose of the auto-negotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its li nk partner. auto-negotiation is a mechanism for exchanging configuration information between two lin k-partners and automatically selecting the highest performance mode of operation supported by both si des. auto-negotiation is fully defined in clause 28 and clause 40 of the ie ee 802.3 specification. once auto-negotiation has completed, information ab out the resolved link can be passed back to the controller via the integrated serial management interface (smi) . the results of the negotiation process are reflected in the speed indication field of the phy special control / status register as well as the auto negotiation link partner ability register . the advertised capabilities of the phy are stored in auto negotiation advertisement register . the defaults advertised by the device are determined as described in section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 31 . the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller. when enabled, auto-negotia tion is started by the occurrence of one of the following events: ? hardware reset ? software reset ? power-down reset ? link status down ? setting the restart auto-negotiate bit of the basic control register on detection of one of these events, the device begi ns auto-negotiation by transmitting bursts of fast link pulses (flp). the data transmitted by an fl p burst is known as a ?link code word.? this exchange of information allows link partners to determine the highest common ability (hcd). once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if all of the required flp bursts are not received. writing the 100base-tx full duplex , 100base-tx , 10base-t full duplex , and 10base-t bits of the auto negotiation adve rtisement register allows software control of the advertised capabilities.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 20 smsc lan8810/lan8810i datasheet however, writing the auto negotiation advertisement register does not automatica lly re-start auto- negotiation. the restart auto-negotiate bit of the basic control register must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing the auto- negotiation enable bit of the basic control register . auto-negotiation also resolves the master/slave clocking relationship between two phys for a 1000base-t link. refer to section 3.1.4, "maste r/slave," on page 20 for additional information. 3.1.1 restarting auto-negotiation auto-negotiation can be restarted at any time by using the restart auto-negotiate bit of the basic control register . auto-negotiation will also re-start if the li nk is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. if the management entity restarts au to-negotiation by writing to the restart auto-negotiate bit, the device will respond by stopping all transmission/receivi ng operations. auto-negotiation will restart after approximately 1200 ms. the link partner will have also dropped the link and will resume auto- negotiation. 3.1.2 disabling auto-negotiation auto-negotiation can be disabled via software by clearing the auto-negotiation enable bit of the basic control register . the device will then force its speed of operation to reflect the information in the speed select[1] , speed select[0] , and duplex mode bits of the basic control register . these bits are ignored when auto-negotiation is enabled. 3.1.3 parallel detection if the lan8810/lan8810i is connected to a device la cking the ability to auto-negotiate (i.e., no flps are detected), it is able to determine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case, the link is presumed to be half-dupl ex per the ieee standard. this ability is known as ?parallel detection?. th is feature ensures inter operability with legacy link partners. the ethernet mac has access to informa tion regarding parallel detect via the auto negotiation expansion register . if a link is formed via parallel detection, the link partner auto-negotiation able bit of the auto negotiation expansion register is cleared to indicate that the link partner is not capable of auto-negotiation. if a fault occurs during parallel detection, the parallel detection fault bit of this register is set. the auto negotiation link partner ability register is updated with informat ion from the link partner which is coded in the received flps. if the link partner is not auto-negotiation capable, then the auto negotiation link partner ability register is updated after completion of parallel detection to reflect the speed capability of the link partner. parallel detect cannot be used to establish gigabit ethernet links because echo cancellation and signal recovery on a gigabit ethernet link requires resoluti on of the master/slave cl ock relationship, which requires the exchange of flps. 3.1.4 master/slave in 1000base-t, one of the two link partner device s must be configured as master and the other as slave. the master device transmits data using the lo cal clock, while the slave device uses the clock recovered from incoming data. the master and slave assignments are set using the configuration pins as described in section 3.8.1.2.2, "configuring t he mode of operation (c onfig[3:2])," on page 31 or by using the master/slave manual config enable and master/slave manual config value bits of the master/slave
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 21 revision 1.0 (02-06-13) datasheet control register . if both the link partner and the loca l device are manually given the same master/slave assignment, an error will be indicated in the master/slave configuration fault bit of the master/slave status register . depending on the link partner configuration, the manual master/slave mode can be resolved to sixteen possible outcomes, as shown in table 3.1 . 3.1.5 manual operation the device supports a manual (forced) operation for te st purposes. in manual operation, the user sets the link speed (10mbps or 100mbps) and the duplex state (full or half). auto-negotiation must be disabled in order to ma nually configure the speed and the duplex. this may be accomplished using the configuration pins, as described in section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 31 , or by using the basic control register register as described in section 3.1.2, "disabling auto-negotiation," on page 20 . for 10base-t and 100base-tx, the link state of the device is determined by the speed select[1] , speed select[0] , and duplex mode bits of the basic control register . manual operation at a link speed of 1000mbps is not supported. 3.1.6 half vs. full-duplex half-duplex operation relies on the csma/cd (carrier sense multiple access / collision detect) protocol to handle network traffic and collisions. in this mode, the internal carrier sense signal, crs, responds to both transmit and receive activity. if data is received while the phy is transmitting, a collision results. table 3.1 master/slave resolution for 1000base-t lan8810/lan8810i advertisement link partner advertisement lan8810/lan8810i result link partner result single-port single-port m/s resolved by r andom seed m/s resolved by random seed single-port multi-port slave master single-port manual master slave master single-port manual slave master slave multi-port single-port master slave multi-port multi-port m/s resolved by r andom seed m/s resolved by random seed multi-port manual master slave master multi-port manual slave master slave manual master single-port master slave manual master multi-port master slave manual master manual master no link no link manual master manual slave master slave manual slave single-port slave master manual slave multi-port slave master manual slave manual master slave master manual slave manual slave no link no link
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 22 smsc lan8810/lan8810i datasheet in full-duplex mode, the phy is able to transmit and receive data simultaneously and collision detection is disabled. in this mode, the internal crs res ponds only to receive activity. in 10base-t and 100base-t mode, crs is redefined to respond only to received activity. in 1000base-t, crs is disabled. table 3.2 describes the behavior of the internal crs bit under all receive/transmit conditions. note 3.1 the internal crs signal operates in two modes: active and low. when in active mode, the internal crs will transition high and low upon line activity, where a high value indicates a carrier has been detected. in low mode, the internal crs stays low and does not indicate carrier detection. 3.2 hp auto-mdix hp auto-mdix facilitates the use of cat-5 (100base-t) me dia utp interconnect cable without consideration of interface wiring sc heme. if a user plugs in either a direct connect lan cable, or a cross-over patch cable, as shown in figure 3.1 , the auto-mdix phy is capable of configuring the twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pins of the connecting device. it can automatically re-assi gn channel 0 and 1 if required to establish a link. in 1000base-t mode, it can re- assign channel 2 and 3. crossover resolution pr ecedes the actual auto-negotiation process that involves exchange of fl ps to advertise capabili ties. automatic mdi/mdix is described in ieee 802.3ab clause 40, section 40.8.2. since the rx and tx lin e pairs are interchangeable, special pcb design table 3.2 crs behavior mode speed duplex activity crs behavior ( note 3.1 ) manual 10 mbps half-duplex transmitting active manual 10 mbps half-duplex receiving active manual 10 mbps full-duplex transmitting low manual 10 mbps full-duplex receiving active manual 100 mbps half-duplex transmitting active manual 100 mbps half-duplex receiving active manual 100 mbps full-duplex transmitting low manual 100 mbps full-duplex receiving active auto-negotiation 10 mbps half-duplex transmitting active auto-negotiation 10 mbps half-duplex receiving active auto-negotiation 10 mbps full-duplex transmitting low auto-negotiation 10 mbps full-duplex receiving active auto-negotiation 100 mbps half-duplex transmitting active auto-negotiation 100 mbps half-duplex receiving active auto-negotiation 100 mbps full-duplex transmitting low auto-negotiation 100 mbps full-duplex receiving active
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 23 revision 1.0 (02-06-13) datasheet considerations are needed to accommodate the sym metrical magnetics and termination of an auto- mdix design. auto-mdix is enabled by default, and can be disabled by the auto mdix disable bit in the 10/100 mode control/status register . when auto-mdix is disabled, the tx and rx pins can be configured manually by the mdi/mdi-x 0:1 and mdi/mdi-x 2:3 bits in the extended mode control/status register . the device includes an advanced crossover resolution capability called semi crossover. this is an extension to hp auto-mdix that corrects for a cabl e with only two pairs crossed. if semi crossover is enabled, after the device has attempted to establish a link with all four signal pairs normal or crossed, it will attempt to establish a link with pairs 2/3 switched and 0/1 straight, and then with pairs 0/1 switched and pairs 2/3 straight. the semi crossover is enabled by default, and can be disabled by the semi crossover enable bit in the 10/100 mode control/status register . after resolution of crossed pairs is complete, us ing either hp auto-mdix or the semi crossover function, the mdi/mdi-x stat us is reported through the xover resolution 0:1 and xover resolution 2:3 bits of the user status 2 register . 3.2.1 required ethernet magnetics the magnetics selected for use with the device shou ld be an auto-mdix style magnetic available from several vendors. refer to smsc application note 8. 13 "suggested magnetics" for the latest qualified and suggested magnetics. vendors and part nu mbers are provided in this application note. figure 3.1 cable connection types: stra ight-through, crossover, semi crossover 1 2 3 4 5 6 7 8 tr0p 1 2 3 4 5 6 7 8 tr0p direct connect cable rj-45 8-pin straight-through 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 crossover cable rj-45 8-pin crossover tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0n tr1p tr2p tr2n tr1n tr3p tr3n tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 0/1 straight, 2/3 crossed rj-45 8-pin semi crossover tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 0/1 crossed, 2/3 straight rj-45 8-pin semi crossover tr0p tr2p tr3p tr1p tr3n tr1n tr2n tr0n tr0p tr0n tr1p tr2p tr2n tr1n tr3p tr3n
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 24 smsc lan8810/lan8810i datasheet 3.3 gmii interface the device communicates with an external mac usin g the gigabit media independent interface (gmii). the gmii is compliant with the ieee 802.3 sta ndard, and provides support for 1000base-t, 100base- tx, or 10base-t operation. for 1000base-t, the mac generated 125mhz gtxclk transmit clock is used to synchronize the txd, txen and txer signals. for 100base-tx and 10base-t ope ration, the device generated txclk transmit clock is used to synchronize the txd, txen and txer signals. txclk is 25mhz or 2.5mhz for 100base-tx and 10base-t operation, respectively. txer and txen are both driven by the mac and indicate a transmit error and valid trans mit data, respectively. on the receiver side, the device generated rxclk is used to synchronize the rxd, rxdv, rxer, col and crs signals for all modes of operation. the gmii provides backwards co mpatibility with the legacy mii. table 3.3, "gmii/mii signal mapping" describes which pins are used in each mode. timing information for the gmii/m ii interface is provided in section 5.5, "ac specifications," on page 87 . for additional information on the gmii/mi i interface, refer to t he ieee 802.3 s pecification. 3.3.1 mii isolate mode the device may be configured to electrica lly isolate the gmii pins by setting the isolate bit of the basic control register . in this mode, all mac data interface output pins are high and all mac data interface input pins are ignored. in this mode, the smi inte rface is kept active, allowing the mac to access the smi registers and generate interrupts. all mdi operations are halted while in isolate mode. table 3.3 gmii/mii signal mapping gmii mode (ieee 802.3 clause 35) mii mode (ieee 802.3 clause 22) txd[3:0] txd[3:0] txd[7:4] txen txen txer txer txclk (10/100mbps operation) txclk gtxclk (1000mbps operation) col col crs crs rxd[3:0] rxd[3:0] rxd[7:4] rxdv rxdv rxer rxer rxclk rxclk
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 25 revision 1.0 (02-06-13) datasheet 3.4 serial manageme nt interface (smi) the serial management interface is used to cont rol the device and obtain its status. this interface supports the standard phy registers required by claus e 22 of the 802.3 standard, as well as ?vendor- specific? registers allowed by the sp ecification. non-support ed registers (such as 11 to 14) will be read as hexadecimal ?ffff?. device registers are detailed in chapter 4, "register descriptions," on page 43 . at the system level, smi provides 2 signals: mdio and mdc. the mdc signal is an aperiodic clock provided by the station management controller (smc ). mdio is a bi-directional data smi input/output signal that receives serial data (commands) from the controller smc and sends serial data (status) to the smc. the minimum time between edges of th e mdc is 160 ns. there is no maximum time between edges. the minimum cycle ti me (time between two consecutiv e rising or two consecutive falling edges) is 400 ns. these modest timing requirement s allow this interface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. the frame structure and timing of the data is shown in figure 3.1 and figure 3.2 . the timing relationships of the mdio signals are further described in section 5.5.7, "smi timing," on page 95 . figure 3.1 mdio timing and frame structure - read cycle figure 3.2 mdio timing and frame structure - write cycle mdc mdio read cycle ... 32 1's 0110a4a3a2a1a0r4r3r2r1r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy mdc mdio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 26 smsc lan8810/lan8810i datasheet 3.5 interrupt management the device supports multiple interrupt capabilities wh ich are not a part of th e ieee 802.3 specification. an active low asynchronous interrupt signal ma y be generated on the irq pin when selected events are detected, as configured by the interrupt mask register . to set an interrupt, the corresponding mask bit in the interrupt mask register must be set (see table 3.4 ). when the associated event occurs, the irq pin will be asserted. when the corresponding event to deassert irq is true, the irq pin will be deasserted. all interrupts are masked following a reset. note: table 3.4 utilizes register index and bit number referencing in lieu of individual names. for example, ?30.10? is used to reference bit 10 (tr ansmitter elastic buffer overflow interrupt enable) of the interrupt mask register (register index 30). note 3.2 the energyon bit of the 10/100 mode control/status register (17.1) defaults to ?1? after a hardware reset. if no energy is detected before 256ms, the energyon bit will be cleared. when energyon is ?0? and energy is detected, due to the establishment of a valid link or the phy auto-negotiation moving past the ability detect state, the energyon bit will be set and the int7 bit of the interrupt source flags register will assert. if energyon is set and the energy is removed, the int7 bit will assert. the energyon bit will clear 256ms after the interrupt. if the phy is in manual mode, int7 will be asserted 256ms after the link is broken. if the phy is auto-negotiating, int7 will be asserted 256ms after the phy returns to the ability detect state (maximum of 1.5s after the link is broken). table 3.4 interrupt management table mask interrupt source flag interrupt source event to assert irq event to deassert irq 30.15:11 29.15:11 reserved -na- -na- -na- -na- 30.10 29.10 transmitter elastic buffer overflow -na- -na- ( note 3.3 ) transmitter elastic buffer overflow overflow condition resolved 30.9 29.9 transmitter elastic buffer underflow -na- -na- ( note 3.3 ) transmitter elastic buffer underflow underflow condition resolved 30.8 29.8 idle error count overflow 10.7:0 idle error count idle error count overflow reading register 10 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3.2 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 falling 1.5 or reading register 29 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 reserved -na- -na- -na- -na- 30.2 29.2 parallel detection fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29 or re-autonegotiate or link down 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 falling of 6.1 or reading register 6, or reading register 29 re-auto-negotiate, or link down.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 27 revision 1.0 (02-06-13) datasheet to prevent an unexpected assertion of irq, the energyon interrupt mask ( int7_en ) should always be cleared as part of the energyon interrupt service routine. note 3.3 the transmitter fifo depth can be adjusted via the transmitter fifo depth field of the extended mode control/status register (19.10:9). 3.6 resets the device provides the following chip-level reset sources: ? hardware reset (nreset) ? software reset ? power-down reset 3.6.1 hardware reset (nreset) a hardware reset will occur when the system reset nreset input pin is driven low. when nreset is asserted, it must be held low for the minimum time specified in section 5.5.3, "power-on reset timing," on page 89 to ensure proper reset to the phy. following a hardware reset, the device resets the device registers and relatches the configuration straps and config[3:0] pins. note: a hardware reset (nreset assertion) is required follo wing power-up. refer to section 5.5.3, "power-on reset timing," on page 89 for additional information. 3.6.2 software reset a software reset is initiated by writing a ?1? to the phy soft reset (reset) bit of the basic control register . this self-clearing bit will return to ?0? after approximately 256 s, at which time the phy reset is complete. this reset initializes the logic within the phy, with the exception of register bits marked as ?nasr? (not affected by software reset). following a software reset, the device configuration is reloaded from the register bit values, and not from the configuration straps and config[3:0] pins. the device does not relatch the hardware configuration settings. for example, if the device is powered up and a configuration strap is changed from its initial power up state, a software reset will not load the new strap setting. 3.6.3 power-down reset a power-down reset is automatically activated when the device comes out of the power-down mode. during power-down, the registers are not reset. configuration straps and config[3:0] pins are not latched as a result of a power-down reset. the power-down reset is internally extended by 256 s after exiting the power-down mode to allow the plls to stabilize before the logic is released from reset. refer to section 3.7, "power-down modes," on page 28 for details on the various power-down modes.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 28 smsc lan8810/lan8810i datasheet 3.7 power-down modes the device supports 3 power-down modes: ? general power-down ? energy detect power-down ? hardware power-down 3.7.1 general power-down this power-down mode is controlled by the power down bit of the basic control register . in this mode, the entire device is powered-down except for th e serial management interface and macclk output. the device remains in the general power-down mode while power down is set. when power down is cleared, the device powers up and is automatically reset (via a power-down reset ). additionally setting the macclkdis bit of the extended mode control/status register will disable the macclk pin output and power-down the pll. for maximum po wer savings, auto-negotiation should be disabled before enabling the general power-down mode. 3.7.2 energy detect power-down this power-down mode is controlled by the edpwrdown bit of the 10/100 mode control/status register . in this mode, when no energy is present on the line, nothing is transmitted and the device is powered-down except for the management interface, macclk, the squelch circuit and the energyon logic. the energyon bit in the 10/100 mode control/status register is asserted when there is valid energy from the line (100base-tx, 10base-t, or auto -negotiation signals) and the phy powers-up. it automatically resets itself into th e previous state prior to power-down, and stays in active mode as long as energy exists on the line. if the engergyon interrupt is enabled ( int7_en of the interrupt mask register ), irq is asserted. note: the first and possibly second packet to activate energyon may be lost. 3.7.3 hardware power-down this power-down mode is controlled by the hpd pin. in this mode, the entire device is powered-down except for the serial management interface. the hpd_mode configuration strap selects whether the pll will be shut down when in hardware power-down mode. to exit the hardware power-down mode, the hpd pin must be deasserted, followed by the deassertion of the power down bit in the basic control register . if the hardware power-down mode is set to shut down the pll, a software reset must also be issued. note: the device will wake-up in the hardware powe r-down mode if the hpd pin is asserted during hardware reset. note: for additional information on the hpd_mode configuration strap, refer to section 3.8.1.1, "configuration straps," on page 29 .
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 29 revision 1.0 (02-06-13) datasheet 3.8 configuration the device mode of operation may be controlled by hardware and software (register-selectable) configuration options. the init ial configuration may be select ed in hardware as described in section 3.8.1 . in addition, register-selectable software configuration options may be used to further define the functionality of the transceiver as described in section 3.8.2 . the device supports both ieee 802.3-2005 compliant and vendo r-specific register functions. 3.8.1 hardware configuration hardware configuration is controlled via mult iple configuration straps and the config[3:0] configuration pins. these items are de tailed in the following sub-sections. 3.8.1.1 configuration straps configuration straps are multi-func tion pins that are driven as outpu ts during normal operation. during a hardware reset (nreset) , these outputs are tri-stated. the high or low state of the signal is latched following de-assertion of the reset and is used to de termine the default configuration of a particular feature. ta b l e 3 . 5 details the configuration straps. configuration straps are also listed as part of chapter 2, "pin description and configuration," on page 10 with underlined names. configuration straps include internal resistors in order to prevent the signal from floating when unconnected. if a particular configur ation strap is connected to a load, an external pull-up or pull-down should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. note: the system designer must guarantee that c onfiguration straps meet the timing requirements specified in section 5.5.3, "power-on reset timing," on page 89 . if configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. note: configuration straps must never be driven as inputs. if require d, configuration straps can be augmented, or overridden with external resistors. 3.8.1.2 config[3:0] configuration pins the device provides 4 dedicated configuration pins, config[3:0], which are used to select the default smi address and mode of operation. the config[3:0] configuration pi ns differ from configuration straps in that they are single-purpose pins and have different latch timing requirements. the high or low states of the config[3:0] pins are latched following deassertion of a hardware reset (nreset) . refer to section 5.5.3, "power-on reset timing," on page 89 for additional config[3:0] timing information. each config[3:0] configuration pi n can be connected in one of fo ur ways. the configuration pin value (cpv) represented by each connection option is shown in ta b l e 3 . 6 . table 3.5 configuration straps configuration strap description logic 0 (pd) logic 1 (pu) macclk_sel selects the macclk output clock frequency 125mhz (default) 25mhz refclk_sel selects the reference clock frequency 25mhz (default) 125mhz hpd_mode selects the hardware power-down (hpd) mode hpd with pll disabled (default) hpd with pll enabled
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 30 smsc lan8810/lan8810i datasheet using the cpv nomenclature for each config[3:0] pin, section 3.8.1.2.1 describes how to configure the smi address and section 3.8.1.2.2 describes how to configure the initial mode of operation. note: the hpd pin is also a dedicated configuration pi n. hpd forces the entire device to power down except for the management interface. the hardware power-down mode is described in section 3.7.3, "hardware power-down," on page 28 . 3.8.1.2.1 configuring th e smi address (config[1:0]) the smi address may be configured via hardware to any value between 0 and 7. if an address greater than 7 is required, the user can configure the phy address using software configuration via the phyadd[4:0] field of the 10/100 special modes register (after smi communication at an address is established). the config1 pin is used to configure bo th the smi address and the value of the pause operation (pause) bit in the auto negotiation advertisement register . the user must first determine the desired pause value. the configuration pin values for co nfig1 and config0 should then be selected using table 3.7 (pause=0) or ta b l e 3 . 8 (pause=1), respectively. table 3.6 hardware connection determi nes configuration pin value (cpv) config[x] connects to: value gnd cpv(0) 100_led cpv(1) 1000_led cpv(2) vdd cpv(3) table 3.7 smi address configuration with pause=0 phyadd[2:0] config1 config0 000 cpv(0) cpv(0) 001 cpv(0) cpv(1) 010 cpv(0) cpv(2) 011 cpv(0) cpv(3) 100 cpv(1) cpv(0) 101 cpv(1) cpv(1) 110 cpv(1) cpv(2) 111 cpv(1) cpv(3)
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 31 revision 1.0 (02-06-13) datasheet 3.8.1.2.2 configuring the mode of operation (config[3:2]) this section describes the init ial modes of operation that are available using the config[3:2] configuration pins. the user may configure additional modes using software configuration when the config[3:2] options do not include the desired mode. the config3 pin is used to configure the values of the mod field (19.15:11) and the macclkdis bit (19.3) of the extended mode control/status register . to select a default c onfiguration mode via the config[3:0] pins, the user must first select whether to enable or disable the macclk ( macclkdis bit). the configuration pin va lues for config 3 and config2 should be selected using ta b l e 3 . 9 to set macclkdis =0, or ta b l e 3 . 1 0 to set macclkdis =1. these tables also detail how the mod field of the extended mode control/status register will be configured. section 3.8.1.2.3 describes how the mod field controls other configuration bits in the device. when a soft reset is issued via the phy soft reset (reset) bit of the basic control register , configuration is controlled by the register bit values and the config[ 3:0] pins have no affect. likewise, changing the mod field of the extended mode contro l/status register bits does not change the configuration of the device in this case. note: table 3.9 and ta b l e 3 . 1 0 utilize register index and bit number referencing in lieu of individual names. table 3.8 smi address configuration with pause=1 phyadd[2:0] config1 config0 000 cpv(2) cpv(0) 001 cpv(2) cpv(1) 010 cpv(2) cpv(2) 011 cpv(2) cpv(3) 100 cpv(3) cpv(0) 101 cpv(3) cpv(1) 110 cpv(3) cpv(2) 111 cpv(3) cpv(3)
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 32 smsc lan8810/lan8810i datasheet table 3.9 configuring the mode of operation with macclkdis=0 mode definitions config3 config2 reg 19 [15:11] 10base-t half duplex. au to-negotiation disabled. cpv(0) cpv(0) 00000 10base-t full duplex. auto-negotiation disabled. cpv(0) cpv(1) 00001 100base-tx half duplex. au to-negotiation disabled. crs is active during transmit & receive. cpv(0) cpv(2) 00010 100base-tx half duplex. au to-negotiation disabled. crs is active during receive. cpv(0) cpv(3) 00011 all mode capable (10/100/1000). auto-negotiation enabled. auto master/slave resolution single port. cpv(1) cpv(0) 00111 10base-t/100base-tx capable. auto-negotiation enabled. crs is active during transmit & receive. cpv(1) cpv(1) 00100 all mode capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution slave port. cpv(1) cpv(2) 01001 all capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution master port. cpv(1) cpv(3) 01010 table 3.10 configuring the mode of operation wi th macclkdis=1 mode definitions config3 config2 reg 19 [15:11] 10base-t half duplex. auto-negot iation disabled. cpv(2) cpv(0) 00000 10base-t full duplex. auto-negotiation disabled. cpv(2) cpv(1) 00001 100tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. cpv(2) cpv(2) 00010 100base-tx half duplex. au to-negotiation disabled. crs is active during receive. cpv(2) cpv(3) 00011 all mode capable (10/100/1000). auto-negotiation enabled. auto master/slave resolution single port. cpv(3) cpv(0) 00111 10base-t/100base-tx capable. auto-negotiation enabled. crs is active during transmit & receive. cpv(3) cpv(1) 00100 all mode capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution slave port. cpv(3) cpv(2) 01001 all mode capable (10/100/1000). auto-negotiation enabled. manual master/slave resolution master port. cpv(3) cpv(3) 01010
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 33 revision 1.0 (02-06-13) datasheet 3.8.1.2.3 configuration bits impacted by the mode of operation immediately after a reset, the mod field of the extended mode control/status register will be set dependent on the configuration pin va lues of the config3 and config2 pins, as described in section 3.8.1.2.2 . ta b l e 3 . 11 details how the mod field effects other device c onfiguration register bits. note: table 3.11 utilizes register index and bit number referencing in lieu of individual names. 3.8.2 software configuration the serial management interface (smi) allows for the configuration and control of multiple transceivers. several 16-bit status and control registers are accessible through the management interface pins mdc and mdio for 10/100/1000mbps operation. the device implements all the required mii registers and optional registers as described in chapter 4, "register descriptions," on page 43 . configuring the smi address is described in section 3.8.1.2.1 . refer to section 3.4, "serial management interface (smi)," on page 25 for additional information on the smi. table 3.11 register bits impacted by the mode of operation (mod) reg 19 [15:11] mode definitions reg 0 [13,12,8,6] reg 4 [8,7,6,5] reg 9 [12,11,10,9,8] 00000 10base-t half duplex. auto-negotiation disabled. 0000 xxxx xxx00 00001 10base-t full duplex. auto-negotiation disabled. 0010 xxxx xxx00 00010 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 1000 xxxx xxx00 00011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1010 xxxx xxx00 00100 100base-tx half duplex. auto-negotiati on enabled. crs is active during transmit & receive. 1100 0100 xxx00 00101 reserved --- 00110 reserved --- 00111 all capable. auto-negotiation enabled. auto master/slave re solution single port. 01x1 1111 00011 01000 reserved --- 01001 all capable. auto-negotiation enabled. manual master/slave resolution slave port. 01x1 1111 10011 01010 all capable. auto-negotiation enabled. manual master/slave resolution master port. 01x1 1111 11111 01011 - 11111 reserved ---
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 34 smsc lan8810/lan8810i datasheet 3.9 miscellaneous functions 3.9.1 leds the device provides the following led signals to enable visual indication of status: ? 1000_led ? 100_led ? 10_led ? act_led in all modes, the full duplex led (act_led) is dr iven immediately after auto-negotiation has resolved the duplex state and before the link is establis hed. the speed leds (1000 _led, 100_led, 10_led) are driven after a link is established. th ree led modes of operation are available: ? led mode 1 ( ta b l e 3 . 1 2 ) ? led mode 2 ( ta b l e 3 . 1 3 ) ? led mode 3 (default mode - table 3.14 ) the led mode is configured via the led_mode[1:0] field of the extended mode control/status register . the functional operation of the leds in each mode is described in ta b l e 3 . 1 2 , table 3.13 and table 3.14 . note: led mode 3 is the default mode of operati on and requires four leds for full operation. note: led modes 1 and 2 require two dual led packa ges (two leds in each package). led mode 2 provides collision detection, while led mode 1 does not. note 3.4 activity will cause duplex led color to blink. table 3.12 led mode 1 oper ation - led_mode[1:0]=01b led status description 100_led on color1 100base-t link 1000_led on color2 1000base-t link 100_led & 1000_led on color3 10base-t link 10_led on color1 note 3.4 link operates at full duplex act_led on color2 transmit/receive activity 10_led & act_ led off half duplex, no activity on color1 full duplex, no activity off/color2 half duplex, transmit/receive activity color1/color2 full duplex, transmit/receive activity
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 35 revision 1.0 (02-06-13) datasheet note 3.5 activity will cause duplex led color to blink. 3.9.2 variable voltage i/o the device?s digital i/o pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. these pins can operate at +2.5v or 3.3v. the applied i/o voltage must maintain its value within the tolerances specified in chapter 5, "operational characteristics" . varying the voltage up or down after the transceiver has completely powe red-on can cause errors in the transceiver operation. refer to chapter 5, "operational characteristics," on page 82 for additional information. table 3.13 led mode 2 oper ation - led_mode[1:0]=10b led status description 100_led on color1 1000base-t link 1000_led on color2 100base-t link 100_led & 1000_led on color3 10base-t link 10_led on color1 note 3.5 link operates at full duplex act_led on color2 transmit/receive activity 10_led & act_led on color3 collision off half duplex, no activity on color1 full duplex, no activity off/color2 half duplex, transmit/receive activity color1/color2 full duplex, transmit/receive activity table 3.14 led mode 3 operation - led_mode[1:0]=11b led status description 1000_led on 1000base-t link blinking transmit/receive activity 100_led on 100base-t link blinking transmit/receive activity 10_led on 10base-t link blinking transmit/receive activity act_led on link operates at full duplex off link operates at half duplex
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 36 smsc lan8810/lan8810i datasheet 3.9.3 isolate mode the device data paths may be electrically isolat ed from the gmii inte rface by setting the isolate bit of the basic control register to ?1?. in isolation mode, the tran sceiver does not respond to the txd, txen and txer inputs, but does respond to management transactions. isolation provides a means for multiple transceiver s to be connected to the same gmii interface without contention. by default, the transcei ver is not isolated (on power-up, isolate =0). 3.9.4 carrier sense the carrier sense signal is output on crs. carrie r sense operation is defined in the ieee 802.3u standard. the phy asserts carrier sense based only on receive activity whenever the phy is either in repeater mode or full-dupl ex mode. otherwise, the phy asserts ca rrier sense based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 consecutive ones is detected before a /j/k/ start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t /r/ end?of-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintain ed. carrier is treated similarly for idle followed by some non-idle symbol. 3.9.5 collision detect a collision is the occurrence of simultaneous transmit and receive operations. the col output is asserted to indicate that a collision has been detected. col remains active for the duration of the collision. col is changed asynchronously to bot h rxclk and txclk. a collision can only occur in half-duplex mode. the col output becomes inactive during full duplex mode. col may be tested by setting the collision test bit of the basic control register . this enables the collision test. col will be asserted within 512 bit times of txen rising and will be de-asserted within 4 bit times of txen falling. in 10base-t mode, col pulses for approximately 10 bi t times (1us), 2us after each transmitted packet (de-assertion of txen). this serves as the signal quality error (sqe) signa l and indicates that the transmission was successful. 3.9.6 link integrity this section details the establis hment, maintenance and removal of links between the device and a link partner in 1000base-t, 100base-tx and 10base-t modes. link status is reported in the link status bit of the basic status register . the link status is also us ed to drive the device leds as described in section 3.9.1, "leds," on page 34 . 3.9.6.1 establishing and maintaining a link once a link state is determined via auto-negotiation , parallel detection, or forced operation, the device and the link partner establish a link. the completion of the auto-negotiati on process is reported via the auto-negotiate complete bit of the basic status register and issues an interrupt as described in section 3.5, "inte rrupt management," on page 26 . the speed of the link is reported in the speed indication field of the phy special control / status register . the speed is also reported on the led pins for any link.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 37 revision 1.0 (02-06-13) datasheet failure to complete the auto-negotiation process is reported through the following status bits: ? parallel detection fault reported in the auto negotiation expansion register while operating in 10base-t or 100base-tx modes. ? master/slave configuration fault reported in the master/slave status register while operating in 1000base-t mode. a fault occurs if the master/slave configuration conditions do not allow master/slave resolution, as defined in the master/slave manual config enable and master/slave manual config value bits in the master/slave control register of the local and remote link partners. 3.9.6.2 1000base-t for 1000base-t links, th e device and its link partne r enter a training phase after completion of the auto-negotiation process. the links exchange idle symbols and use the information obtained from receiving this signal to set their adaptive filter coefficients. these coefficients are used in the receiver to equaliz e the incoming signal, as well as eliminate signal impairments such as echo and cross-talk. each side indicates completion of the training phase to its link partner by changing the encoding of the idle-symbols it transmits. the link is established after both sides indicate completion of the training phase. each side continues to send idle symbols whenever it has no data to tr ansmit. the link is maintained as long as valid idle, data, or carrier extension symbols are received. status of both local and remote receivers is reported in the local receiver status and remote receiver status bits of the master/slave status register . the device also pr ovides an advanced auto li nk breaker feature (only for 1000base-t links). using this feature, the link can be taken down if the bit error rate (ber) exceeds the threshold defined in link break threshold field of the link control register . the error counting occurs during the idle time for a period commensurate with the specified ber. th e auto link breaker feature is enabled via the link break enable bit of the link control register . 3.9.6.3 100base-tx for 100base-tx links, the device and its link partner begin transmitting idle symbols after completion of the auto-negotiation process. ea ch side continues sending idle symbols whenever it has no data to transmit. the link is maintained as long as valid idle symbols or data are received. 3.9.6.4 10base-t for 10base-t links, the device and its link partner begin exchanging normal link pulses (nlps) after completion of the auto-negotiation process. the device transmits an nlp every 16ms and expects to receive an nlp every 8 to 24ms. a link is ma intained as long as nlps are received. 3.9.6.5 taking down a link the device takes down an established link when t he required conditions are no longer met. when a link is down, data transmission st ops. for 10base-t links, the link is taken down after nlps are no longer received. for 100base-tx an d 1000base-t links, the link is ta ken down after valid idle codes are no longer received. after a link is down, the device does the following: ? if auto-negotiation is enabled, the device re-e nters the auto-negotiation phase and begins transmitting flps ? if auto-negotiation is not enabled, the device transmits nlps in 10base-t mode, and mlt-3s in 100base-tx mode.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 38 smsc lan8810/lan8810i datasheet 3.9.7 speed optimizer the speed optimize function is designed to resolve th e issue of using auto-negotiation to establish a link on impaired cable plants. examples of impaired cable plants for 1000base-t (gigabit) connections include: ? channel 2 twisted pair cable plant is broken ? channel 3 twisted pair cable plant is broken ? channel 2 and 3 twisted pair cable plants are broken ? cable plant is too long examples of impaired cable plants for 100base-tx connections include: ? cable plant is too long ? using wrong cable plant (such as cat-3) the speed optimize function requires the mac to support 1000/100/10 mbps speeds, 1000/100 mbps speeds, 1000/10 mbps or 100/10 mbps speeds. if a link fails to establish after the link partner s go through auto-negotiation several times at the hcd (highest common denominator), the device advertises the next highest-allowable speed (as set in the auto negotiation advertisement register ) and restarts auto-negotiation with the new speed. when 1000base-t is advertised, the speed optimize function can change its advertised speed from 1000base-t to 100base-tx and from 100base-tx to 10base-t. wh en 100base-tx is advertised, the speed optimize function can change its advertised speed from 100base-tx to 10base-t. if a previous link has used the speed optimize function to establish a link, when the link goes down, the device begins advertising with all capable speeds. the speed optimize function resets itself to advertise hcd/all speed capabilities after any of the following occurrences: ? hardware reset ? software reset ? while link partners exchange link pulses through th e speed optimize process, the device does not receive link pulses for a period of few seconds ? after an established link goes down the speed optimize function is enabled via speed optimize enable bit in the 10/100 mode control/status register . when a link (with a speed slower than hcd) is being established through the speed optimize process, it is reported via the speed optimize status bit in the user status 2 register . 3.9.8 loopback operation the local loopback mode is enabled by setting the loopback bit of the basic control register . in this mode, the scrambled transmit data (output of the scrambler) is looped into the receive logic (input of the descrambler). this mode is useful as a boar d diagnostic and serves as a quick functional verification of the device. the col signal will be inactive in this mode, unless the collision test bit of the basic control register is set. note: during transmission in local loopback mode, nothing is transmitted to the line and the transmitters are powered down.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 39 revision 1.0 (02-06-13) datasheet 3.9.9 ieee 1149.1 (j tag) boundary scan the device includes an integrated jtag boundary-scan te st port for board-level testing. the interface consists of four pins (tdo, tdi, tck and tms) and in cludes a state machine, data register array, and an instruction register. the jtag pins are described in table 2.5, ?jtag pins,? on page 15 . the jtag interface conforms to the ieee standard 1149.1 - 1990 standard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck, while the output signal tdo is clocked on the falling edge. the jtag logic is reset via a hardware reset or when the tms and tdi pins are high for five tck periods. the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 3 . 1 5 . note: all digital i/o pins support ieee 1149.1 operat ion. analog pins and the xo pin do not support ieee 1149.1 operation. 3.9.10 advanced features the device implements several advanced features to enhance manageability of the ethernet link. these features are detailed in the following sub-sections. 3.9.10.1 crossover indicators the device reports crossed channels in the xover resolution 0:1 and xover resolution 2:3 fields of the user status 2 register . this feature is useful for troubl e-shooting problems during network installation. 3.9.10.2 polarity inversion indicators the device automatically detects and corrects inverted signal polarity. this is reported in the polarity inversion bits ( polarity_inv_3 , polarity_inv_2 , polarity_inv_1 and polarity_inv_0 ) of the user status 1 register . the polarity inversion bit for channel 1 ( polarity_inv_1 ) is valid after auto-negotiation is complete as indicated by the auto-negotiate complete bit of the basic status register . the polarity inversion bits for channels 0, 2 and 3 ( polarity_inv_0 , polarity_inv_2 , polarity_inv_3 ) are valid only after the link is up as indicated by the link status bit of the basic status register . table 3.15 ieee 1149.1 op codes instruction op code comment bypass 111 mandatory instruction sample/preload 010 mandatory instruction extest 000 mandatory instruction clamp 011 optional instruction highz 100 optional instruction idcode 001 optional instruction
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 40 smsc lan8810/lan8810i datasheet 3.9.10.3 receive error-free packets counter the quality of a link can be monitored by using the receive error-free packets counter. the device counts the number of good packets received and reports a 48-bit value across 3 advanced registers: receive error-free packets counter low register , receive error-free packets counter mid register , and receive error-free packet s counter high register . the receive error-free pa ckets counter low register latches the two other related counter regi sters and must always be read first. the receive error-free packets co unter high register register must be read last, and will automatically clear the counter. 3.9.10.4 crc error counter this 48-bit counter counts the number of crc er rors detected. it?s value can be read across 3 advanced registers: crc error counter low register , crc error counter mid register , and crc error counter high register . the crc error counter low register latches the two other related counter registers and must always be read first. the crc error counter high register must be read last, and will automatically clear the counter. 3.9.10.5 receive error during data counter this 16-bit counter counts the number of errors th at occurred while data was being received. the value is read from the receive error during data counter register . 3.9.10.6 receive error during idle counter this 16-bit counter counts the number of errors that occurred during idle. the value is read from the receive error during idle counter register register. 3.9.10.7 transmitted packets counter this 48-bit counter counts the number of packets that were transmitted. it?s value can be read across 3 advanced registers: transmit packet counter low register , transmit packet counter mid register , and transmit packet counter high register . the transmit packet counter low register latches the two other related counter registers and must always be read first. the transmit packet counter high register must be read last, and it will automatically clear the counter.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 41 revision 1.0 (02-06-13) datasheet 3.10 application diagrams this section provides typical applic ation diagrams for the following: ? simplified application diagram ? power supply & twisted pair interface diagram 3.10.1 simplified application diagram figure 3.1 simplified application diagram 8 lan8810/ lan8810i txd[7:0] txclk txen txer tr0p tr0n magnetics rj45 tr1p tr1n tr2p tr2n tr3p tr3n 8 rxd[7:0] rxclk rxdv 25mhz config[3:0] 4 interface mdio mdc nreset macclk rxer gtxclk irq col crs xi xo jtag (optional) tdi tms tck tdo hpd gmii 10_led 100_led 1000_led act_led
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 42 smsc lan8810/lan8810i datasheet 3.10.2 power supply & twiste d pair interface diagram figure 3.2 power supply & twisted pair interface diagram lan8810/lan8810i ethrbias vss 8.06k ohm 1% (x4) vdd12a vdd12pll c bypass vdd12bias c bypass vdd12core (x6) c bypass vddvario (x6) c bypass x6 x6 power supply 2.5 ? 3.3v power supply 1.2v magnetics tr0p tr0n 1 2 3 4 5 6 7 8 1000 pf 2 kv circuitry within the dotted line is for channel 0. duplicate this circuit for channels 1, 2 and 3. rj45 75 c bypass 49.9 49.9 0.022uf note: 0.022uf capacitor is optional. in an emi constrained environment, populate this capacitor. the component must be placed close to the transformer.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 43 revision 1.0 (02-06-13) datasheet chapter 4 register descriptions this chapter describes the various control and status registers (csr?s). all registers follow the ieee 802.3 (clause 22.2.4) management register set. all fu nctionality and bit definitions comply with these standards. the ieee 802.3 specified register index (i n decimal) is included with each register definition, allowing for addressing of these registers via the serial management interface (smi) protocol. the device registers are categorized into following groups: ? primary phy registers ? advanced phy registers 4.1 register nomenclature table 4.1 describes the register bit attri butes used throughout this document. many of these register bit notations can be co mbined. some examples of this are shown below: ? r/w: can be written. will return current setting on a read. ? r/wac: will return current setting on a read. writing anything clears the bit. table 4.1 register bit types register bit type notation register bit description r read: a register or bit with this attribute can be read. w write: a register or bit with th is attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-on ly, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect. wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents is self-cleared after the being set. writes of zero have no effect. contents can be read. ro/lh read only, latch high: this mode is used by the ether net phy registers. bits with this attribute will stay high until the bit is read. af ter it a read, the bit will remain high, but will change to low if the condition th at caused the bit to go high is removed. if the bit has not been read the bit will remain high regardless of if its cause has been removed. nasr not affected by software reset: the state of nasr bits does not change on assertion of a software reset. x either a 1 or 0. reserved reserved field: reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. the value of reserved bits is not guaranteed on a read.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 44 smsc lan8810/lan8810i datasheet 4.2 primary phy registers the primary phy registers are accessed via the smi bu s. an index is used to access individual primary registers. primary phy regi ster indexes are shown in table 4.2, "phy control and status registers" . additional read-only advanced register s are indirectly accessible via the advanced register address port and advanced register read data port . section 4.3, "advanced phy registers," on page 68 provides detailed information regarding the advanced registers. note: all unlisted register index values are no t supported and should not be addressed. note: the nasr (not affected by software reset) designation is only applicable when the phy soft reset (reset) bit of the basic contro l register is set. table 4.2 phy control and status registers index (in decimal) register name 0 basic control register 1 basic status register 2 phy identifier 1 register 3 phy identifier 2 register 4 auto negotiation advertisement register 5 auto negotiation link partner ability register 6 auto negotiation expansion register 7 auto negotiation next page tx register 8 auto negotiation next page rx register 9 master/slave control register 10 master/slave st atus register 15 extended status register 16 link control register 17 10/100 mode control/status register 18 10/100 special modes register 19 extended mode control/status register 20 advanced register address port 21 advanced register read data port 27 control / status indications register 29 interrupt source flags register 30 interrupt mask register 31 phy special control / status register
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 45 revision 1.0 (02-06-13) datasheet 4.2.1 basic control register note 4.1 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 33 ? index (in decimal): 0 size: 16 bits bits description type default 15 phy soft reset (reset) 1 = phy software reset. this bit is self-clearing. when setting this bit, do not set other bits in this register. the conf iguration is set from the register bit values as described in section 3.6.2, "software reset," on page 27 . note: the phy will be in the normal mode after a phy software reset. r/w sc 0b 14 loopback 0 = normal operation 1 = loopback mode r/w 0b 13 speed select[0] together with speed select[1] , sets speed per the following table: [speed select1][speed select 0] 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved note: ignored if the auto-negotiation enable bit of this register is 1. r/w note 4.1 12 auto-negotiation enable 0 = disable auto-negotiate process 1 = enable auto-negotiate process (overrides the speed select[0] , speed select[1] , and duplex mode bits of this register) r/w note 4.1 11 power down 0 = normal operation 1 = general power down mode note: auto-negotiation enable must be cleared before setting this bit. r/w 0b 10 isolate 0 = normal operation 1 = electrical isolation of phy from gmii r/w 0b 9 restart auto-negotiate 0 = normal operation 1 = restart auto-negotiate process note: bit is self-clearing. r/w sc 0b 8 duplex mode 0 = half duplex 1 = full duplex note: ignored if the auto-negotiation enable bit of this register is 1. r/w note 4.1 7 collision test 0 = disable col test 1 = enable col test r/w 0b 6 speed select[1] see description for speed select[0] for details. ro note 4.1 5:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 46 smsc lan8810/lan8810i datasheet 4.2.2 basic status register index (in decimal): 1 size: 16 bits bits description type default 15 100base-t4 0 = no t4 ability 1 = t4 able ro 0b 14 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 1b 13 100base-tx half duplex 0 = no tx half duplex ability 1 = tx with half duplex ro 1b 12 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 1b 11 10base-t half duplex 0 = no 10mbps with half duplex ability 1 = 10mbps with half duplex ro 1b 10 100base-t2 full duplex 0 = phy not able to perform full duplex 100base-t2 1 = phy able to perform full duplex 100base-t2 ro 0b 9 100base-t2 half duplex 0 = phy not able to perfo rm half duplex 100base-t2 1 = phy able to perform half duplex 100base-t2 ro 0b 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 1b 7:6 reserved ro - 5 auto-negotiate complete 0 = auto-negotiate process not completed 1 = auto-negotiate process completed ro 0b 4 remote fault 0 = no remote fault 1 = remote fault condition detected ro/lh 0b 3 auto-negotiate ability 0 = unable to perform auto-negotiation function 1 = able to perform aut o-negotiation function ro 1b 2 link status 0 = link is down 1 = link is up ro/ll 0b 1 jabber detect 0 = no jabber condition detected 1 = jabber condition detected ro/lh 0b 0 extended capabilities 0 = does not support extended capabilities registers 1 = supports extended capabilities registers ro 1b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 47 revision 1.0 (02-06-13) datasheet 4.2.3 phy identifier 1 register index (in decimal): 2 size: 16 bits bits description type default 15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. oui=00800fh r/w 0007h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 48 smsc lan8810/lan8810i datasheet 4.2.4 phy identifier 2 register note 4.2 the default value of this field will vary dependant on the silicon revision number. index (in decimal): 3 size: 16 bits bits description type default 15:10 phy id number assigned to the 19th through 24th bits of the oui. r/w c0h 9:4 model number six-bit manufacturer?s model number. r/w 0ch 3:0 revision number four-bit manufacturer?s revision number. r/w note 4.2
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 49 revision 1.0 (02-06-13) datasheet 4.2.5 auto negotiation advertisement register note 4.3 the default is determined by the config1 pin as described in section 3.8.1.2.1, "configuring the smi address (config[1:0])," on page 30 note 4.4 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 33 . index (in decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable note: this device does not support next page ability. r/w 0b 14 reserved ro - 13 remote fault 0 = no remote fault 1 = remote fault detected r/w 0b 12 reserved ro - 11 asymmetric pause 0 = asymmetrical pause direct ion is not supported by mac 1 = asymmetrical pause direction is supported by mac r/w 0b 10 pause operation (pause) 0 = pause operation is not supported by mac 1 = pause operation is supported by mac r/w note 4.3 9 reserved ro - 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex r/w note 4.4 7 100base-tx 0 = no tx ability 1 = tx able r/w note 4.4 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex r/w note 4.4 5 10base-t 0 = no 10mbps ability 1 = 10mbps able r/w note 4.4 4:0 selector field 00001 = i eee 802.3 r/w 00001b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 50 smsc lan8810/lan8810i datasheet 4.2.6 auto negotiation link partner ability register index (in decimal): 5 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received 1 = link code word received from partner ro 0b 13 remote fault 0 = no remote fault 1 = remote fault detected ro 0b 12:11 reserved ro - 10 pause operation (pause) 0 = pause operation is not supported by remote mac 1 = pause operation is supported by remote mac ro 0b 9 100base-t4 0 = no t4 ability 1 = t4 able note: this phy does not support t4 ability. ro 0b 8 100base-tx full duplex 0 = no tx full duplex ability 1 = tx with full duplex ro 0b 7 100base-tx 0 = no tx ability 1 = tx able ro 0b 6 10base-t full duplex 0 = no 10mbps with full duplex ability 1 = 10mbps with full duplex ro 0b 5 10base-t 0 = no 10mbps ability 1 = 10mbps able ro 0b 4:0 selector field 00001 = i eee 802.3 ro 00001b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 51 revision 1.0 (02-06-13) datasheet 4.2.7 auto negotiation expansion register index (in decimal): 6 size: 16 bits bits description type default 15:5 reserved ro - 4 parallel detection fault 0 = no fault detected by parallel detection logic 1 = fault detected by parallel detection logic ro/lh 0b 3 link partner next page able 0 = link partner does not have next page ability 1 = link partner has next page ability ro 0b 2 next page able 0 = local device does not have next page ability 1 = local device has next page ability ro 0b 1 page received 0 = new page not yet received 1 = new page received ro/lh 0b 0 link partner auto -negotiation able 0 = link partner does not have auto-negotiation ability 1 = link partner has auto-negotiation ability ro 0b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 52 smsc lan8810/lan8810i datasheet 4.2.8 auto negotiation n ext page tx register index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot comply with message 1 = device will comply with message r/w 0b 11 toggle 0 = previous value was high 1 = previous value was low ro 0b 10:0 message code message/unformatted code field rw 00 0000 0001b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 53 revision 1.0 (02-06-13) datasheet 4.2.9 auto negotiation n ext page rx register index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 1b 12 acknowledge 2 0 = device cannot comply with message 1 = device will comply with message ro 0b 11 toggle 0 = previous value was high 1 = previous value was low ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 54 smsc lan8810/lan8810i datasheet 4.2.10 master/slave control register note 4.5 the default is determined by the config[3:2] pins as described in section 3.8.1.2.3, "configuration bits impacted by the mode of operation," on page 33 . index (in decimal): 9 size: 16 bits bits description type default 15:13 test mode 000 = normal mode 001 = test mode 1 - transmit waveform test 010 = test mode 2 - transmit jitter test in master mode 011 = test mode 3 - transmit jitter test in slave mode 100 = test mode 4 - transmitter distortion test 101 = reserved 110 = reserved 111 = reserved note: setting these bits may prevent co rrect link partner connection if both the device phy and link pa rtner phy are set as masters. r/w 000b 12 master/slave manual config enable 0 = disable master-slave manual configuration value 1 = enable master-slave manual configuration value r/w note 4.5 11 master/slave manual config value active only when the master/slave manual config enable bit of this register is 0. 0 = slave 1 = master r/w note 4.5 10 port type active only when the master/slave manual config enable bit of this register is 0. 0 = single port device 1 = multiport device r/w note 4.5 9 1000base-t full duplex 0 = advertise phy is not 100 0base-t full duplex capable 1 = advertise phy is 1000 base-t full duplex capable r/w note 4.5 8 1000base-t half duplex 0 = advertise phy is not 100 0base-t half duplex capable 1 = advertise phy is 1000 base-t half duplex capable r/w note 4.5 7:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 55 revision 1.0 (02-06-13) datasheet 4.2.11 master/slave status register index (in decimal): 10 size: 16 bits bits description type default 15 master/slave configuration fault 0 = no master-slave configuration fault detected 1 = master-slave configuration fault detected ro/lh 0b 14 master/slave configuration resolution 0 = local phy configuration resolved to slave 1 = local phy configuration resolved to master ro 0b 13 local receiver status 0 = local receiver not ok 1 = local receiver ok ro 0b 12 remote receiver status 0 = remote receiver not ok 1 = remote receiver ok ro 0b 11 lp 1000t fd this bit is valid only when the page received bit of the auto negotiation expansion register is 1. 0 = link partner is not capable of 1000base-t full duplex 1 = link partner is capa ble of 1000base-t full duplex ro 0b 10 lp 1000t hd this bit is valid only when the page received bit of the auto negotiation expansion register is 1. 0 = link partner is not capable of 1000base-t half duplex 1 = link partner is capa ble of 1000base-t half duplex ro 0b 9:8 reserved ro - 7:0 idle error count cumulative count of the errors detected when the receiver is receiving idles. these bits are reset to all zeroes when the error count is read by the management function or upon executio n of a hardware reset, software reset, or logical reset. this field is held at all ones in case of over-flow. this field can be used to trigger an interrupt upon overflow. refer to section 3.5, "interrupt ma nagement," on page 26 for additional information. ro 00h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 56 smsc lan8810/lan8810i datasheet 4.2.12 extended status register index (in decimal): 15 size: 16 bits bits description type default 15 1000base-x full duplex 0 = phy not able to perfo rm full duplex 1000base-x 1 = phy able to perform full duplex 1000base-x ro 0b 14 1000base-x half duplex 0 = phy not able to perfo rm half duplex 1000base-x 1 = phy able to perform half duplex 1000base-x ro 0b 13 1000base-t full duplex 0 = phy not able to perfo rm full duplex 1000base-t 1 = phy able to perform full duplex 1000base-t ro 1b 12 1000base-t half duplex 0 = phy not able to perfo rm half duplex 1000base-t 1 = phy able to perform half duplex 1000base-t ro 1b 11:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 57 revision 1.0 (02-06-13) datasheet 4.2.13 link control register index (in decimal): 16 size: 16 bits bits description type default 15:10 reserved ro - 9:8 speed optimize control this register sets the number of auto negotiation attempts before the speed optimize mechanism redu ces the advertised speed. 00 = 7 attempts 01 = 5 attempts 10 = 4 attempts 11 = 3 attempts note: refer to section 3.9.7, "speed optimizer," on page 38 for additional information. r/w 00b 7:6 reserved ro - 5:4 link break threshold idle error threshold for failing the link, if link break in enabled. 00 = link break threshold is 10e-8. 01 = link break threshold is 10e-9. 10 = link break threshold is 10e-10. 11 = link break threshold is 10e-11 r/w 10b 3 link break enable 0 = link break is disabled 1 = link break is enabled r/w 0b 2 power optimization disable 0 = automatic power optimization is enabled 1 = automatic power optimization is disabled (power consumption is maximum) r/w 0b 1 reserved ro - 0 lrst logic reset. this bit generates a reset that put all the logic into a known state, but does not affect the register sets and 10/100 circuits. this bit is not a self-clearing bit. writing "1" to this bit generates synchronous reset. ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 58 smsc lan8810/lan8810i datasheet 4.2.14 10/100 mode control/status register index (in decimal): 17 size: 16 bits bits description type default 15 edshort energy detect short detection mode 0 = normal detect mode 1 = short detect mode r/w 0b 14 fastrip 10base-t fast mode 0 = normal operation 1 = activates phyt_10 test mode r/w 0b 13 edpwrdown enable the energy detect power-down mode 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled r/w 0b 12 ed power down mode select energy detect power down mode 0 = ed power down mode without nlp transmission 1 = ed power down mode with nlp transmission r/w 0b 11:8 reserved ro - 7 speed optimize enable 0 = disable speed optimize 1 = enable speed optimize note: refer to section 3.9.7, "speed optimizer," on page 38 for additional information. r/w 0b 6 autoneg np enable 0 = next page is disabled in the auto-negotiation process 1 = next page is enabled in the auto-negotiation process r/w 1b 5 auto mdix disable 0 = auto xover is enabled 1 = auto xover is disabled selection is done manually r/w 0b 4 auto next page disable setting this bit disables automatic next page exchange in 1000base-t. advertising of next pages then depends on the value of the next page bit of the auto negotiation advertisement register . in this case, if next page is cleared, only the base page is sent. 0 = normal operation 1 = automatic next page is disabled r/w 0b 3:2 reserved ro - 1 energyon this bit indicates whether energy is detec ted on the line. it is reset to ?1? by a hardware reset. when a so ftware reset is asserted, this bit is cleared. if this bit was set prior to a software reset, it will cause the int7 bit of the interrupt source flags register to be set. therefore, after a software or hardware reset, the int7 bit should be cleared by writing a ?1? to it. refer to section 3.5, "interrupt management," on page 26 for additional energyon information. ro 1b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 59 revision 1.0 (02-06-13) datasheet 0 semi crossover enable setting this register enables semi cross over. 0 = disable semi cross over 1 = enable semi cross over note: refer to section 3.2, "hp auto-mdix," on page 22 for additional information. r/w 0b bits description type default
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 60 smsc lan8810/lan8810i datasheet 4.2.15 10/100 speci al modes register note 4.6 the default is determined by the config[1:0] pins as described in section 3.8.1.2.1, "configuring the smi address (config[1:0])," on page 30 . index (in decimal): 18 size: 16 bits bits description type default 15 enable rxdv early assertion setting this bit enables early assert ion of rxdv in 10base-t. rxdv is asserted before the sfd. 0 = disable 1 = enable r/w 0b 14 10bt hd loopback disable setting this bit disables mii loopback in 10base-t half duplex mode. 0 = normal operation 1 = activates phyt_10 test mode r/w nasr 000000b 13:8 reserved ro - 7 crc error counter data source setting this bit changes the data source of the 1000base-t crc error counter. 0 = data source in 1000base-t received data 1 = data source in 1000base-t transmitted data r/w 0b 6 mclk25en enable an 25mhz mac clock output. 0 = 125mhz 1 = 25mhz ro 0b 5 reserved ro - 4:0 phyadd[4:0] the phy address is used for the smi add ress and for the initialization of the cipher (scrambler) key. r/w nasr note 4.6
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 61 revision 1.0 (02-06-13) datasheet 4.2.16 extended mode control/status register note 4.7 the default mode is determined by the config[3:2] pins as described in section 3.8.1.2.2, "configuring the mode of operation (config[3:2])," on page 31 note 4.8 .the default is determined by the config3 pin as described in section 3.8.1.2.2, "configuring the mode of oper ation (config[3:2])," on page 31 . index (in decimal): 19 size: 16 bits bits description type default 15:11 mod configures mode of operation. refer to section 3.8.1.2.2, "configuring the mode of operation (c onfig[3:2])," on page 31 for details. r/w nasr note 4.7 10:9 transmitter fifo depth 00 = 4 bytes 01 = 5 bytes 10 = 6 bytes 11 = 7 bytes r/w 00b 8:6 reserved ro - 5:4 led_mode[1:0] 00 = reserved 01 = led mode 1 10 = led mode 2 11 = led mode 3 refer to section 3.9.1, "leds," on page 34 for additional information. r/w 11b 3 macclkdis 0 = normal mode, macclk pin is toggling at 125mhz or 25mhz 1 = disable macclk pin from toggling, (driving it low) r/w nasr note 4.8 2 mdi/mdi-x 0:1 selects between mdi and mdi-x for channel 0 and channel 1 only if the auto mdix disable bit of the 10/100 mode control/status register is 1. 0 = mdi 1 = mdi-x rw 0b 1 mdi/mdi-x 2:3 selects between mdi and mdi-x for channel 2 and channel 3 only if the auto mdix disable bit of the 10/100 mode control/status register is 1. 0 = mdi 1 = mdi-x rw 0b 0 conditional parallel detect 0 = parallel detect. ( auto negotiation advertisement register is ignored.) 1 = conditional parallel detect only at the speed advertised in the auto negotiation advertisement register . 10base-t half duplex ( 10base-t bit =1) 100base-tx half duplex ( 100base-tx bit =1) rw 0b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 62 smsc lan8810/lan8810i datasheet 4.2.17 advanced register address port note: refer to section 4.3, "advanced ph y registers," on page 68 for additional information on the advanced register set. index (in decimal): 20 size: 16 bits bits description type default 15 read when this bit is set to 1, the contents of the advanced regi ster selected by the register address field are latched to the advanced register read data port . this bit is self-cleared. sc 0b 14:7 reserved must be written with 00000011b for proper operation. the values of reserved bits are not guaranteed on a read. r/w - 6:0 register address the address of the advanced register being accessed (0-12). ro 0000000b
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 63 revision 1.0 (02-06-13) datasheet 4.2.18 advanced register read data port note: refer to section 4.3, "advanced ph y registers," on page 68 for additional information on the advanced register set. index (in decimal): 21 size: 16 bits bits description type default 15:0 read data read from the advanced register selected via the advanced register address port . ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 64 smsc lan8810/lan8810i datasheet 4.2.19 control / status indications register index (in decimal): 27 size: 16 bits bits description type default 15:5 reserved ro - 4 xpol polarity state of the 10base-t: 0 = normal polarity 1 = reversed polarity ro 0b 3:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 65 revision 1.0 (02-06-13) datasheet 4.2.20 interrupt source flags register note: refer to section 3.5, "interrupt management," on page 26 for additional information. index (in decimal): 29 size: 16 bits bits description type default 15:11 reserved ro - 10 int10 0 = not source of interrupt 1 = transmitter elastic buffer overflow lh/wc 0b 9 int9 0 = not source of interrupt 1 = transmitter elastic buffer underflow lh/wc 0b 8 int8 0 = not source of interrupt 1 = idle error count overflow lh/wc 0b 7 int7 0 = not source of interrupt 1 = energyon generated this bit is set when there is a ?0? to ?1? transition of the energyon bit in the 10/100 mode contro l/status register . this occurs when transitioning from no energy detected to energy detected, or vice versa. lh/wc 0b 6 int6 0 = not source of interrupt 1 = auto-negotiation complete lh/wc 0b 5 int5 0 = not source of interrupt 1 = remote fault detected lh/wc 0b 4 int4 0 = not source of interrupt 1 = link down (link status negated) lh/wc 0b 3 int3 0 = not source of interrupt 1 = auto-negotiation lp acknowledged lh/wc 0b 2 int2 0 = not source of interrupt 1 = parallel detection fault or master/slave configuration fault lh/wc 0b 1 int1 0 = not source of interrupt 1 = auto-negotiation page received lh/wc 0b 0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 66 smsc lan8810/lan8810i datasheet 4.2.21 interrupt mask register note: refer to section 3.5, "interrupt management," on page 26 for additional information. index (in decimal): 30 size: 16 bits bits description type default 15:11 reserved ro - 10 int10_en transmitter elastic buffer overflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 9 int9_en transmitter elastic buffer underflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 8 int8_en idle error count overflow interrupt enable. 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 7 int7_en energyon interrupt enable 0 = interrupt source is masked 1 = interrupt source is enabled r/w 0b 6 int6_en auto-negotiation interrupt enable 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 5 int5_en remote fault detected interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 4 int4_en link down (link status negated) interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 3 int3_en auto-negotiation lp acknowledge interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 2 int2_en parallel detection fault or master/slave configuration fault interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 1 int1_en auto-negotiation page received interrupt enable. 0 = interrupt source is masked. 1 = interrupt source is enabled. r/w 0b 0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 67 revision 1.0 (02-06-13) datasheet 4.2.22 phy special control / status register note 4.9 set according to the results of auto-negotiation. index (in decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 auto-negotiation done indication 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done note: this is a duplicate of register 1.5, however reads to register 31 do not clear status bits. ro 0b 11:5 reserved ro - 4:2 speed indication hcdspeed value: [001]=10mbps half-duplex [101]=10mbps full-duplex [010]=100base-tx half-duplex [110]=100base-tx full-duplex ro note 4.9 1:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 68 smsc lan8810/lan8810i datasheet 4.3 advanced phy registers the advanced phy registers are acce ssed using the following procedure: 1. write to the advanced register address port with the read bit set high, and the address of the desired advanced register in the register address field. 2. read the contents of the selected register from advanced register read data port . note: the advanced registers cannot be written. all advanced regist ers are comprised of read-only (ro), or read-to-clear (rc) bits. 4.3.1 advanced register mapping table 4.3 advanced register mapping register number register name u0 user status 1 register u1 user status 2 register u2 receive error-free packets counter high register u3 receive error-free packets counter mid register u4 receive error-free packets counter low register u5 crc error counter high register u6 crc error counter mid register u7 crc error counter low register u8 receive error during data counter register u9 receive error during idle counter register u10 transmit packet counter high register u11 transmit packet counter mid register u12 transmit packet counter low register
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 69 revision 1.0 (02-06-13) datasheet 4.3.2 user status 1 register index: u0 size: 16 bits bits description type default 15 pllready 0 = pll is not locked 1 = pll is locked ro 0b 14 polarity_inv_3 this bit indicates reverse polarity on channel 3 when operating in 1000base-t mode. 0 = channel 3 polarity is correct 1 = channel 3 polarity is reversed ro 0b 13 polarity_inv_2 this bit indicates reverse polarity on channel 2 when operating in 1000base-t mode. 0 = channel 2 polarity is correct 1 = channel 2 polarity is reversed ro 0b 12 polarity_inv_1 this bit indicates reverse polarity on channel 1 when operating in 1000base-t mode. 0 = channel 1 polarity is correct 1 = channel 1 polarity is reversed ro 0b 11 polarity_inv_0 this bit indicates reverse polarity on channel 0 when operating in 1000base-t mode. 0 = channel 0 polarity is correct 1 = channel 0 polarity is reversed ro 0b 10:9 reserved ro - 8 clkref_sel 0 = reference clock frequency = 125mhz 1 = reference clock frequency = 25mhz the value of this bit is based upon the configuration strap settings, as detailed in section 3.8.1.1, "configur ation straps," on page 29 . ro 0b 7:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 70 smsc lan8810/lan8810i datasheet 4.3.3 user status 2 register index: u1 size: 16 bits bits description type default 15 xover resolution 0:1 0 = channel 0 and channel 1 resolved as mdi. 1 = channel 0 and channel 1 resolved as mdi-x. ro 0b 14 xover resolution 2:3 0 = channel 2 and channel 3 resolved as mdi. 1 = channel 2 and channel 3 resolved as mdi-x. ro 0b 13 speed optimize status when set, indicates the link was established using the speed optimize mechanism. note: refer to section 3.9.7, "speed optimizer," on page 38 for additional information. ro 0b 12:0 reserved ro -
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 71 revision 1.0 (02-06-13) datasheet 4.3.4 receive error-free pack ets counter high register note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packets counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. index: u2 size: 16 bits bits description type default 15:0 rcvgpkt[47:32] counts the received error-free packets. contains the 16 upper bits of the 48-bit counter. reading this register resets all bi ts in the receive error-free packets counter. ro/ rc 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 72 smsc lan8810/lan8810i datasheet 4.3.5 receive error-free pack ets counter mid register note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packets counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. index: u3 size: 16 bits bits description type default 15:0 rcvgpkt[31:16] counts the received error-free packets. contains the 16 middle bits of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 73 revision 1.0 (02-06-13) datasheet 4.3.6 receive error-free pack ets counter low register note: the 48-bit receive error-free packets counter is split across 3 registers. in order to read the counter correctly, the registers must be read in the following order: receive error-free packets counter low register , receive error-free packets counter mid register , receive error-free packets counter high register . after reading the high register, the counter will be automatically cleared. index: u4 size: 16 bits bits description type default 15:0 rcvgpkt[15:0] counts the received error-free packets. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 74 smsc lan8810/lan8810i datasheet 4.3.7 crc error counter high register note: the 48-bit crc error counter is split across 3 regi sters. in order to read the counter correctly, the registers must be read in the following order: crc error counter low register , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. index: u5 size: 16 bits bits description type default 15:0 crcerr[47:32] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 upper bits of the 48-bit counter. reading this register resets all bits in the crc error counter. ro/ rc 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 75 revision 1.0 (02-06-13) datasheet 4.3.8 crc error counter mid register note: the 48-bit crc error counter is split across 3 regi sters. in order to read the counter correctly, the registers must be read in the following order: crc error counter low register , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. index: u6 size: 16 bits bits description type default 15:0 crcerr[31:16] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 middle bits of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 76 smsc lan8810/lan8810i datasheet 4.3.9 crc error counter low register note: the 48-bit crc error counter is split across 3 regi sters. in order to read the counter correctly, the registers must be read in the following order: crc error counter low register , crc error counter mid register , crc error counter high register . after reading the high register, the counter will be automatically cleared. index: u7 size: 16 bits bits description type default 15:0 crcerr[15:0] counts the crc errors, which are gener ated by the crc checker circuit. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 77 revision 1.0 (02-06-13) datasheet 4.3.10 receive error during data counter register index: u8 size: 16 bits bits description type default 15:0 rxerind_data[15:0] counts the assertions of rxer (going from low to high) when rxdv is high . ro/ rc 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 78 smsc lan8810/lan8810i datasheet 4.3.11 receive error during idle counter register index: u9 size: 16 bits bits description type default 15:0 rxerind_idle[15:0] counts the assertions of rxer (going from low to high) when rxdv is low . ro/ rc 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 79 revision 1.0 (02-06-13) datasheet 4.3.12 transmit packet counter high register note: the 48-bit transmit packet counter is split ac ross 3 registers. in order to read the counter correctly, the registers must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. index: u10 size: 16 bits bits description type default 15:0 txpkt[47:32] counts the number of transmitted packets. contains the 16 upper bits of the 48-bit counter. reading this register resets all bits in the trans mit packet counter. ro/ rc 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 80 smsc lan8810/lan8810i datasheet 4.3.13 transmit packet counter mid register note: the 48-bit transmit packet counter is split ac ross 3 registers. in order to read the counter correctly, the registers must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. index: u11 size: 16 bits bits description type default 15:0 txpkt[31:16] counts the number of transmitted packets. contains the 16 middle bits of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 81 revision 1.0 (02-06-13) datasheet 4.3.14 transmit packet counter low register note: the 48-bit transmit packet counter is split ac ross 3 registers. in order to read the counter correctly, the registers must be read in the following order: transmit packet counter low register , transmit packet counter mid register , transmit packet counter high register . after reading the high register, the counter will be automatically cleared. index: u12 size: 16 bits bits description type default 15:0 txpkt[15:0] counts the number of transmitted packets. contains the 16 low-order bi ts of the 48-bit counter. ro 0000h
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 82 smsc lan8810/lan8810i datasheet chapter 5 operational characteristics 5.1 absolute maximum ratings* supply voltage (vddvario) ( note 5.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +3.6v analog supply voltage (vdd12a) ( note 5.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +1.5v digital core supply voltage (vdd12core) ( note 5.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +1.5v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +3 .6v positive voltage on signal pins, with respect to ground ( note 5.2 ). . . . . . . . . . . . . . . . . . . . . . . . .+6.0v negative voltage on signal pins, with respect to ground ( note 5.3 ) . . . . . . . . . . . . . . . . . . . . . . . . -0.5v positive voltage on xi, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 4.6v positive voltage on xo, with re spect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2. 5v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5.4 junction to ambient ( ja ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22.5 o c/w junction to top of package ( jt ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 o c/w storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 latch-up performance per eia/jesd 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+/-150ma note 5.1 when powering this device from laboratory or system power su pplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggeste d that a clamp circuit be used. note 5.2 this rating does not apply to the following pins: xi, xo, ethrbias. note 5.3 this rating does not apply to the following pins: ethrbias. note 5.4 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. *stresses exceeding those listed in this section c ould cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 5.2, "operating conditions**" , section 5.4, "dc specifications" , or any other applicable section of this specification is not im plied. note, device signals are not 5 volt tolerant unless specified otherwise.
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 83 revision 1.0 (02-06-13) datasheet 5.2 operating conditions** supply voltage (vddvario) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25v to +3 .6v supply voltage (vdd12a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14v to + 1.26v digital core supply voltage (vdd12core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14v to +1.26v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25v to +3.6 v ambient operating temperature in still air (t a ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 5.4 **proper operation of the device is guaranteed only within the ranges s pecified in this section. after the device has completed power-up, vddvario and t he magnetics power supply must maintain their voltage level within +/-10%. varying the voltage gr eater than +/-10% after the device has completed power-up can cause errors in device operation. 5.3 power consumption this section details the power consumption of the device as measured during various modes of operation. power consumption values are provided fo r both the device-only, and for the device plus ethernet components. power dissipation is impact ed by temperature, supply voltage, and external source/sink requirements. all measurements were taken at +25 c. note: all power consumption values are preliminary and subject to change. note 5.5 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. note 5.6 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. table 5.1 power consumption - 1000base-t linked parameter typical unit supply current (vddvario) (@ +3.3v) 36 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 454 ma external magnetics current (@ +3.3v) 202 ma total power dissipation (device only) ( note 5.5 ) 665 mw total power dissipation (devic e and ethernet components) ( note 5.5 ) 1331 mw table 5.2 power consumption - 100base-tx linked parameter typical unit supply current (vddvario) (@ +3.3v) 24 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 82 ma external magnetics current (@ +3.3v) 63 ma total power dissipation (device only) ( note 5.6 ) 177 mw total power dissipation (devic e and ethernet components) ( note 5.6 ) 385 mw
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 84 smsc lan8810/lan8810i datasheet note 5.7 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. note 5.8 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. note 5.9 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. table 5.3 power consumption - 10base-t linked parameter typical unit supply current (vddvario) (@ +3.3v) 21 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 32 ma external magnetics current (@ +3.3v) 123 ma total power dissipation (device only) ( note 5.7 ) 107 mw total power dissipation (devic e and ethernet components) ( note 5.7 ) 513 mw table 5.4 power consumption - energy detect parameter typical unit supply current (vddvario) (@ +3.3v) 30 ma supply current (vdd12core, vdd12bia s, vdd12pll, vdd12a) (@ +1.2v) 28 ma external magnetics current (@ +3.3v) 21 ma total power dissipation (device only) ( note 5.8 ) 133 mw total power dissipation (devic e and ethernet components) ( note 5.8 ) 203 mw table 5.5 power consumption - hardware power down (pll enabled) parameter typical unit supply current (vddvario) (@ +3.3v) 0.12 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 17.29 ma external magnetics current (@ +3.3v) 7.00 ma total power dissipation (device only) ( note 5.9 ) 21.16 mw total power dissipation (devic e and ethernet components) ( note 5.9 ) 44.26 mw
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 85 revision 1.0 (02-06-13) datasheet note 5.10 when the external magnetics operate at +2 .5v, current consumption remains the same. however, ethernet component power cons umption will be reduced accordingly. 5.4 dc specifications note 5.11 this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resistors add +/- 50ua per-pin (typical). table 5.6 power consumption - hardware power down (pll disabled) parameter typical unit supply current (vddvario) (@ +3.3v) 0.12 ma supply current (vdd12core, vdd12bias, vdd12pll, vdd12a) (@ +1.2v) 4.39 ma external magnetics current (@ +3.3v) 0.02 ma total power dissipation (device only) ( note 5.10 ) 5.68 mw total power dissipation (devic e and ethernet components) ( note 5.10 ) 5.73 mw table 5.7 i/o buffer characteristics parameter symbol min 2.5v typ 3.3v typ max units notes vis type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddvario) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 0.64 0.81 102 -10 1.15 1.29 136 1.41 1.65 138 3.6 1.76 1.90 288 10 3 v v v v mv ua pf schmitt trigger schmitt trigger note 5.11 vo6 type buffers low output level high output level v ol v oh vddvario - 0.4 0.4 v v i ol = 6ma i oh = -6ma vo8 type buffers low output level high output level v ol v oh vddvario - 0.4 0.4 v v i ol = 8ma i oh = -8ma iclk type buffer (xi input) low input level high input level v ili v ihi -0.3 1.4 0.5 3.6 v v note 5.12
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 86 smsc lan8810/lan8810i datasheet note 5.12 xi can optionally be driven from a 25mhz single-ended clock oscillator. note 5.13 ieee 802.ab test mode 1 note 5.14 from 1/2 of average v op , test mode 1 note 5.15 ieee 802.ab distortion processing note 5.16 measured at line side of transformer, line replaced by 100 (+/- 1%) resistor. note 5.17 offset from 16ns pulse width at 50% of pulse peak. note 5.18 measured differentially. note 5.19 min/max voltages guaranteed as measured with 100 resistive load. table 5.8 1000base-t transceiver characteristics parameter symbol min typ max units notes peak differential output voltage v op 670 820 mv note 5.13 signal amplitude symmetry v ss 1% note 5.13 signal scaling v sc 2% note 5.14 output droop v od 73.1 % note 5.13 transmission distortion 10 mv note 5.15 table 5.9 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 5.16 peak differential output voltage low v ppl -950 - -1050 mvpk note 5.16 signal amplitude symmetry v ss 98 - 102 % note 5.16 signal rise and fall time t rf 3.0 - 5.0 ns note 5.16 rise and fall symmetry t rfs --0.5ns note 5.16 duty cycle distortion d cd 35 50 65 % note 5.17 overshoot and undershoot v os --5% jitter 1.4 ns note 5.18 table 5.10 10base-t transceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 5.19 receiver differential squelch threshold v ds 300 420 585 mv
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 87 revision 1.0 (02-06-13) datasheet 5.5 ac specifications this section details the various ac ti ming specifications of the device. note: the gmii/mii timing adheres to the ieee 80 2.3 specification. re fer to the ieee 802.3 specification for additional gmii/mii timing information. note: the ethernet tx/rx pin timing adheres to the ieee 802.3 specificatio n. refer to the ieee 802.3 specification for detailed ethernet timing information. 5.5.1 equivalent test load output timing specifications assume a 25pf equival ent test load, unless otherw ise noted, as illustrated in figure 5.1 . figure 5.1 output equivalent test load 25 pf output
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 88 smsc lan8810/lan8810i datasheet 5.5.2 power sequence timing power supplies must adhere to the following rules: ? all power supplies of the same voltage must be powered up/down together. ? there is no power-up sequencing requirement, however all power supplies must reach operational levels within the time periods specified in ta b l e 5 . 11 . ? there is no power-down sequencing or timing requirement, however the device must not be powered for an extended period of time wit hout all supplies at operational levels. ? following initial power-on, or if a power supply br ownout occurs (i.e., one or more supplies drops below operational limits), a power-on reset must be executed once all power supplies reach operational levels. refer to section 5.5.3, "power-on reset timing," on page 89 for power-on reset requirements. ? do not drive input signals without power supplied to the device. note: violation of these specificat ions may damage the device. note: the vddvario power supply can be run at 2.5v or 3.3v. note: the magnetics power supply can be run at 2.5v or 3.3v. figure 5.2 power sequence timing table 5.11 power sequence timing values symbol description min typ max units t pon power supply turn on time 0 25 ms all 3.3v power supply pins all 2.5v power supply pins all 1.2v power supply pins t pon
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 89 revision 1.0 (02-06-13) datasheet 5.5.3 power-on reset timing figure 5.3 illustrates the nreset, configuration str ap/pin, and config[3:0] timing requirements in relation to power-on. a hardware reset (nreset assertion) is requi red following powe r-up. for proper operation, nreset must be a sserted for no less than t rstia . the nreset pin can be asserted at any time, but must not be deasserted before t purstd after all external power supplies have reached operational levels. in order for valid configuration strap values to be read at power-up, the t css and t csh timing constraints must be followed. in order for config[3:0] values to be read at power-up, the t cs and t ch timing constraints must be followed. refer to section 3.6.1, "hardware reset (nreset)," on page 27 for additional information. note: device configuration straps are latched as a result of nreset assertion. refer to section 3.8.1.1, "configuration straps," on page 29 details. configuration straps must only be pulled high or low and must not be driven as inputs. note: nreset deassertion mu st be monotonic. figure 5.3 power-on reset timing table 5.12 power-on reset timing values symbol description min typ max units t purstd external power supplies at operational level to nreset deassertion 25 ms t purstv external power supplies at operational level to nreset valid 0ns t rstia nreset input assertion time 100 s t css configuration strap pins set up to nreset deassertion 200 ns t csh configuration strap pins hold after nreset deassertion 10 ns t otaa output tri-state after nreset assertion 50 ns t odad output drive after deassertion 40 800 ns t cs config[3:0] setup to nreset deassertion 0 ns t ch config[3:0] hold after nreset deassertion 1 us t css nreset configuration straps t csh configuration strap pins output drive all external power supplies t purstd v opp t cs config[3:0] t ch t rstia t odad t purstv t otaa
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 90 smsc lan8810/lan8810i datasheet 5.5.4 reset timing figure 5.4 illustrates the nreset pin timing requirements. for proper operation, nreset must be asserted for no less than t rstia . in order for valid configuration strap values to be read upon a nreset assertion, the t css and t csh timing constraints must be followed. in order for config [3:0] values to be read at power-up, the t cs and t ch timing constraints must be followed. refer to section 3.6.1, "hardware reset (nreset)," on page 27 for additional information. note: a hardware reset (nreset assertion) is required follo wing power-up. refer to section 5.5.3, "power-on reset timing," on page 89 for additional information. note: device configuration straps are latched as a result of nreset assertion. refer to section 3.8.1.1, "configuration straps," on page 29 details. configuration straps must only be pulled high or low and must not be driven as inputs. figure 5.4 reset timing table 5.13 reset timing values symbol description min typ max units t rstia nreset input assertion time 1 s t css configuration strap pins set up to nreset deassertion 200 ns t csh configuration strap pins hold after nreset deassertion 10 ns t otaa output tri-state after nreset assertion 50 ns t odad output drive after deassertion 40 800 ns t cs config[3:0] setup to nreset deassertion 0 ns t ch config[3:0] hold after nreset deassertion 1 us t css nreset configuration straps t csh configuration strap pins output drive t cs config[3:0] t ch t rstia t odad t otaa
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 91 revision 1.0 (02-06-13) datasheet 5.5.5 gmii timi ng (1000base-t) this section specifies the gmii interface transmit and receive timing. please refer to section 3.3, "gmii interface," on page 24 for additional details. note: all gmii timing specifications assume a point-to-point test circ uit as defined in section 35.4.2.2 of the ieee 802.3- 2005 specification. note 5.20 min/max limits are non-sustainable long term. note 5.21 t r and t f are measured from v il_ac(max) =0.7v to v ih_ac(min) =1.9v. figure 5.5 gmii transmit timing table 5.14 gmii transmit timing values symbol description min max units notes f gtxclk gtxclk frequency 125 - 100ppm 125 + 100ppm mhz t clkp gtxclk period 7.5 8.5 ns note 5.20 t clkh gtxclk high time 2.5 ns t clkl gtxclk low time 2.5 ns t val txd[7:0], txen, txer setup time to rising edge of gtxclk 2.0 ns t hold txd[7:0], txen, txer hold time after rising edge of gtxclk 0.0 ns t r gtxclk rise time 1 ns note 5.21 t f gtxclk fall time 1 ns note 5.21 gtxclk txd[7:0], txen, txer t clkh t clkl t clkp t hold t val t r t f
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 92 smsc lan8810/lan8810i datasheet note 5.22 t r and t f are measured from v il_ac(max) =0.7v to v ih_ac(min) =1.9v. figure 5.6 gmii receive timing table 5.15 gmii receive timing values symbol description min max units notes t clkp rxclk period 7.5 ns t clkh rxclk high time 2.5 ns t clkl rxclk low time 2.5 ns t val rxd[7:0], rxdv, rxer output valid from rising edge of rxclk 5.0 ns t hold rxd[7:0], rxdv, rxer output hold from rising edge of rxclk 0.5 ns t r rxclk rise time 1 ns note 5.22 t f rxclk fall time 1 ns note 5.22 rxclk rxd[7:0], rxer, rxdv t clkh t clkl t clkp t hold t hold t val t val t r t f
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 93 revision 1.0 (02-06-13) datasheet 5.5.6 mii timing ( 100base-tx, 10base-t) this section specifies the mii interface tr ansmit and receive timing. please refer to section 3.3, "gmii interface," on page 24 for additional details. note 5.23 40ns for 100base-tx operation, 400ns for 10 base-t operation. note 5.24 timing was designed for system load between 10 pf and 25 pf. figure 5.7 mii receive timing table 5.16 mii receive timing values symbol description min max units notes t clkp rxclk period note 5.23 ns t clkh rxclk high time t clkp *0.4 t clkp *0.6 ns t clkl rxclk low time t clkp *0.4 t clkp *0.6 ns t val rxd[3:0], rxdv output valid from rising edge of rxclk 28.0 ns note 5.24 t hold rxd[3:0], rxdv output hold from rising edge of rxclk 10.0 ns note 5.24 rxclk rxd[3:0] rxdv t clkh t clkl t clkp t val t hold t val t val t hold
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 94 smsc lan8810/lan8810i datasheet note 5.25 40ns for 100base-tx operation, 400ns for 10 base-t operation. note 5.26 timing was designed for system load between 10 pf and 25 pf. figure 5.8 mii transmit timing table 5.17 mii transmit timing values symbol description min max units notes t clkp txclk period note 5.25 ns t clkh txclk high time t clkp *0.4 t clkp *0.6 ns t clkl txclk low time t clkp *0.4 t clkp *0.6 ns t su txd[3:0], txen setup time to rising edge of txclk 12.0 ns note 5.26 t hold txd[3:0], txen hold time after rising edge of txclk 0ns note 5.26 txclk t su txd[3:0] txen t clkh t clkl t clkp t hold t su t hold t hold t su t hold
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 95 revision 1.0 (02-06-13) datasheet 5.5.7 smi timing this section specifies the smi timing of the device. please refer to section 3.4, "serial management interface (smi)," on page 25 for additional details. figure 5.9 smi timing table 5.18 smi timing values symbol description min max units notes t clkp mdc period 400 ns t clkh mdc high time 160 (80%) ns t clkl mdc low time 160 (80%) ns t val mdio (read from phy) output valid from rising edge of mdc 300 ns t ohold mdio (read from phy) output hold from rising edge of mdc 0ns t su mdio (write to phy) se tup time to rising edge of mdc 10 ns t ihold mdio (write to phy) inpu t hold time after rising edge of mdc 10 ns mdc mdio t clkh t clkl t clkp t ohold mdio t su t ihold (data-out) (data-in) t ohold t val
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 96 smsc lan8810/lan8810i datasheet 5.5.8 jtag timing this section specifies the jtag timi ng of the device. please refer to section 3.9.9, "ieee 1149.1 (jtag) boundary scan," on page 39 for additional details. figure 5.10 jtag timing table 5.19 jtag timing values symbol description min max units notes t tckp tck clock period 66.67 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi, tms setup to tck rising edge 10 ns t h tdi, tms hold from tck rising edge 10 ns t dov tdo output valid from tck falling edge 16 ns t dohinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi, tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t dohinvld
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 97 revision 1.0 (02-06-13) datasheet 5.6 clock circuit the device can accept either a 25mhz crystal (prefe rred) or a 25mhz single-ended clock oscillator (+/- 50ppm) input. if the single-ended clock oscillator method is implemented, xo should be left unconnected and xi should be driven with a nominal 0-3.3v clock signal. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (xi/xo). see table 5.20 for the recommended crystal specifications. note 5.27 the maximum allowable values for frequency tolerance and frequency stability are application dependant. since any particular application must meet the ieee +/-50 ppm total ppm budget, the combination of these tw o values must be approximately +/-45 ppm (allowing for aging). note 5.28 frequency deviation over time is also referred to as aging. note 5.29 the total deviation for the transmitter clock frequency is specified by ieee 802.3u as +/- 50 ppm. note 5.30 0 o c for commercial version, -40 o c for industrial version. note 5.31 +70 o c for commercial version, +85 o c for industrial version. note 5.32 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xo/xi pin and pcb capacitance values are required to accurately calculate the value of the two exte rnal load capacitors. these two external load capacitors determine the accuracy of the 25.000 mhz frequency. table 5.20 crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 5.27 frequency stability over temp f temp - - +/-50 ppm note 5.27 frequency deviation over time f age - +/-3 to 5 - ppm note 5.28 total allowable ppm budget - - +/-50 ppm note 5.29 shunt capacitance c o -7pf load capacitance c l -18pf drive level p w 300 - - uw equivalent series resistance r 1 --50ohm operating temperature range note 5.30 - note 5.31 o c xi pin capacitance - 3 typ - pf note 5.32 xo pin capacitance - 3 typ - pf note 5.32
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 98 smsc lan8810/lan8810i datasheet chapter 6 package outline 6.1 72-qfn package notes: 1. all dimensions are in millimeters unless otherwise noted. 2. dimension ?b? applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. the pin 1 identifier may vary, but is always located within the zone indicated. figure 6.1 72-qfn package table 6.1 72-qfn dimensions min nominal max remarks a 0.80 0.85 1.00 overall package height a1 0.00 0.02 0.05 standoff a2 - 0.65 0.80 mold cap thickness d/e 9.90 10.00 10.10 x/y body size d1/e1 9.65 9.75 9.85 x/y mold cap size d2/e2 5.90 6.00 6.10 x/y exposed pad size l 0.30 0.40 0.50 terminal length b 0.18 0.25 0.30 terminal width k 1.50 - - center pad to pin clearance e 0.50 bsc terminal pitch
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet smsc lan8810/lan8810i 99 revision 1.0 (02-06-13) datasheet figure 6.2 72-qfn recommended pcb land pattern
gmii 10/100/1000 ethernet transceiver with hp auto-mdix support datasheet revision 1.0 (02-06-13) 100 smsc lan8810/lan8810i datasheet chapter 7 datasheet revision history table 7.1 customer revision history revision level & date secti on/figure/entr y correction rev. 1.0 (02-06-13) document co-branded: microchip logo added, company disclaimer modified. rev. 1.0 (08-02-12) section 5.3, "power consumption" updated power numbers with latest lab measurements. all added commercial version. table 5.15, ?gmii receive timing values,? on page 92 removed t val min value and added t val max value of 5.0ns. rev. 1.0 (06-29-11) all initial release

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