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  september 2003 1/24 ? main features n i2c bus control n 5 y/cvbs inputs, 3 y/cvbs outputs n 3 c inputs, 1 c output n 2 rgb/yprpb inputs, 1 rgb/yprpb output n 6 db gain on all 150 w buffer outputs n integrated 150 w buffers n video muting on all outputs n bottom clamp on all cvbs/y, average clamp on c inputs, bottom clamp on rgb, sync-tip clamp on prpb signals n bandwidth: 17 mhz n crosstalk: 50 db description the STV6618 is a highly integrated i2c bus- controlled video switch matrix, optimized for use in recordable digital video disk applications or dvd players. it is adapted to video signals with 1h and 2h formats video routings. it provides required for connections to two external devices (europe 2 scarts), internal tuners, digital encoders and recorders. tqfp44 (10 x 10 x 1.4 mm) (thin full plastic quad flat pack) order code : STV6618 STV6618 video switch matrix for dvds
STV6618 2/24 table of contents chapter 1 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 pin connections ........................................................................................................... ....... 3 1.2 pin description .......................................................................................................... ......... 4 chapter 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 absolute maximum ratings ................................................................................................ 7 2.2 thermal data .............................................................................................................. ........ 7 2.3 recommended operating conditions .................................................................................. 7 2.4 video section characteristics .............................................................................................. 8 2.5 fast blanking section characteristics ................................................................................. 9 2.6 chroma section characteristics ......................................................................................... 10 2.7 digital outputs ............................................................................................................ ........ 10 2.8 i2c bus characteristics ...................................................................................................... 1 1 chapter 3 i2c bus selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1 i2c bus addresses ............................................................................................................. 12 3.2 power-on reset: bus register initial conditions ............................................................... 15 chapter 4 input/output groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 chapter 5 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 chapter 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 chapter 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3/24 STV6618 general overview 1 general overview 1.1 pin connections figure 1: pinout diagram fbout_tv fbin_aux vdd scl sda gndd cin_tv y/cvbsin_tv digout1 cin_tun y/cvbsout_tv vccb3 r/pr/cout_tv vccb2 g/yout_tv c_gate b/pbout_tv gndb y/cvbsout_aux vccb 1 cout_aux y/cvbsout_rec vccb_rec y/cvbsin_aux r/pr/cin_aux digout5 g/yin_aux b/pbin_aux gnd2 b/pbin_enc g/yin_enc r/pr/cin_enc vcc yin_enc cin_enc decv cvbsin_enc 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 digout2 digout4 digout6 gndb_rec 11 10 9 8 7 6 5 4 3 2 1 gnd1 digout3 y/cvbsin_tun
general overview STV6618 4/24 1.2 pin description pin no. symbol description 1 y/cvbsin_tun y/cvbs input from tuner 2 digout3 digital output pin 3 3 gnd1 ground supply 1 for video inputs 4 cvbsin_enc cvbs input from encoder 5 decv video decoupling capacitor 6 cin_enc chroma input from encoder 7 yin_enc y input from encoder 8 v cc +5 v power supply for video inputs 9 r/pr/cin_enc red or pr or chroma input from encoder 10 g/yin_enc green or y input from encoder 11 b/pbin_enc blue or pb input from encoder 12 gnd2 ground supply 2 for video inputs 13 b/pbin_aux blue or pb input from auxiliary (scart2 or external cinch) 14 digout4 digital output pin 4 15 g/yin_aux green or y input from auxiliary (scart2 or external cinch) 16 digout5 digital output pin 5 17 r/pr/cin_aux red or pr or chroma input from auxiliary (scart2 or external cinch) 18 digout6 digital output pin 6 19 y/cvbsin_aux y/cvbs input from auxiliary (scart2 or external cinch) 20 vccb_rec video output recorder buffer supply pin 21 y/cvbsout_rec y/cvbs output to recorder 22 gndb_rec ground supply for recorder buffer 23 cout_aux chroma output to auxiliary (scart2 or external cinch) 24 vccb1 video output buffer supply pin 25 y/cvbsout_aux y/cvbs output to auxiliary (scart2 or external cinch) 26 gndb ground supply for video buffer 27 b/pbout_tv blue or pb output to tv (scart1 or external cinch) 28 c_gate external transistor command for bidirectinnal b/c scart i/o 29 g/yout_tv green or y output to tv (scart1 or external cinch) 30 vccb2 video buffer 31 r/pr/cout_tv red or pr or chroma output to tv (scart1 or external cinch) 32 vccb3 video output buffer supply pin 33 y/cvbsout_tv y/cvbs output to tv (scart1 or external cinch) 34 fbout_tv fast blanking output to tv (scart1) 35 fbin_aux fast blanking input from auxiliary (scart2)
5/24 STV6618 general overview 36 vdd +5 v digital power supply 37 scl i2c bus clock 38 sda i2c bus data 39 gndd digital ground supply 40 cin_tv chroma input from tv (scart1 or external cinch) 41 y/cvbsin_tv y/cvbs input from tv (scart1 or external cinch) 42 digout1 digital output pin 1 43 cin_tun chroma input from tuner 44 digout2 digital output pin 2 figure 2: STV6618 input/output diagram pin no. symbol description scart1 tv r/pr/cout_tv g/yout_tv b/pbout_tv fbout_tv y/cvbsout_tv y/cvbsin_tv tuner y/cvbsin_tun encoder r/pr/cin_enc g/yin_enc b/pbin_enc cvbsin_enc cin_enc yin_enc recorder y/cvbs_rec scart2 r/pr/cin_aux g/yin_aux b/pb_aux fbin_aux y/cvbsin_aux cout_aux cout_rec cin_tv transistor c_gate STV6618 (tqfp 44) digout1 digout2 y/cvbsout_aux cin_tun digout3 digout4 digout5 digout6 (auxiliary)
general overview STV6618 6/24 figure 3: STV6618 block diagram y/cvbsin_tun y/cvbsin_tv y/cvbsin_aux cvbsin_enc g/yin_aux r/pr/cin_aux b/pbin_aux g/yin_enc r/pr/cin_enc b/pbin_enc yin_enc cin_tv cin_enc mute 0 db y/cvbsout_rec STV6618 recorder mute 6 db y/cvbsout_tv scart1 mute 6 db y/cvbsout_aux scart2 mute 6 db r/pr/cout_tv mute 6 db g/yout_tv scart1 scart1 mute 6 db b/pbout_tv scart1 y/cvbs_tun y/cvbs_tv y/cvbs_aux cvbsin_enc yin_enc cin_tv cin_enc g/yin_enc g/yin_aux r/pr/cin_aux b/pbin_aux r/pr/cin_enc b/pbin_enc fbout_tv scl fbin_aux 0v 5v sda c_gate i 2c bus cvbsin_tun y/cvbsin_tv y/cvbsin_aux cvbsin_enc yin_enc mute 6 db cout_aux y/cvbsin_aux cvbsin_enc yin_enc cvbsin_tun y/cvbsin_tv cvbsin_enc yin_enc cin__tv cin_enc cin_enc r/pr/cin_aux r/pr/cin_enc g/yin_aux g/yin_enc b/pbin_aux b/pbin_enc fbin_aux cin_tun cin_tun cin__tun digout1 digout2 digout3 digout4 digout5 digout6 bo. clamp bo. clamp bo. clamp bo. clamp bo. clamp av. clamp av. clamp av. clamp bo. clamp bo. clamp sync sep. bot/sync/av. bo. / sync sync sep. bot/sync/av. bo. / sync
7/24 STV6618 electrical characteristics 2 electrical characteristics 2.1 absolute maximum ratings 2.2 thermal data 2.3 recommended operating conditions t amb = 25 c, v ccv = 5 v, v dd = 5 v, r out_vrec = 4.7 k w , r out_vbuf = 150 w , unless otherwise specified. output impedances of sources: r gv = 75 w . symbol parameter value unit v dd digital section 6v v ccv video section 6v v i voltage at pin 1 to gnd - video pins - bus pins, digout1,2,3 and c_gate 0, 5.5 0, 5.5 v v digout4-5-6 voltage at pin digout4-5-6 0, 13 v v esd maximum esd voltage allowed. 100 pf capacitor discharged through 1.5 k w serial resistor (human body model) 4 kv t oper operating ambient temperature 0, +70 c t stg storage temperature -20, +150 c symbol parameter value unit r thja junction-ambient thermal resistance (maximum) on a single-layer board 70 c/w symbol parameter test conditions min. typ. max. unit supply voltages v dd digital supply voltage 4.75 5.00 5.25 v v ccv video operating supply voltage 4.75 5.00 5.25 v active mode (all channels on) i dd digital supply current v dd = 5 v, 3.5 5.0 6.5 ma i ccv total video supply current v ccv = 5 v, no load 31 45 58 ma standby mode (all channels off) i dd digital supply current v dd = 5 v 3.0 4.5 6.0 ma i ccvstd total video supply current v cc = 5 v 0.5 1.0 ma
electrical characteristics STV6618 8/24 2.4 video section characteristics t amb = 25 c, v ccv = 5 v, v dd = 5 v, r out_vrec = 4.7 k w , r out_vbuf = 150 w , unless otherwise specified. output impedances of sources: r gv = 75 w . symbol parameter test conditions min. typ. max. unit v dcin_bot dc input level bottom sync pulse 1.9 2.0 2.2 v i clamp_bot clamping current, bottom clamp at v dcin - 400 mv 123ma i leak input leakage current v in = v dcin + 1 v, bottom clamp input 15 a v dcin_ysync dc input level y input, yprpb mode, black level 2.2 2.3 2.5 v v dcin_sync dc input level sync clamp input (pr,pb) sync signal on y input 2.9 3.0 3.1 v i clamp_sync max. clamping current during sync clamp sync clamp input (pr,pb) at v dcin - 400 mv 100 a c in input capacitance 2 pf v in maximum input signal y/cvbs, rgb pr, pb 1.5 1.0 v pp dyn dynamic output signal y/cvbs, rgb pr, pb 3 2 v pp bw bandwidth at -3 db y/cvbs out rgb out pr/pb out v in = 0.7 v pp v in = 0.7 v pp v in = 0.7 v pp 14 14 14 17 17 17 mhz flatness video band gain spread (15 khz to 5 mhz) y/cvbs out rgb out pr/pb out v in = 1 v pp v in = 1 v pp v in = 0.7 v pp 0.5 0.5 0.5 db cti crosstalk isolation between input channel v in = 1 v pp at 4.43 mhz on 1 point 54 1 60 db cto crosstalk isolation between output channel v in = 1 v pp at 4.43 mhz on 1 point, r load = 150 w 50 1 55 db r out output resistance 5 10 w g0v gain at video outputs (0 db), recorder output v in = 1 v pp and gain = 0 db at 1mhz -0.5 0.0 0.5 db g6v gain at video outputs (6 db) v in = 1 v pp and gain = 6 db at 1mhz 5.5 6.0 6.5 db rgbmatch gain matching between rgb outputs v in = 0.7 v pp and gain = 6 db at 1mhz -0.3 0.3 db dc outzy/cvss dc output voltage, tv and aux y/cvbs outputs bottom sync pulse 2 mute 2 0.32 0.57 0.40 0.60 0.43 0.67 v dc outrec dc output voltage, recorder y/cvbs output bottom sync pulse 2 mute 2 1.2 1.3 1.3 1.4 1.4 1.5 v
9/24 STV6618 electrical characteristics 2.5 fast blanking section characteristics dc outrgb dc output voltage, rgb outputs black level 2 mute 2 0.45 0.50 0.60 0.60 0.70 0.70 v dc outyout dc output voltage, tv y output (g/ yout_tv, yprpb mode) bottom sync pulse 2 mute 2 0.50 0.45 0.60 0.60 0.70 0.70 v dc outprpb dc output voltage, prpb outputs black level 2 mute 2 1.4 1.4 1.5 1.5 1.6 1.6 v dphi differential phase, y/cvbs v in = 1 v pp at 4.43 mhz 0.2 2.5 deg. dg differential gain, y/cvbs v in = 1 v pp at 4.43 mhz 0.3 5 % mute mute suppression v in = 1 v pp at 5 mhz on 1 point -55 db lnl luminance non-linearity 0.3 3 % vsn video signal-to-noise ratio 3 75 db 1. minimum crosstalk values estimated during qualification phase, based on st evaluation board measurement, tqfp44 package soldered on board. 2. measured at ic output pin. 3. signal-to-noise = 20log (voutblack-to-white = 0.7 v pp / vnoise(mvrms) weighted ccir 567) symbol parameter test conditions min. typ. max. unit input mode fb low/high input low/high level threshold 0.4 0.7 0.9 v i in input current 210 a output mode fb low output low level r load = 150 w 0.5 v fb high output high level r load = 150 w 3.0 3.4 3.8 v fb del fast blanking rgb delay at 50% on digital rgb transients, at 2 v on fb rise transient, at 1 v on fb fall, c load = 10 pf maximum 15 ns fb trans fb transitions at fb output rise time fall time c load = 10 pf maximum between 10% and 90% between 90% and 10% 10 10 ns symbol parameter test conditions min. typ. max. unit
electrical characteristics STV6618 10/24 2.6 chroma section characteristics t amb = 25 c, v ccv = 5 v, v dd = 5 v, r out_vrec = 4.7 k w , r out_vbuf = 150 w, unless otherwise specified. output impedances of sources: r gv = 75 w . 2.7 digital outputs t amb = 25 c, v ccv = 5 v, v dd = 5 v. symbol parameter test conditions min. typ. max. unit v dcin dc input level 2.9 3.0 3.1 v r in input resistance 30 50 k w c in input capacitance 2 pf v in max input signal 1.0 v pp dyn dynamic output signal 2.0 v pp dc out dc output voltage aux c output no chroma input signal 1 1. measured at ic output pin. 1.4 1.5 1.6 v cbw chroma bandwidth v in = 1 v pp at -3 db 10 15 mhz cti crosstalk isolation between input channel v in = 1 v pp at 4.43 mhz, on one input 54 2 2. minimum crosstalk values estimated during qualification phase, based on st evaluation board measurement, tqfp44 package soldered on board. 60 db cto crosstalk isolation between output channel v in = 1 v pp at 4.43 mhz, on one input, r load = 150 w 50 2 55 db r out output resistance 5 10 w g6c gain at chroma outputs v in = 1 v pp and gain = 6 db at 1mhz 5.5 6.0 6.5 db mute mute suppression v in = 1 v pp at 4.43 mhz, on one input -55 db ctoydel chroma to luma delay, source y/c v in = v pp at 4.43 mhz 20 ns symbol parameter test conditions min. typ. max. unit c_gate_h pull-up resistor value to vccb3 16 20 24 k w c_gate_l output low level i in = 0 ma i in = 1 ma 0.3 0.7 v c_gate_h output high level r load = 20 k w v dd v digout1-2-3 load external pull-up resistor value to vdd 10 k w digout1-2-3 low output low level, digout1-2-3 r load = 10 k w 0.7 v digout1-2-3 middle output middle level, digout1-2-3 r load = 10 k w 2.2 v digout1-2-3 high output high level,digout1-2-3 r load = 10 k w, opened collector output v dd v digout4-5-6 low output low level, digout4-5-6 i load = 2 ma 0.7 v digout4-5-6 high output high level, digout4-5-6 opened collector output 13 v
11/24 STV6618 electrical characteristics 2.8 i2c bus characteristics t amb = 25 c, v ccv = 5 v, v dd = 5 v note: the device can also operate at 400 khz and can interface with +3.3 v or + 5 v logic levels. symbol parameter test conditions min. typ. max. unit scl v il low level input voltage -0.3 1.5 v v ih high level input voltage 2.3 5.5 v i li input leakage current v in = 0 to 5.5 v -10 0 10 s sda v il low level input voltage -0.3 1.5 v v ih high level input voltage 2.3 5.5 v i li input leakage current v in = 0 to 5.5 v -10 0 10 s c i input capacitance 10 pf t r input rise time 1.5 v to 3 v 1 s t f input fall time 3 v to 1.5 v 300 ns v ol low level output voltage i ol = 3 ma 0.4 v t f output fall time 3 v to 1.5 v 250 ns c l load capacitance 400 pf timing t low clock low period 4.7 s t high clock high period 4 s t su,dat data setup time 250 ns t hd,dat data hold time 0 340 ns t su,sto setup time from clock high to stop 4 s t buf start setup time following a stop 4.7 s t hd,sta start hold time 4 s t su,sta start setup time following clock low to high transition 4.7 s figure 4: i2c bus timing t buf t low t high t hd,sta t r t f t su,sta t hd,dat t su,dat t su,sto sda scl sda
i2c bus selection STV6618 12/24 3 i2c bus selection data transfers follow the usual i2c format; i.e. after the start condition (s), a 7-bit slave address is sent, followed by an eight-bit data direction bit (w). an 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. the ics i2c bus decoder enables the automatic incrementation mode in write mode. string format write only mode (s = start condition, p = stop condition, a = acknowledge) read only mode slave address auto increment mode 3.1 i2c bus addresses write address: 1001 0100 = 94(hex) input signal summary (write mode) s slave address 0 a sub-address a data a p s slave address 1 a data a p addressa7a6a5a4a3a2a1 value1001010 s slave address 0 a sub-address a data0 a data1 a .... datan a p sub-address sub-address +1 sub-address + n reg addr (hex) data d7 d6 d5 d4 d3 d2 d1 d0 y/cvbs and c output selection 00 digout6 not used tv y/cvbs output selection recorder y/cvbs output selection 01 digout5 not used auxiliary c output selection auxiliary y/cvbs output selection rgb/yprpb & fast blanking selection 02 rgb/yprpb high impedance state rgb or yprpb or c mode selection auxiliary or encoder selection fast blanking selection digital outputs 03 digout4 digout3 digout2 control digout1 control c_gate control
13/24 STV6618 i2c bus selection note: unused data must be set to 0. standby 04 tv output standby aux chroma output standby aux cvbs output standby rec output standby aux input disable tv input disable tun input disable enc input disable reg. addr (hex) description bits data comments d7 d6 d5 d4 d3 d2 d1 d0 00 recorder y/cvbs output selection 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 mute yin_enc cvbsin_enc y/cvbsin_aux y/cvbsin_tv ycvbsin_tun not allowed not allowed tv y/cvbs output selection 2 x x x x x x x x x x x x 0 0 1 1 0 1 0 1 x x x x x x x x x x x x y/cvbs_aux yin_enc cvbsin_enc mute digout6 control 1 0 1 x x x x x x x x x x x x x x 0 = low level 1 = high level 01 aux (scart2) y/cvbs output selection 3 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 y/cvbsin_tv yin_enc cvbsin_enc ycvbsin_tun mute not allowed not allowed not allowed aux (scart2) chroma output selection 2 x x x x x x x x x x x x 0 0 1 1 0 1 0 1 x x x x x x x x x x x x mute cin_enc cin_tv cin_tun digout5 control 1 0 1 x x x x x x x x x x x x x x 0 = low level 1 = high level reg addr (hex) data d7 d6 d5 d4 d3 d2 d1 d0
i2c bus selection STV6618 14/24 reg. addr (hex) description bits data comments d7 d6 d5 d4 d3 d2 d1 d0 02 fast blanking output control 2 x x x x x x x x x x x x x x x x x x x x x x x x 0 0 1 1 0 1 0 1 fbin_aux fb forced to low level fb forced to high level not allowed rgb/yprpb output selection 2 x x x x x x x x x x x x x x x x 0 0 1 1 0 1 0 1 x x x x x x x x rgb/yprpb_aux rgb/yprpb_enc cin_enc (pin 6) at r/pr/cout_tv, b/pbout & g/yout muted rgb/yprpb mute rgb or yprpb or c selection 2 x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 x x x x x x x x x x x x x x x x rgb mode selection, bottom clamp at rgb inputs, aux. input selected rgb mode selection, bottom clamp at rgb inputs, enc. input selected cin_aux (pin 17)selected, average clamp at r/pr/cin_aux input, gin_aux (bottom clamp) selected, bin_aux (bottom clamp) selected cin_enc (pin 9)selected, average clamp at r/pr/cin_enc input, gin_enc (bottom clamp) selected, bin_enc (bottom clamp) selected yprpb mode selection, sync pulse clamp at pr pb inputs, black clamp at y input, aux. input selected yprpb mode selection, sync pulse clamp at pr pb inputs, black clamp at y input, enc. input selected yprpb mode selection, delayed sync pulse clamp at pr pb inputs, black clamp at y input, aux. input select yprpb mode selection, delayed sync pulse clamp at pr pb inputs, black clamp at y input, enc. input select rgb/yprpb control 2 0 0 1 0 1 x x x x x x x x x x x x x x x x x x x rgb/yprpb outputs active rgb/yprpb outputs high imp state red output active, green and blue high imp. state
15/24 STV6618 i2c bus selection 3.2 power-on reset: bus register initial conditions power-on reset is active when supply v dd < 3.5 v. non-significant bits (x) are pre-set to 0. reg. addr (hex) description bits data comments d7 d6 d5 d4 d3 d2 d1 d0 03 c_gate output control 1 x x x x x x x x x x x x x x 0 1 low level high level digout1 2 x x x x x x x x x x x x x x x 0 1 1 x 0 1 x x x low level mid level high level digout2 2 x x x x x x x x x 0 1 1 x 0 1 x x x x x x x x x low level mid level high level digout3 2 x x x 0 1 1 x 0 1 x x x x x x x x x x x x x x x low level mid level high level digout4 control 1 0 1 x x x x x x x x x x x x x x 0 = low level 1 = high level 04 enc inputs 1 x x x x x x x x x x x x x x 0 1 inputs active inputs disabled tun inputs 1 x x x x x x x x x x x x 0 1 x x inputs active inputs disabled tv inputs 1 x x x x x x x x x x 0 1 x x x x inputs active inputs disabled aux inputs 1 x x x x x x x x 0 1 x x x x x x inputs active inputs disabled rec outputs 1 x x x x x x 0 1 x x x x x x x x y/cvbsout_rec outputs on y/cvbsout_rec outputs off aux outputs 1 x x x x 0 1 x x x x x x x x x x y/cvbsout_aux outputs on y/cvbsout_aux outputs off cout_aux output 1 x x 0 1 x x x x x x x x x x x x cout_aux outputs on cout_aux outputs off (high imped.) tv outputs 1 0 1 x x x x x x x x x x x x x x tv video outputs on tv video outputs off full stop 8 11111111 only i2c bus supplied, and digital outputs reg. addr (hex) data comments d7 d6 d5 d4 d3 d2 d1 d0 00 00000000 rec. cvbs output muted, tv cvbs output to aux. cvbs input, digital output low level 01 00000000 aux. cvbs output to tv cvbs input, aux. chroma output muted, digital output low level 02 00000000 fb output to aux. fb input, tv rgb output to aux. rgb inputs, rgb outputs active 03 0 0 0 0 0 0 0 0 c_gate output low level, digout outputs low level 04 0 0 0 0 0 0 0 0 all inputs outputs active
input/output groups STV6618 16/24 4 input/output groups figure 5: c_gate logic output (pin 28) figure 6: video outputs (pins 23, 25, 27, 29, 31 and 33) figure 7: ycvbsout_rec recorder output (pin 21) v dd 5v 18 k w 50 w v dd 5v protected pad v ccb1,2,3 protected pad ib v ccb1,2,3 v ccb1,2,3 v ccb_rec 5v protected pad v ccb_rec 5v figure 8: fast blanking inputs (pin 35) figure 9: i2c bus scl i/o (pin 37) figure 10: fast blanking output (pin 34) v ccb3 protected pad v dd 5v tri vdd_float 10 k w v dd 5v protected pad v dd v ccb3 v ccb3 protected pad
17/24 STV6618 input/output groups figure 11: bottom clamped video inputs (pins 1, 4, 7, 19 and 41) figure 12: digout 1, 2 and 3 (pins 42, 44 and 2) figure 13: digout 4, 5 and 6 (pins 14, 16 and 18) 15 k w v cc 5v tri v cc 5v protected pad 5k w 2v + v be float_bus v dd 5v float_digout v dd 5v figure 14: average clamped video inputs (pins 6, 40 and 43) figure 15: decv (pin 5) figure 16: i2c bus sda i/o (pin 38) 25 k w v cc 5v v cc 5v protected pad 5k w 25 k w tri protected pad v cc 5v protected pad 10 k w 40 k w v cc 5v v cc 5v vdd_float acknowledge 10 k w v dd 5v protected pad
input/output groups STV6618 18/24 figure 17: r/pr/c inputs (pins 9 and 17) figure 18: g/y inputs (pins 10 and 15) figure 19: b/pb inputs (pins 11 and 13) v cc 5v protected pad 50 k w 5k w v cc 5v botclamp v cc 5v protected pad 5k w v cc 5v botclamp 15 k w 2v + v be 20 k w sepsel tri v cc 5v protected pad 5k w v cc 5v botclamp 15 k w tri 2v + v be
19/24 STV6618 input/output groups figure 20: power supply connection these symbols represent some huge diode and zener-like components used for esd protection of the device. they are not supposed to be paths for any current in normal operation mode. vccb3 vccb2 vccb1 vccb_rec 32 30 24 20 5v float_vidouts 3 8 gnd1 12 gnd2 39 gndd 36 v dd v cc 5v 5v float_v dd 12 v float_digouts 26 gndb 22 gndb_rec
application diagrams STV6618 20/24 5 application diagrams figure 21: yprpb application r55 r40 75 j5 y j6 pb r46 10k r41 75 aux inputs s-vhs y . . c r56 12v vcc r53 c46 100n c41 100n t2 npn c44 100n j12 pb r30 to r35: expected loads on decoder outputs r35 75 j3 y/cvbs c25 100n r32 75 r34 75 j2 c tuner y/cvbs j11 y j9 y/cvbs enc y r47 10k r50 10k enc pr c48 100n c29 100n c30 100n r49 10k c28 10 r36 75 enc pb dout 2 j7 y/cvbs c32 100n c42 10 c39 100n r43 75 c36 1 enc cvbs c26 100n r54 r39 75 r51 j8 c c43 100n scl dout 6 vdd j10 pr vcc rec y/cvbs vccb c40 47n tuner c j1 y/cvbs r37 75 enc c j4 pr dout 4 c35 100n r44 75 dout 1 aux outputs vccb c33 100n enc y tv outputs r30 75 r48 10k c37 100n c27 100n vccb r33 75 c34 100n r38 75 r45 10k sda c38 100n rec c tv inputs r31 75 r42 470 c31 10 dout 5 dout 3 c47 1 all grounds must be linked un der the ic r52 c45 100n u3 STV6618 4 8 6 7 5 9 10 11 3 41 40 12 19 14 17 16 15 18 13 20 21 22 25 24 23 30 33 31 32 29 28 27 34 35 36 37 38 39 42 1 44 43 2 26 cvbsin_enc vcc cin8enc yin8enc decv r/pr/cin_enc g/yin_enc b/pbin_enc gnd1 y/cvbsin_tv cin_tv gnd2 y/cvbsin_aux digout4 r/pr/cin_aux digout5 g/yin_aux digout6 b/pbin_aux vccb_rec y/cvbsout_rec gndb_rec y/cvbsout_aux vccb1 cout_aux vccb2 y/cvbsout_tv r/pr/cout_tv vccb3 g/yout_tv c_gate b/pb_out_tv fbout_tv fbin_aux vdd scl sda gndd digout1 y/cvbsin_tun digout2 cin_tun digout3 gndb
21/24 STV6618 application diagrams figure 22: 2 scart / rgb signal application enc c c24 100n r8 75 c14 100n tuner c r1 75 r10 75 r6 75 r28 c17 100n dout 1 c1 100n r25 vcc enc b dout 4 r11 75 dout 5 c4 10 r19 10k vccb enc r all grounds must be linked un der the ic vcc c22 100n c12 100n c13 100n c23 100n r23 10k r9 75 c18 10 r24 r4 75 c3 100n sda r22 10k r2 75 q2 jfet n aux1 scart 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 r13 to r18: expected loads on decoder outputs scl vdd c11 100n c15 100n c20 100n r17 4k7 rec y/cvbs u1 STV6618 4 8 6 7 5 9 10 11 3 41 40 12 19 14 17 16 15 18 13 20 21 22 25 24 23 30 33 31 32 29 28 27 34 35 36 37 38 39 42 1 44 43 2 26 cvbsin_enc vcc cin8enc yin8enc decv r/pr/cin_enc g/yin_enc b/pbin_enc gnd1 y/cvbsin_tv cin_tv gnd2 y/cvbsin_aux digout4 r/pr/cin_aux digout5 g/yin_aux digout6 b/pbin_aux vccb_rec y/cvbsout_rec gndb_rec y/cvbsout_aux vccb1 cout_aux vccb2 y/cvbsout_tv r/pr/cout_tv vccb3 g/yout_tv c_gate b/pb_out_tv fbout_tv fbin_aux vdd scl sda gndd digout1 y/cvbsin_tun digout2 cin_tun digout3 gndb c5 100n r27 dout 6 r3 75 r21 10k c16 47n c10 100n 12v r20 10k dout 3 tuner y/cvbs dout 2 r26 c2 100n c21 100n c9 100n c7 10 vccb r12 75 r29 enc y tv1 scart 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 r5 75 enc g c19 100n r7 75 q1 jfet n enc cvbs c8 100n r18 10k c6 100n
package mechanical data STV6618 22/24 6 package mechanical data figure 23: 44-pin thin quad flat package a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 b c l1 l k 0.10m m .004 seating plane
23/24 STV6618 revision history 7 revision history the following table summarizes the modifications applied to this document. revision description date 1.0 first issue 24 april 2001 new pinout proposal, to improve connection to tv scart. slight correction of electrical parameters (changed value in bold). correction of digout1-2-3 i2c control specification (changed value in bold) 27 april 2001 new pinout proposal, to improve connection to scarts. application layout hypothesis: 1 layer pcb, ic on lower side (copper side), scart on upper side 7 may 2001 application diagrams added. vdcin chroma section: 3.0v instead of 2.3v previously. vdcin , video section, prpb: 3.0v instead of 2.3v previously 11 may 2001 add fast blanking section electrical characteristics. update application schematic diagrams 7 june 2001 1.1 addition of section 4: input/output groups on page 16 . 21 june 2001 1.2 document reformatted. replaced figure 22: 2 scart / rgb signal application on page 21 . 6 july 2001 1.3 cin = 1 vpp changed to "vin = 1 vpp in cbw parameter in section 2.6 . symbols for a pnp, npn and current source as well as their connections added to figure 17 . 2 oct 2001 1.4 update of crosstalk and dc output voltage data in section 2.4 and section 2.6 . modification of register 2 data in section 3.1 . replaced figure 21 and figure 22 . 10 oct 2001 1.5 update of crosstalk data and output voltage values in section 2.4 and section 2.6 . updated figure 3 and figure 22 . 26 oct 2001 1.6 chroma output gain (g6c) parameters updated in section 2.6 . 14 jan 2002 1.7 addition of minimum/maximum values for certain parameters in section 2: electrical characteristics . document upgraded to datasheet status. 24 may 2002 1.8 modification of bandwidth parameter (17 mhz) and figure 3 . 24 sept. 2002
revision history STV6618 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pr eviously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com


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