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publication number am29f004b_00 revision e amendment 4 issue date may 9, 2006 am29f004b data sheet this product has been retired and is not recommend ed for designs. please contact your spansion representative for alternates. availability of this document is retained fo r reference and historical purposes only. the following document contains inform ation on spansion memory products. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary. for more information please contact your local sales office for additi onal information about spansion memory solutions.
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data sheet publication# am29f004b_00 revision: e amendment: 4 issue date: may 9, 2006 this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. am29f004b 4 megabit (512 k x 8-bit) cmos 5.0 volt-only boot sector flash memory distinctive characteristics ? 5.0 volt single power supply operation ? minimizes system-level power requirements ? high performance ? access times as fast as 70 ns ? manufactured on 0.32 m process technology ? ultra low power consumption (typical values at 5 mhz) ? 20 ma typical active read current ? 30 ma typical program/erase current ? 1 a typical standby mode current ? flexible sector architecture ? one 16 kbyte, two 8 kbyte, one 32 kbyte, and seven 64 kbyte sectors ? supports full chip erase ? sector protection features: a hardware method of locking a sector to prevent any program or erase operations within that sector sectors can be locked in-system or via programming equipment temporary sector unprotect feature allows code changes in previously locked sectors ? top or bottom boot block configurations available ? minimum 1,000,000 write cycle guarantee per sector ? package option ? 32-pin plcc ? compatible with jedec standards ? pinout and software compatible with single- power supply flash ? superior inadvertent write protection ? embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies data at specified addresses ? erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion ? 20-year data retention at 125 c this product has been retired and is not recommended for desi gns. please contact your spansion representative for alternates. availability of this document is retained for reference and historical purposes only.
2 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet general description the am29f004b is a 4 mbit, 5.0 volt-only flash memory device organized as 524,288 bytes. the data appears on dq0?dq7. the device is offered in a 32-pin plcc package. this device is designed to be programmed in-system with the standard system 5.0 volt v cc supply. a 12.0 volt v pp is not required for program or erase operations. the device can also be programmed in standard eprom programmers. the device offers access times of up to 70 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus contention each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regu - lated voltages are provided for the program and erase operations. the am29f004b is entirely comm and set compatible with the jedec single-power-supply flash standard . commands are written to the command r egister using standard micropro - cessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and program - ming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automatical ly preprograms the array (if it is not already programmed) be fore executing the erase opera - tion. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling), or dq6 (toggle) status bits . after a program or erase cycle is completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con - tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature dis - ables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true back - ground erase can thus be achieved. the device offers a standby mode as a power-saving fea - ture. once the system places the device into the standby mode power consumption is greatly reduced. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri - cally erases all bits within a sector simultaneously via fowler- nordheim tunnelling. the data is programmed using hot elec - tron injection.
may 9, 2006 am29f004b_00 _ e4 am29f004b 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . . 8 am29f004b device bus operations ................................................8 requirements for reading array data ..................................... 8 writing commands/command sequences .............................. 8 program and erase operation status ...................................... 8 standby mode .......................................................................... 8 output disable mode ................................................................ 9 am29f004b top boot block sector addresses ...............................9 am29f004b bottom boot block sector addresses ..........................9 autoselect mode ..................................................................... 10 am29f004b autoselect codes (high voltage method) ..................10 sector protection/unprotection ............................................... 10 in-system sector protect/sector unprotect algorithms ..................11 temporary sector unprotect .................................................. 12 temporary sector unprotect operation ..........................................12 hardware data protection ...................................................... 13 low v cc write inhibit ......................................................................13 write pulse glitch protection ..........................................................13 logical inhibit ..................................................................................13 power-up write inhibit ....................................................................13 command definitions . . . . . . . . . . . . . . . . . . . . . . 13 reading array data ................................................................ 13 reset command ..................................................................... 13 autoselect command sequence ............................................ 13 byte program command sequence ....................................... 13 program operation ..........................................................................14 chip erase command sequence ........................................... 14 sector erase command sequence ........................................ 14 erase operation ..............................................................................15 erase suspend/erase resume commands ........................... 15 am29f004b command definitions .................................................16 write operation status . . . . . . . . . . . . . . . . . . . . . 17 dq7: data# polling ................................................................. 17 data# polling algorithm ...................................................................17 dq6: toggle bit i .................................................................... 18 dq2: toggle bit ii ................................................................... 18 reading toggle bits dq6/dq2 ............................................... 18 dq5: exceeded timing limits ................................................ 18 dq3: sector erase timer ....................................................... 18 toggle bit algorithm ....................................................................... 19 write operation status ................................................................... 19 absolute maximum ratings . . . . . . . . . . . . . . . . 20 maximum negative overshoot waveform ..................................... 20 maximum positive overshoot waveform ....................................... 20 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 20 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21 ttl/nmos compatible .......................................................... 21 cmos compatible .................................................................. 22 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 23 test setup ...................................................................................... 23 test specifications ......................................................................... 23 key to switching waveforms . . . . . . . . . . . . . . . 23 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 read operations .................................................................... 24 read operations timings .............................................................. 24 erase/program operations ..................................................... 25 program operation timings ........................................................... 26 chip/sector erase operation timings ............................................ 26 data# polling timings (during embedded algorithms) .................. 27 toggle bit timings (during embedded algorithms) ....................... 27 dq2 vs. dq6.................................................................................. 27 sector unlock sequence timing diagram ..................................... 28 sector relock timing diagram ...................................................... 28 sector protect/unprotect timing diagram ..................................... 29 alternate ce# controlled eras e/program operations ............ 30 alternate ce# controlled write operation timings ........................ 31 erase and programming performance . . . . . . . 32 latchup characteristics . . . . . . . . . . . . . . . . . . . 32 plcc pin capacitance . . . . . . . . . . . . . . . . . . . . 32 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 33 pl 032?32-pin plastic leaded chip carrier ......................... 33 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 34
4 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29f004b speed option v cc = 5.0 v 10% -70 -90 max access time, ns (t acc ) 70 90 max ce# access time, ns (t ce ) 70 90 max oe# access time, ns (t oe ) 30 35 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 ? dq7 sector switches data latch y-gating cell matrix address latch a0?a18
may 9, 2006 am29f004b_00 _ e4 am29f004b 5 data sheet connection diagrams 1 31 30 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a12 a15 a16 a18 v cc we# a17 dq1 dq2 v ss dq3 dq4 dq5 dq6 standard 48-pin tsop plcc
6 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet pin configuration a0?a18 = 19 addresses dq0?dq7 = 8 data inputs/outputs ce# = chip enable oe# = output enable we# = write enable v cc = +5.0 v single power supply (see product selector guide for device speed ratings and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 19 8 dq0?dq7 a0?a18 ce# oe# we#
may 9, 2006 am29f004b_00 _ e4 am29f004b 7 data sheet ordering information standard product amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup - ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29f004b t -70 j i temperature range i = industrial (?40 c to +85 c) f = industrial (?40 c to +85 c) for pb-free package e = extended (?55 c to +125 c) k = extended (?55 c to +125 c) for pb-free package package type j = 32-pin rectangular plastic leaded chip carrier (pl 032) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector device number/description am29f004b 4 megabit (512 k x 8-bit) cmos flash memory 5.0 volt-only program and erase valid combinations v cc voltage am29f004bt-70 am29f004bb-70 ji, jf 5.0 v 10% am29f004bt-90 am29f004bb-90 ji, je, jf, jk
8 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that stor e the commands, along with the address and data information needed to execute the com - mand. the contents of the regi ster serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and cont rol levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29f004b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, d in = data in, d out = data out, a in = address in note: see the sections on sector protection and temporary sector unprotect for more information. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microproce ssor read cycles th at assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command r egister contents are altered. see reading array data on page 13 for more information. refer to the ac read operations table for timing specifica - tions and to the read operations timings diagram for the timing waveforms. i cc1 in the dc characteristics table repre - sents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. see the command definitions on page 13 section for details on erasing a sector or the entire chip, or sus - pending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autosel ect mode. the system can then read autoselect codes from the in ternal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode on page 10 and autoselect command sequence sec - tions for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics on page 24 section contains timing specifica - tion tables and timing diagrams for write operations. program and erase operation status during an erase or program ope ration, the system may check the status of the operation by reading the status bits on dq7? dq0. standard read cycle timings and i cc read specifications apply. refer to write operation status on page 17 for more information, and to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, in dependent of the oe# input. the device enters the cmos standby mode when ce# pin is held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce# pin is held at v ih . the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected du ring erasure or programming, the device draws active current until the operation is completed. in the dc characteristics tables, i cc3 represents the standby current specification. operation ce# oe# we# a0?a18 dq0?dq7 read l l h a in d out write l h l a in d in cmos standby v cc 0.5 v x x x high-z ttl standby h x x x high-z output disable l h h x high-z temporary sector unprotect (see note) x x x x x
may 9, 2006 am29f004b_00 _ e4 am29f004b 9 data sheet output disable mode when the oe# input is at v ih , output from the device is dis - abled. the output pins are placed in the high impedance state. table 2. am29f004b top boot block sector addresses table 3. am29f004b bottom boot block sector addresses sector a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 x x x 64 00000h?0ffffh sa1 0 0 1 x x x 64 10000h?1ffffh sa2 0 1 0 x x x 64 20000h?2ffffh sa3 0 1 1 x x x 64 30000h?3ffffh sa4 1 0 0 x x x 64 40000h?4ffffh sa5 1 0 1 x x x 64 50000h?5ffffh sa6 1 1 0 x x x 64 60000h?6ffffh sa7 1 1 1 0 x x 32 70000h?77fffh sa8 1 1 1 1 0 0 8 78000h?79fffh sa9 1 1 1 1 0 1 8 7a000h?7bfffh sa10 1 1 1 1 1 x 16 7c000h?7ffffh sector a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 0 0 x 16 00000h?03fffh sa1 0 0 0 0 1 0 8 04000h?05fffh sa2 0 0 0 0 1 1 8 06000h?07fffh sa3 0 0 0 1 x x 32 08000h?0ffffh sa4 0 0 1 x x x 64 10000h?1ffffh sa5 0 1 0 x x x 64 20000h?2ffffh sa6 0 1 1 x x x 64 30000h?3ffffh sa7 1 0 0 x x x 64 40000h?4ffffh sa8 1 0 1 x x 0 64 50000h?5ffffh sa9 1 1 0 x x 1 64 60000h?6ffffh sa10 1 1 1 x x x 64 70000h?7ffffh
10 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet autoselect mode the autoselect mode provides manufacturer and device iden - tification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algo - rithm. however, the autoselect codes can also be accessed in-system through t he command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a1, and a0 must be as shown in auto select codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t care. when all neces - sary bits are set as requir ed, the programming equipment may then read the corresponding identifier code on dq7? dq0. to access the autoselect code s in-system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see command definitions on page 13 for details on using the autoselect mode. table 4. am29f004b autoselect codes (high voltage method) l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector protection/unprotection the hardware sector protecti on feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previo usly protected sectors. the primary method requires v id on the oe# pin only, and can be implemented either in-system or via programming equipment. figure 1, on page 11 and 2 show the algorithms and figure 16, on page 28 , figure 17, on page 28 , and figure 18, on page 29 show the timing diagrams. this method uses standard microprocessor bus cycle timing in addition to the sector unlock and sector relock sequences. for sector unpro - tect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equip - ment required v id on address pin a9 and oe#. this method is compatible with programmer r outines written for earlier 5.0 volt-only amd flash devices. publication number 22289 con - tains further details; contac t an amd representative to request a copy. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s express - flash? service. contact an amd representative for details. it is possible to determine whet her a sector is protected or unprotected. see autoselect mode on page 10 for details. description ce# oe# we# a18 to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id x l x l l 01h device id: am29f004b (top boot block) l l h x x v id x l x l h 77h l l h device id: am29f004b (bottom boot block) l l h x x v id x l x l h 7bh l l h sector protection verification l l h sa x v id x l x h l 01h (protected) 00h (unprotected)
may 9, 2006 am29f004b_00 _ e4 am29f004b 11 data sheet figure 1. in-system sector protect/sector unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a5 = 1, a1 = 1, a0 = 0 set up sector address wait 150 15 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 (requires 1 s access time) start plscnt = 1 set oe# = v id . write sector unlock sequence with command 24h wait 1 s data = 01h? set oe# = v id . write sector relock sequence. set oe# = v ih . sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt sector unprotect: write 60h to sector address with a6 = 1, a5 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 1.5 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 (requires 1 s access time) start plscnt = 1 set oe# = v id . write sector unlock sequence with command 24h wait 1 s data = 00h? last sector verified? sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt no all sectors protected? protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no no yes no yes no sector protect algorithm sector unprotect algorithm write 60h to any address with a6 = 1, a5 = 1, a1 = 1, a0 = 0 write 60h to any address with a6 = 0, a5 = 1, a1 = 1, a0 = 0 protect another sector? reset plscnt = 1 set oe# = v id . write sector relock sequence. set oe# = v ih . set oe# = v il set oe# = v ih set oe# = v ih set oe# = v il
12 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet temporary sector unprotect this feature allows temporary unprotection of previously pro - tected sectors to change data in-system. the sector unprotect mode is activated by setting the oe# pin to 12.0 volts (v id ). figure 2 shows the algorithm, and figure 16, on page 28 and figure 17, on page 28 show the timing dia - grams, for this feature. while oe# is at v id , the sector unlock sequence is written to the devi ce. after the sector unlock sequence is written, the oe# pin is taken back to v ih . the device is now in the temporary sector unprotect mode. while in this mode, formerly protected sectors can be pro - grammed or erased by select ing the appropriate sector address during programming or erase operations. either sector erase or chip erase operations can be performed in this mode. byte program operations require only two cycles, while sector and chip erase operations only require four cycles. refer to the command definitions table. exiting the temporary sector unprotect mode is accomplished by either removing v cc from the device or by taking oe# back to v id and writing the sector relock sequence. after writing the sector relock sequence, the oe# pin is taken back to v ih and all previously protec ted sectors are protected again. figure 2. temporary sector unprotect operation write the three-cycle unlock sequence with com- mand 20h (figure 16) perform erase or program operations oe# = v ih temporary sector unprotect completed (note 2) oe# = v ih (note 1) notes: 1. all protected sectors unprotected. 2. all previously pr otected sectors are protected once again. start oe# = v id oe# = v id write the two-cycle sector relock sequence (fig- ure 17)
may 9, 2006 am29f004b_00 _ e4 am29f004b 13 data sheet hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might oth - erwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pr otects data during v cc power-up and power-down. the command register and all internal pro - gram/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept co mmands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appro - priate timing diagrams in ac characteristics on page 24 . reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase su spend mode. th e system can read array data using the standa rd read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see reset command for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset command section, next. see also ?requirements for reading array data? in the device bus operations on page 8 section for more informa - tion. the read operations table provides the read parameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once pro - gramming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect comma nd sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command seque nce allows the host system to access the manufacturer and devices codes, and deter - mine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h or retrieves the manufacturer code. a read cycle at address xx01h returns the device code. a read cycle containing a se ctor address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to t he sector address tables for valid sector addresses. the system must write the rese t command to ex it the autose - lect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write
14 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet cycles, followed by the program set-up command. the program address and data are written next, which in turn ini - tiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the programmed cell margin. (note that if the device is in the temporary sector unprotect mode, the byte program command sequence only requires two cycles.) the command definitions table shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system c an determine the status of the program operation by using dq7 or dq6. see write operation status on page 17 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. the sector erase command sequence should be reinitiate d once the device returns to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1 , or cause the data# polling algorithm to indicate the oper - ation was successful. howeve r, a succeeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 ?. note: see the appropriate command definitions table for program command sequence. figure 3. program operation chip erase command sequence chip erase is a six-bus-cycl e operation. t he chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm autom atically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. (note that if the device is in the temporary sector unprotect mode, the chip erase command sequen ce only requires four cycles.) the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. the system can determine the st atus of the erase operation by using dq7, dq6, or dq2. see write operation status on page 17 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 4, on page 15 illustrates the algorithm for the erase operation. see the erase/program operations on page 25 for parameters, and to figure 12, on page 26 for timing waveforms. sector erase command sequence sector erase is a six-bus-cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by t he address of the sector to be erased, and the sector erase command. (note that if the device is in the temporary sector unprotect mode, the sector erase command sequen ce only requires four cycles.) the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm auto - matically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is wr itten, a sector erase time- out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time betwe en these additiona l cycles must be less than 50 s, otherwise the last address and command might not be accepted, and eras ure may begin. it is recom - mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
may 9, 2006 am29f004b_00 _ e4 am29f004b 15 data sheet sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer timed out. (see dq3: sector erase timer on page 18 .) the time-out begins from t he rising edge of the final we# pulse in the command sequence. once the sector erase operation begins, only the erase suspend command is valid. all other commands are ignored. the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determi ne the status of the erase operation by using dq7, dq6, or dq2. refer to write oper - ation status on page 17 for information on these status bits. figure 4 illustrates the algorithm for the erase operation. refer to the erase/program operations on page 25 for parameters, and to the sector erase operations timing diagram for timing waveforms. note: 1. see the appropriate command definitions table for erase command sequence. 2. see dq3: sector erase timer on page 18 for more information. figure 4. erase operation erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo - rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-sus - pended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to deter - mine if a sector is actively erasing or is erase-suspended. see write operation status on page 17 for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-sus - pended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status on page 17 for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence on page 13 for more information. the system must write the erase resume command (address bits are don?t care ) to exit the erase suspend mode and continue the sector erase oper ation. further writes of the resume command are ignored. another erase suspend command can be written after the device resumes erasing. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
16 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a18?a13 uniquely select any sector. sa+ = the sector address must be asserted in combination with a0 = 0, a1 = 1, a5 = 1, and a6 = 0 (for protect) or 1 (for unprotect). notes: 1. see ta b l e 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or aut oselect data, all bus cycles are write operations. 4. address bits a18?a11 are don?t cares for unlock and command cycles, except when pa or sa is required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. see autoselect command sequence on page 13 for more information. 9. to activate the sequence, oe# must be at v id . 10. the sector relock command in the second cycle may be written as either 00h or f0h. 11. the system may read and progra m in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase sus - pend mode. table 5. am29f004b command definitions command sequence (note 1) cycles bus cycles (notes 2?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id, top boot block 4 555 aa 2aa 55 555 90 x01 77 device id, bottom boot block 4 555 aa 2aa 55 555 90 x01 7b sector protect verify (note 8) 4 555 aa 2aa 55 555 90 (sa) x02 00 01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 temporary sector unprotect mode (note 9) enter tsu mode 3 555 aa 2aa 55 555 20 program 2 xxx a0 pa pd sector erase 4 xxx 80 xxx aa xxx 55 sa 30 chip erase 4 xxx 80 xxx aa xxx 55 555 10 sector unlock (note 9) 3 555 aa 2aa 55 555 24 sa+ 60 sa+ 60 sa+ 40 sector relock (notes 9, 10) 2 xxx 90 xxx 00
may 9, 2006 am29f004b_00 _ e4 am29f004b 17 data sheet write operation status the device provides several bits to determine t he status of a write operation: dq2, dq 3, dq5, dq6, and dq7. ta b l e 6 on page 19 and the following subsections describe the functions of these bits. dq7 and dq6 each offer a method for deter - mining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of th e datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is com - plete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a pro - tected sector, data# polling on dq7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling pro - duces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device en ters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sec - tors, and ignores the selected sectors that are protected. when the system detects dq 7 changes from the comple - ment to true data, it can re ad valid data at dq7?dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. the data# polling timings (during embedded algorithms) figure in the ac characteristics on page 24 section illustrates this. ta b l e 6 on page 19 shows the outputs for data# polling on dq7. figure 5, on page 17 shows the data# polling algorithm. notes: 1. va = valid address for progra mming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
18 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protec ted, dq6 toggles for approxi - mately 100 s, then returns to reading array data. if not all selected sectors are protec ted, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 6 for the toggle bit algo - rithm, and to the toggle bit timings figure in the ?ac characteristics? section for the timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii . dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system re ads at addresses within those sectors that were selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether t he sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase sus - pend, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to ta b l e 6 on page 19 to compare outputs for dq2 and dq6. figure 6, on page 19 shows the toggle bit algorithm in flow - chart form, and the section dq2: toggle bit ii on page 18 explains the algorithm. see also the dq6: toggle bit i on page 18 subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6, on page 19 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to deter - mine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, t he system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device completed the program or erase opera - tion. the system can read arra y data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system deter - mines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the devi ce successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation su ccessfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggli ng and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginn ing of the algorithm when it returns to determine the status of the operation (top of figure 6, on page 19 ). dq5: exceeded ti ming limits dq5 indicates whether the program or erase time exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may app ear if the system tries to program a 1 to a location that is previously programmed to 0 . only an erase operation can change a ?0? back to a 1 . under this condition, the device halts the operation, and when the operation exceeds the timing limits, dq5 produces a 1 . under both these conditions, th e system must issue the reset command to return the devi ce to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase opera - tion started. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when th e time-out is complete, dq3 switches from 0 to 1 . the system may ignore dq3 if the system can guarantee that the time between additional sector
may 9, 2006 am29f004b_00 _ e4 am29f004b 19 data sheet erase commands is always less than 50 s. see also the sector erase command sequence on page 14 section. after the sector erase command sequence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the device accepts the command sequence, and then read dq3. if dq3 is 1 , the internally con - trolled erase cycle started; all further commands (other than erase suspend) are ignored until the erase operation is com - plete. if dq3 is 0 , the device accepts additional sector erase commands. to ensure the command was accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status chec k, the last command might not have been accepted. ta b l e 6 on page 19 shows the outputs for dq3. table 6. write operation status notes: 1. dq7 and dq2 require a valid addres s when reading status information. refer to t he appropriate subsection for further details. 2. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 18 for more information. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. figure 6. toggle bit algorithm (notes 1, 2) (note 1) operation dq7 (note 1) dq6 dq5 (note 2) dq3 dq2 (note 1) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
20 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . . . . . . ?55 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . ?2.0 v to +7.0 v a9 , oe# (note 2) . . . . . . . . . . . . . . . . . . . . ?2.0 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +7.0 v output short circuit current (note 3) . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7, on page 20 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8, on page 20 . 2. minimum dc input voltage on pins a9 and oe# is ?0.5 v. during voltage transitions, a9 and oe# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7, on page 20 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +13.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the devi ce to absolute maximum rating con - ditions for extended periods ma y affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . . . . . . ?55c to +125c v cc supply voltages v cc for 5% devices. . . . . . . . . . . . . . . .+4.75 v to +5.25 v v cc for 10% devices. . . . . . . . . . . . . . . . .+4.5 v to +5.5 v operating ranges define those limits between which the func - tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 7. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 8. maximum positive overshoot waveform
may 9, 2006 am29f004b_00 _ e4 am29f004b 21 data sheet dc characteristics ttl/nmos compatible notes: 1. maximum i cc specifications are tested with v cc = v ccmax . 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe# input load current (note 4 ) v cc = v cc max ; a9, oe# = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il , oe# = v ih 20 30 ma i cc2 v cc active write current (notes 1, 3, 4) ce# = v il , oe# = v ih 30 40 ma i cc3 v cc standby current (note 1) ce#, oe# = v ih 0.4 1 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high voltage i oh = ?2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
22 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet dc characteristics cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v ccmax . 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. i cc active while embedded erase or embedded program is in progress. 4. not 100% tested. 5. i cc3 = 20 a max at extended temperature (>+85 c). parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, input load current (note 4 ) v cc = v cc max ; a9, oe# = 12.5 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il , oe# = v ih 20 30 ma i cc2 v cc active write current (notes 1 , 3 , 4 ) ce# = v il , oe# = v ih 30 40 ma i cc3 v cc standby current (notes 1 , 5 ) ce# = v cc 0.5 v 0.3 5 a v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage 3.2 4.2 v
may 9, 2006 am29f004b_00 _ e4 am29f004b 23 data sheet test conditions table 7. test specifications key to switching waveforms 2.7 k c l 6.2 k 5.0 v device under te s t figure 9. test setup note: diodes are in3064 or equivalent test condition 70, 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 100 pf input rise and fall times 20 ns input pulse levels 0.45?2.4 v input timing measurement reference levels 0.8, 2.0 v output timing measurement reference levels 0.8, 2.0 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
24 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet ac characteristics read operations notes: 1. not 100% tested. 2. see ta b l e 7 and figure 9, on page 23 for test specifications. parameter description speed options jedec std test setup -70 -90 unit t avav t rc read cycle time (note 1) min 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 90 ns t elqv t ce chip enable to output delay oe# = v il max 70 90 ns t glqv t oe output enable to output delay max 30 35 ns t ehqz t df chip enable to output high z (note 1) max 20 20 ns t ghqz t df output enable to output high z (note 1) max 20 20 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe t df t oh figure 10. read operations timings
may 9, 2006 am29f004b_00 _ e4 am29f004b 25 data sheet ac characteristics erase/program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 32 for more information. parameter speed options jedec std description -70 -90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 45 ns t dvwh t ds data setup time min 30 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 45 ns t whwl t wph write pulse width high min 20 ns t whwh1 t whwh1 programming operation (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) ty p 1 sec t vcs v cc setup time (note 1) min 50 s
26 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet ac characteristics figure 11. program operation timings oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (?see write operation status on page 17 ). figure 12. chip/sector erase operation timings
may 9, 2006 am29f004b_00 _ e4 am29f004b 27 data sheet ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows fi rst status cycle after command sequence, last status read cycle, and array data read cycle. figure 13. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read c ycle, and array data read cycle. figure 14. toggle bit timings (during embedded algorithms) n ote: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address wi thin an erase-suspended sector . figure 15. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
28 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet ac characteristics figure 16. sector unlock sequ ence timing diagram figure 17. sector relock timing diagram parameter all speed options jedec std. description unit t vidr v id rise and fall time (not 100% tested) min 500 ns oe# a18 ? a0 d7 ? d0 ce# we# aah 555h 55h 2aah 20h/24h 555h t vidr if 20h is written, sector unprotect mode is enabled. if 24h is written, command mode sector protect/unprotect is enabled. device is ready to read from array. v id v ss , v il or v ih oe# a18 ? a0 d7 ? d0 ce# we# 90h xxxh f0h or 00h xxxh t vidr v id v ss , v il or v ih t vidr 0 v or 5 v device exits temporary sector unprotect mode or command mode sector protect/unprotect. returns to reading array data. device is in either temporary sector unprotect mode or command mode sector protect/unprotect.
may 9, 2006 am29f004b_00 _ e4 am29f004b 29 data sheet ac characteristics notes: 1. to enable the command mode sector protection/unprotection algorithm, the system must issue the command 24h in the sector unlock sequence. 2. for sector protection, a valid address consists of the sector address with a6 = 0, a5 = 1, a1 = 1, a0 = 0. for sector unprotection, a valid address consis ts of the sector address with a6 = 1, a5 = 1, a1 = 1, a0 = 0. figure 18. sector protect/unprotect timing diagram oe# a18 ? a0 d7 ? d0 ce# we# 60h xxxh 60h valid (note 2) valid (note 2) 40h v id sector relock sequence (two cycles) sector unlock sequence (three cycles) v ss array data v ih
30 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet ac characteristics alternate ce# cont rolled erase/pr ogram operations 1. not 100% tested. 2. see erase and programming performance on page 32 for more information. parameter speed options jedec std. description -70 -90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 30 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 45 ns t ehel t cph ce# pulse width high min 20 ns t whwh1 t whwh1 programming operation (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) ty p 1 sec
may 9, 2006 am29f004b_00 _ e4 am29f004b 31 data sheet ac characteristics t ghel t ws oe# ce# we# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase notes: 1. pa = program address, pd = program data, dq7# = complement of data written to device, d out = data written to device. 2. figure indicates the last two bus cycles of the command sequence. figure 19. alternate ce# controlled writ e operation timings
32 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0 v v cc , 1,000,000 cycles. additional ly, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5 v (4.75 v for 5% devices), 1,000,000 cycles. 3. the typical chip programming time is cons iderably less than the maximum chip progra mming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorit hm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle sequence for the program command. see ta b l e for further information on command definitions. 6. the device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. plcc pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 1 8 s excludes 00h programming prior to erasure (note 4) chip erase time 8 s byte programming time 7 300 s excludes system level overhead (note 5) chip programming time (note 3) 3.6 10.8 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9 and oe#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test conditions typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf parameter test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
may 9, 2006 am29f004b_00 _ e4 am29f004b 33 data sheet physical dimensions pl 032?32-pin plastic leaded chip carrier dwg rev ah; 10/99
34 am29f004b am29f004b_00 _ e4 may 9, 2006 data sheet revision summary revision a (january 1999) initial release. revision b (march 10, 1999) global revised document into full data sheet. revision b+1 (march 18, 1999) in-system sector protect/sector unprotect algorithms figure added requirements for assert ing address a5 and setting oe# to v ih during both algorithms. command definitions table added a5 requirement to definition for sa+ in the legend. in the fourth cycle of the sector relock sequence, changed address from xxx to sa+. sector protect/unprotect timing diagram modified drawing to indicate that oe# should be dropped to v ih during the third cycle. revision b+2 (may 14, 1999) ordering information changed the temperature range in the example to i. device bus operation table corrected the highest bit in the address range column header to a18. command definitions table in note 4, changed the address range for bits that are don?t care to a18?a12. dc characteristics table in note 5, deleted reference to i cc4 . read operations timings and alternate ce# controlled write operations figures deleted reset# waveform. revision b+3 (july 12, 1999) global deleted all references to the pdip package. changed data sheet status to preliminary. in-system sector protect/unprotect algorithms figure added tolerance specifications to the 150 s and 15 ms waits. clarified that reading from t he sector address during either sector protect or unprotect algorithm requires an access time of 1 s. revision c (november 12, 1999) ac characteristics?figure 11, program operations timing and figure 12, chip/sector erase operations deleted t ghwl and changed oe# waveform to start at high. physical dimensions replaced figures with more detailed illustrations. revision d (february 22, 2000) global the ?preliminary? designation was removed from the docu- ment. parameters are now stable, and only speed, package, and temperature range combinat ions are expected to change in future data sheet revisions. revision e (november 29, 2000) added table of contents. ordering information deleted burn-in option. table , command definitions in note 4, corrected lower address bit of don?t care range to a11. revision e+1 (march 28, 2005) global added colophon updated trademark ordering information added pb-free temperature ranges for industrial and extended packaging added valid combination codes revision e+2 (july 26, 2005) global removed all 55 ns information from the datasheet. revision e+3 (december 23, 2005) global eliminated 120 speed option from entire document. revision e4 (may 9, 2006) added ?not recommended for new designs? note.
may 9, 2006 am29f004b_00 _ e4 am29f004b 35 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita - tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con - templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and pr evention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au - thorization by the respective government entit y will be required for export of those products. trademarks copyright ? 2000-2006 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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