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| rene s a s 1 6 -bit c m os s in g le- c hip mi c r oco mp u te r m16 c family / m16 c /tin y s erie s m16c/28 group 16 rev. 0.60 revision date: february. 01. 2004 hardware manual www.renesas.com before using this material, please visit the our website to confirm that this is the most current document available. rej09b0047-0060z
keep safety first in your circuit designs! notes regarding these materials ? renesas technology corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. ? these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. ? renesas technology corporation assumes no responsibility for any damage, or infringe- ment of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that custom- ers contact renesas technology corporation or an authorized renesas technology cor- poration product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any dam- age, liability or other loss resulting from the information contained herein. ? renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten- tially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product con- tained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. ? please contact renesas technology corporation for further details on these materials or t he products contained therein. how to use this manual this hardware manual provides detailed information on features in the m16c/28 group microcomputer. users are expected to have basic knowledge of electric circuits, logical circuits and micro- computer. *2 rw: read and write ro: read only wo: write only C : nothing is assigned *1 blank:set to "0" or "1" according to your intended use 0: set to "0" 1: set to "1" x: nothing is assigned *3 terms to use here are explained as follows. ? nothing is assigned nothing is assigned to the bit concerned. when write, set to "0" for new function in future plan. ? reserved bit reserved bit. set the specified value. ? avoid this setting the operation at having selected is not guaranteed. ? function varies depending on each operation mode bit function varies depending on peripheral function mode. refer to register diagrams in each mode. *3 xxx register symbol address after reset xxx xxx 00 16 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bit 1 0: xxx 0 1: xxx 1 0: avoid this setting 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bit xxx5 xxx7 xxx6 function nothing is assigned. when write, should set to "0". when read, its content is indeterminate. xxx bit function varies depending on each operation mode should set to "0" 0 (b3) (b2) rw rw rw rw wo rw ro xxx bit 0: xxx 1: xxx *1 *2 each register diagram contains bit functions with the following symbols and descriptions. contents hardware overview hardware overview and electrical characteristics hardware specifications (pin assignments, memory maps, specifications of peripheral func- tions, electrical characteristics, timing charts) detailed description about instructions and mi- crocomputer performance by each instruction ? application examples of peripheral functions ? sample programs ? introductory description about basic functions in m16c family ? programming method with the assembly and c languages document short sheet m16c family documents data sheet hardware manual software manual application note a-1 table of contents quick reference to pages classified by address ......... b-1 1. overview ............................................................................ 1 1.1 applications............................................................................................... 1 1.2 performance outline ................................................................................. 2 1.3 block diagram ............................................................................................4 1.4 product list ............................................................................................... 6 1.5 pin configuration .......................................................................................8 1.6 pin description .........................................................................................10 2. central processing unit (cpu)....................................... 12 2.1 data registers (r0, r1, r2 and r3) ........................................................12 2.2 address registers (a0 and a1)...............................................................12 2.3 frame base register (fb) .......................................................................13 2.4 interrupt table register (intb) ...............................................................13 2.5 program counter (pc) .............................................................................13 2.6 user stack pointer (usp) and interrupt stack pointer (isp) ................13 2.7 static base register (sb) ........................................................................13 2.8 flag register (flg) ..................................................................................13 2.8.1 carry flag (c flag) ................................................................................................. 13 2.8.2 debug flag (d flag) ............................................................................................... 13 2.8.3 zero flag (z flag) .................................................................................................. 13 2.8.4 sign flag (s flag) ................................................................................................... 13 2.8.5 register bank select flag (b flag) ....................................................................... 13 2.8.6 overflow flag (o flag) ........................................................................................... 13 2.8.7 interrupt enable flag (i flag) ................................................................................ 13 2.8.8 stack pointer select flag (u flag) ........................................................................ 13 2.8.9 processor interrupt priority level (ipl) ............................................................... 13 2.8.10 reserved area ...................................................................................................... 13 a-2 3. memory ............................................................................ 14 4. special function register (sfr) map ........................... 15 5. reset ................................................................................ 22 5.1 hardware reset ........................................................................................22 5.1.1 hardware reset 1 ................................................................................................... 22 5.1.2 hardware reset 2 ................................................................................................... 22 5.2 software reset .........................................................................................23 5.3 watchdog timer reset ............................................................................23 5.4 oscillation stop detection reset ...........................................................23 5.5 voltage detection circuit.........................................................................25 5.5.1 voltage detection interrupt ................................................................................... 28 5.5.1.1 precautions ............................................................................................................ ...... 28 5.5.1.1.1. limitations on stop mode ............................................................................................ ....... 28 5.5.1.1.2. limitations on wait instruction ..................................................................................... .... 29 6. processor mode .............................................................. 30 7. clock generation circuit ................................................ 31 7.1 main clock ................................................................................................38 7.2 sub clock .................................................................................................39 7.3 ring oscillator clock ...............................................................................40 7.4 pll clock..................................................................................................40 7.5 cpu clock and peripheral function clock ............................................42 7.5.1 cpu clock ............................................................................................................... 4 2 7.5.2 peripheral function clock (f1, f2, f8, f32, f1sio, f2sio, f8sio, f32sio, fad, fc32) ...................... 42 7.6 power control ..........................................................................................43 7.6.1 normal operation mode ........................................................................................ 43 7.6.1.1 high-speed mode ....................................................................................................... .43 7.6.1.2 pll operation mode ................................................................................................... 4 3 7.6.1.3 medium-speed mode .................................................................................................. 43 7.6.1.4 low-speed mode ........................................................................................................ .43 7.6.1.5 low power dissipation mode .................................................................................... 43 a-3 7.6.1.6 ring oscillator mode ................................................................................................... 44 7.6.1.7 ring oscillator low power dissipation mode ........................................................... 44 7.6.2 wait mode ............................................................................................................... 4 4 7.6.2.1 peripheral function clock stop function ................................................................ 44 7.6.2.2 entering wait mode.................................................................................................... .44 7.6.2.3 pin status during wait mode ..................................................................................... 44 7.6.2.4 exiting wait mode ..................................................................................................... .. 45 7.6.3 stop mode .............................................................................................................. 4 6 7.6.3.1 entering stop mode ..................................................................................................... 46 7.6.3.2 pin status during stop mode ...................................................................................... 46 7.6.3.3 exiting stop mode ...................................................................................................... .. 46 7.7 system clock protective function .........................................................50 7.8 oscillation stop and re-oscillation detect function ...........................50 7.8.1 operation when cm27 bit = 0 (oscillation stop detection reset) .................... 51 7.8.2 operation when cm27 bit = 1 (oscillation stop and re-oscillation detect interrupt) ................. 51 7.8.3 how to use oscillation stop and re-oscillation detect function ..................... 52 8. protection......................................................................... 53 9. interrupts.......................................................................... 54 9.1 type of interrupts .....................................................................................54 9.1.1 software interrupts ................................................................................................ 55 9.1.1.1 undefined instruction interrupt .................................................................................. 55 9.1.1.2 overflow interrupt ..................................................................................................... ... 55 9.1.1.3 brk interrupt .......................................................................................................... ..... 55 9.1.1.4 int instruction interrupt .............................................................................................. 55 9.1.2 hardware interrupts ............................................................................................... 56 9.1.2.1 special interrupts ..................................................................................................... .... 56 _______ 9.1.2.1.1 nmi interrupt ........................................................................................................ ................. 56 ________ 9.1.2.1.2 dbc interrupt ........................................................................................................ ................ 56 9.1.2.1.3 watchdog timer interrupt ............................................................................................. ....... 56 9.1.2.1.4 oscillation stop and re-oscillation detection interrupt ................................................... 56 9.1.2.1.5 voltage down detection interrupt ..................................................................................... .. 56 9.1.2.1.6 single-step interrupt ................................................................................................ ............. 56 9.1.2.1.7 address match interrupt .............................................................................................. ........ 56 9.1.2.2 peripheral function interrupts ................................................................................... 56 9.2 interrupts and interrupt vector ...............................................................57 a-4 9.2.1 fixed vector tables ................................................................................................ 57 9.2.2 relocatable vector tables ..................................................................................... 58 9.3 interrupt control ......................................................................................59 9.3.1 i flag ................................................................................................................... ..... 62 9.3.2 ir bit ................................................................................................................... ..... 62 9.3.3 ilvl2 to ilvl0 bits and ipl ................................................................................... 62 9.4 interrupt sequence ..................................................................................63 9.4.1 interrupt response time ....................................................................................... 64 9.4.2 variation of ipl when interrupt request is accepted ......................................... 64 9.4.3 saving registers .................................................................................................... 65 9.4.4 returning from an interrupt routine .................................................................... 67 9.5 interrupt priority .......................................................................................67 9.5.1 interrupt priority resolution circuit ..................................................................... 67 ______ 9.6 int interrupt .............................................................................................69 ______ 9.7 nmi interrupt .............................................................................................70 9.8 key input interrupt ...................................................................................70 9.9 address match interrupt..........................................................................71 10. watchdog timer ............................................................ 73 11. dmac .............................................................................. 75 11.1 transfer cycles .....................................................................................80 11.1.1 effect of source and destination addresses .................................................... 80 11.1.2 effect of software wait ....................................................................................... 80 11.2. dma transfer cycles ............................................................................82 11.3 dma enable ............................................................................................83 11.4 dma request ..........................................................................................83 11.5 channel priority and dma transfer timing ........................................84 12. timers............................................................................. 85 12.1 timer a ...................................................................................................87 12.1.1. timer mode .......................................................................................................... 90 12.1.2. event counter mode ........................................................................................... 91 12.1.2.1 counter initialization by two-phase pulse signal processing .............................. 95 a-5 12.1.3. one-shot timer mode ......................................................................................... 96 12.1.4. pulse width modulation (pwm) mode ............................................................... 98 12.2 timer b .................................................................................................101 12.2.1 timer mode ........................................................................................................ 103 12.2.2 event counter mode .......................................................................................... 104 12.2.3 pulse period and pulse width measurement mode ....................................... 105 12.2.4 a-d trigger mode .............................................................................................. 107 12.3 three-phase motor control timer function ..................................... 109 12.3.1 position-data-retain function ........................................................................... 120 12.3.1.1 operation of the position-data-retain function .................................................... 120 12.3.1.2 position-data-retain function control register .................................................... 121 12.3.1.2.1 w-phase position data retain bit (pdrw) ..................................................................... 121 12.3.1.2.2 v-phase position data retain bit (pdrv) ....................................................................... 121 12.3.1.2.3 u-phase position data retain bit (pdru) ...................................................................... 121 12.3.1.2.4 retain-trigger polarity select bit (pdrt) ....................................................................... 121 13. timer s (input capture/output compare) ................. 122 13.1 base timer ............................................................................................134 13.1.1 base timer reset register ................................................................................ 138 13.2 interrupt operation ..............................................................................139 13.3 dma support ........................................................................................139 13.4 time measurement function ............................................................. 140 13.5 waveform generation function..........................................................144 13.5.1 single-phase waveform output mode ............................................................. 145 13.5.2 phase-delayed waveform output mode .......................................................... 147 13.5.3 set/reset waveform output (sr waveform output) mode ............................ 149 13.6 i/o port function select ......................................................................151 13.6.1 inpc17 alternate input pin selection ............................................................... 152 ________ 13.6.2 digital debounce function for pin p17/int5/inpc17 ..................................... 152 14. serial i/o ....................................................................... 153 14.1. uarti (i=0 to 2) ...................................................................................153 14.1.1. clock synchronous serial i/o mode ................................................................ 163 14.1.1.1 clk polarity select function.................................................................................. 167 14.1.1.2 lsb first/msb first select function .................................................................... 167 14.1.1.3 continuous receive mode ....................................................................................... 168 a-6 14.1.1.4 serial data logic switch function (uart2) ............................................................. 168 14.1.1.5 transfer clock output from multiple pins function (uart1) ................................ 168 _______ _______ 14.1.1.6 cts/rts separate function (uart0) ..................................................................... 169 14.1.2. clock asynchronous serial i/o (uart) mode ................................................ 170 14.1.2.1. lsb first/msb first select function .................................................................... 174 14.1.2.2. serial data logic switching function (uart2) ................................................... 175 14.1.2.3. txd and rxd i/o polarity inverse function (uart2) .......................................... 175 _______ _______ 14.1.2.4. cts/rts separate function (uart0) ................................................................... 176 14.1.3 special mode 1 (i2c bus mode)(uart2) ......................................................... 177 14.1.3.1 detection of start and stop condition ................................................................... 183 14.1.3.2 output of start and stop condition ....................................................................... 183 14.1.3.3 arbitration ........................................................................................................... ...... 184 14.1.3.4 transfer clock ........................................................................................................ .. 185 14.1.3.5 sda output ............................................................................................................ ... 185 14.1.3.6 sda input ............................................................................................................. ..... 185 14.1.3.7 ack and nack ....................................................................................................... 18 6 14.1.3.8 initialization of transmission/reception .............................................................. 186 14.1.4 special mode 2 (uart2) .................................................................................... 187 14.1.4.1 clock phase setting function ............................................................................... 190 14.1.4.1.1 master (internal clock) ............................................................................................. ........ 190 14.1.4.1.2 slave (external clock) .............................................................................................. ........ 190 14.1.5 special mode 3 (ie bus mode)(uart2) ........................................................... 192 14.1.6 special mode 4 (sim mode) (uart2) ............................................................... 194 14.1.6.1 parity error signal output ....................................................................................... 197 14.1.6.2 format ............................................................................................................... ....... 198 14.2 si/o3 and si/o4 ...................................................................................199 14.2.1 si/oi operation timing .............................................................................................. 202 14.2.2 clk polarity selection .............................................................................................. 202 14.2.3 functions for setting an souti initial value ........................................................... 203 15. a-d converter .............................................................. 204 15.1 operation modes ................................................................................. 210 15.1.1 one-shot mode ................................................................................................... 210 15.1.2 repeat mode ....................................................................................................... 212 15.1.3 single sweep mode ........................................................................................... 214 15.1.4 repeat sweep mode 0 ....................................................................................... 216 15.1.5 repeat sweep mode 1 ....................................................................................... 218 15.1.6 simultaneous sample sweep mode ................................................................. 220 15.1.7 delayed trigger mode 0 ..................................................................................... 223 15.1.8 delayed trigger mode 1 ..................................................................................... 229 a-7 15.2 resolution select function .................................................................235 15.3 sample and hold ................................................................................. 235 15.4 current consumption reducing function ........................................235 15.5 analog input pin and external sensor equivalent circuit example 235 15.6 precautions of using a-d converter ..................................................236 16. multi-master i 2 c bus interface .................................... 237 16.1 i 2 c0 data shift register (s00 register) ...............................................246 16.2 i 2 c0 address register (s0d0 register) ...............................................246 16.3 i 2 c0 clock control register (s20 register) .......................................247 16.3.1 bits 0 to 4: scl frequency control bits (ccr0?cr4) .................................. 247 16.3.2 bit 5: scl mode specification bit (fast mode) ........................................... 247 16.3.3 bit 6: ack bit (ack bit) ................................................................................... 247 16.3.4 bit 7: ack clock bit (ack) ................................................................................ 247 16.4 i 2 c0 control register 0 (s1d0 register) ............................................249 16.4.1 bits 0 to 2: bit counter (bc0?c2) .................................................................. 249 16.4.2 bit 3: i2c interface enable bit (es0) ................................................................. 249 16.4.3 bit 4: data format select bit (als) ................................................................... 249 16.4.4 bit 6: i 2 c bus interface reset bit (ihr) ............................................................. 249 16.4.5 bit 7: i 2 c bus interface pin input level select bit (tiss) ................................. 250 16.5 i 2 c0 status register (s10 register) ................................................... 251 16.5.1 bit 0: last receive bit (lrb) ............................................................................. 251 16.5.2 bit 1: general call detection flag (adr0) ........................................................ 251 16.5.3 bit 2: slave address comparison flag (aas) .................................................. 251 16.5.4 bit 3: arbitration lost detection flag (al)(note 1) ........................................... 251 16.5.5 bit 4: i 2 c bus interface interrupt request bit (pin) ......................................... 252 16.5.6 bit 5: bus busy flag (bb) .................................................................................. 252 16.5.7 bit 6: communication mode select bit (transfer direction select bit: trx) . 253 16.5.8 bit 7: communication mode select bit (master/slave select bit: mst) ....... 253 16.6 i 2 c0 control register 1 (s3d0 register) .............................................254 16.6.1 bit 0 : interrupt enable bit by stop condition (sim ) ..................................... 254 16.6.2 bit 1: interrupt enable bit at the completion of data receive (wit) ............... 254 16.6.3 bits 2,3 : port function select bits ped, pec ................................................. 255 16.6.4 bits 4,5 : sda/scl logic output value monitor bits sdam/sclm ................ 256 a-8 16.6.5 bits 6,7 : i 2 c system clock select bits ick0, ick1 .......................................... 256 16.6.6 the address receive in stop mode/wait mode............................................ 256 16.7 i 2 c0 control register 2 (s3d0 register) ..............................................257 16.7.1 bit0: time out detection function enable bit (toe) ........................................ 258 16.7.2 bit1: time out detection flag (tof ) ................................................................ 258 16.7.3 bit2: time out detection period select bit (tosel) ........................................ 258 16.7.4 bits 3,4,5: i 2 c system clock select bits (ick2-4) ............................................ 258 16.7.5 bit7: stop condition detection interrupt request bit (scpin) ...................... 258 16.8 i 2 c0 start/stop condition control registers (s2d0 register) .......259 16.8.1 bit0-bit4: start/stop condition setting bits (ssc0-ssc4) ........................ 259 16.8.2 bit5: scl/sda interrupt pin polarity select bit (sip)...................................... 259 16.8.3 bit6 : scl/sda interrupt pin select bit (sis) ................................................... 259 16.8.4 bit7: start/stop condition generation select bit (stspsel) .................... 259 16.9 start condition generation method ...............................................260 16.10 start condition duplicate protect function ...................................261 16.11 stop condition generation method ............................................... 261 16.12 start/stop condition detect operation .......................................263 16.13 address data communication ........................................................ 264 16.13.1 example of master transmit .......................................................................... 264 16.13.2 example of slave receive .............................................................................. 265 16.14 usage precautions ............................................................................ 267 17. programmable i/o ports ............................................. 270 17.1 port pi direction register (pdi register, i = 0 to 3, 6 to 10) .............270 17.2 port pi register (pi register, i = 0 to 3, 6 to 10) ................................270 17.3 pull-up control register 0 to pull-up control register 2 (pur0 to pur2 registers) ........270 17.4 port control register ...........................................................................270 17.5 pin assignment control register (pacr) .......................................... 271 17.6 digital debounce function ..................................................................271 18. electrical characteristics ........................................... 284 18.1. normal version ....................................................................................284 a-9 18.2. t version ..............................................................................................305 19. flash memory version ................................................ 326 19.1 flash memory performance ................................................................326 19.2 memory map .........................................................................................328 19.3 functions to prevent flash memory from rewriting ...................... 331 19.3.1 rom code protect function ............................................................................. 331 19.3.2 id code check function .................................................................................... 331 19.4 cpu rewrite mode ...............................................................................333 19.4.1 ew0 mode ........................................................................................................... 334 19.4.2 ew1 mode ........................................................................................................... 334 19.5 register description ............................................................................335 19.5.1 flash memory control register 0 (fmr0): ........................................................ 335 ?mr 00 bit .................................................................................................................... ......... 335 ?mr01 bit ..................................................................................................................... ......... 335 ?mr02 bit ..................................................................................................................... ......... 335 ?mstp bit ..................................................................................................................... ......... 335 ?mr06 bit ..................................................................................................................... ......... 335 ?mr07 bit ..................................................................................................................... ......... 335 19.5.2 flash memory control register 1 (fmr1): ........................................................ 336 ?mr11 bit ..................................................................................................................... ......... 336 ?mr16 bit ..................................................................................................................... ......... 336 ?mr17 bit ..................................................................................................................... ......... 336 19.5.3 flash memory control register 4 (fmr4): ........................................................ 336 ?mr40 bit ..................................................................................................................... ......... 336 ?mr41 bit ..................................................................................................................... ......... 336 ?mr46 bit ..................................................................................................................... ......... 336 19.6 precautions in cpu rewrite mode .................................................... 341 19.6.1 operation speed ................................................................................................ 341 19.6.2 prohibited instructions ...................................................................................... 341 19.6.3 interrupts ............................................................................................................ 34 1 19.6.4 how to access .................................................................................................... 341 19.6.5 writing in the user rom space ........................................................................ 341 19.6.5.1 ew0 mode .............................................................................................................. ... 341 19.6.5.2 ew1 mode .............................................................................................................. ... 341 19.6.6 dma transfer ...................................................................................................... 342 19.6.7 writing command and data .............................................................................. 342 a-10 19.6.8 wait mode ........................................................................................................... 342 19.6.9 stop mode ........................................................................................................... 342 19.6.10 low power consumption mode and ring oscillator-low power consumption mode .................... 342 19.7 software commands ...........................................................................343 19.7.1 read array command (ff 16 ) ............................................................................. 343 19.7.2 read status register command (70 16 ) ............................................................. 343 19.7.3 clear status register command (50 16 ) ............................................................ 344 19.7.4 program command (40 16 ) .................................................................................. 344 19.7.5 block erase ......................................................................................................... 345 19.8 status register .....................................................................................347 19.8.1 sequence status (sr7 and fmr00 bits ) ......................................................... 347 19.8.2 erase status (sr5 and fmr07 bits) ................................................................. 347 19.8.3 program status (sr4 and fmr06 bits) ............................................................ 347 19.8.4 full status check ............................................................................................... 348 19.9 standard serial i/o mode ....................................................................350 19.9.1 id code check function .................................................................................... 350 19.9.2 example of circuit application in standard serial i/o mode ......................... 354 19.10 parallel i/o mode ................................................................................356 19.10.1 rom code protect function ........................................................................... 356 20. package ........................................................................ 357 register index ................................................................... 358 b-1 quick reference to pages classified by address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address note: the blank areas are reserved and cannot be accessed by users. register symbol page 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 watchdog timer start register wdts watchdog timer control register wdc processor mode register 0 pm0 system clock control register 0 cm0 system clock control register 1 cm1 address match interrupt enable register aier protect register prcr processor mode register 1 pm1 oscillation stop detection register cm2 pll control register 0 plc0 processor mode register 2 pm2 address match interrupt register 0 rmad0 address match interrupt register 1 rmad1 dma0 control register dm0con dma0 transfer counter tcr0 dma1 control register dm1con dma1 source pointer sar1 dma1 destination pointer dar1 dma0 destination pointer dar0 dma0 source pointer sar0 voltage detection register 1 vcr1 voltage detection register 2 vcr2 voltage down detection interrupt register d4int uart0 transmit interrupt control register s0tic uart0 receive interrupt control register s0ric uart1 transmit interrupt control register s1tic uart1 receive interrupt control register s1ric dma1 transfer counter tcr1 int3 interrupt control register int3ic ic/oc 0 interrupt control register icoc0ic ic/oc 1 interrupt control register icoc1ic i 2 c-bus interface interrupt control register iicic ic/oc base timer interrupt control register btic s cl s da interrupt control register scldaic si/o4 interrupt control register s4ic, int5 interrupt control register int5ic si/o3 interrupt control register, s3ic, int4 interrupt control register int4ic uart2 bus collision detection interrupt control register bcnic dma0 interrupt control register dm0ic dma1 interrupt control register dm1ic key input interrupt control register kupic a-d conversion interrupt control register adic uart2 transmit interrupt control register s2tic uart2 receive interrupt control register s2ric timer a0 interrupt control register ta0ic timer a1 interrupt control register ta1ic timer a2 interrupt control register ta2ic timer a3 interrupt control register ta3ic timer a4 interrupt control register ta4ic timer b0 interrupt control register tb0ic timer b2 interrupt control register tb2ic int0 interrupt control register int0ic int1 interrupt control register int1ic int2 interrupt control register int2ic timer b1 interrupt control register tb1ic 30 30 33 34 72 53 35 74 25, 74 72 72 26 26 37 36 26 79 79 79 78 79 79 79 78 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 address register symbol page b-2 quick reference to pages classified by address note 1: the blank areas are reserved and cannot be accessed by users. note 2: this register is included in the flash memory version. 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02fe 16 02ff 16 peripheral clock select register pclkr flash memory control register 0 fmr0 flash memory control register 1 fmr1 351 351 36 (note 2) (note 2) address register symbol page address register symbol page (note 2) flash memory control register 4 fmr4 352 pin assignment control register pacr ring oscillator control register rocr 281 34 p1 7 digital debounce register p17ddr nmi digital debounce register nddr 282 282 241 i 2 c0 data shift register s00 i 2 c0 address register s0d0 i 2 c0 control register 0 s1d0 i 2 c0 clock control register s20 i 2 c0 start/stop condition control register s2d0 i 2 c0 control register 1 s3d0 i 2 c0 control register 2 s4d0 i 2 c0 status register s10 240 242 241 246 244 245 243 tm/wg register 0 g1tm0/g1po0 129,130 tm/wg register 1 g1tm1/g1po1 tm/wg register 2 g1tm2/g1po2 tm/wg register 3 g1tm3/g1po3 tm/wg register 4 g1tm4/g1po4 tm/wg register 5 g1tm5/g1po5 tm/wg register 6 g1tm6/g1po6 tm/wg register 7 g1tm7/g1po7 wg control register 0 g1pocr0 129 wg control register 1 g1pocr1 129 wg control register 2 g1pocr2 129 wg control register 3 g1pocr3 129 wg control register 4 g1pocr4 129 wg control register 5 g1pocr5 129 wg control register 6 g1pocr6 129 wg control register 7 g1pocr7 129 tm control register 0 g1tmcr0 128 tm control register 1 g1tmcr1 128 tm control register 2 g1tmcr2 128 tm control register 3 g1tmcr3 128 tm control register 4 g1tmcr4 128 tm control register 5 g1tmcr5 128 tm control register 6 g1tmcr6 128 tm control register 7 g1tmcr7 128 base timer register g1bt 124 base timer control register 0 g1bcr0 124 base timer control register 1 g1bcr1 126 tm prescale register 6 g1tpr6 128 tm prescale register 7 g1tpr7 128 function enable register g1fe 131 function select register g1fs 131 base timer reset register g1btrr 127 divider register g1dv 125 129,130 129,130 129,130 129,130 129,130 129,130 129,130 interrupt request register g1ir 132 interrupt enable register 0 g1ie0 133 interrupt enable register 1 g1ie1 133 b-3 quick reference to pages classified by address note : the blank areas are reserved and cannot be accessed by users. 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr trigger select register trgsr timer a0 register ta0 timer a1 register ta1 timer a2 register ta2 timer b0 register tb0 timer b1 register tb1 timer b2 register tb2 one-shot start flag onsf timer a0 mode register ta0mr timer a1 mode register ta1mr timer a2 mode register ta2mr timer b0 mode register tb0mr timer b1 mode register tb1mr timer b2 mode register tb2mr up-down flag udf timer a3 register ta3 timer a4 register ta4 timer a3 mode register ta3mr timer a4 mode register ta4mr clock prescaler reset flag cpsrf uart0 transmit/receive mode register u0mr uart0 transmit buffer register u0tb uart0 receive buffer register u0rb uart1 transmit/receive mode register u1mr uart1 transmit buffer register u1tb uart1 receive buffer register u1rb uart0 bit rate generator u0brg uart0 transmit/receive control register 0 u0c0 uart0 transmit/receive control register 1 u0c1 uart1 bit rate generator u1brg uart1 transmit/receive control register 0 u1c0 uart1 transmit/receive control register 1 u1c1 dma1 request cause select register dm1sl dma0 request cause select register dm0sl uart transmit/receive control register 2 ucon timer b2 special mode register tb2sc 88, 102, 116 89 89, 102 89, 116 88 102 102 102, 116 87 87, 117 87 101 101 108, 115 158 157 157 159 160 157 158 157 157 159 160 157 159 77 78 88 88, 114 88, 114 88 88, 114 87, 117 87, 117 101, 117 address register symbol page 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register ta11 timer a2-1 register ta21 dead time timer dtt timer b2 interrupt occurrence frequency set counter ictb2 three-phase pwm control register 0 invc0 three-phase pwm control register 1 invc1 three-phase output buffer register 0 idb0 three-phase output buffer register 1 idb1 interrupt request cause select register ifsr si/o3 transmit/receive register s3trr si/o4 transmit/receive register s4trr si/o3 control register s3c si/o3 bit rate generator s3brg si/o4 bit rate generator s4brg si/o4 control register s4c uart2 special mode register u2smr uart2 receive buffer register u2rb uart2 transmit buffer register u2tb uart2 transmit/receive control register 0 u2c0 uart2 transmit/receive mode register u2mr uart2 transmit/receive control register 1 u2c1 uart2 bit rate generator u2brg timer a4-1 register ta41 uart2 special mode register 2 u2smr2 uart2 special mode register 3 u2smr3 interrupt request cause select register 2 ifsr2a uart2 special mode register 4 u2smr4 114 114 114 111 112 113 113 113 113 200 200 200 200 200 200 162 162 161 161 158 157 157 159 160 157 61 61, 69 address register symbol page position-data-retain function contol register pdrf 121 b-4 quick reference to pages classified by address note : the blank areas are reserved and cannot be accessed by users. 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d control register 1 adcon1 port p9 register p9 pull-up control register 0 pur0 port control register pcr a-d register 7 ad7 a-d register 0 ad0 a-d register 1 ad1 a-d register 2 ad2 a-d register 3 ad3 a-d register 4 ad4 a-d register 5 ad5 a-d register 6 ad6 a-d control register 0 adcon0 a-d control register 2 adcon2 port p0 register p0 port p0 direction register pd0 port p1 register p1 port p1 direction register pd1 port p2 register p2 port p2 direction register pd2 port p3 register p3 port p3 direction register pd3 port p6 register p6 port p6 direction register pd6 port p7 register p7 port p7 direction register pd7 port p8 register p8 port p8 direction register pd8 port p9 direction register pd9 port p10 register p10 port p10 direction register pd10 pull-up control register 1 pur1 pull-up control register 2 pur2 208 208 208 208 208 208 208 208 206 206 206 279 279 278 278 279 279 278 278 279 279 278 278 279 279 278 278 279 278 280 280 280 281 address register symbol page a-d convert status register 0 adstat0 208 a-d trigger control register adtrgcon 207 m16c/28 group single-chip 16-bit cmos microcomputer rej09b0047-0060z rev.0.60 2004.02.01 rev.0.60 2004.02.01 page 1 of n rej09b0047-0060z 1. overview the m16c/28 group of single-chip microcomputers is built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and is packaged in a 64-pin and 80-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc- tion efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and a dmac which combined with fast instruction pro- cessing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 applications audio, cameras, office/communications/portable/industrial equipment, home appliances (inverter solution), etc specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. ------table of contents------ m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 2 of n rej09b0047-0060z item performance number of basic instructions 91 instructions shortest instruction execution time 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) (normal-ver./t-ver.) 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) (normal-ver.) 50 ns (f(bclk)= 20mh z , v cc = 4.2v to 5.5v -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2v to 5.5v -40 to 125 c) (v-ver.) memory rom (see the product list) capacity ram (see the product list) i/o port 71 lines multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart0, uart1) uart, clock synchronous 1 channel (uart2) uart, clock synchronous, i 2 c bus 1 , or iebus 2 2 channels (si/o3, si/o4) clock synchronous 1 channel (multi-master i 2 c bus 1 ) a-d converter 10 bits x 24 channels dmac 2 channels (trigger: 31 sources) watchdog timer 15 bits x 1 (with prescaler) interrupt 25 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? ring oscillator( main-clock oscillation stop detect function) ? pll frequency synthesizer low voltage detection circuit present power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) (normal-ver.) v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) v cc =3.0v to 5.5v (t-ver.) v cc =4.2v to 5.5v (v-ver.) flash memory program/erase voltage 2.7v to 5.5v (normal-ver.) 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times ( block a ,block b : 10,000 times (option 3 ) ) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, when stop mode) operating ambient temperature -20 to 85 c / -40 to 85 c (option 3 ) (normal-ver.) -40 to 85 c (t-ver.) -40 to 105 c / -40 to 125 c (v-ver.) package 80-pin plastic mold qfp notes: 1. i 2 c bus is a registered trademark of philips. 2. iebus is a trademark of nec electronics corporation. 3. if you desire this option, please so specify. table 1.2.1. performance outline of m16c/28 group (80-pin device) 1.2 performance outline table 1.2.1 lists performance outline of m16c/28 group 80-pin device. table 1.2.2 lists performance outline of m16c/28 group 64-pin device. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 3 of n rej09b0047-0060z item performance number of basic instructions 91 instructions shortest instruction execution time 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) (normal-ver./t-ver.) 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) (normal-ver.) 50 ns (f(bclk)= 20mh z , v cc = 4.2v to 5.5v -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2v to 5.5v -40 to 125 c) (v-ver.) memory rom (see the product list) capacity ram (see the product list) i/o port 55 lines multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart0, uart1) uart, clock synchronous 1 channel (uart2) uart, clock synchronous, i 2 c bus 1 , or iebus 2 1 channel (si/o3) clock synchronous 1 channel (multi-master i 2 c bus 1 ) a-d converter 10 bits x 13 channels dmac 2 channels (trigger: 30 sources) watchdog timer 15 bits x 1 (with prescaler) interrupt 24 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? ring oscillator( main-clock oscillation stop detect function) ? pll frequency synthesizer low voltage detection circuit present power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) (normal-ver.) v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) v cc =3.0v to 5.5v (t-ver.) v cc =4.2v to 5.5v (v-ver.) flash memory program/erase voltage 2.7v to 5.5v (normal-ver.) 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times ( block a ,block b : 10,000 times (option 3 ) ) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, when stop mode) operating ambient temperature -20 to 85 c / -40 to 85 c (option 3 ) (normal-ver.) -40 to 85 c (t-ver.) -40 to 105 c / -40 to 125 c (v-ver.) package 64-pin plastic mold qfp notes: 1. i 2 c bus is a registered trademark of philips. 2. iebus is a trademark of nec electronics corporation. 3. if you desire this option, please so specify. table 1.2.2. performance outline of m16c/28 group (64-pin device) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 4 of n rej09b0047-0060z i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer a-d converter (10bits x 24 channels) u(s)art/sio (channel 0) serial ports system clock generator xin-xout xcin-xcout ring oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram u(s)art/sio (channel 1) u(s)art/sio/i 2 c/iebus (channel 2) 3-phase pwm port p0 8 port p1 8 port p2 8 port p3 8 port p6 8 port p7 8 port p8 8 port p9 7 port p10 8 timer s input capture (8 channels) output compare (8 channels) flash rom (data flash) multi-master i 2 c bus sio (channel 3) sio (channel 4) dmac (2 channels) low voltage detect pll frequency synthesizer 1.3 block diagram figure 1.3.1 is a block diagram of the m16c/28 group, 80-pin device. figure 1.3.1. m16c/28 group, 80-pin block diagram m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 5 of n rej09b0047-0060z figure 1.3.2 is a block diagram of the m16c/28 group, 64-pin device. figure 1.3.2. m16c/28 group, 64-pin block diagram i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer a-d converter (10bits x 13 channels) system clock generator xin-xout xcin-xcout ring oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram 3-phase pwm port p0 4 port p1 3 port p2 8 port p3 4 port p6 8 port p7 8 port p8 8 port p9 4 port p10 8 timer s input capture (8 channels) output compare (8 channels) flash rom (data flash) u(s)art/sio (channel 0) serial ports u(s)art/sio (channel 1) u(s)art/sio/i 2 c/iebus (channel 2) multi-master i 2 c bus sio (channel 3) pll frequency synthesizer low voltage detect dmac (2 channels) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 6 of n rej09b0047-0060z 1.4 product list tables 1.4.1 to 1.4.3 list the m16c/28 group products and figure 1.4.1 shows the type numbers, memory sizes and packages. table 1.4.1. product list (1) -normal version as of november 2003 type no. rom capacity ram capacity package type remarks m30280f6hp ** 48k + 4k byte 4k byte m30280f8hp ** 64k + 4k byte 4k byte 80p6q-a m30280fahp ** 96k + 4k byte 8k byte flash rom version m30281f6hp ** 48k + 4k byte 4k byte m30281f8hp ** 64k + 4k byte 4k byte 64p6q-a m30281fahp ** 96k + 4k byte 8k byte m30280m4-xxxhp * 32k byte 2k byte m30280m6-xxxhp * 48k byte 4k byte 80p6q-a m30280m8-xxxhp * 64k byte 4k byte mask rom version m30281m4-xxxhp * 32k byte 2k byte m30281m6-xxxhp * 48k byte 4k byte 64p6q-a m30281m8-xxxhp * 64k byte 4k byte * : under planning ** : under development table 1.4.2. product list (2) -t version as of november 2003 type no. rom capacity ram capacity package type remarks m30280f6thp ** 48k + 4k byte 4k byte m30280f8thp ** 64k + 4k byte 4k byte 80p6q-a m30280fathp ** 96k + 4k byte 8k byte flash rom version m30281f6thp ** 48k + 4k byte 4k byte (t-version) m30281f8thp ** 64k + 4k byte 4k byte 64p6q-a m30281fathp ** 96k + 4k byte 8k byte M30280M4T-XXXHP * 32k byte 2k byte m30280m6t-xxxhp * 48k byte 4k byte 80p6q-a m30280m8t-xxxhp * 64k byte 4k byte mask rom version m30281m4t-xxxhp * 32k byte 2k byte (t-version) m30281m6t-xxxhp * 48k byte 4k byte 64p6q-a m30281m8t-xxxhp * 64k byte 4k byte * : under planning ** : under development m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 7 of n rej09b0047-0060z package type: hp : package 80p6q, 64p6q version (no): normal version t : t version v : v version rom capacity / ram capacity: 4: (32k) bytes /2k bytes 6: (48k+4k) bytes (note 1) /4k bytes 8: (64k+4k) bytes (note 1) /4k bytes a: (96k+4k) bytes (note 1) /8k bytes c: (128k+4k) bytes (note 1,2) /12k bytes note 1: only flash memory version exists in "+4k bytes" note 2: under planning memory type: m: mask rom version f: flash memory version type no. m 3 0 2 8 0 f 8 t h p m16c/28 group m16c family shows pin count (the value itself has no specific meaning) figure 1.4.1. type no., memory size, and package table 1.4.2. product list (3) -v version as of november 2003 type no. rom capacity ram capacity package type remarks m30280f6vhp ** 48k + 4k byte 4k byte m30280f8vhp ** 64k + 4k byte 4k byte 80p6q-a m30280favhp ** 96k + 4k byte 8k byte flash rom version m30281f6vhp ** 48k + 4k byte 4k byte (v-version) m30281f8vhp ** 64k + 4k byte 4k byte 64p6q-a m30281favhp ** 96k + 4k byte 8k byte m30280m4v-xxxhp * 32k byte 2k byte m30280m6v-xxxhp * 48k byte 4k byte 80p6q-a m30280m8v-xxxhp * 64k byte 4k byte mask rom version m30281m4v-xxxhp * 32k byte 2k byte (v-version) m30281m6v-xxxhp * 48k byte 4k byte 64p6q-a m30281m8v-xxxhp * 64k byte 4k byte * : under planning ** : under development m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 8 of n rej09b0047-0060z m30280fx-xxxhp 1 2 3 4 5 6 7 8 9 10 11 12 p9 5 /an 25 /clk 4 13 14 15 16 17 18 19 20 cnvss reset x out vss x in vcc 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 a v cc v r e f a v ss p8 4 /int 2 /zp p9 3 /an 24 p9 2 /tb 2in p9 1 /tb 1in p9 0 /tb 0in p8 7 /x cin p8 6 /x cout p8 5 /nmi/sd p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p8 0 /ta 4out /u p7 7 /ta 3in p 7 6 /t a 3 o u t p 7 5 /t a 2 in /w p 7 4 /t a 2 o u t /w p 7 2 /c l k 2 /t a 1 o u t /v /r x d 1 p 7 1 /r x d 2 /s c l /t a 0 in /c l k 1 p 6 7 /t x d 1 p 6 6 /r x d 1 p 6 5 /c l k 1 p 3 7 p 3 6 p 3 5 p 3 4 p 3 3 p 3 2 /s o u t 3 p 3 1 /s in 3 p 3 0 /c l k 3 p 6 3 /t x d 0 p6 2 /rxd 0 p6 1 /clk 0 p6 0 /rts 0 /cts 0 p2 7 /outc1 7 /inpc1 7 p2 6 /outc1 6 /inpc1 6 p2 5 /outc1 5 /inpc1 5 p2 4 /outc1 4 /inpc1 4 p2 3 /outc1 3 /inpc1 3 p2 2 /outc1 2 /inpc1 2 p2 1 /outc1 1 /inpc1 1 /scl mm p2 0 /outc1 0 /inpc1 0 /sda mm p1 7 /int 5 /inpc1 7 p1 6 /int 4 p1 5 /int 3 /ad trg p1 4 p1 3 /an 23 p1 2 /an 22 p1 1 /an 21 p1 0 /an 20 p0 7 /an 07 p 0 6 /a n 0 6 p 0 5 /a n 0 5 p 0 4 /a n 0 4 p 0 3 /a n 0 3 p 0 2 /a n 0 2 p 0 1 /a n 0 1 p 0 0 /a n 0 0 p 1 0 3 /a n 3 p 1 0 2 /a n 2 p 1 0 1 /a n 1 p 1 0 0 /a n 0 p 9 7 /a n 2 7 /s in 4 p 9 6 /a n 2 6 /s o u t 4 p 7 3 /c t s 2 /r t s 2 /t a 1 in /v /t x d 1 p 1 0 7 /a n 7 /k i 3 p 1 0 4 /a n 4 /k i 0 p 1 0 5 /a n 5 /k i 1 p 1 0 6 /a n 6 /k i 2 p 6 4 /r t s 1 /c t s 1 /c t s 0 /c l k s 1 /idv /idw /idu { / p 7 0 /t x d 2 s d a /t a 0 o u t 0 /r t s 1 /c t s 1 /c t s /c l k s 1 note. set pacr2 to pacr0 bit in the pacr register to "011 2 " before you input and output it after resetting to each pin. when the pacr register isn t set up, the input and output function of some of the pins are disabled. package: 80p6q-a figure 1.5.1. pin configuration (top view) of m16c/28 group, 80-pin package pin configuration (top view) 1.5 pin configuration figures 1.5.1 and 1.5.2 show the pin configurations (top view). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 9 of n rej09b0047-0060z figure 1.5.2. pin configuration (top view) of m16c/28 group, 64-pin package pin configuration (top view) m30281fx-xxxhp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnvss vss vcc 21 22 23 2 4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 5 5 54 53 5 2 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 avcc avss 1 7 18 19 20 p9 1 /tb 1in p9 0 /tb 0in p8 7 /x cin p8 6 /x cout x out x in p8 4 /int 2 /zp p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p8 0 /ta 4out /u p7 7 /ta 3 in p7 6 /ta 3 o u t p7 5 /ta 2 in /w p7 4 /ta 2 o u t /w p7 2 /clk 2 /ta 1 o u t /v/rxd 1 p7 1 /rxd 2 /scl/ta 0 in /clk 1 p6 7 /txd 1 p6 6 /rxd 1 p6 5 /clk 1 p3 3 p3 2 /s o u t 3 p3 1 /s in 3 p3 0 /clk 3 p6 3 /txd 0 p6 2 /rxd 0 p6 1 /clk 0 p2 7 /outc1 7 /inpc1 7 p2 6 /outc1 6 /inpc1 6 p2 5 /outc1 5 /inpc1 5 p2 4 /outc1 4 /inpc1 4 p2 3 /outc1 3 /inpc1 3 p2 2 /outc1 2 /inpc1 2 p2 1 /outc1 1 /inpc1 1 /scl mm p2 0 /outc1 0 /inpc1 0 /sda mm p0 3 /an 03 p0 2 /an 0 2 p0 1 /an 0 1 p0 0 /an 0 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 p10 0 /an 0 v r e f p9 3 /an 2 4 p9 2 /tb 2 in p8 5 /nmi/sd reset p7 3 /cts 2 /rts 2 /ta 1 in /v/txd 1 p6 0 /rts 0 /cts 0 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p6 4 /rts 1 /cts 1 /cts 0 /clks 1 p1 5 /int 3 /ad trg /idv p1 6 /int 4 /idw p1 7 /int 5 /inpc1 7 /idu p7 0 /txd 2 /sda /ta 0 o u t 1 /rts 1 /cts 1 0 /cts /clks { note. set pacr2 to pacr0 bit in the pacr register to "010 2 " before you input and output it after resetting to each pin. when the pacr register isn t set up, the input and output function of some of the pins are disabled. package: 64p6q-a m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 10 of n rej09b0047-0060z table 1.6.1 pin description(1) 1.6 pin description table 1.6.1 and 1.6.2 describes the available pins. pin name signal name i/o type function v cc ,v ss power supply apply 0v to the vss pin, and the following voltage to the vcc pin. input 2.7 to 5.5v (normal-ver.) 3.0 to 5.5v (t-ver.) 4.2 to 5.5v (v-ver.) cnv ss cnv ss input connect this pin to vss. ____________ reset reset input input "l" on this input resets the microcomputer. x in clock input input these pins are provided for the main clock generating circuit input/ x out clock output output output. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. if x in is not used (for external oscillator or external clock) connect x in pin to v cc and leave x out pin open. av cc analog power this pin is a power supply input for the a-d converter. connect this supply input pin to v cc . av ss analog power this pin is a power supply input for the a-d converter. connect this supply input pin to v ss . v ref reference input this pin is a reference voltage input for the a-d converter. voltage input p0 0 ~p0 7 i/o port p0 input/output this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of four pins.software can also select this port to function as a-d converter input pins. p0 4 ~p0 7 is not in 64 pin version. p1 0 ~p1 7 i/o port p1 input/output this is an 8-bit i/o port equivalent to p0. additional software-select able secondary functions are: 1) p1 0 to p1 3 can act as a-d converter input pins; 2) p1 5 to p1 7 can be configured as external interrupt pins; 3) p1 5 to p1 7 can be configured as position-data-retain function input pins,and; 4) p1 5 can input a trigger for the a-d converter. p1 0 ~p1 4 is not in 64 pin version. p2 0 ~p2 7 i/o port p2 input/output this is an 8-bit i/o port equivalent to p0. software can also select this port to perform as i/o for the timer s (all pins), and multimaster i 2 c bus (p2 0 and p2 1 only) p3 0 ~p3 7 i/o port p3 input/output this is an 8-bit i/o port equivalent to p0. p3 0 to p3 2 also function as sio3 i/o, as selected by software. p3 4 ~p3 7 is not in 64 pin version. p6 0 ~p6 7 i/o port p6 input/output this is an 8-bit i/o port equivalent to p0. pins in this port also func- tion as uart0 and uart1 i/o, as selected by software. p7 0 ~p7 7 i/o port p7 input/output this is an 8-bit i/o port equivalent to p0. p7 can also function as i/o for timer a0-a3, as selected by software. additional programming options are: p7 0 to p7 3 can assume uart1 and uart2 i/o capa- bilities, and p7 2 to p7 5 can function as output pins for the three- phase motor control timer. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.60 2004.02.01 page 11 of n rej09b0047-0060z table 1.6.2 pin description(2) pin name signal name i/o type function p8 0 ~p8 7 i/o port p8 input/output this is an 8-bit i/o port equivalent to p0. additional software-select able secondary functions are: 1) p8 0 and p8 1 can act as either i/o for timer a4, or as output pins for the three-phase motor control timer; 2) p8 2 to p8 4 can be configured as external interrupt pins. p8 4 can be used for timer a zphase function; 3) p8 5 can be used _______ _____ as nmi/sd. p8 5 can not be used as i/o port while the three-phase motor control is enabled. apply a stable "h" to p8 5 after setting the direction register for p8 5 to "0" when the three-phase motor control is enabled, and; 4) p8 6 and p8 7 can serve as i/o pins for the sub-clock generation circuit. in this latter case, a quartz oscillator must be connented between p8 6 (x cout pin) and p8 7 (x cin pin). p9 0 ~p9 3 , i/o port p9 input/output this is an 7-bit i/o port equivalent to p0. additional software-select p9 5 ~p9 7 able secondary functions are: 1) p9 0 to p9 2 can act as timer b0~b2 input pins; 2) p9 3 , p9 5 to p9 7 can act as a-d converter input pins, and; 3) p9 6 to p9 7 can assume si/o4 i/o. p9 5 to p9 7 is not in 64 pin version. p10 0 ~p10 7 i/o port p10 input/output this is an 8-bit i/o port equivalent to p0. this port can also function as a-d converter input pins, as selected by software. furthermore, p10 4 -p10 7 can also function as input pins for the key input interrupt function. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit(cpu) rev.0.60 2004.02.01 page 12 of n rej09b0047-0060z 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1. central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit(cpu) rev.0.60 2004.02.01 page 13 of n rej09b0047-0060z 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0 . 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0 . 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1 . 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0 . 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0 , and are enabled when the i flag is 1 . the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0 ; usp is selected when the u flag is 1 . the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 3. memory rev.0.60 2004.02.01 page 14 of n rej09b0047-0060z 3. memory figure 3.1 is a memory map of the m16c/28 group. the linear address space of 1m bytes extends from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30280f8hp,there are 64 kbytes of internal rom from f0000 16 to fffff 16 . the vector table for fixed interrupts, such as reset and nmi, is mapped from fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table register(intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30280fahp, 8k bytes of internal ram is mapped to the space from 00400 16 to 023ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. these devices also contain two blocks of flash rom as data flash memory to store data. these two blocks of 2k bytes are located from 0f000 16 to 0ffff 16 on all versions. the sfr area is mapped from 00000 16 to 003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is allocated to the address from ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the "m16c/60 and m16c/20 series software manual". figure 3.1. memory map 00000 16 xxxxx 16 fffff 16 00400 16 yyyyy 16 internal rom area (program area) sfr area internal ram area ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc reserved internal rom area (data area) reserved 0f000 16 xxxxx 16 yyyyy 16 f8000 16 00bff 16 internal ram area internal rom area memory size 013ff 16 023ff 16 f4000 16 f0000 16 2k byte 4k byte 8k byte 32k byte 48k byte 64k byte memory size e8000 16 96k byte e0000 16 128k byte (note2) note 1 : the block a (2k bytes) and block b (2k bytes) are shown (only flash memory) note 2 : under planning (note1) 0ffff 16 nmi m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 15 of n rej09b0047-0060z note 1: the blank areas are reserved and cannot be accessed by users. note 2: the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. note 3: tjhe wdc5 bit is "0" (cold start) immediately after power-on. it can only be set to "1" in a program. it is set to "0" when the input voltage at the vcc pin drops to vdet2 or less while the vc25 bit in the vcr2 register is set to "1"(ram retention limit dete ction circuit enable). note 4: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. x : noting is mapped to this bit ? : value indeterminate at reset 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register name acronym value after reset processor mode register 0 pm0 00 16 processor mode register 1 pm1 00001000 2 system clock control register 0 cm0 01001000 2 system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr xx000000 2 oscillation stop detection register (note 2) cm2 0x000010 2 watchdog timer start register wdts ?? 16 watchdog timer control register wdc 00?????? 2 (note 3) address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 voltage detection register 1 (note 4) vcr1 00001000 2 voltage detection register 2 (note 4) vcr2 00 16 pll control register 0 plc0 0001x010 2 processor mode register 2 pm2 xxx00000 2 voltage down detection interrupt register d4int 00 16 dma0 source pointer sar0 ?? 16 ?? 16 x? 16 dma0 destination pointer dar0 ?? 16 ?? 16 x? 16 dma0 transfer counter tcr0 ?? 16 ?? 16 dma0 control register dm0con 00000?00 2 dma1 source pointer sar1 ?? 16 ?? 16 x? 16 dma1 destination pointer dar1 ?? 16 ?? 16 x? 16 dma1 transfer counter tcr1 ?? 16 ?? 16 dma1 control register dm1con 00000?00 2 4. special function register (sfr) map figure 4.1. sfr map (1 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 16 of n rej09b0047-0060z int3 interrupt control register int3ic xx00?000 2 ic/oc 0 interrupt control register icoc0ic xxxx?000 2 ic/oc 1 interrupt control register, i 2 c-bus interface interrupt control register icoc1ic, iicic x xxx?000 2 ic/oc base timer interrupt control register, s cl s da interrupt control register btic, scldaic xxxx?000 2 si/o4 interrupt control register, int5 interrupt control register s4ic, int5ic xx00?000 2 si/o3 interrupt control register, int4 interrupt control register s3ic, int4ic xx00?000 2 uart2 bus collision detection interrupt control register bcnic xxxx?000 2 dma0 interrupt control register dm0ic xxxx?000 2 dma1 interrupt control register dm1ic xxxx?000 2 key input interrupt control register kupic xxxx?000 2 a-d conversion interrupt control register adic xxxx?000 2 uart2 transmit interrupt control register s2tic xxxx?000 2 uart2 receive interrupt control register s2ric xxxx?000 2 uart0 transmit interrupt control register s0tic xxxx?000 2 uart0 receive interrupt control register s0ric xxxx?000 2 uart1 transmit interrupt control register s1tic xxxx?000 2 uart1 receive interrupt control register s1ric xxxx?000 2 timer a0 interrupt control register ta0ic xxxx?000 2 timer a1 interrupt control register ta1ic xxxx?000 2 timer a2 interrupt control register ta2ic xxxx?000 2 timer a3 interrupt control register ta3ic xxxx?000 2 timer a4 interrupt control register ta4ic xxxx?000 2 timer b0 interrupt control register tb0ic xxxx?000 2 timer b1 interrupt control register tb1ic xxxx?000 2 timer b2 interrupt control register tb2ic xxxx?000 2 int0 interrupt control register int0ic xx00?000 2 int1 interrupt control register int1ic xx00?000 2 int2 interrupt control register int2ic xx00?000 2 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register name acronym value after reset note 1: the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset figure 4.2. sfr map (2 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 17 of n rej09b0047-0060z 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02fe 16 02ff 16 note 1:the blank areas are reserved and cannot be accessed by users. note 2:this register is included in the flash memory version. x : noting is mapped to this bit ? : value indeterminate at reset address register name acronym value after reset flash memory control register 4 (note 2) fmr4 01000000 2 flash memory control register 1 (note 2) fmr1 000???0? 2 flash memory control register 0 (note 2) fmr0 ??000001 2 ring oscillator control register rocr 00000101 2 pin assignment control register pacr 00 16 peripheral clock select register pclkr 00000011 2 i 2 c0 data shift register s00 ?? 16 i 2 c0 address register s0d0 00 16 i 2 c0 control register 0 s1d0 00 16 i 2 c0 clock control register s20 00 16 i 2 c0 start/stop condition control register s2d0 00011010 2 i 2 c0 control register 1 s3d0 00110000 2 i 2 c0 control register 2 s4d0 00 16 i 2 c0 status register s10 0001000x 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 4.3. sfr map (3 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 18 of n rej09b0047-0060z note 1:the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 tm/wg register 0 g1tm0/g1po0 ?? 16 ?? 16 tm/wg register 1 g1tm1/g1po1 ?? 16 ?? 16 tm/wg register 2 g1tm2/g1po2 ?? 16 ?? 16 tm/wg register 3 g1tm3/g1po3 ?? 16 ?? 16 tm/wg register 4 g1tm4/g1po4 ?? 16 ?? 16 tm/wg register 5 g1tm5/g1po5 ?? 16 ?? 16 tm/wg register 6 g1tm6/g1po6 ?? 16 ?? 16 tm/wg register 7 g1tm7/g1po7 ?? 16 ?? 16 wg control register 0 g1pocr0 0x00x000 2 wg control register 1 g1pocr1 0x00x000 2 wg control register 2 g1pocr2 0x00x000 2 wg control register 3 g1pocr3 0x00x000 2 wg control register 4 g1pocr4 0x00x000 2 wg control register 5 g1pocr5 0x00x000 2 wg control register 6 g1pocr6 0x00x000 2 wg control register 7 g1pocr7 0x00x000 2 tm control register 0 g1tmcr0 00 16 tm control register 1 g1tmcr1 00 16 tm control register 2 g1tmcr2 00 16 tm control register 3 g1tmcr3 00 16 tm control register 4 g1tmcr4 00 16 tm control register 5 g1tmcr5 00 16 tm control register 6 g1tmcr6 00 16 tm control register 7 g1tmcr7 00 16 base timer register g1bt ?? 16 ?? 16 base timer control register 0 g1bcr0 00 16 base timer control register 1 g1bcr1 00 16 tm prescale register 6 g1tpr6 00 16 tm prescale register 7 g1tpr7 00 16 function enable register g1fe 00 16 function select register g1fs 00 16 base timer reset register g1btrr ?? 16 ?? 16 divider register g1dv 00 16 interrupt request register g1ir ?? 16 interrupt enable register 0 g1ie0 00 16 interrupt enable register 1 g1ie1 00 16 nmi digital debounce register nddr ff 16 p17 digital debounce register p17ddr ff 16 address register name acronym value after reset figure 4.4. sfr map (4 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 19 of n rej09b0047-0060z 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 note 1: the blank areas are reserved and cannot be accessed by users. note 2: write "1" to bit 0 after reset. x : noting is mapped to this bit ? : value indeterminate at reset timer a1-1 register ta11 ?? 16 ?? 16 timer a2-1 register ta21 ?? 16 ?? 16 timer a4-1 register ta41 ?? 16 ?? 16 three-phase pwm control register 0 invc0 00 16 three-phase pwm control register 1 invc1 00 16 three-phase output buffer register 0 idb0 00 16 three-phase output buffer register 1 idb1 00 16 dead time timer dtt ?? 16 timer b2 interrupt occurrence frequency set counter ictb2 x? 16 position-data-retain function contol register pdrf xxxx0000 2 interrupt request cause select register 2 ifsr2a 00xxxxxx 2 (note 2) interrupt request cause select register ifsr 00 16 si/o3 transmit/receive register s3trr ?? 16 si/o3 control register s3c 01000000 2 si/o3 bit rate generator s3brg ?? 16 si/o4 transmit/receive register s4trr ?? 16 si/o4 control register s4c 01000000 2 si/o4 bit rate generator s4brg ?? 16 uart2 special mode register 4 u2smr4 00 16 uart2 special mode register 3 u2smr3 000x0x0x 2 uart2 special mode register 2 u2smr2 x0000000 2 uart2 special mode register u2smr x0000000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 bit rate generator u2brg ?? 16 uart2 transmit buffer register u2tb ???????? 2 xxxxxxx? 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 receive buffer register u2rb ???????? 2 ?????xx? 2 address register name acronym value after reset figure 4.5. sfr map (5 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 20 of n rej09b0047-0060z 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 one-shot start flag onsf 00 16 trigger select register trgsr 00 16 up-down flag udf 00 16 timer a0 register ta0 ?? 16 ?? 16 timer a1 register ta1 ?? 16 ?? 16 timer a2 register ta2 ?? 16 ?? 16 timer a3 register ta3 ?? 16 ?? 16 timer a4 register ta4 ?? 16 ?? 16 timer b0 register tb0 ?? 16 ?? 16 timer b1 register tb1 ?? 16 ?? 16 timer b2 register tb2 ?? 16 ?? 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 timer b0 mode register tb0mr 00??0000 2 timer b1 mode register tb1mr 00?x0000 2 timer b2 mode register tb2mr 00?x0000 2 timer b2 special mode register tb2sc x0000000 2 uart0 transmit/receive mode register u0mr 00 16 uart0 bit rate generator u0brg ?? 16 uart0 transmit buffer register u0tb ???????? 2 xxxxxxx? 2 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart0 receive buffer register u0rb ???????? 2 ?????xx? 2 uart1 transmit/receive mode register u1mr 00 16 uart1 bit rate generator u1brg ?? 16 uart1 transmit buffer register u1tb ???????? 2 xxxxxxx? 2 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart1 receive buffer register u1rb ???????? 2 ?????xx? 2 uart transmit/receive control register 2 ucon x0000000 2 dma0 request cause select register dm0sl 00 16 dma1 request cause select register dm1sl 00 16 address register name acronym value after reset note 1:the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset figure 4.6. sfr map (6 of 7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.60 2004.02.01 page 21 of n rej09b0047-0060z figure 4.7. sfr map (7 of 7) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d register 0 ad0 ???????? 2 xxxxxx?? 2 a-d register 1 ad1 ???????? 2 xxxxxx?? 2 a-d register 2 ad2 ???????? 2 xxxxxx?? 2 a-d register 3 ad3 ???????? 2 xxxxxx?? 2 a-d register 4 ad4 ???????? 2 xxxxxx?? 2 a-d register 5 ad5 ???????? 2 xxxxxx?? 2 a-d register 6 ad6 ???????? 2 xxxxxx?? 2 a-d register 7 ad7 ???????? 2 xxxxxx?? 2 a-d trigger control register adtrgcon xxxx0000 2 a-d convert status register 0 adstat0 00000x00 2 a-d control register 2 adcon2 00 16 a-d control register 0 adcon0 00000??? 2 a-d control register 1 adcon1 00 16 port p0 register p0 ?? 16 port p1 register p1 ?? 16 port p0 direction register pd0 00 16 port p1 direction register pd1 00 16 port p2 register p2 ?? 16 port p3 register p3 ?? 16 port p2 direction register pd2 00 16 port p3 direction register pd3 00 16 port p6 register p6 ?? 16 port p7 register p7 ?? 16 port p6 direction register pd6 00 16 port p7 direction register pd7 00 16 port p8 register p8 ?? 16 port p9 register p9 ???x???? 2 port p8 direction register pd8 00 16 port p9 direction register pd9 000x0000 2 port p10 register p10 ?? 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00 16 pull-up control register 2 pur2 00 16 port control register pcr 00 16 note 1:the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset address register name acronym value after reset m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 22 of n rej09b0047-0060z 5. reset there are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla- tion stop detection reset. 5.1 hardware reset there are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 hardware reset 1 ____________ ____________ a reset is applied using the reset pin. when an l signal is applied to the reset pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see ____________ table 5.1.1.1 pin status when reset pin level is l ). the internal ring oscillator is initialized and used as sysem clock. ____________ when the input level at the reset pin is released from l to h , the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. the internal ram ____________ is not initialized. if the reset pin is pulled l while writing to the internal ram, the internal ram becomes indeterminate. figure 5.1.1.1 shows the example reset circuit. figure 5.1.1.2 shows the reset sequence. table ____________ 5.1.1.1 shows the status of the other pins while the reset pin is l . figure 5.1.1.3 shows the cpu register status after reset. refer to sfr map for sfr status after reset. 1. when the power supply is stable ____________ (1) apply an l signal to the reset pin. (2) wait td(roc) or more. ____________ (3) apply an h signal to the reset pin. 2. power on ____________ (1) apply an l signal to the reset pin. (2) let the power supply voltage increase until it meets the recommended operating condition. (3) wait td(p-r) or more until the internal power supply stabilizes. (4) wait td(roc) or more. ____________ (5) apply an h signal to the reset pin. 5.1.2 hardware reset 2 this reset is generated by the microcomputer s internal voltage detection circuit. the voltage detec- tion circuit monitors the voltage supplied to the v cc pin. if the vc26 bit in the vcr2 register is set to 1 (reset level detection circuit enabled), the microcom- puter is reset when the voltage at the v cc input pin drops below vdet3. similarly, if the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit en- abled), the microcomputer is reset when the voltage at the vcc input pin drops below vdet2. conversely, when the input voltage at the v cc pin rises to vdet3 or more, the pins and the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. it takes about td(s-r) before the program starts running after vdet3 is detected. the initialized pins and registers and the status thereof are the same as in hardware reset 1. set the cm10 bit in the cm1 register to 1 (stop mode) after setting the vc25 bit to 1 (ram retention limit detection circuit enabled), and the microcomputer will be reset when the voltage at the vcc input pin drops below vdet2 and comes out of reset when the voltage at the v cc input pin rises above vdet3. during stop mode, the value set in the vc26 bit has no effect. therefore, no reset is generated even when the input voltage at the v cc pin drops to vdet3 or less. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 23 of n rej09b0047-0060z 5.2 software reset when the pm03 bit in the pm0 register is set to 1 (microcomputer reset), the microcomputer has its pins, cpu, and sfr initialized. then the program is executed starting from the address indicated by the reset vector. the device will reset using internal ring oscillator as the system clock. at software reset, some sfr s are not initialized. refer to sfr . 5.3 watchdog timer reset when the pm12 bit in the pm1 register is 1 (reset when watchdog timer underflows), the microcomputer initializes its pins, cpu and sfr if the watchdog timer underflows. the device will reset using internal ring oscillator as the system clock. then the program is executed starting from the address indicated by the reset vector. at watchdog timer reset, some sfr s are not initialized. refer to sfr . 5.4 oscillation stop detection reset when the cm27 bit in the cm2 register is 0 (reset at oscillation stop detection), the microcomputer initializes its pins, cpu and sfr, coming to a halt if it detects main clock oscillation circuit stop. refer to the section oscillation stop, re-oscillation detection function . at oscillation stop detection reset, some sfr s are not initialized. refer to the section sfr . figure 5.1.1.1. example reset circuit reset v cc reset v cc 0v 0v more than td(roc) + td(p-r) equal to or less than 0.2v cc equal to or less than 0.2v cc recommended operating voltage m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 24 of n rej09b0047-0060z ____________ table 5.1.1.1. pin status when reset pin level is l status pin name p0 to p3, p6 to p10 input port (high impedance) figure 5.1.1.3. cpu register status after reset b15 b0 data register(r0) address register(a0) frame base register(fb) program counter(pc) interrupt table register(intb) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) flag register(flg) 0000 16 0000 16 0000 16 aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl 0000 16 0000 16 0000 16 0000 16 0000 16 b19 b0 content of addresses ffffe 16 to ffffc 16 b15 b0 b15 b0 b15 b0 b7 b8 00000 16 data register(r1) data register(r2) data register(r3) address register(a1) 0000 16 0000 16 0000 16 figure 5.1.1.2. reset sequence td(p-r) more than td(roc) cpu clock address roc reset content of reset vector cpu clock 28cycles ffffe 16 ffffc 16 v cc m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 25 of n rej09b0047-0060z 5.5 voltage detection circuit the voltage detection circuit has circuits to monitor the input voltage at the v cc pin, each checking the input voltage with respect to vdet2, vdet3, and vdet4, respectively. use the vc25 to vc27 bits in the vcr2 register to select whether or not to enable these circuits. the vc25 bit in the vcr2 register needs to be set to 1 (the internal ram retention limit detection circuit enable) when using hardware reset 2 in stop mode, or when using the wdc5 bit. wdc5 bit = 1 shows state of the internal ram retention.use the reset level detection circuit for hardware reset 2. the voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than vdet4 or less than vdet4 by monitoring the vc13 bit in the vcr1 register. furthermore, a voltage down detection interrupt can be generated. figure 5.5.1. voltage detection circuit block b7 b6 b5 vcr2 register reset cm10 bit=1 (stop mode) + e vdet2 + vdet3 + vdet4 e noise rejection voltage down detection interrupt b3 vcr1 register vc13 bit internal power on reset write to wdc register s r q warm/cold >t q 1 shot td(s-r) internal reset signal ( l active) wdc5 bit internal power supply voltage stable time e (cold start, warm start) v cc t d q half latch figure 5.5.2. wdc register watchdog timer control register symbol address after reset wdc 000f 16 00xxxxxx 2 (note 2) function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit must set to 0 0 ro rw rw rw cold start / warm start discrimination flag (note 1, 2) 0 : cold start 1 : warm start wdc5 note 1: writing to the wdc register causes the wdc5 bit to be set to 1 (warm start). note 2: the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 when the input voltage at the v cc pin drops to v det 2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enable). (b4-b0) (b6) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 26 of n rej09b0047-0060z figure 5.5.3. vcr1 register, vcr2 register, and d4int register vc13 voltage detection register 1 symbol address after reset (note 2) vcr1 0019 16 00001000 2 voltage down monitor flag (note 1) bit name function bit symbol rw b7 b 6 b 5 b4 b 3 b 2 b1 b 0 note 1: the vc13 bit is useful when the vc27 bit of vcr2 register is set to 1 (voltage down detection circuit enable). the vc13 bit is always 1 (v cc vdet4) when the vc27 bit in the vcr2 register is set to 0 (voltage down detection circuit disable). note 2: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 0:v cc < vdet4 1:v cc vdet4 ro 0 0 0 0 0 0 0 rw rw reserved bit reserved bit must set to 0 must set to 0 voltage detection register 2 (note 1) symbol address after reset (note 6) vcr2 001a 16 00 16 bit name bit symbol b7 b 6 b 5 b4 b 3 b 2 b1 b 0 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: when not in stop mode, to use hardware reset 2, set the vc26 bit to 1 (reset level detection circuit enable). note 3: to use hardware reset 2 in stop mode, set the vc25 bit to 1 (ram retention limit detection circuit enable). vc26 bit is disabled in stop mode. (the microcomputer is not reset even if the voltage input to vcc 1 pin becomes lower than vdet3.) note 4: to use the wdc5 bit in the wdc register, set the vc25 bit to 1 (ram retention limit detection circuit enable). note 5: when the vc13 bit in the vcr1 register and d42 bit in the d4int register are used or the d40 bit is set to 1 (voltage down detection interrupt enable), set the vc27 bit to 1 (voltage down detection circuit enable). note 6: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. note 7: the detection circuit does not start o p eration until td ( e-a ) ela p ses after the vc25 bit , vc26 bit , or vc27 bit are vc25 ram retention limit detection monitor bit (notes 3, 4, 7) 0: disable ram retention limit detection circuit 1: enable ram retention limit detection circuit vc26 vc27 rw rw rw rw rw 0 0 0 0 0 function reserved bit must set to 0 reset level monitor bit (notes 2, 3, 7) 0: disable reset level detection circuit 1: enable reset level detection circuit voltage down monitor bit (note 5) 0: disable voltage down detection circuit 1: enable voltage down detection circuit (b2-b0) (b7-b4) (b4-b0) d40 voltage down detection interrupt register (note 1) symbol address after reset d4int 001f 16 00 16 voltage down detection interrupt enable bit (note 5) bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : disable 1 : enable d41 stop mode deactivation control bit (note 4) 0: disable (do not use the voltage down detection interrupt to get out of stop mode) 1: enable (use the voltage down detection interrupt to get out of stop mode) d42 voltage change detection flag (note 2) 0: not detected 1: vdet4 passing detection d43 wdt overflow detect flag 0: not detected 1: detected df0 sampling clock select bit 00 : cpu clock divided by 8 01 : cpu clock divided by 16 10 : cpu clock divided by 32 11 : cpu clock divided by 64 df1 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: useful when the vc27 bit in the vcr2 register is set to 1 (voltage down detection circuit enabled). if the vc27 bit is set to 0 (voltage down detection circuit disable), the d42 bit is set to 0 (not detect). note 3: this bit is set to 0 by writing a 0 in a program. (writing a 1 has no effect.) note 4: if the voltage down detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the d41 bit by writing a 0 and then a 1 . note 5: the d40 bit is effective when the vcr2 register vc27 bit = 1. to set the d40 bit to 1 , follow the procedure described below. (1) set the vc27 bit to 1 . (2) wait for td(e-a) until the detection circuit is actuated. ( 3 ) wait for the sam p lin g time ( refer to table 5.5.1.2 sam p lin g clock periods ) . b5 b4 rw rw rw rw (note 3) rw rw rw (b7-b6) function (note 3) nothing is assigned. when write, set to 0 . when read, its content is 0 . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 27 of n rej09b0047-0060z figure 5.5.4. typical operation of hardware reset 2 vdet4 vdet3 5.0v 5.0v v cc internal reset signal vc13 bit vc25 bit set to 1 in a program (ram retention limit detection circuit enable) (1) when stop mode is not used 5.0v 5.0v v cc wdc5 bit vc13 bit vc25 bit set to 1 in a program (warm start) set to 1 in a program (ram retention limit detection circuit enable) (1) when stop mode is used internal reset signal cm10 bit set to 1 in a program (stop mode) v ss undefined undefined undefined undefined undefined vc26 bit set to 1 in a program (reset level detection circuit enable) undefined undefined reset vdet4 vdet3r v ss vdet2 reset vdet3r vdet3s vdet3s vdet2 wdc5 bit set to 1 in a program (warm start) undefined the above diagram applies to the following case: ? the cm10 bit in the cm1 register =0 (clock oscillating, not in stop mode) ? the vc27 bit in the vcr2 register is set to 1 after reset (voltage down detection circuit enabled)(to use vc13) the above diagram applies to the following case: ? the vc27 bit in the vcr2 register is set to 1 after reset (voltage down detection circuit enabled)(to use vc13) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 28 of n rej09b0047-0060z 5.5.1 voltage detection interrupt a voltage down detection interrupt request is generated when the input voltage at the v cc pin rises to vdet4 or more or drops below vdet4 while the d40 bit in the d4int register is set to 1 (voltage down detection interrupt enable). the voltage down detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt. to use the voltage down detection interrupt to get out of stop mode, set the d41 bit in the d4int register to 1 (enable). the d42 bit in the d4int register becomes 1 when passing through vdet4 is detected after the voltage inputted to the v cc pin is up or down. a voltage down detection interrupt is generated when the d42 bit changes state from 0 to 1 . the d42 bit needs to be cleared to 0 by software. however, when d41 bit is 1 and the microcontroller is in stop mode, if the voltage down detection interrupt occurs (due to voltage applied at v cc increases, passing through vdet4), the microcontroller awakes from stop mode with no regard to the status of the d42 bit. table 5.5.1.1 shows the voltage down detection interrupt request generation conditions. it is possible to set the sampling clock detecting that the voltage applied to the v cc pin has passed through vdet4 with the df1 to df0 bits of d4int register. table 5.5.1.2 shows sampling clock periods. table 5.5.1.1. voltage detection interrupt request generation conditions d41 bit vc27 bit operation mode d40 bit d42 bit cm02 bit vc13 bit normal operation mode(note 1) wait mode (note 2) stop mode (note 2) note 1: the status except the wait mode and stop mode is handled as the normal mode.(refer to clock generating circuit ) note 2: refer to limitations on stop mode , limitations on wait mode . note 3: an interrupt request for voltage reduction is generated a sampling time after the value of the vc13 bit has changed. refer to the figure 5.5.1.1.2.2.voltage down detection interrupt generation circuit operation example for details. 0 to 1 1 0 1 1 0 1 to 0 0 to 1 1 to 0 0 to 1 0 to 1 0 to 1 0 to 1 1 (note 3) (note 3) (note 3) (note 3) C : 0 or 1 table 5.5.1.2. sampling clock periods cpu clock (mhz) df1 to df0=00 (cpu clock divided by 8) sampling clock (s) 16 3.0 6.0 12.0 24.0 df1 to df0=01 (cpu clock divided by 16) df1 to df0=10 (cpu clock divided by 32) df1 to df0=11 (cpu clock divided by 64) 5.5.1.1 precautions 5.5.1.1.1. limitations on stop mode before setting the cm10 bit in the cm1 register to 1 (stop mode), be sure to clear the cm02 bit in the cm0 register to 0 (do not stop the peripheral function clock). if the cm10 bit in the cm1 register is set to 1 (stop mode) when the vc13 bit in the vcr1 register is 1 (v cc vdet4) while the vc27 bit in the vcr2 register is 1 (voltage down detection circuit enable) and the d40 bit in the d4int register is 1 (voltage down detection interrupt enable) and d41 bit in the d4int register is 1 (voltage down detection interrupt is used to get out of stop mode), a voltage down detection interrupt is immediately generated, causing the microcomputer to exit stop mode. in systems where the microcomputer enters stop mode when the input voltage at the v cc pin drops below vdet4 and exits stop mode when the input voltage rises to vdet4 or more, make sure the cm10 bit is set to 1 when vc13 bit is 0 (v cc < vdet4). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. reset rev.0.60 2004.02.01 page 29 of n rej09b0047-0060z 5.5.1.1.2. limitations on wait instruction if the wait instruction is executed when the vc13 bit in the vcr1 register is 1 (v cc vdet4) while the vc27 bit in the vcr2 register is 1 (voltage down detection circuit enable) and the d40 bit in the d4int register is 1 (voltage down detection interrupt enable), a voltage down detection interrupt is immediately generated, causing the microcomputer to exit wait mode. in systems where the microcomputer enters wait mode when the input voltage at the v cc pin drops below vdet4 and exits wait mode when the input voltage rises to vdet4 or more, make sure the d42 bit is cleared to "0" when vc13 bit is 0 (v cc < vdet4) before executing the wait instruction. figure 5.5.1.1.2.1. voltage down detection interrupt generation block voltage down detection interrupt generation circuit watchdog timer interrupt signal d42 bit is set to 0 (not detected) by writing a 0 in a program. vc27 bit is set to 0 (voltage down detection circuit disabled), the d42 bit is set to 0 . vc27 vc13 voltage down detection circuit d4int clock(the clock with which it operates also in wait mode) d42 df1, df0 1/2 00 2 01 2 10 2 11 2 1/2 1/2 1/8 non-maskable interrupt signal oscillation stop, re-oscillation detection interrupt signal voltage down detection interrupt signal watchdog timer block this bit is set to 0 (not detected) by writing a 0 in a program. watchdog timer underflow signal d43 d41 cm02 wait instruction(wait mode) d40 v cc v ref + - noise rejection (rejection wide:200 ns) voltage down detection signal h when vc27 bit= 0 (disabled) noise rejection circuit digital filter cm10 figure 5.5.1.1.2.2. voltage down detection interrupt generation circuit operation example output of the digital filter (note 2) d42 bit note 1 : d40 is 1 (voltage down detection interrupt enabled) note 2 : output of the digital filter shown in figure 1.5.8. voltage down detection interrupt signal no voltage down detection interrupt signals are generated when the d42 bit is h . sampling set to 0 in a program (not detected) vc13 bit v cc sampling sampling sampling set to 0 in a program (not detected) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 6. processor mode rev.0.60 2004.02.01 page 30 of n rej09b0047-0060z 6. processor mode this device functions in single-chip mode only. figures 6.1 and 6.2 detail the associated registers. figure 6.2. pm1 register processor mode register 1 (note 1) symbol address after reset pm1 0005 16 0000100 0 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 flash data block access bit (note 2) 0: disabled 1: enabled (note 3) pm10 rw pm17 wait bit (note 5) 0 : no wait state 1 : with wait state (1 wait) 0 : watchdog timer interrupt 1 : watchdog timer reset (note 4) watchdog timer function select bit pm12 rw rw rw rw rw note 1: write to this register after setting the prc1 bit in the prcr register to "1" (write enable). note 2: to access the two 2k-byte data areas in data block a and data block b, this bit must be set to "1". note 3: when cpu rewrite mode (fmr01="1"), this bit is automatically set to "1" during that time. note 4: pm12 bit is set to 1 by writing a 1 in a program. (writing a 0 has no effect.) note 5: when pm17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal ram or the internal rom. should be set to "0". (b1) reserved bit should be set to "1". reserved bit should be set to "0". (b6-b4) reserved bit (b3) 0 1 0 figure 6.1. pm0 register processor mode register 0 (note) symbol address after reset pm0 0004 16 0000000 0 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 setting this bit to "1" resets the microcomputer. when read, its content is "0". software reset bit pm03 rw rw rw note: write to this register after setting the prc1 bit in the prcr register to "1" (write enable). should be set to "0". (b2-b0) reserved bit should be set to "0". (b7-b4) reserved bit 000 0 000 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 31 of n rej09b0047-0060z cpu clock source peripheral function clock source use of clock main clock oscillation circuit sub clock oscillation circuit item cpu clock source timer a, b s clock source clock frequency 0 to 20 mhz 32.768 khz ceramic oscillator crystal oscillator usable oscillator crystal oscillator x in , x out pins to connect oscillator x cin , x cout presence oscillation stop, restart function presence oscillating oscillator status after reset stopped externally derived clock can be input other pll frequency synthesizer 10 to 20 mhz presence stopped variable ring oscillator cpu clock source peripheral function clock source cpu and peripheral function clock sources when the main clock stops oscillating selectable source frequency: f 1(roc) , f 2(roc) , f 3(roc) selectable divider: by 2, by 4, by 8 presence oscillating cpu clock source peripheral function clock source (cpu clock source) 7. clock generation circuit the clock generation circuit contains four oscillator circuits as follows: (1) main clock oscillation circuit (2) sub clock oscillation circuit (3) variable ring oscillator (available at reset, oscillation stop detect function) (4) pll frequency synthesizer table 7.1 lists the clock generation circuit specifications. figure 7.1 shows the clock generation circuit. figures 7.2 to 7.6 show the clock-related registers. table 7.1. clock generation circuit specifications m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 32 of n rej09b0047-0060z variable ring oscillator f c32 cm02, cm04, cm05, cm06, cm07: cm0 register bits cm10, cm11, cm16, cm17: cm1 register bits pclk0, pclk1: pclk register bits cm21, cm27 : cm2 register bits 1/32 main clock generating circuit f c cm02 cm04 cm10=1(stop mode) q s r wait instruction cm05 q s r nmi interrupt request level judgment output reset software reset f c cpu clock cm07 = 0 cm07 = 1 divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17 cm16=00 2 cm06=0 cm17 cm16=01 2 cm06=0 cm17 cm16=10 2 cm06=1 cm06=0 cm17 cm16=11 2 d a details of divider sub-clock generating circuit x cin x cout x out x in f 8 f 32 c b b 1/2 c f 32sio f 8sio f ad f 1 e e 1/2 1/4 1/8 1/16 1/32 pclk0=1 pll frequency synthesizer 0 1 cm21=1 cm11 cm21=0 pll clock sub-clock ring oscillator clock pclk0=0 f 2 f 1sio pclk1=1 pclk1=0 f 2sio main clock rocr0,rocr1 rocr2, rocr3 oscillation stop, re- oscillation detection circuit d4int clock bclk figure 7.1. clock generation circuit phase comparator charge pump voltage control oscillator (vco) pll clock main clock 1/2 programmable counter internal low- pass filter pll frequency synthesizer pulse generation circuit for clock edge detection and charge, discharge control charge, discharge circuit reset generating circuit oscillation stop, re-oscillation detection interrupt generating circuit main clock oscillation stop detection reset cm27=0 cm21 switch signal oscillation stop, re-oscillation detection signal oscillation stop, re-oscillation detection circuit cm27=1 1/2 1/2 1/2 rocr3 rocr2=11 2 ring oscillator clock 1/8 1/4 1/2 rocr3 rocr2=10 2 rocr3 rocr2=01 2 rocr1 rocr0=00 2 f 1(roc) f 2(roc) f 3(roc) rocr1 rocr0=01 2 rocr1 rocr0=11 2 variable ring oscillator m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 33 of n rej09b0047-0060z 0 system clock control register 0 (note 1) symbol address after reset cm0 0006 16 01001000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm07 cm05 cm04 cm03 cm02 cm06 wait mode peripheral function clock stop bit (note 10) 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high 0 : i/o port p8 6 , p8 7 1 : x cin -x cout generation function(note 9) main clock stop bit (notes 3, 10, 12, 13) 0 : on (note 4) 1 : off (note5) main clock division select bit 0 (notes 7, 13, 14) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (notes 6, 10, 11, 12) 0 : main clock, pll clock, or ring oscillator clock 1 : sub-clock note 1: write to this register after setting the prc0 bit of prcr register to 1 ? (write enable). note 2: the cm03 bit is set to 1 ? (high) when the cm04 bit is set to 0 ? (i/o port) or the microcomputer goes to a stop mode. note 3: this bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipatio n mode is selected. this bit cannot be used for detection as to whether the main clock stopped or not. to stop the main clock, the following setting is required: (1) set the cm07 bit to 1 ? (sub-clock select) or the cm21 bit of cm2 register to 1 ? (ring oscillator select) with the sub-cl ock stably oscillating. (2) set the cm20 bit of cm2 register to 0 ? (oscillation stop, re-oscillation detection function disabled). (3) set the cm05 bit to 1 ? (stop) . note 4: during external clock input, set to "0"(on). note 5: when cm05 bit is set to 1, the x out pin goes h ? . furthermore, because the internal feedback resistor remains connected, the x in pin is pulled h ? to the same level as x out via the feedback resistor. note 6: after setting the cm04 bit to 1 ? (x cin -x cout oscillator function), wait until the sub-clock oscillates stably before switching the cm07 bit from 0 ? to 1 ? (sub-clock). note 7: when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the cm0 6 bit is set to 1 ? (divide-by-8 mode). note 8: the f c32 clock does not stop. during low speed or low power dissipation mode, do not set this bit to 1 ? (peripheral clock turned off when in wait mode). note 9: to use a sub-clock, set this bit to 1 ? . also make sure ports p8 6 and p8 7 are directed for input, with no pull-ups. note 10: when the pm21 bit of pm2 register is set to 1 ? (clock modification disable), writing to the cm02, cm05, and cm07 bits has no effect. note 11: if the pm21 bit needs to be set to 1 ? , set the cm07 bit to 0 ? (main clock) before setting it. note 12: to use the main clock as the clock source for the cpu clock, follow the procedure below. (1) set the cm05 bit to 0 ? (oscillate) . (2) wait until td(m-l) elapses or the main clock oscillation stabilizes, whichever is longer. (3) set the cm11, cm21 and cm07 bits all to 0 ? . note 13: when the cm21 bit = 0 (ring oscillaor turned off) and the cm05 bit = 1 (main clock turned off), the cm06 bit is fixed to "1" (divide-by-8 mode) and the cm15 bit is fixed to "1" (drive capability high). note 14: to return from ring oscillator mode to high-speed or middle-speed mode set the cm06 and cm15 bits both to "1". rw port x c select bit (note 2) rw rw rw rw rw rw rw reserved bits must set to "0" (b1-b0) 0 figure 7.2. cm0 register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 34 of n rej09b0047-0060z system clock control register 1 (note 1) symbol address after reset cm1 0007 16 00100000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (notes 4, 6) 0 : clock on 1 : all clocks off (stop mode) note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: when entering stop mode from high or middle speed mode, or when the cm05 bit is set to 1 (main clock turned off) in low speed mode, the cm15 bit is set to 1 (drive capability high). note 3: effective when the cm06 bit is 0 (cm16 and cm17 bits enable). note 4: if the cm10 bit is 1 (stop mode), x out goes h and the internal feedback resistor is disconnected. the x cin and x cout pins are placed in the high-impedance state. when the cm11 bit is set to 1 (pll clock), or the cm20 bit of cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the cm10 bit to 1 . note 5: after setting the plc07 bit in plc0 register to 1 (pll operation), wait until tsu (pll) elapses before setting the cm11 bit to 1 (pll clock). note 6: when the pm21 bit of pm2 register is set to 1 (clock modification disable), writing to the cm10, cm011 bits has no effect. when the pm22 bit of pm2 register is set to 1 (watchdog timer count source is ring oscillator clock), writing to the cm10 bit has no effect. note 7: effective when cm07 bit is 0 and cm21 bit is 0 . cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high rw cm16 cm17 reserved bit must set to 0 main clock division select bits (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 00 cm11 system clock select bit 1 (notes 6, 7) 0 : main clock 1 : pll clock (note 5) rw rw rw rw rw rw (b4-b2) figure 7.3. cm1 register figure 7.4. rocr register b7 b6 b5 b4 b3 b2 b1 b0 rw rocr0 rocr1 ring oscillator control register (note 1) symbol address after reset rocr 025c 16 00000101 2 bit name function bit symbol frequency select bits rw rw reserved bit (b7-b4) must set to 0 rw 00 00 0 0 : f 1 (roc) 0 1 : f 2 (roc) 1 0 : not supported 1 1 : f 3 (roc) b1 b0 rocr2 rocr3 divider select bits rw rw 0 0 : not supported 0 1 : divide by 2 1 0 : divide by 4 1 1 : divide by 8 b3 b2 note 1 : write to this register after setting the prc0 bit of prcr register to "1" (write enable). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 35 of n rej09b0047-0060z b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 oscillation stop detection register (note 1) symbol address after reset cm2 000c 16 0x000010 2 bit name function bit symbol system clock select bit 2 (notes 2, 3, 6, 8, 11, 12 ) 0: oscillation stop, re-oscillation detection function disabled 1: oscillation stop, re-oscillation detection function enabled 0: main clock or pll clock 1: ring oscillator clock (ring oscillator oscillating) oscillation stop, re- oscillation detection bit (notes 7, 9, 10, 11) note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), and the cpu clock source is the main clock, the cm21 bit is automatically set to 1 (ring oscillator clock) if the main clock stop is detected. note 3: if the cm20 bit is 1 and the cm23 bit is 1 (main clock not oscillating), do not set the cm21 bit to 0 . note 4: this flag is set to 1 when the main clock is detected to have stopped or when the main clock is detected to have restarted oscillating. when this flag changes state from 0 to 1 , an oscillation stop, reoscillation restart detection interrupt is generated. use this flag in an interrupt routine to discriminate the causes of interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog timer interrupt. the flag is cleared to 0 by writing a 0 in a program. (writing a 1 has no effect. nor is it cleared to 0 by an oscillation stop or an oscillation restart detection interrupt request acknowledged.) if when the cm22 bit = 1 an oscillation stoppage or an oscillation restart is detected, no oscillation stop, reoscillation restart detection interrupts are generated. note 5: read the cm23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. note 6: effective when the cm07 bit of cm0 register is 0 . note 7: when the pm21 bit of pm2 register is 1 (clock modification disabled), writing to the cm20 bit has no effect. note 8: when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), and the cm11 bit is 1 (the cpu clock source is pll clock), the cm21 bit remains unchanged even when main clock stop is detected. if the cm22 bit is 0 under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the cm21 bit to 1 (ring oscillator clock) inside the interrupt routine. note 9: set the cm20 bit to 0 (disable) before entering stop mode. after exiting stop mode, set the cm20 bit back to 1 (enable). note 10: set the cm20 bit to 0 (disable) before setting the cm05 bit of cm0 register. note 11: the cm20, cm21 and cm27 bits do not change at oscillation stop detection reset. note 12: when the cm21 bit = 0 (ring oscillator turned off) and the cm05 bit = 1 (main clock turned off), the cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high). cm22 cm23 oscillation stop, re- oscillation detection flag 0: main clock stop,or re-oscillation not detected 1: main clock stop,or re-oscillation detected 0: main clock oscillating 1: main clock not oscillating x in monitor flag (note 4) cm27 0: oscillation stop detection reset 1: oscillation stop, re-oscillation detection interrupt nothing is assigned. when write, set to 0 . when read, its content is indeterminate. operation select bit (when an oscillation stop, re-oscillation is detected) (note 11) rw rw rw rw ro (b6) (note 5) reserved bit (b5-b4) must set to 0 rw 00 figure 7.5. cm2 register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 36 of n rej09b0047-0060z figure 7.6. pclkr register and pm2 register function bit symbol bit name peripheral clock select register (note) symbol address when reset pclkr 025e 16 00000011 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pclk0 timers a, b clock select bit (clock source for the timers a, b, the timer s, and the dead timer) 0 : f 2 1 : f 1 000 reserved bit must set to 0 note: write to this register after setting the prc0 bit of prcr register to 1 (write enable). 000 pclk1 si/o clock select bit (clock source for uart0 to uart2, si/o3, si/o4) 0 : f 2sio 1 : f 1sio rw rw rw (b7-b2) function bit symbol bit name processeor mode register 2 (note 1) symbol address when reset pm2 001e 16 xxx00000 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pm20 specifying wait when accessing sfr during pll operation 0 : 2 wait 1 : 1 wait 00 nothing is assigned. when write, set to 0 . when read, its content is indeterminate. pm21 system clock protective bit 0 : clock is protected by prcr register 1 : clock modification disabled rw rw rw (b7-b5) pm22 pm24 (b3) wdt count source protective bit reserved bit 0 : cpu clock is used for the watchdog timer count source 1 : ring oscillator clock is used for the watchdog timer count source must set to 0 p8 5 /nmi configuration bit rw rw (note 2) (note 3,4) (note 3,5) (note 6,7) note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note 2: this bit can only be rewritten while the plc07 bit is 0 (pll turned off). also, to select a 16mhz or higher pll clock or sytem clock, set this bit to 0 (2 wait). note 3: once this bit is set to 1 , it cannot be cleared to 0 in a program. note 4: setting the pm21 bit to 1 results in the following conditions: ? the bclk is not halted by executing the wait instruction. ? writting to the following bits has no effect. cm02 bit of cm0 register cm05 bit of cm0 register (main clock is not halted) cm07 bit of cm0 register (cpu clock source does not change) cm10 bit of cm1 register (stop mode is not entered) cm11 bit of cm1 register (cpu clock source does not change) cm20 bit of cm2 register (oscillation stop, re-oscillation detection function settings do not change) all bit of plc0 register (pll frequency synthesizer setting do not change) note 5: setting the pm22 bit to 1 results in the following conditions: ? the ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. ? the cm10 bit of cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) ? the watchdog timer does not stop when in wait mode. note 6: for nmi function, the pm24 bit must be set to 1 (nmi function) in first instruction after rest. once this bit is set to 1 , it cannot be cleared to 0 in a program. when the pm24 bit is set to 1 , the p8 5 direction register must be 0 . note 7: sd input is valid regardless of the pm24 setting. 0 : p8 5 function (nmi disable) 1 : nmi function m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 37 of n rej09b0047-0060z figure 7.7. plc0 register plc00 plc01 plc02 plc07 (note 3) (note 4) function note 1: write to this register after setting the prc0 bit of prcr register to "1" (write enable). note 2: when the pm21 bit of pm2 register is "1" (clock modification disable), writing to this register has no effect. note 3: these three bits can only be modified when the plc07 bit = "0" (pll turned off). the value once written to this bit cannot be modified. note 4: before setting this bit to "1" , set the cm07 bit to "0" (main clock), set the cm17 to cm16 bits to "00 2 " (main clock undivided mode), and set the cm06 bit to "0" (cm16 and cm17 bits enable). pll control register 0 (note 1, note 2) pll multiplying factor select bit nothing is assigned. when write, set to "0". when read, its content is indeterminate. reserved bit operation enable bit 0 0 0: 0 0 1: multiply by 2 0 1 0: multiply by 4 0 1 1: 1 0 0: 1 0 1: 1 1 0: 1 1 1: 0: pll off 1: pll on must set to "1" bit name bit symbol symbol address after reset plc0 001c 16 0001 x010 2 rw b1b0 b2 reserved bit must set to "0" do not set rw rw rw rw rw rw do not set (b4) (b6-b5) (b3) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 38 of n rej09b0047-0060z microcomputer (built-in feedback resistor) x in x out externally derived clock open v cc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. figure 7.1.1. examples of main clock connection circuit the following describes the clocks generated by the clock generation circuit. 7.1 main clock the main clock is generated by the main clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the main clock oscillator circuit is configured by connecting a resonator between the x in and x out pins. the main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the main clock oscillator circuit may also be configured by feeding an externally generated clock to the x in pin. figure 7.1.1 shows the examples of main clock connection circuit. the power consumption in the chip can be reduced by setting the cm05 bit of cm0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the cpu clock to a sub clock or ring oscillator clock. in this case, x out goes h . furthermore, because the internal feedback resistor remains on, x in is pulled h to x out via the feedback resistor. during stop mode, all clocks including the main clock are turned off. refer to power control . if the main clock is not used, it is recommended to connect the x in pin to v cc to reduce power consump- tion during reset. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 39 of n rej09b0047-0060z microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd v cc figure 7.2.1. examples of sub clock connection circuit 7.2 sub clock the sub clock is generated by the sub clock oscillation circuit. this clock is used as the clock source for the cpu clock, as well as the timer a and timer b count sources. the sub clock oscillator circuit is configured by connecting a crystal resonator between the x cin and x cout pins. the sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the sub clock oscillator circuit may also be configured by feeding an externally generated clock to the x cin pin. figure 7.2.1 shows the examples of sub clock connection circuit. after reset, the sub clock is turned off. at this time, the feedback resistor is disconnected from the oscilla- tor circuit. to use the sub clock for the cpu clock, set the cm07 bit of cm0 register to 1 (sub clock) after the sub clock becomes oscillating stably. during stop mode, all clocks including the sub clock are turned off. refer to power control . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 40 of n rej09b0047-0060z 7.3 ring oscillator clock this clock is supplied by a variable ring oscillator. this clock is used as the clock source for the cpu and peripheral function clocks. in addition, if the pm22 bit of pm2 register is 1 (ring oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (refer to 10. watchdog timer ? count source protective mode ). after reset, the ring oscillator clock divided by 16 is used for the cpu clock. it can also be turned on by setting the cm21 bit of cm2 register to 1 (ring oscillator clock), and is used as the clock source for the cpu and peripheral function clocks. if the main clock stops oscillating when the cm20 bit of cm2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), the ring oscillator automatically starts operating, supplying the neces- sary clock for the microcomputer. 7.4 pll clock the pll clock is generated from the main clock by a pll frequency synthesizer. this clock is used as the clock source for the cpu and peripheral function clocks. after reset, the pll clock is turned off. the pll frequency synthesizer is activated by setting the plc07 bit to 1 (pll operation). when the pll clock is used as the clock source for the cpu clock, wait t su (pll) for the pll clock to be stable, and then set the cm11 bit in the cm1 register to 1 . before entering wait mode or stop mode, be sure to set the cm11 bit to 0 (cpu clock source is the main clock). furthermore, before entering stop mode, be sure to set the plc07 bit in the plc0 register to 0 (pll stops). figure 7.4.1 shows the procedure for using the pll clock as the clock source for the cpu. the pll clock frequency is determined by the equation below. pll clock frequency=f(x in ) x (multiplying factor set by the plc02 to plc00 bits plc0 register (however, 10 mhz pll clock frequency 20 mhz) the plc02 to plc00 bits can be set only once after reset. table 7.4.1 shows the example for setting pll clock frequencies. x in (mhz) plc02 plc01 plc00 multiplying factor pll clock (mhz)(note) 10 0 0 1 2 20 50 1 0 4 note: 10mhz pll clock frequency 20mhz. table 7.4.1. example for setting pll clock frequencies m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 41 of n rej09b0047-0060z figure 7.4.1. procedure to use pll clock as cpu clock source start set the cm07 bit to 0 (main clock), the cm17 to cm16 bits to 00 2 (main clock undivided), and the cm06 bit to 0 (cm16 and cm17 bits enabled). (note) set the plc02 to plc00 bits (multiplying factor). (to select a 16 mhz or higher pll clock) set the pm20 bit to 0 (2-wait states). set the plc07 bit to 1 (pll operation). wait until the pll clock becomes stable (t su (pll)). set the cm11 bit to 1 (pll clock for the cpu clock source). end note : pll operation mode can be entered from high speed mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 42 of n rej09b0047-0060z 7.5 cpu clock and peripheral function clock the cpu clock is used to operate the cpu and peripheral function clocks are used to operate the periph- eral functions. 7.5.1 cpu clock this is the operating clock for the cpu and watchdog timer. the clock source for the cpu clock can be chosen to be the main clock, sub clock, ring oscillator clock or the pll clock. if the main clock or ring oscillator clock is selected as the clock source for the cpu clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in cm0 register and the cm17 to cm16 bits in cm1 register to select the divide-by-n value. when the pll clock is selected as the clock source for the cpu clock, the cm06 bit should be set to 0 and the cm17 to cm16 bits to 00 2 (undivided). after reset, the ring oscillator clock divided by 16 provides the cpu clock. note that when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power dissipation mode, or when the cm05 bit of cm0 register is set to 1 (main clock turned off) in low-speed mode, the cm06 bit of cm0 register is set to 1 (divide-by-8 mode). 7.5.2 peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad , f c32 ) these are operating clocks for the peripheral functions. of these, fi (i = 1, 2, 8, 32) and fi sio are derived from the main clock, pll clock or ring oscillator clock by dividing them by i. the clock fi is used for timers a and b, and fi sio is used for serial i/o. the f ad clock is produced from the main clock, pll clock or ring oscillator clock, and is used for the a-d converter. when the wait instruction is executed after setting the cm02 bit of cm0 register to 1 (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fi sio and f ad clocks are turned off. the f c32 clock is produced from the sub clock, and is used for timers a and b. this clock can only be used when the sub clock is on. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 43 of n rej09b0047-0060z 7.6 power control there are three power control modes. for convenience sake, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 normal operation mode normal operation mode is further classified into seven modes. in normal operation mode, because the cpu clock and the peripheral function clocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consumption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source to which switched must be oscillating stably. if the new clock source is the main clock, sub clock or pll clock, allow a sufficient wait time in a program until it becomes oscillating stably. note that operation modes cannot be changed directly from low speed or low power dissipation mode to ring oscillator or ring oscillator low power dissipation mode. nor can operation modes be changed directly from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation mode. when the cpu clock source is changed from the ring oscillator to the main clock, change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the cm06 bit of cm0 register was set to 1 ) in the ring oscillator mode. 7.6.1.1 high-speed mode the main clock divided by 1 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.2 pll operation mode the main clock multiplied by 2 or 4 provides the pll clock, and this pll clock serves as the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. pll operation mode can be entered from high speed mode. if pll operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. 7.6.1.3 medium-speed mode the main clock divided by 2, 4, 8 or 16 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.4 low-speed mode the sub clock provides the cpu clock. the main clock is used as the clock source for the peripheral function clock when the cm21 bit is set to 0 (ring oscillator turned off), and the ring oscillator clock is used when the cm21 bit is set to 1 (ring oscillator oscillating). the f c32 clock can be used as the count source for timers a and b. 7.6.1.5 low power dissipation mode in this mode, the main clock is turned off after being placed in low speed mode. the sub clock provides the cpu clock. the f c32 clock can be used as the count source for timers a and b. peripheral function clock can use only f c32 . simultaneously when this mode is selected, the cm06 bit of cm0 register becomes 1 (divided by 8 mode). in the low power dissipation mode, do not change the cm06 bit. consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 44 of n rej09b0047-0060z 7.6.1.6 ring oscillator mode the selected ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the cpu clock. the ring oscillator clock is also the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. the ring oscillator frequency can be selected using the ring oscillator control register (rocr:025c 16 ) bits 0 to 3. see figure.7.4 for details. when the operation mode is returned to the high and medium speed modes, set the cm06 bit to 1 (divided by 8 mode). 7.6.1.7 ring oscillator low power dissipation mode the main clock is turned off after being placed in ring oscillator mode. the cpu clock can be selected as in the ring oscillator mode. the ring oscillator clock is the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. 1(note 1) modes cm2 register cm21 cm1 register cm11 cm17, cm16 cm0 register cm07 cm06 cm05 cm04 pll operation mode 0100 2 00 high-speed mode 0 0 00 2 00 0 medium- speed mode 0001 2 00 0 0010 2 00 0 divided by 2 00 01 0 0011 2 00 0 low-speed mode 1 0 1 low power dissipation mode 11 ring oscillator mode (note 3) 1 divided by 4 divided by 8 divided by 16 ring oscillator low power dissipation mode note 1: when the cm05 bit is set to 1 ? (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and cm06 bit is set to 1 ? (divided by 8 mode) simultaneously . note 2: the divide-by-n value can be selected the same way as in ring oscillator mode. 0 0 101 2 000 110 2 000 110 111 2 00 0 100 2 00 0 (note 2) divided by 2 divided by 4 divided by 8 divided by 16 divided by 1 1(note 1) (note 2) 1 note 3: variable ring oscillator frequency can be any of those described in the section "variable ring oscillator mode". 0 0 7.6.2 wait mode in wait mode, the cpu clock is turned off, so are the cpu (because operated by the cpu clock) and the watchdog timer. however, if the pm22 bit of pm2 register is 1 (ring oscillator clock for the watchdog timer count source), the watchdog timer remains active. because the main clock, sub clock, ring oscillator clock and pll clock all are on, the peripheral functions using these clocks keep operating. 7.6.2.1 peripheral function clock stop function if the cm02 bit is 1 (peripheral function clocks turned off during wait mode), the f 1 , f 2 , f 8 , f 32 , f 1sio , f 8sio , f 32sio and f ad clocks are turned off when in wait mode, with the power consumption reduced that much. however, f c32 remains on. 7.6.2.2 entering wait mode the microcomputer is placed into wait mode by executing the wait instruction. when the cm11 bit = 1 (cpu clock source is the pll clock), be sure to clear the cm11 bit to 0 (cpu clock source is the main clock) before going to wait mode. the power consumption of the chip can be reduced by clearing the plc07 bit to 0 (pll stops). 7.6.2.3 pin status during wait mode the i/o port pins retain their status held just prior to wait mode. table 7.6.1.1. setting clock related bit and modes m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 45 of n rej09b0047-0060z interrupt cm02=0 cm02=1 nmi interrupt can be used serial i/o interrupt can be used when operating with internal or external clock can be used when operating with external clock key input interrupt can be used can be used a-d conversion interrupt can be used in one-shot mode or single sweep mode timer a interrupt can be used in all modes can be used in event counter mode or when the count source is fc32 timer b interrupt int interrupt can be used can be used (do not use) can be used multi-master i 2 c interrupt can be used (do not use) table 7.6.2.4.1. interrupts to exit wait mode 7.6.2.4 exiting wait mode ______ the microcomputer is moved out of wait mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of exit wait mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disabled) before execut- ing the wait instruction. the peripheral function interrupts are affected by the cm02 bit. if cm02 bit is 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. if cm02 bit is 1 (peripheral function clocks turned off during wait mode), the peripheral func- tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. table 7.6.2.4.1 lists the interrupts to exit wait mode. if the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the wait instruction. 1. in the ilvl2 to ilvl0 bits of interrupt control register, set the interrupt priority level of the periph eral function interrupt to be used to exit wait mode. also, for all of the peripheral function interrupts not used to exit wait mode, set the ilvl2 to ilvl0 bits to 000 2 (interrupt disable). 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit wait mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt routine is executed. the cpu clock turned on when exiting wait mode by a peripheral function interrupt is the same cpu clock that was on when the wait instruction was executed. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 46 of n rej09b0047-0060z 7.6.3 stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and the peripheral functions clocked by these clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to vcc pin is v ram or more, the internal ram is retained. when applying 2.7 or less voltage to vcc pin, make sure vcc v ram . however, the peripheral functions clocked by external signals keep operating. the following interrupts can be used to exit stop mode. ______ ? nmi interrupt ? key interrupt ______ ? int interrupt ? timer a, timer b interrupt (when counting external pulses in event counter mode) ? serial i/o interrupt (when external clock is selected) ? voltage down detection interrupt (refer to voltage down detection interrupt for an operating condition) 7.6.3.1 entering stop mode the microcomputer is placed into stop mode by setting the cm10 bit of cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit of cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit of cm10 register is set to 1 (main clock oscillator circuit drive capability high). before entering stop mode, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disable). also, if the cm11 bit is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and the plc07 bit to 0 (pll turned off) before entering stop mode. 7.6.3.2 pin status during stop mode the i/o pins retain their status held just prior to entering stop mode. 7.6.3.3 exiting stop mode ______ the microcomputer is moved out of stop mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of stop mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disable) before setting the cm10 bit to 1 . if the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the cm10 bit to 1 . 1. in the ilvl2 to ilvl0 bits of interrupt control register, set the interrupt priority level of the periph- eral function interrupt to be used to exit stop mode. also, for all of the peripheral function interrupts not used to exit stop mode, set the ilvl2 to ilvl0 bits to 000 2 . 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit stop mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt service routine is executed. ______ which cpu clock will be used after exiting stop mode by a peripheral function or nmi interrupt is determined by the cpu clock that was on when the microcomputer was placed into stop mode as follows: if the cpu clock before entering stop mode was derived from the sub clock: sub clock if the cpu clock before entering stop mode was derived from the main clock: main clock divide-by-8 if the cpu clock before entering stop mode was derived from the ring oscillator clock: ring oscillator clock divide-by-8 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 47 of n rej09b0047-0060z figure 7.6.1. state transition to stop mode and wait mode reset medi um - sp eed m ode ( di vi ded- by- 8 m ode) hi gh- sp eed , medi um - sp eed m ode st op m ode wai t m ode i nt er r upt c m 10=1 i nt er r upt low - sp eed , l ow pow er di ssi pat i on m ode c m 10=1 st op m ode i nt er r upt wai t m ode i nt er r upt c m 10=1 st op m ode al l osci l l at or s st opped i nt er r upt wai t m ode wai t i nst r uct i on i nt er r upt cpu oper at i on st oppe d when l ow - speed m ode when l ow pow er di ssi pat i on m ode pll oper at i on m ode not es 1, 2 note 1: do not go directly from pll operation mode to wait or stop mode. note 2: pll operation mode can be entered from high speed mode. similarly, pll operation mode can be changed back to high speed mode. note 3: when the pm21 bit = 0 (system clock protective function unused). note 4: the ring oscillator clock divided by 8 provides the cpu clock. note 5: write to the cm0 register and cm1 register simultaneously by accessing in word units while cm21 = 1 (ring oscillator tu rned off). note 6: before entering stop mode, be sure to clear the cm20 bit in the cm2 register to "0" (oscillation stop and oscillation r estart detection function disabled). wai t m ode i nt er r upt cm 10=1 i nt er r upt ( not e 4) st op m ode wai t i nst r uct i on wai t i nst r uct i on wai t i nst r uct i on ri ng osci l l at or m ode ( sel ect abl e f r equency) ri ng osci l l at or m ode ( f 2 ( roc) / 16) nor mal oper at i on m ode cm 21=1 cm 21=0 cm 07=0 cm 06=1 cm 05=0 cm 11=0 cm 10=1 ( not e 5) ri ng osci l l at or l ow pow er di ssi pat i on m ode c m 10=1 st op m ode i nt er r upt wai t m ode i nt er r upt wai t i nst r uct i on figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. figure 7.6.1.1 shows the state transition in normal operation mode. table 7.6.1 shows a state transition matrix describing allowed transition and setting. the vertical line shows current state and horizontal line shows state after transition. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 48 of n rej09b0047-0060z figure 7.6.1.1. state transition in normal mode cm04=0 cpu clock: f(pll) cm07=0 cm06=0 cm17=0 cm16=0 pll operation mode cm07=0 cm06=0 cm17=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 high-speed mode cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 cm07=0 low-speed mode cm07=0 low power dissipation mode cm06=1 cm15=1 ring oscillator mode cpu clock ring oscillator mode cpu clock cpu clock ring oscillator low power dissipation mode cpu clock cm07=0 low-speed mode plc07=1 cm11=1 (note 6) plc07=0 cm11=0 (note 7) cm04=0 plc07=1 cm11=1 plc07=0 cm11=0 cm04=0 cm04=1 cm04=1 cm04=1 cm04=0 cm04=1 cm07=0 (note 2, note 4) cm07=1 (note 3) cm05=1 (note 1, note 9) cm05=0 cm21=0 (note 8) cm21=1 cm21=0 (note 8) cm21=1 cm21=0 cm21=1 main clock oscillation ring oscillator clock oscillation sub clock oscillation f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 pll operation mode cpu clock: f(pll) cpu clock: f(x in ) high-speed mode middle-speed mode (divide by 2) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 cpu clock: f(x cin ) cpu clock: f(x cin ) cpu clock: f(x cin ) cm05=0 m0 m cm05=1 (note 1) cm05=1 (note 1) cm05=0 (note 6) (note 7) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) middle-speed mode (divide by 2) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) cpu clock: f(x in ) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 ring oscillator low power dissipation mode notes: 1: avoid making a transition when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2: wait for td(m-l) or the main clock oscillation stabilization time whichever is longer before switching over. 3: switch clock after oscillation of sub-clock is sufficiently stable. 4: change cm17 and cm16 before changing cm06. 5: transit in accordance with arrow. 6: pll operation mode can only be entered from high speed mode. also, wait until the pll clock is sufficiently stable before c hanging operation modes. to select a 16 mhz or higher pll clock, set the pm20 bit to 0 (sfr accessed with two wait states) before setting plc07 to 1 (pll operation). 7: pll operation mode can only be changed to high speed mode. if the pm20 bit = 0 (sfr accessed with two wait states), set plc 07 to 0 (pll turned off) before setting the pm20 bit to 1 (sfr accessed with one wait state). 8: set the cm06 bit to 1 (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode. 9: when the cm21 bit = 0 (ring oscillator turned off) and the cm05 bit = 1 (main clock turned off), the cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 49 of n rej09b0047-0060z table 7.6.1. allowed transition and setting high-speed mode, middle-speed mode ring oscillator mode stop mode wait mode ring oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 current state state after transition see table a 8 -- (8) (18) 5 (9) 7 -- (10) (11) 1, 6 (12) 3 (14) 4 -- -- -- -- -- (13) 3 (15) -- -- -- -- -- -- -- (10) -- -- -- -- -- -- -- -- (18) (18) -- -- (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) -- -- (18) 5 (18) 5 (18) (18) (18) (18) (18) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) setting operation cm04 = 0 sub clock turned off cm04 = 1 sub clock oscillating cm06 = 0, cpu clock no division mode cm17 = 0 , cm16 = 0 cm06 = 0, cpu clock division by 2 mode cm17 = 0 , cm16 = 1 cm06 = 0, cpu clock division by 4 mode cm17 = 1 , cm16 = 0 cm06 = 1 cpu clock division by 8 mode cm06 = 0, cpu clock division by 16 mode cm17 = 1 , cm16 = 1 cm07 = 0 main clock, pll clock, or ring oscillator clock selected cm07 = 1 sub clock selected cm05 = 0 main clock oscillating cm05 = 1 main clock turned off plc07 = 0, cm11 = 0 main clock selected plc07 = 1, cm11 = 1 pll clock selected cm21 = 0 main clock or pll clock selected cm21 = 1 ring oscillator clock selected cm10 = 1 transition to stop mode wait instruction transition to wait mode hardware interrupt exit stop mode or wait mode notes: 1. avoid making a transition when the cm21 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm21 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. ring oscillator clock oscillates and stops in low-speed mode. in this mode, the ring oscillator can be used as peripheral fu nction clock. sub clock oscillates and stops in pll operation mode. in this mode, sub clock can be used as peripheral function clock. 3. pll operation mode can only be entered from and changed to high-speed mode. 4. set the cm06 bit to 1 (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode. 5. when exiting stop mode, the cm06 bit is set to 1 (division by 8 mode). 6. if the cm05 bit is set to 1 (main clock stop), then the cm06 bit is set to 1 (division by 8 mode). 7. a transition can be made only when sub clock is oscillating. 8. state transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in th e table below. --: cannot transit (11) 1 high-speed mode, middle-speed mode ring oscillator mode stop mode wait mode ring oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 see table a 8 see table a 8 (3) (3) (3) (3) (4) (4) (4) (4) (5) (7) (7) (5) (5) (5) (7) (7) (6) (6) (6) (6) no division divided by 2 (3) (3) (3) (3) (4) (4) (4) (4) (5) (5) (5) (5) (7) (7) (7) (7) (6) (6) (6) (6) (1) (1) (1) (1) (1) (2) (2) (2) (2) (2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- sub clock oscillating sub clock turned off --: cannot transit divided by 4 divided by 8 divided by 16 no division divided by 2 divided by 4 divided by 8 divided by 16 no division divided by 4 sub clock oscillating sub clock turned off divided by 8 divided by 16 divided by 2 no division divided by 4 divided by 8 divided by 16 divided by 2 9. ( ) : setting method. refer to following table. cm04, cm05, cm06, cm07 : bit of cm0 register cm10, cm11, cm16, cm17 : bit of cm1 register cm20, cm21 : bit of cm2 register plc07 : bit of plc0 register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 50 of n rej09b0047-0060z 7.7 system clock protective function when the main clock is selected for the cpu clock source, this function protects the clock from modifica- tions in order to prevent the cpu clock from becoming halted by run-away. if the pm21 bit of pm2 register is set to 1 (clock modification disabled), the following bits are protected against writes: ? cm02, cm05, and cm07 bits in cm0 register ? cm10, cm11 bits in cm1 register ? cm20 bit in cm2 register ? all bits in plc0 register before the system clock protective function can be used, the following register settings must be made while the cm05 bit of cm0 register is 0 (main clock oscillating) and cm07 bit is 0 (main clock selected for the cpu clock source): (1) set the prc1 bit of prcr register to 1 (enable writes to pm2 register). (2) set the pm21 bit of pm2 register to 1 (disable clock modification). (3) set the prc1 bit of prcr register to 0 (disable writes to pm2 register). do not execute the wait instruction when the pm21 bit is 1 . 7.8 oscillation stop and re-oscillation detect function the oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and reoscillation. at oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated. depending on the cm27 bit of cm2 register. the oscillation stop detection function can be enabled and disabled by the cm20 bit in the cm2 register. table 7.8.1 lists a specification overview of the oscillation stop and re-oscillation detect function. table 7.8.1. specification overview of oscillation stop and re-oscillation detect function item specification oscillation stop detectable clock and f(x in ) 2 mhz frequency bandwidth enabling condition for oscillation stop, set cm20 bit to 1 (enable) re-oscillation detection function operation at oscillation stop, ? reset occurs (when cm27 bit =0) re-oscillation detection ? oscillation stop, re-oscillation detection interrupt occurs(when cm27 bit =1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 51 of n rej09b0047-0060z 7.8.1 operation when cm27 bit = 0 (oscillation stop detection reset) when main clock stop is detected when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to sfr , reset ). this status is reset with hardware reset 1 or hardware reset 2. also, even when re-oscillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (during main clock stop, do not set the cm20 bit to 1 and the cm27 bit to 0 .) 7.8.2 operation when cm27 bit = 1 (oscillation stop and re-oscillation detect interrupt) when the main clock corresponds to the cpu clock source and the cm20 bit is 1 (oscillation stop and re-oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt: ? oscillation stop and re-oscillation detect interrupt request occurs. ? the ring oscillator starts oscillation, and the ring oscillator clock becomes the cpu clock and clock source for peripheral functions in place of the main clock. ? cm21 bit = 1 (ring oscillator clock for cpu clock source) ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) when the pll clock corresponds to the cpu clock source and the cm20 bit is 1 , the system is placed in the following state if the main clock comes to a halt: since the cm21 bit remains unchanged, set it to 1 (ring oscillator clock) inside the interrupt routine. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) ? cm21 bit remains unchanged when the cm20 bit is 1 , the system is placed in the following state if the main clock re-oscillates from the stop condition: ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock re-oscillation detected) ? cm23 bit = 0 (main clock oscillation) ? cm21 bit remains unchanged m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 7. clock generation circuit rev.0.60 2004.02.01 page 52 of n rej09b0047-0060z 7.8.3 how to use oscillation stop and re-oscillation detect function ? the oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. if the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the cm22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. ? where the main clock re-oscillated after oscillation stop, return the main clock to the cpu clock and peripheral function clock source in the program. figure 7.8.3.1 shows the procedure for switching the clock source from the ring oscillator to the main clock. ? simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the cm22 bit be- comes 1 . when the cm22 bit is set at 1 , oscillation stop, re-oscillation detection interrupt are dis- abled. by setting the cm22 bit to 0 in the program, oscillation stop, re-oscillation detection interrupt are enabled. ? if the main clock stops during low speed mode where the cm20 bit is 1 , an oscillation stop, re-oscilla- tion detection interrupt request is generated. at the same time, the ring oscillator starts oscillating. in this case, although the cpu clock is derived from the sub clock as it was before the interrupt occurred, the peripheral function clocks now are derived from the ring oscillator clock. ? to enter wait mode while using the oscillation stop, re-oscillation detection function, set the cm02 bit to 0 (peripheral function clocks not turned off during wait mode). ? since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function dis- abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the cm05 bit is altered. ? this function cannot be used if the main clock frequency is 2 mhz or less. in that case, set the cm20 bit to 0 . figure 7.8.3.1. procedure to switch clock source from ring oscillator to main clock main clock switch inspect the cm23 bit do this check a number of times set the cm22 bit to 0 (main clock stop, re-oscillation not detected). set the cm21 bit to 0 (main clock for the cpu clock source)(note) 1(main clock stop) 0(main clock oscillation) the main clock is confirmed to be active a number of times. all of cm21-23 are the cm2 register bits end note: if the clock source for cpu clock is to be changed to pll clock, set to pll operation mode after set to high-speed mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 8. protection rev.0.60 2004.02.01 page 53 of n rej09b0047-0060z 8. protection in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 8.1 shows the prcr register. the following lists the registers protected by the prcr register. ? registers protected by prc0 bit: cm0, cm1, cm2, plc0, rocr and pclkr registers ? registers protected by prc1 bit: pm0, pm1, pm2, tb2sc, invc0 and invc1 registers ? registers protected by prc2 bit: pd9 , pacr and s4c registers ? registers protected by prc3 bit: vcr2 and d4int registers set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction. the prc0, prc1 and prc3 bits are not automati- cally cleared to 0 by writing to any address. they can only be cleared in a program. protect register symbol address after reset prcr 000a 16 xx000000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write protected 1 : write enabled prc1 prc0 prc2 function rw note: the prc2 bit is set to 0 by writing to any address after setting it to 1 . other bits are not set to 0 by writing to any address, and must therefore be set in a program. 0 rw rw rw nothing is assigned. when write, set to 0 . when read, its content is indeterminate. reserved bit must set to 0 rw protect bit 0 protect bit 1 protect bit 2 enable write to cm0, cm1, cm2, rocr, plc0 and pclkr registers 0 : write protected 1 : write enabled enable write to pm0, pm1, pm2, tb2sc, invc0 and invc1 registers 0 : write protected 1 : write enabled enable write to pd9, pacr and s4c registers prc3 rw protect bit 3 0 : write protected 1 : write enabled enable write to vcr2 and d4int registers (b5-b4) (b7-b6) 0 figure 8.1. prcr register 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 54 of n rej09b0047-0060z ? maskable interrupt: an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt: an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 9.1.1. interrupts interrupt ? ? ? ? ? ? ? ? ? ? ? software (non-maskable interrupt) hardware ? ? ? ? ? ? ? ? special (non-maskable interrupt) peripheral function (note 1) (maskable interrupt) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? ? ? _______ nmi ________ dbc (note 2) watchdog timer oscillation stop and re-oscillation detection voltage down detection single step (note 2) address match note 1: peripheral function interrupts are generated by the microcomputer's internal functions. note 2: do not normally use this interrupt because it is provided exclusively for use by development support tools. 9. interrupts 9.1 type of interrupts figure 9.1.1 shows types of interrupts. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 55 of n rej09b0047-0060z 9.1.1 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non- maskable interrupts. 9.1.1.1 undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. 9.1.1.2 overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag set to 1 (the operation resulted in an overflow). the following are instructions whose o flag changes by arith- metic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub 9.1.1.3 brk interrupt a brk interrupt occurs when executing the brk instruction. 9.1.1.4 int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt nos. 0 to 63 can be specified for the int instruction. because software interrupt nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the int instruction. in software interrupt nos. 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an interrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in software interrupt nos. 32 to 63, the u flag does not change state during instruction execution, and the sp then selected is used. 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 56 of n rej09b0047-0060z 9.1.2 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral function inter- rupts. 9.1.2.1 special interrupts special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 nmi interrupt _______ _______ an nmi interrupt is generated when input on the nmi pin changes state from high to low. for details _______ about the nmi interrupt, refer to the section "nmi interrupt". ________ 9.1.2.1.2 dbc interrupt this interrupt is exclusively for debugger, do not use in any other circumstances. 9.1.2.1.3 watchdog timer interrupt generated by the watchdog timer. once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to the section "watchdog timer". 9.1.2.1.4 oscillation stop and re-oscillation detection interrupt generated by the oscillation stop and re-oscillation detection function. for details about the oscilla- tion stop and re-oscillation detection function, refer to the section "clock generating circuit". 9.1.2.1.5 voltage down detection interrupt generated by the voltage detection circuit. for details about the voltage detection circuit, refer to the section "voltage detection circuit". 9.1.2.1.6 single-step interrupt do not normally use this interrupt because it is provided exclusively for use by development support tools. 9.1.2.1.7 address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmad0 or rmad1 register, if the corresponding enable bit (aier register s aier0 or aier1bit) is set to 1 . for details about the address match interrupt, refer to the section address match interrupt . 9.1.2.2 peripheral function interrupts peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. the interrupt sources for peripheral function interrupts are listed in table 1.11.2. relocatable vector tables . for details about the peripheral functions, refer to the description of each peripheral function in this manual. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 57 of n rej09b0047-0060z interrupt source vector table addresses remarks reference address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction m16c/60, m16c/20 overflow fffe0 16 to fffe3 16 interrupt on into instruction serise software brk instruction fffe4 16 to fffe7 16 maual address match fffe8 16 to fffeb 16 address match interrupt single step (note) fffec 16 to fffef 16 watchdog timer ffff0 16 to ffff3 16 watchdog timer oscillation stop and re-oscillation detection clock generating circuit voltage down detection voltage detection circuit ________ dbc (note) ffff4 16 to ffff7 16 _______ nmi ffff8 16 to ffffb 16 _______ nmi interrupt reset ffffc 16 to fffff 16 reset note: do not normally use this interrupt because it is provided exclusively for use by development sup- port tools. figure 9.2.1. interrupt vector aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa 0 0 0 0 high address aaaaaaaa aaaaaaaa 0 0 0 0 0 0 0 0 vector address (l) lsb msb vector address (h) 9.2 interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respective interrupt vectors. when an interrupt request is accepted, the cpu branches to the address set in the corresponding interrupt vector. figure 9.2.1 shows the interrupt vector. 9.2.1 fixed vector tables the fixed vector tables are allocated to the addresses from fffdc 16 to fffff 16 . table 9.2.1.1 lists the fixed vector tables. in the flash memory version of microcomputer, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to the section "flash memory rewrite disabling function". table 9.2.1.1. fixed vector tables if the contents of address fffe7 16 is ff 16 , program ex- ecution starts from the address shown by the vector in the relocatable vector table. 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 58 of n rej09b0047-0060z table 9.2.2.1. relocatable vector tables software interrupt number reference note 1: address relative to address in intb. note 2: use the ifsr register's ifsr6 and ifsr7 bits to select. note 3: during i 2 c bus mode, nack and ack interrupts comprise the interrupt source. note 4: use the ifsr2a register s ifsr26 and ifsr27 bits to select. note 5: these interrupts cannot be disabled using the i flag. note 6: bus collision detection : during ie bus mode, this bus collision detection constitutes the cause of an interrupt. during i 2 c bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt. vector address (note 1) address (l) to address (h) 0 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 to 10 15 16 5 6 7 8 4 9 1 to 3 interrupt source brk instruction int3 si/o3, int4 si/o4, int5 icoc interrupt 1, i 2 c-bus interface icoc interrupt 0 (note 2) (note 2) dma0 dma1 key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt uart 2 bus collision detection uart2 transmit, nack2 (note 3) uart2 receive, ack2 (note 3) ( note 4 ) icoc base timer, s cl /s da ( note 4 ) m16c/60, m16c/20 series software manual int interrupt timer s timer s multi-master i 2 c-bus interface serial i/o int interrupt serial i/o dmac key input interrupt a-d convertor serial i/o timer int interrupt m16c/60, m16c/20 series software manual (note 5) (reserved) +0 to +3 (0000 16 to 0003 16 ) +44 to +47 (002c 16 to 002f 16 ) +48 to +51 (0030 16 to 0033 16 ) +52 to +55 (0034 16 to 0037 16 ) +56 to +59 (0038 16 to 003b 16 ) +68 to +71 (0044 16 to 0047 16 ) +72 to +75 (0048 16 to 004b 16 ) +76 to +79 (004c 16 to 004f 16 ) +80 to +83 (0050 16 to 0053 16 ) +84 to +87 (0054 16 to 0057 16 ) +88 to +91 (0058 16 to 005b 16 ) +92 to +95 (005c 16 to 005f 16 ) +96 to +99 (0060 16 to 0063 16 ) +100 to +103 (0064 16 to 0067 16 ) +104 to +107 (0068 16 to 006b 16 ) +108 to +111 (006c 16 to 006f 16 ) +112 to +115 (0070 16 to 0073 16 ) +116 to +119 (0074 16 to 0077 16 ) +120 to +123 (0078 16 to 007b 16 ) +124 to +127 (007c 16 to 007f 16 ) +128 to +131 (0080 16 to 0083 16 ) +252 to +255 (00fc 16 to 00ff 16 ) +40 to +43 (0028 16 to 002b 16 ) +60 to +63 (003c 16 to 003f 16 ) +64 to +67 (0040 16 to 0043 16 ) +20 to +23 (0014 16 to 0017 16 ) +24 to +27 (0018 16 to 001b 16 ) +28 to +31 (001c 16 to 001f 16 ) +32 to +35 (0020 16 to 0023 16 ) +16 to +19 (0010 16 to 0013 16 ) +36 to +39 (0024 16 to 0027 16 ) to (note 5) (note 6) 9.2.2 relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a reloacatable vector table area. table 9.2.2.1 lists the relocatable vector tables. setting an even address in the intb register results in the interrupt sequence being executed faster than in the case of odd addresses. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 59 of n rej09b0047-0060z 9.3 interrupt control the following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. what is explained here does not apply to nonmaskable interrupts. use the flg register s i flag, ipl, and each interrupt control register s ilvl2 to ilvl0 bits to enable/ disable the maskable interrupts. whether an interrupt is requested is indicated by the ir bit in each interrupt control register. figure 9.3.1 shows the interrupt control registers. also, the following interrupts share a vector and an interrupt control register. ________ ? int4 and sio3 ________ ? int5 and sio4 ? icoc base timer and s cl /s da ? icoc interrupt 1 and i 2 c-bus interface an interrupt request is set by the ifsr6, ifsr7 bits in the ifsr register and the ifsr26 and ifsr27 bits in the ifsr2a register. figure 9.3.2 shows the ifsr, ifsr2a registers. 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 60 of n rej09b0047-0060z figure 9.3.1. interrupt control registers symbol address after reset int3ic 0044 16 xx00x000 2 s4ic/int5ic 0048 16 xx00x000 2 s3ic/int4ic 0049 16 xx00x000 2 int0ic to int2ic 005d 16 to 005f 16 xx00x000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol no functions are assigned. when writing to these bits, write 0 . the values in these bits when read are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge (notes 3, 4) 1 : selects rising edge must always be set to 0 ilvl1 ilvl2 note 1: this bit can only be reset by writing 0 (do not write 1 ). note 2: to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts of the usage notes reference book. note 3: if the ifsr register s ifsri bit (i = 0 to 5) is 1 (both edges), set the intiic register s pol bit to 0 (falling edge). note 4: set the s3ic or s4ic register s pol bit to 0 (falling edge) when the ifsr register s ifsr6 bit = 0 (si/o3 selected) or ifsr7 bit = 0 (si/o4 selected), respectively. (note 1) interrupt control register (note 2) b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa bit name function bit symbol rw symbol address after reset icoc0ic 0045 16 xxxxx000 2 icoc1ic, iicic (note 3) 0046 16 xxxxx000 2 btic, scldaic (note 3) 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dm0ic, dm1ic 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 s0tic to s2tic 0051 16 , 0053 16 , 004f 16 xxxxx000 2 s0ric to s2ric 0052 16 , 0054 16 , 0050 16 xxxxx000 2 ta0ic to ta4ic 0055 16 to 0059 16 xxxxx000 2 tb0ic to tb2ic 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 no functions are assigned. when writing to these bits, write 0 . the values in these bits when read are indeterminate. (note 1) note 1: this bit can only be reset by writing 0 (do not write 1 ). note 2: to rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts of the usage notes reference book. note 3: use the ifsr2a register to select. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 rw rw rw rw (b7-b4) rw rw rw rw rw rw rw rw (b7-b6) (b5) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 61 of n rej09b0047-0060z figure 9.3.2. ifsr register and ifsr2a register interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa int0 interrupt polarity switching bit 0 : si/o3 1 : int4 0 : si/o4 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 2) note 1: when setting this bit to 1 (= both edges), make sure the int0ic to int5ic register s pol bit is set to 0 (= falling edge). note 2: when setting this bit to 0 (= si/o3, si/o4), make sure the s3ic and s4ic registers pol bit is set to 0 (= falling edge). (note 2) interrupt request cause select register 2 bit name function bit symbol rw symbol address after reset ifsr2a 035e 16 00xxxxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa 0 : icoc base timer 1 : s cl /s da 0 : icoc interrupt 1 1 : i 2 c-bus interface ifsr26 ifsr27 interrupt request cause select bit interrupt request cause select bit rw rw must be set to 1 . (b5-b1) nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. note 1: set this bit to "1" befor you enable interrupt after resetting. ifsr20 1 reserved bit rw (note 1) 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 62 of n rej09b0047-0060z 9.3.1 i flag the i flag enables or disables the maskable interrupt. setting the i flag to 1 (= enabled) enables the maskable interrupt. setting the i flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 ir bit the ir bit is set to 1 (= interrupt requested) when an interrupt request is generated. then, when the interrupt request is accepted and the cpu branches to the corresponding interrupt vector, the ir bit is cleared to 0 (= interrupt not requested). the ir bit can be cleared to 0 in a program. note that do not write 1 to this bit. table 9.3.3.2. interrupt priority levels enabled by ipl table 9.3.3.1. settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high enabled interrupt priority levels interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 9.3.3 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using the ilvl2 to ilvl0 bits. table 1.11.3 shows the settings of interrupt priority levels and table 1.11.4 shows the interrupt priority levels enabled by the ipl. the following are conditions under which an interrupt is accepted: i flag = 1 ir bit = 1 interrupt priority level > ipl the i flag, ir bit, ilvl2 to ilvl0 bits and ipl are independent of each other. in no case do they affect one another. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 63 of n rej09b0047-0060z 9.4 interrupt sequence an interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 9.4.1 shows time required for executing the interrupt sequence. (1) the cpu gets interrupt information (interrupt number and interrupt request priority level) by reading the address 00000 16 . then it clears the ir bit for the corresponding interrupt to 0 (interrupt not requested). (2) the flg register immediately before entering the interrupt sequence is saved to the cpu s internal temporary register (note) . (3) the i, d and u flags in the flg register become as follows: the i flag is cleared to 0 (interrupts disabled). the d flag is cleared to 0 (single-step interrupt disabled). the u flag is cleared to 0 (isp selected). however, the u flag does not change state if an int instruction for software interrupt nos. 32 to 63 is executed. (4) the cpu s internal temporary register (note) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the accepted interrupt is set in the ipl. (7) the start address of the relevant interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. note: this register cannot be used by user. indeterminate 123456789 1011 12 13 14 15 16 17 18 indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate sp-2 sp-4 vec vec+2 pc cpu clock address bus data bus wr rd the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. figure 9.4.1. time required for executing interrupt sequence 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 64 of n rej09b0047-0060z interrupt sources 7 level that is set to ipl _______ watchdog timer, nmi, oscillation stop and re-oscillation detection, voltage down detection _________ software, address match, dbc, single-step not changed 9.4.2 variation of ipl when interrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 9.4.2.1 is set in the ipl. shown in table 9.4.2.1 are the ipl values of software and special interrupts when they are accepted. table 9.4.2.1. ipl level that is set to ipl when a software or special interrupt is accepted instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) the time from when an interrupt request is generated till when the instruction then executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) the time during which the interrupt sequence is executed. for details, see the table below. note, however, that the values in this table must be increased 2 cycles for the dbc interrupt and 1 cycle for the address match and single-step interrupts. interrupt vector address even even odd odd sp value even odd even odd without wait 18 cycles 19 cycles 19 cycles 20 cycles figure 9.4.1.1. interrupt response time 9.4.1 interrupt response time figure 9.4.1.1 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in figure 9.4.1.1) and the time during which the interrupt sequence is executed ((b) in figure 9.4.1.1). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 65 of n rej09b0047-0060z 9.4.3 saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits of the pc and the 4 high-order (ipl) and 8 low-order bits of the flg register, 16 bits in total, are saved to the stack first. next, the 16 low-order bits of the pc are saved. figure 9.4.3.1 shows the stack status before and after an interrupt request is accepted. the other necessary registers must be saved in a program at the beginning of the interrupt routine. use the pushm instruction, and all registers except sp can be saved with a single instruction. address content of previous stack stack [sp] sp value before interrupt request is accepted. m m C 1 m C 2 m C 3 m C 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m C 1 m C 2 m C 3 m C 4 address flg l content of previous stack stack flg h pc h [sp] new sp value content of previous stack m + 1 msb lsb pc l pc m figure 9.4.3.1. stack status before and after acceptance of interrupt request 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 66 of n rej09b0047-0060z figure 9.4.3.2. operation of saving register (2) sp contains odd number [sp] (odd) [sp] C 1 (even) [sp] C 2(odd) [sp] C 3 (even) [sp] C 4(odd) [sp] C 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) sp contains even number [sp] (even) [sp] C 1(odd) [sp] C 2 (even) [sp] C 3(odd) [sp] C 4 (even) [sp] C 5 (odd) note: [sp] denotes the initial value of the sp when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address pc m stack flg l pc l sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. pc m stack flg l pc l saved, 8 bits at a time flg h pc h flg h pc h the operation of saving registers carried out in the interrupt sequence is dependent on whether the sp (note) , at the time of acceptance of an interrupt request, is even or odd. if the stack pointer (note) is even, the flg register and the pc are saved, 16 bits at a time. if odd, they are saved in two steps, 8 bits at a time. figure 9.4.3.2 shows the operation of the saving registers. note: when any int instruction in software numbers 32 to 63 has been executed, this is the sp indicated by the u flag. otherwise, it is the isp. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 67 of n rej09b0047-0060z 9.5 interrupt priority if two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. for maskable interrupts (peripheral functions), any desired priority level can be selected using the ilvl2 to ilvl0 bits. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 9.5.1 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. 9.4.4 returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the reit instruction at the end of the interrupt routine. thereafter the cpu returns to the program which was being executed before accepting the interrupt request. return the other registers saved by a program within the interrupt routine using the popm or similar instruction before executing the reit instruction. 9.5.1 interrupt priority resolution circuit the interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. figure 9.5.1.1 shows the circuit that judges the interrupt priority level. figure 9.5.1. hardware interrupt priority reset oscillation stop and re-oscillation detection, voltage down detection peripheral function single step address match high low nmi dbc 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 68 of n rej09b0047-0060z figure 9.5.1.1. interrupts priority select circuit timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception, ack2 a-d conversion dma1 uart 2 bus collision timer a0 uart1 transmission uart0 transmission uart2 transmission, nack2 key input interrupt dma0 ipl i flag int1 int2 int0 watchdog timer dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt highest lowest priority of peripheral function interrupts (if priority levels are same) icoc interrupt 1, i 2 c-bus interface int3 icoc base timer, s cl /s da icoc interrupt 0 si/o4, int5 si/o3, int4 address match interrupt request level resolution output to clock generating circuit (fig.7.1.) oscillation stop and re-oscillation detection voltage down detection m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 69 of n rej09b0047-0060z ______ 9.6 int interrupt _______ inti interrupt (i=0 to 5) is triggered by the edges of external inputs. the edge polarity is selected using the ifsr register's ifsri bit. ________ ________ ________ to use the int4 interrupt, set the ifsr register's ifsr6 bit to "1" (=int4). to use the int5 interrupt, set the ________ ifsr register's ifsr7 bit to "1" (=int5). after modifiying the ifsr6 or ifsr7 bit, clear the corresponding ir bit to "0" (=interrupt not requested) before enabling the interrupt. ________ the int5 input has an effective digital debounce function for a noise rejection. refer to " 17.6 digital debounce function " for this detail. figure 9.6.1 shows the ifsr registers. figure 9.6.1. ifsr register interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa int0 interrupt polarity switching bit 0 : si/o3 1 : int4 0 : si/o4 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 2) note 1: when setting this bit to 1 (= both edges), make sure the int0ic to int5ic register s pol bit is set to 0 (= falling edge). note 2: when setting this bit to 0 (= si/o3, si/o4), make sure the s3ic and s4ic registers pol bit is set to 0 (= falling edge). (note 2) 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 70 of n rej09b0047-0060z interrupt control circuit kupic register key input interrupt request ki 3 ki 2 ki 1 ki 0 pur2 register's pu25 bit pd10 register's pd10_7 bit pull-up transistor pd10 register's pd10_7 bit pd10 register's pd10_6 bit pd10 register's pd10_5 bit pd10 register's pd10_4 bit pull-up transistor pull-up transistor pull-up transistor figure 9.8.1. key input interrupt ______ 9.7 nmi interrupt _______ _______ an nmi interrupt request is generated when input on the nmi pin changes state from high to low, after the _______ ______ nmi interrupt was enabled by writing a 1 to bit 4 of register pm2. the nmi interrupt is a non-maskable interrupt, once it is enabled. _______ the input level of this nmi interrupt input pin can be read by accessing the p8 register s p8_5 bit. _______ nmi is disabled by default after reset (the pin is a gpio pin, p8 5 ) and can be enabled using bit 4 of pm2 register. once enabled, it can only be disabled by a reset signal. _______ the nmi input has an effective digital debounce function for a noise rejection. refer to " 17.6 digital debounce function " for this detail. 9.8 key input interrupt of p10 4 to p10 7 , a key input interrupt is generated when input on any of the p10 4 to p10 7 pins which has had the pd10 register s pd10_4 to pd10_7 bits set to 0 (= input) goes low. key input interrupts can be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as analog input ports. figure 9.8.1 shows the block diagram of the key input interrupt. note, however, that while input on any pin which has had the pd10_4 to pd10_7 bits set to 0 (= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 9. interrupts rev.0.60 2004.02.01 page 71 of n rej09b0047-0060z table 9.9.2. relationship between address match interrupt sources and associated registers address match interrupt sources address match interrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 9.9 address match interrupt an address match interrupt request is generated immediately before executing the instruction at the address indicated by the rmadi register (i=0 to 1). set the start address of any instruction in the rmadi register. use the aier register s aier0 and aier1 bits to enable or disable the interrupt. note that the address match interrupt is unaffected by the i flag and ipl. for address match interrupts, the value of the pc that is saved to the stack area varies depending on the instruction being executed (refer to saving registers ). (the value of the pc that is saved to the stack area is not the correct return address.) therefore, follow one of the methods described below to return from the address match interrupt. ? rewrite the content of the stack and then use the reit instruction to return. ? restore the stack to its previous state before the interrupt request was accepted by using the pop or similar other instruction and then use a jump instruction to return. table 9.9.1 shows the value of the pc that is saved to the stack area when an address match interrupt request is accepted. figure 9.9.1 shows the aier, rmad0 and rmad1 registers. ? 16-bit op-code instruction ? instruction shown below among 8-bit operation code instructions add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b:s #imm8,dest stnz.b:s #imm8,dest stzx.b:s #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest=a0 or a1) instructions other than the above instruction at the address indicated by the rmadi register value of the pc that is saved to the stack area the address indicated by the rmadi register +2 the address indicated by the rmadi register +1 value of the pc that is saved to the stack area : refer to saving registers . table 9.9.1. value of the pc that is saved to the stack area when an address match interrupt request is accepted. 9. interrupts m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 72 of n rej09b0047-0060z bit name bit symbol symbol address after reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function rw aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address after reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 b7 b6 b5 b4 b3 b2 b1 b0 address setting register for address match interrupt function setting range address match interrupt register i (i = 0 to 1) 00000 16 to fffff 16 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) rw rw (b7-b2) rw rw nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. figure 9.9.1. aier register, rmad0 and rmad1 registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 10. watchdog timer rev.0.60 2004.02.01 page 73 of n rej09b0047-0060z 10. watchdog timer the watchdog timer is the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the cpu clock using the prescaler. whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per- formed when the watchdog timer underflows after reaching the terminal count can be selected using the pm12 bit of pm1 register. the pm12 bit can only be set to 1 (reset). once this bit is set to 1 , it cannot be set to 0 (watchdog timer interrupt) in a program. refer to 5.3 watchdog timer reset for the details of watchdog timer reset. when the main clock source is selected for cpu clock, ring oscillator clock, pll clock,the wdc register's the wdc7 bit value for prescaler can be chosen to be 16 or 128. if a sub-clock is selected for cpu clock, the prescaler is always 2 no matter how the wdc7 bit is set. the period of watchdog timer can be calcu- lated as given below. the period of watchdog timer is, however, subject to an error due to the prescaler. for example, when cpu clock = 16 mhz and the divide-by-n value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. the watchdog timer is initialized by writing to the wdts register. the prescaler is initialized after reset. note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the wdts register. in stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. counting is re- sumed from the held value when the modes or state are released. figure 10.1 shows the block diagram of the watchdog timer. figure 10.2 shows the watchdog timer-related registers. ? count source protective mode in this mode, a ring oscillator clock is used for the watchdog timer count source. the watchdog timer can be kept being clocked even when cpu clock stops as a result of run-away. before this mode can be used, the following register settings are required: (1) set the prc1 bit of prcr register to 1 (enable writes to pm1 and pm2 registers). (2) set the pm12 bit of pm1 register to 1 (reset when the watchdog timer underflows). (3) set the pm22 bit of pm2 register to 1 (ring oscillator clock used for the watchdog timer count source). (4) set the prc1 bit of prcr register to 0 (disable writes to pm1 and pm2 registers). (5) write to the wdts register (watchdog timer starts counting). with main clock source chosen for cpu clock, ring oscillator clock, pll clock watchdog timer period = with sub-clock chosen for cpu clock prescaler dividing (2) x watchdog timer count (32768) cpu clock watchdog timer period = prescaler dividing (16 or 128) x watchdog timer count (32768) cpu clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 10. watchdog timer rev.0.60 2004.02.01 page 74 of n rej09b0047-0060z watchdog timer start register (note) symbol address after reset wdts 000e 16 indeterminate wo b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. rw note : write to the wdts register after the watchdog timer interrupt occurs. figure 10.2. wdc register and wdts register cpu clock write to wdts register reset pm12 = 0 watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 1/2 prescaler pm12 = 1 watchdog timer interrupt request reset pm22 = 0 pm22 = 1 ring oscillator clock figure 10.1. watchdog timer block diagram watchdog timer control register symbol address after reset wdc 000f 16 00xxxxxx 2 (note 2) function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit must set to 0 0 ro rw rw rw cold start / warm start discrimination flag (note 1, 2) 0 : cold start 1 : warm start wdc5 note 1: writing to the wdc register causes the wdc5 bit to be set to 1 (warm start). note 2: the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 when the input voltage at the v cc pin drops to v det 2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enable). (b4-b0) (b6) setting the pm22 bit to 1 results in the following conditions ? the ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. ? the cm10 bit of cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) ? the watchdog timer does not stop when in wait mode. watchdog timer period = watchdog timer count (32768) ring oscillator clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 75 of n rej09b0047-0060z 11. dmac the dmac (direct memory access controller) allows data to be transferred without the cpu intervention. two dmac channels are included. each time a dma request occurs, the dmac transfers one (8 or 16-bit) data from the source address to the destination address. the dmac uses the same data bus as used by the cpu. because the dmac has higher priority of bus control than the cpu and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a dma request is generated. figure 11.1 shows the block diagram of the dmac. table 11.1 shows the dmac specifications. figures 11.2 to 11.4 show the dmac-related registers. figure 11.1 dmac block diagram a a a a a a aa aa aa aa a a aa aa aa aa aa a a a a a a data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a a a aa aa dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. aa aa aa aa aa aa a a a a a a a a a a aa aa aa aa a a a a a a a a a a dma request is generated by a write to the dmisl register (i = 0,1) s dsr bit, as well as by an interrupt request which is generated by any function specified by the dmisl register s dms and dsel3 to dsel0 bits. however, unlike in the case of interrupt requests, dma requests are not affected by the i flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, dma requests are always accepted. furthermore, because the dmac does not affect interrupts, the interrupt control register s ir bit does not change state due to a dma transfer. a data transfer is initiated each time a dma request is generated when the dmicon register s dmae bit = 1 (dma enabled). however, if the cycle in which a dma request is generated is faster than the dma transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. for details, refer to dma requests . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 76 of n rej09b0047-0060z item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors ________ ________ falling edge of int0 or int1 (note 1, note 2) ________ ________ both edge of int0 or int1 timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transfer, uart0 reception interrupt requests uart1 transfer, uart1 reception interrupt requests uart2 transfer, uart2 reception interrupt requests si/o3, si/o4 interrupt requests a-d conversion interrupt requests timer s(icoc) requests software triggers channel priority dma0 > dma1 (dma0 takes precedence) transfer unit 8 bits or 16 bits transfer address direction forward or fixed (the source and destination addresses cannot both be in the forward direction.) transfer mode single transfer transfer is completed when the dmai transfer counter (i = 0,1) underflows after reaching the terminal count. repeat transfer when the dmai transfer counter underflows, it is reloaded with the value of the dmai transfer counter reload register and a dma transfer is con tinued with it. dma interrupt request generation timing when the dmai transfer counter underflowed dma startup data transfer is initiated each time a dma request is generated when the dmaicon register s dmae bit = 1 (enabled). dma shutdown single transfer ? when the dmae bit is set to 0 (disabled) ? after the dmai transfer counter underflows repeat transfer when the dmae bit is set to 0 (disabled) when a data transfer is started after setting the dmae bit to 1 (en abled), the forward address pointer is reloaded with the value of the sari or the dari pointer whichever is specified to be in the forward direction and the dmai transfer counter is reloaded with the value of the dmai transfer counter reload register. table 11.1 dmac specifications notes: 1. dma transfer is not effective to any interrupt. dma transfer is affected neither by the i flag nor by the interrupt control register. 2. the selectable causes of dma requests differ with each channel. 3. make sure that no dmac-related registers (addresses 0020 16 to 003f 16 ) are accessed by the dmac. reload timing for forward ad- dress pointer and transfer counter m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 77 of n rej09b0047-0060z dma0 request cause select register symbol address after reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. when write, set to 0 . when read, its content is 0 . software dma request bit a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int0 pin icoc base timer 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 icoc channel 0 0 0 1 1 2 timer a1 icoc channel 1 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 C 0 1 1 0 2 timer a4 two edges of int0 pin 0 1 1 1 2 timer b0 C 1 0 0 0 2 timer b1 C 1 0 0 1 2 timer b2 C 1 0 1 0 2 uart0 transmit icoc channel 2 1 0 1 1 2 uart0 receive icoc channel 3 1 1 0 0 2 uart2 transmit icoc channel 4 1 1 0 1 2 uart2 receive icoc channel 5 1 1 1 0 2 a-d conversion icoc channel 6 1 1 1 1 2 uart1 transmit icoc channel 7 bit name dma request cause expansion select bit dms 0: basic cause of request 1: extended cause of request rw rw rw rw rw rw (b5-b4) refer to note note: the causes of dma0 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below. figure 11.2 dm0sl register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 78 of n rej09b0047-0060z dmai control register (i=0,1) symbol address after reset dm0con 002c 16 00000x00 2 dm1con 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 2) destination address direction select bit (note 2) 0 : fixed 1 : forward dsd dad nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: the dmas bit can be set to 0 by writing 0 in a program (this bit remains unchanged even if 1 is written). note 2: at least one of the dad and dsd bits must be 0 ( address direction fixed ) . (note 1) dma1 request cause select register symbol address after reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 software dma request bit dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int1 pin icoc base timer 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 icoc channel 0 0 0 1 1 2 timer a1 icoc channel 1 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 si/o3 0 1 1 0 2 timer a4 si/o4 0 1 1 1 2 timer b0 two edges of int1 1 0 0 0 2 timer b1 C 1 0 0 1 2 timer b2 C 1 0 1 0 2 uart0 transmit icoc channel 2 1 0 1 1 2 uart0 receive icoc channel 3 1 1 0 0 2 uart2 transmit icoc channel 4 1 1 0 1 2 uart2 receive/ack2 icoc channel 5 1 1 1 0 2 a-d conversion icoc channel 6 1 1 1 1 2 uart1 receive icoc channel 7 bit name dma request cause expansion select bit dms rw rw rw rw rw rw (b5-b4) rw rw rw rw rw rw rw (b7-b6) note: the causes of dma1 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below. nothing is assigned. when write, set to 0 . when read, its content is 0 . a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . 0: basic cause of request 1: extended cause of request refer to note figure 11.3 dm1sl register, dm0con register, and dm1con registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 79 of n rej09b0047-0060z b7 b0 b7 b0 (b8) (b15) function set the transfer count minus 1. the written value is stored in the dmai transfer counter reload register, and when the dmae bit of dmicon register is set to 1 (dma enabled) or the dmai transfer counter underflows when the dmasl bit of dmicon register is 1 (repeat transfer), the value of the dmai transfer counter reload register is transferred to the dmai transfer counter. when read, the dmai transfer counter is read. symbol address after reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) setting range 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw set the source address of transfer symbol address after reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) (note) setting range 00000 16 to fffff 16 nothing is assigned. when write, set 0 . when read, these contents are 0 . symbol address after reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function set the destination address of transfer dmai destination pointer (i = 0, 1)(note) setting range 00000 16 to fffff 16 b7 (b23) rw rw rw rw rw note: if the dsd bit of dmicon register is 0 (fixed), this register can only be written to when the dmae bit of dmicon register is 0 (dma disabled). if the dsd bit is 1 (forward direction), this register can be written to at any time. if the dsd bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. nothing is assigned. when write, set 0 . when read, these contents are 0 . note: if the dad bit of dmicon register is 0 (fixed), this register can only be written to when the dmae bit of dmicon register is 0 (dma disabled). if the dad bit is 1 (forward direction), this register can be written to at any time. if the dad bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. figure 11.4 sar0, sar1, dar0, dar1, tcr0, and tcr1 registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 80 of n rej09b0047-0060z 11.1 transfer cycles the transfer cycle consists of a memory or sfr read (source read) bus cycle and a write (destination write) bus cycle. the number of read and write bus cycles is affected by the source and destination addresses of transfer. furthermore, the bus cycle itself is extended by a software wait. 11.1.1 effect of source and destination addresses if the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. 11.1.2 effect of software wait for memory or sfr accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. figure 11.1.1 shows the example of the cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. for example, when data is transferred in 16 bit units and when both the source address and destination address are an odd address ((2) in figure 11.1.1), two source read bus cycles and two destination write bus cycles are required. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 81 of n rej09b0047-0060z cpu clock address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) when the transfer unit is 8 or 16 bits and the source of transfer is an even address address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) when the source read cycle under condition (1) has one wait state inserted address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) when the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) when the source read cycle under condition (2) has one wait state inserted note: the same timing changes occur with the respective conditions at the destination as at the source. cpu clock cpu clock cpu clock figure 11.1.1 transfer cycles for source read m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 82 of n rej09b0047-0060z table 11.2.1 dma transfer cycles table 11.2.2 coefficient j, k internal area internal rom, ram sfr no wait with wait 1 1 2 2 2 2 j k 3 3 1 wait 2 wait (note) (note) note : depends on the set value of pm20 bit in pm2 register 11.2. dma transfer cycles any combination of even or odd transfer read and write adresses is possible. table 11.2.1 shows the number of dma transfer cycles. table 11.2.2 shows the coefficient j, k. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k transfer unit access address no. of read cycles no. of write cycles 8-bit transfers even 1 1 (dmbit= 1 ) odd 1 1 16-bit transfers even 1 1 (dmbit= 0 ) odd 2 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 83 of n rej09b0047-0060z 11.3 dma enable when a data transfer starts after setting the dmae bit in dmicon register (i = 0, 1) to 1 (enabled), the dmac operates as follows: (1) reload the forward address pointer with the sari register value when the dsd bit in dmicon register is 1 (forward) or the dari register value when the dad bit of dmicon register is 1 (forward). (2) reload the dmai transfer counter with the dmai transfer counter reload register value. if the dmae bit is set to 1 again while it remains set, the dmac performs the above operation. however, if a dma request may occur simultaneously when the dmae bit is being written, follow the steps below. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously. step 2: make sure that the dmai is in an initial state as described above (1) and (2) in a program. if the dmai is not in an initial state, the above steps should be repeated. 11.4 dma request the dmac can generate a dma request as triggered by the cause of request that is selected with the dms and dsel3 to dsel0 bits of dmisl register (i = 0, 1) on either channel. table 11.4.1 shows the timing at which the dmas bit changes state. whenever a dma request is generated, the dmas bit is set to 1 (dma requested) regardless of whether or not the dmae bit is set. if the dmae bit was set to 1 (enabled) when this occurred, the dmas bit is set to 0 (dma not requested) immediately before a data transfer starts. this bit cannot be set to 1 in a program (it can only be set to 0 ). the dmas bit may be set to 1 when the dms or the dsel3 to dsel0 bits change state. therefore, always be sure to set the dmas bit to 0 after changing the dms or the dsel3 to dsel0 bits. because if the dmae bit is 1 , a data transfer starts immediately after a dma request is generated, the dmas bit in almost all cases is 0 when read in a program. read the dmae bit to determine whether the dmac is enabled. table 11.4.1 timing at which the dmas bit changes state dma factor software trigger peripheral function timing at which the bit is set to 1 timing at which the bit is set to 0 dmas bit of the dmicon register when the dsr bit of dmisl register is set to 1 when the interrupt control register for the peripheral function that is selected by the dsel3 to dsel0 and dms bits of dmisl register has its ir bit set to 1 ? immediately before a data transfer starts ? when set by writing 0 in a program m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 11. dmac rev.0.60 2004.02.01 page 84 of n rej09b0047-0060z 11.5 channel priority and dma transfer timing if both dma0 and dma1 are enabled and dma transfer request signals from dma0 and dma1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of cpu clock), the dmas bit on each channel is set to 1 (dma requested) at the same time. in this case, the dma requests are arbitrated according to the channel priority, dma0 > dma1. the following de- scribes dmac operation when dma0 and dma1 requests are detected active in the same sampling period. figure 11.5.1 shows an example of dma transfer effected by external factors. dma0 request having priority is received first to start a transfer when a dma0 request and dma1 request are generated simultanelously. after one dma0 transfer is completed, a bus arbitration is returned to the cpu. when the cpu has completed one bus access, a dma1 transfer starts. after one dma1 transfer is completed, the bus arbitration is again returned to the cpu. in addition, dma requsts cannot be counted up since each channel has one dmas bit. therefore, when dma requests, as dma1 in figure 11.5.1, occurs more than one time, the dams bit is set to "0" as soon as getting the bus arbitration. the bus arbitration is returned to the cpu when one transfer is completed. aaaa aaaa dma0 aaaa aaaa dma1 dma0 request bit dma1 request bit aaa aaa aaaaaa aaaaaa a a aaaaa aaaaa aa aa cpu int0 int1 obtainment of the bus right an example where dma requests for external causes are detected active at the same cpu clock figure 11.5.1 dma transfer by external factors m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 85 of n rej09b0047-0060z 12. timers eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer a (five) and timer b (three). the count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. figures 12.1 and 12.2 show block diagrams of timer a and timer b configuration, respectively. ? timer mode ? one-shot timer mode ? pulse width measuring (pwm) mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 or f 2 f 8 f 32 ? main clock ? pll clock ? ring oscillator clock x cin set the cpsr bit of cpsrf register to 1 (= prescaler reset) reset clock prescaler timer b2 overflow or underflow 1/2 f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2 figure 12.1. timer a configuration m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 86 of n rej09b0047-0060z figure 12.2. timer b configuration ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 x cin reset clock prescaler timer b2 overflow or underflow ( to timer a count source) timer b1 interrupt timer b2 interrupt 1/8 1/4 f 8 f 32 1/2 f 1 or f 2 ? main clock ? pll clock ? ring oscillator clock set the cpsr bit of cpsrf register to 1 (= prescaler reset) f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 87 of n rej09b0047-0060z 12.1 timer a figure 12.1.1 shows a block diagram of the timer a. figures 12.1.2 to 12.1.4 show registers related to the timer a. the timer a supports the following four modes. except in event counter mode, timers a0 to a4 all have the same function. use the tmod1 to tmod0 bits of taimr register (i = 0 to 4) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows and underflows of other timers. ? one-shot timer mode: the timer outputs a pulse only once before it reaches the minimum count 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses in a given width successively. figure 12.1.2. ta0mr to ta4mr registers tabsr register up-count/down-count tai addresses taj tak timer a0 0387 16 - 0386 16 timer a4 timer a1 timer a1 0389 16 - 0388 16 timer a0 timer a2 timer a2 038b 16 - 038a 16 timer a1 timer a3 timer a3 038d 16 - 038c 16 timer a2 timer a4 timer a4 038f 16 - 038e 16 timer a3 timer a0 always counts down except in event counter mode reload register counter low-order 8 bits aaaa high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 1 or f 2 f 8 f 32 tai in (i = 0 to 4) tb2 overflow ? event counter f c32 clock selection taj overflow (j = i C 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits a a udf register down count tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection to external trigger circuit (note) (note) note: overflow or underflow clock selection timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit rw rw rw rw rw rw rw rw function varies with each operation mode figure 12.1.1. timer a block diagram m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 88 of n rej09b0047-0060z figure 12.1.3. ta0 to ta4 registers, tabsr register, and udf register symbol address after reset ta0 0387 16 , 0386 16 indeterminate ta1 0389 16 , 0388 16 indeterminate ta2 038b 16 , 038a 16 indeterminate ta3 038d 16 , 038c 16 indeterminate ta4 038f 16 , 038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (i= 0 to 4) (note 1) rw divide the count source by n + 1 where n = set value function setting range divide the count source by ffff 16 C n + 1 where n = set value when counting up or by n + 1 when counting down divide the count source by n where n = set value and cause the timer to stop modify the pulse width as follows: pwm period: (2 16 C 1) / fj high level pwm pulse width: n / fj where n = set value, fj = count source frequency 0000 16 to fffe 16 (note 3, 4) note 1: the register must be accessed in 16 bit units. note 2: if the tai register is set to 0000 16 , the counter does not work and timer ai interrupt requests are not generated either. furthermore, if pulse output is selected, no pulses are output from the taiout pin. note 3: if the tai register is set to 0000 16 , the pulse width modulator does not work, the output level on the taiout pin remains low, and timer ai interrupt requests are not generated either. the same applies when the 8 high-order bits of the timer tai register are set to 001 6 while operating as an 8-bit pulse width modulator. note 4: use the mov instruction to write to the tai register. note 5: the timer counts pulses from an external device or overflows or underflows in other timers. 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low-order address) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address after reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count enabled by setting the taimr register s mr2 bit to 0 (= switching source in udf register) during event counter mode. 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled symbol address after reset tabsr 0380 16 00 16 count start flag bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s note 1: use mov instruction to write to this register. note 2: make sure the port direction bits for the ta2 in to ta4i n and ta2 out to ta4 out pins are set to 0 (input mode). note 3: when not using the two-phase pulse signal processing function, set the corresponding bit to 0 . rw rw wo wo wo rw rw rw rw rw rw rw rw rw rw rw rw rw rw wo wo wo timer mode event counter mode one-shot timer mode pulse width modulation mode (16-bit pwm) pulse width modulation mode (8-bit pwm) 0000 16 to ffff 16 0000 16 to ffff 16 0000 16 to ffff 16 (notes 2, 4) mode modify the pulse width as follows: pwm period: (2 8 C 1) x (m + 1)/ fj high level pwm pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency (note 3, 4) (notes 2, 3) (note 5) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 89 of n rej09b0047-0060z symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock prescaler reset flag setting this bit to 1 initializes the prescaler for the timekeeping clock. ( when read, its content is 0 .) cpsr nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 is selected 1 0 : ta0 is selected 1 1 : ta2 is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 is selected 1 0 : ta1 is selected 1 1 : ta3 is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 is selected 1 0 : ta2 is selected 1 1 : ta4 is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 is selected 1 0 : ta3 is selected 1 1 : ta0 is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note : make sure the port direction bits for the ta1 in to ta4 in pins are set to 0 (= input mode). ta1os ta2os ta0os one-shot start flag symbol address after reset onsf 0382 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta0 in is selected 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 rw the timer starts counting by setting this bit to 1 while the tmod1 to tmod0 bits of taimr register (i = 0 to 4) = 10 2 (= one-shot timer mode) and the mr2 bit of taimr register = 0 (=taios bit enabled). when read, its content is 0 . z-phase input enable bit tazie 0 : z-phase input disabled 1 : z-phase input enabled rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b6-b0) (note 2) (note 2) (note 2) note 1: make sure the pd7_1 bit of pd7 register is set to 0 (= input mode). note 2: overflow or underflow (note 1) figure 12.1.4. onsf register, trgsr register, and cpsrf register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 90 of n rej09b0047-0060z item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tai register (i= 0 to 4) 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer underflow tai in pin function i/o port or gate input tai out pin function i/o port or pulse output read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? gate function counting can be started and stopped by an input signal to tai in pin ? pulse output function whenever the timer underflows, the output polarity of tai out pin is inverted. when not counting, the pin outputs a low. 12.1.1. timer mode in timer mode, the timer counts a count source generated internally (see table 12.1.1.1). figure 1.2.1.1.1 shows taimr register in timer mode. table 12.1.1.1. specifications in timer mode note 1: the port direction bit for the tai in pin must be set to 0 (= input mode). timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (ta iout pin is a pulse output pin) gate function select bit 0 0 : gate function not available 0 1 : (tai in pin functions as i/o port) 1 0 : counts while input on the tai in pin is low (note 1) 1 1 : counts while input on the tai in pin is high (note 1) b4 b3 mr2 mr1 mr3 must be set to 0 in timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 rw rw rw rw rw rw rw rw } figure 12.1.1.1. timer ai mode register in timer mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 91 of n rej09b0047-0060z item specification count source ? external signals input to tai in pin (i=0 to 4) (effective edge can be selected in program) ? timer b2 overflows or underflows, timer aj (j=i-1, except j=4 if i=0) overflows or underflows, timer ak (k=i+1, except k=0 if i=4) overflows or underflows count operation ? up-count or down-count can be selected by external signal or program ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divided ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function i/o port or count source input tai out pin function i/o port, pulse output, or up/down-count select input read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function whenever the timer underflows or underflows, the output polarity of tai out pin is inverted . when not counting, the pin outputs a low. 12.1.2. event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. timers a2, a3 and a4 can count two-phase external signals. table 12.1.2.1 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). table 12.1.2.2 lists specifica- tions in event counter mode (when processing two-phase pulse signal with the timers a2, a3 and a4). figure 12.1.2.1 shows taimr register in event counter mode (when not processing two-phase pulse signal). figure 12.1.2.2 shows ta2mr to ta4mr registers in event counter mode (when processing two- phase pulse signal with the timers a2, a3 and a4). table 12.1.2.1. specifications in event counter mode (when not processing two-phase pulse signal) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 92 of n rej09b0047-0060z note 1: during event counter mode, the count source can be selected using the onsf and trgsr registers. note 2: effective when the taitgh and taitgl bits of onsf or trgsr register are 00 2 (tai in pin input). note 3: count down when input on tai out pin is low or count up when input on that pin is high. the port direction bit for tai out pin must be set to 0 (= input mode). symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (tai out pin functions as pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 must be set to 0 in event counter mode tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : udf register 1 : input signal to ta iout pin (note 3) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 can be 0 or 1 when not using two-phase pulse signal processing tmod1 timer ai mode register (i=0 to 4) (when not using two-phase pulse signal processing) rw rw rw rw rw rw rw rw figure 12.1.2.1. taimr register in event counter mode (when not using two-phase pulse signal processing) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 93 of n rej09b0047-0060z item specification count source ? two-phase pulse signals input to tai in or tai out pins (i = 2 to 4) count operation ? up-count or down-count can be selected by two-phase pulse signal ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divide ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read by reading timer a2, a3 or a4 register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to reload register (transferred to counter when reloaded next) select function (note) ? normal processing operation (timer a2 and timer a3) the timer counts up rising edges or counts down falling edges on taj in pin when input signals on taj out pin is h . ? multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that tak in (k=3, 4) pin goes h when the input signal on tak out pin is h , the timer counts up rising and falling edges on tak out and tak in pins. if the phase relationship is such that tak in pin goes l when the input signal on tak out pin is h , the timer counts down rising and falling edges on tak out and tak in pins. table 12.1.2.2. specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3 and a4) taj out up- count up- count up- count down- count down- count down- count taj in (j=2,3) tak out tak in (k=3,4) count up all edges count up all edges count down all edges count down all edges ? counter initialization by z-phase input (timer a3) the timer count value is initialized to 0 by z-phase input. notes: 1. only timer a3 is selectable. timer a2 is fixed to normal processing operation, and timer a4 is fixed to multiply-by-4 processing operation. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 94 of n rej09b0047-0060z note 1: tck1 bit is valid for timer a3 mode register. no matter how this bit is set, timers a2 and a4 always operate in normal processing mode and x4 processing mode, respectively. note 2: if two-phase pulse signal processing is desired, following register settings are required: ? set the udf register s taip bit to 1 (two-phase pulse signal processing function enabled). ? set the trgsr register s taitgh and taitgl bits to 00 2 (taiin pin input). ? set the port direction bits for tai in and tai out to 0 (input mode). timer ai mode register (i=2 to 4) (when using two-phase pulse signal processing) symbol address after reset ta2mr to ta4mr 0398 16 to 039a 16 00 16 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 to use two-phase pulse signal processing, set this bit to 0 . mr2 mr1 mr3 tck1 tck0 01 0 bit name function rw count operation type select bit two-phase pulse signal processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 rw rw rw rw rw rw rw rw to use two-phase pulse signal processing, set this bit to 0 . to use two-phase pulse signal processing, set this bit to 1 . to use two-phase pulse signal processing, set this bit to 0 . figure 12.1.2.2. ta2mr to ta4mr registers in event counter mode (when using two-phase pulse signal processing with timer a2, a3 or a4) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 95 of n rej09b0047-0060z mm+11 2 3 4 5 ta3 out (a phase) count source ta3 in (b phase) timer a3 int2 (z phase) (note) input equal to or greater than one clock cycle of count source note: this timing diagram is for the case where the pol bit of int2ic register = 1 (= rising edge). 12.1.2.1 counter initialization by two-phase pulse signal processing this function initializes the timer count value to 0 by z-phase (counter initialization) input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with z-phase entered from the int2 pin. counter initialization by z-phase input is enabled by writing 0000 16 to the ta3 register and setting the tazie bit in onsf register to 1 (= z-phase input enabled). counter initialization is accomplished by detecting z-phase input edge. the active edge can be cho- sen to be the rising or falling edge by using the pol bit of int2ic register. the z-phase pulse width _______ applied to the int2 pin must be equal to or greater than one clock cycle of the timer a3 count source. the counter is initialized at the next count timing after recognizing z-phase input. figure 12.1.2.1.1 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. if timer a3 overflow or underflow coincides with the counter initialization by z-phase input, a timer a3 interrupt request is generated twice in succession. do not use the timer a3 interrupt when using this function. figure 12.1.2.1.1. two-phase pulse (a phase and b phase) and the z phase m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 96 of n rej09b0047-0060z item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the counter reaches 0000 16 , it stops counting after reloading a new value ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value of tai register 0000 16 to ffff 16 however, the counter does not work if the divide-by-n value is set to 0000 16 . count start condition tais bit of tabsr register = 1 (start counting) and one of the following triggers occurs. ? external trigger input from the tai in pin ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow ? the taios bit of onsf register is set to 1 (= timer starts) count stop condition ? when the counter is reloaded after reaching 0000 16 ? tais bit is set to 0 (= stop counting) interrupt request generation timing when the counter reaches 0000 16 tai in pin function i/o port or trigger input tai out pin function i/o port or pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? pulse output function the timer outputs a low when not counting and a high when counting. table 12.1.3.1. specifications in one-shot timer mode 12.1.3. one-shot timer mode in one-shot timer mode, the timer is activated only once by one trigger. (see table 12.1.3.1.) when the trigger occurs, the timer starts up and continues operating for a given period. figure 12.1.3.1 shows the taimr register in one-shot timer mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 97 of n rej09b0047-0060z figure 12.1.3.1. taimr register in one-shot timer mode bit name timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (tai out pin functions as a pulse output pin) mr2 mr1 mr3 must be set to 0 in one-shot timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : taios bit is enabled 1 : selected by taitgh to taitgl bits trigger select bit external trigger select bit (note 1) 0 : falling edge of input signal to tai in pin (note 2) 1 : rising edge of input signal to tai in pin (note 2) note 1: effective when the taitgh and taitgl bits of onsf or trgsr register are 00 2 (tai in pin input). note 2: the port direction bit for the tai in pin must be set to 0 (= input mode). rw rw rw rw rw rw rw rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 98 of n rej09b0047-0060z 12.1.4. pulse width modulation (pwm) mode in pwm mode, the timer outputs pulses of a given width in succession (see table 12.1.4.1). the counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. figure 12.1.4.1 shows taimr register in pulse width modulation mode. figures 12.1.4.2 and 12.1.4.3 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. table 12.1.4.1. specifications in pulse width modulation mode item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? d own-count (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new value at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs during counting 16-bit pwm ? high level width n / fj n : set value of tai register (i=o to 4) ? cycle time (2 16 -1) / fj fixed fj: count source frequency (f 1 , f 2 , f 8 , f 32 , f c32 ) 8-bit pwm ? high level width n x (m+1) / fj n : set value of tai register high-order address ? cycle time (2 8 -1) x (m+1) / fj m : set value of tai register low-order address count start condition ? tais bit of tabsr register is set to 1 (= start counting) ? the tais bit = 1 and external trigger input from the tai in pin ? the tais bit = 1 and one of the following external triggers occurs ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow count stop condition tais bit is set to 0 (= stop counting) interrupt request generation timing pwm pulse goes l tai in pin function i/o port or trigger input tai out pin function pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 99 of n rej09b0047-0060z figure 12.1.4.1. taimr register in pulse width modulation mode bit name timer ai mode register (i= 0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit rw 11 1 must be set to 1 in pwm mode 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of input signal to tai in pin(note 2) 1: rising edge of input signal to tai in pin(note 2) rw rw rw rw rw rw rw rw 0 : write 1 to tais bit in the tasf register 1 : selected by taitgh to taitgl bits note 1: effective when the taitgh and taitgl bits of onsf or trgsr register are 00 2 (tai in pin input). note 2: the port direction bit for the tai in pin must be set to 0 (= input mode). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.1 timer a rev.0.60 2004.02.01 page 100 of n rej09b0047-0060z 1 / f i x (2 C 1) 16 count source input signal to ta iin pin pwm pulse output from ta iout pin trigger is not generated by this signal h h l l ir bit of taiic register 1 0 f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 note 1: n = 0000 16 to fffe 16 . note 2: this timing diagram is for the case where the tai register is 0003 16 , the taitgh and taitgl bits of onsf or trgsr register = 00 2 (tai in pin input), the mr1 bit of taimr register = 1 (rising edge), and the mr2 bit of taimr register = 1 (trigger selected by taitgh and taitgl bits). 1 / f j x n set to 0 upon accepting an interrupt request or by writing in program count source (note1) input signal to ta iin pin underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin h h h l l l 1 0 set to 0 upon accepting an interrupt request or by writing in program note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to fe 16 . note 4: this timing diagram is for the case where the tai register is 0202 16 , the taitgh and taitgl bits of onsf or trgsr register = 00 2 (tai in pin input), the mr1 bit of taimr register = 0 (falling edge), and the mr2 bit of taimr register = 1 (trigger selected by taitgh and taitgl bits). aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa 1 / f j x (m + 1) x (2 C 1) 8 1 / f j x (m + 1) x n 1 / f j x (m + 1) ir bit of taiic register f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 figure 12.1.4.2. example of 16-bit pulse width modulator operation figure 12.1.4.3. example of 8-bit pulse width modulator operation m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 101 of n rej09b0047-0060z 12.2 timer b figure 12.2.1 shows a block diagram of the timer b. figures 12.2.2 and 12.2.3 show registers related to the timer b. timer b supports the following four modes. use the tmod1 and tmod0 bits of tbimr register (i = 0 to 2) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows or underflows of other timers. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. ? a-d trigger mode: the timer counts only once before it reaches the minimum count "0000 16 " figure 12.2.1. timer b block diagram timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode or a-d trigger mode 0 1 : event counter mode 1 0 : pulse period measurement mode, pulse width measurement mode 1 1 : must not be set b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit (note 1) (note 2) note 1: timer b0. note 2: timer b1, timer b2. rw rw rw rw rw rw rw ro function varies with each operation mode clock source selection ? event counter ? timer ? pulse period measuremnet, pulse width measurement reload register low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 or f 2 f 8 f 32 tbj overflow (note) (j = i C 1, except j = 2 if i = 0) can be selected in only event counter mode tabsr register f c32 polarity switching, edge pulse tbi in (i = 0 to 2) counter reset circuit counter tbi address tbj timer b0 0391 16 - 0390 16 timer b2 timer b1 0393 16 - 0392 16 timer b0 timer b2 0395 16 - 0394 16 timer b1 clock selection note: overflow or underflow. figure 12.2.2. tb0mr to tb2mr registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 102 of n rej09b0047-0060z symbol address after reset tabsr 0380 16 00 16 count start flag bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function rw rw rw rw rw rw rw rw rw symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa a aaaaaaaaaaaaaa a aaaaaaaaaaaaaaaa clock prescaler reset flag cpsr nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. rw rw (b6-b0) setting this bit to 1 initializes the prescaler for the timekeeping clock. (when read, the value of this bit is 0 .) symbol address after reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (i=0 to 2)(note 1) rw measures a pulse period or width function rw rw ro note 1: the register must be accessed in 16 bit units. note 2: the timer counts pulses from an external device or overflows or underflows of other timers. note 3: when this mode is used combining delayed trigger mode 0, set the larger value than the value of the timer b0 register to the timer b1 register. divide the count source by n + 1 where n = set value timer mode event counter mode 0000 16 to ffff 16 divide the count source by n + 1 where n = set value (note 2) 0000 16 to ffff 16 pulse period modulation mode, pulse width modulation mode mode setting range a-d trigger mode (note 3) divide the count source by n + 1 where n = set value and cause the timer stop rw 0000 16 to ffff 16 figure 12.2.3. tb0 to tb2 registers, tabsr register, cpsrf register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 103 of n rej09b0047-0060z item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register (i= 0 to 2) 0000 16 to ffff 16 count start condition set tbis bit (note) to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function i/o port read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) note : the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7. 12.2.1 timer mode in timer mode, the timer counts a count source generated internally (see table 12.2.1.1). figure 12.2.1.1 shows tbimr register in timer mode. table 12.2.1.1 specifications in timer mode timer bi mode register (i= 0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode or a-d trigger mode b1 b0 tmod1 tmod0 mr0 has no effect in timer mode can be set to 0 or 1 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 0 tb0mr register must be set to 0 in timer mode b7 b6 rw rw rw rw rw rw rw ro tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content is indeterminate when write in timer mode, set to 0 . when read in timer mode, its content is indeterminate. figure 12.2.1.1 tbimr register in timer mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 104 of n rej09b0047-0060z item specification count source ? external signals input to tbi in pin (i=0 to 2) (effective edge can be selected in program) ? timer bj overflow or underflow (j=i-1, except j=2 if i=0) count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register 0000 16 to ffff 16 count start condition set tbis bit 1 to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function count source input read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) notes: 1. the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7. 12.2.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see table 12.2.2.1) . figure 12.2.2.1 shows tbimr register in event counter mode. table 12.2.2.1 specifications in event counter mode figure 12.2.2.1 tbimr register in event counter mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : must not be set b3 b2 note 1: effective when the tck1 bit = 0 (input from tbiin pin). if the tck1 bit = 1 (tbj overflow or underflow), these bits can be set to 0 or 1 . note 2: the port direction bit for the tbi in pin must be set to 0 (= input mode). has no effect in event counter mode. can be set to 0 or 1 . event clock select 0 : input from tbi in pin (note 2) 1 : tbj overflow or underflow (j = i C 1, except j = 2 if i = 0) rw rw rw rw rw rw rw ro tb0mr register must be set to 0 in timer mode tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content is indeterminate. when write in event counter mode, set to 0 . when read in event counter mode, its content is indeterminate. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 105 of n rej09b0047-0060z item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? up-count ? counter value is transferred to reload register at an effective edge of mea- surement pulse. the counter value is set to 0000 16 to continue counting. count start condition set tbis (i=0 to 2) bit 3 to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing ? when an effective edge of measurement pulse is input 1 ? timer overflow. when an overflow occurs, mr3 bit of tbimr register is set to 1 (overflowed) simultaneously. mr3 bit is cleared to 0 (no overflow) by writing to tbimr register at the next count timing or later after mr3 bit was set to 1 . at this time, make sure tbis bit is set to 1 (start counting). tbi in pin function measurement pulse input read from timer contents of the reload register (measurement result) can be read by reading tbi register 2 write to timer value written to tbi register is written to neither reload register nor counter notes: 1. interrupt request is not generated when the first effective edge is input after the timer started counting. 2. value read from tbi register is indeterminate until the second valid edge is input after the timer starts counting. 3. the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7. 12.2.3 pulse period and pulse width measurement mode in pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see table 12.2.3.1). figure 12.2.3.1 shows tbimr register in pulse period and pulse width measurement mode. figure 12.2.3.2 shows the operation timing when measuring a pulse period. figure 12.2.3.3 shows the operation timing when measuring a pulse width. table 12.2.3.1 specifications in pulse period and pulse width measurement mode figure 12.2.3.1 tbimr register in pulse period and pulse width measurement mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (measurement between a falling edge and the next falling edge of measured pulse) 0 1 : pulse period measurement (measurement between a rising edge and the next rising edge of measured pulse) 1 0 : pulse width measurement (measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1 : must not be set. function b3 b2 count source select bit timer bi overflow flag ( note) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: this flag is indeterminate after reset. when the tbis bit = 1 (start counting), the mr3 bit is cleared to 0 (no overflow) by writing to the tbimr register at the next count timing or later after the mr3 bit was set to 1 (overflowed). the mr3 bit cannot be set to 1 in a program. the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7. rw rw rw rw rw rw rw ro tb0mr register must be set to 0 in pulse period and pulse width measurement mode tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content turns out to be indeterminate. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 106 of n rej09b0047-0060z figure 12.2.3.3 operation timing when measuring a pulse width measurement pulse h count source timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 1 0 (note 1) (note 1) (note 1) transfer (measured value) (note 1) (note 2) transfer (indeterminate value) reload register counter transfer timing tbis bit tbiic register's ir bit tbimr register's mr3 bit note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the tbimr register's mr1 to mr0 bits are 10 2 (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 2 figure 12.2.3.2 operation timing when measuring a pulse period count source measurement pulse tbis bit tbiic register's ir bit timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 tbimr register's mr3 bit 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the tbimr register's mr1 to mr0 bits are 00 2 (measure the interval from falling edge to falling edge of the measurement pulse). (note 1) (note 1) (note 2) transfer (measured value) 1 reload register counter transfer timing the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 107 of n rej09b0047-0060z 12.2.4 a-d trigger mode a-d trigger mode is used as conversion start trigger for a-d converter in simultaneous sample sweep mode of a-d conversion or delayed trigger mode 0. this mode is used as conversion start trigger of a-d converter. a-d trigger mode is used in timer b0 and timer b1. in this mode, the timer is activated only by one trigger. a-d trigger mode is available only for timer b0 and time b1. figure 12.2.4.1 shows the tbimr register in a-d trigger mode and figure 12.2.4.2 shows the tb2sc register. item specification count source f 1 , f 2 , f 8 , f 32 , and f c32 count operation ? down count ? when the timer underflows, reload register contents are reloaded before stopping counting ? when a trigger is generated during the count operation, the count is not affected divide ratio 1/(n+1) n: setting value of tbi register (i=0,1) 0000 16 -ffff 16 count start condition when the tbis (i=0,1) bit in the tabsr register is "1"(count started), tbien(i=0,1) in tb2sc register is "1" and the following trigger is generated. (selection based on tb2sel, tbitrig (i=0,1) bits of tb2sc) ? timer b2 overflow or underflow ? underflow of timer b2 interrupt generation frequency counter setting count stop condition ? after the count value is 0000 16 and reload register contents are reloaded ? set the tbis bit to "0"(count stopped) i nterrupt request timer underflows (note 1) generation timing tbiin pin function i/o port read from timer count value can be read by reading tbi register write to timer (note 2) ? when writing in the tbi register during count stopped. value is written to both reload register and counter ? when writing in the tbi register during count. value is written to only reload register (transfered to counter when reloaded next) note 1: a-d conversion is started by the timer underflow. for details refer to section 14. a-d converter . note 2: when using in delayed trigger mode 0, set the larger value than the value of the timer b0 register to the timer b1 register. table 12.2.4.1 specifications in a-d trigger mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.2 timer b rev.0.60 2004.02.01 page 108 of n rej09b0047-0060z timer bi mode register (i= 0 to 1) symbol address after reset tb0mr to tb1mr 039b 16 to 039c 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode or a-d trigger mode b1 b0 tmod1 tmod0 mr0 invalid in a-d trigger mode either "0" or "1" is enabled mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 0 tb0mr register set to 0 in a-d trigger mode b7 b6 rw rw rw rw rw rw rw ro tb1mr register nothing is assigned. when write, set to 0 . when read, its content is indeterminate when write in a-d trigger mode, set to 0 . when read in a-d trigger mode, its content is indeterminate. figure 12.2.4.1 tbimr register in delayed trigger mode pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw tb1en timer b1 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1" (a-d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to " 17.6 digital debounce function " for the sd input (note 2) (note 3, 4, 7) (note 5) (note 5) (note 6) (b6-b5) reserved bits must set to "0" figure 12.2.4.2 tb2sc register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 109 of n rej09b0047-0060z 12.3 three-phase motor control timer function timers a1, a2, a4 and b2 can be used to output three-phase motor drive waveforms. table 12.3.1 lists the specifications of the three-phase motor control timer function. figure 12.3.1 shows the block diagram for three-phase motor control timer function. also, the related registers are shown on figure 12.3.2 to figure 12.3.8. table 12.3.1. three-phase motor control timer function specifications active disable function item specification three-phase waveform output pin ___ ___ ___ six pins (u, u, v, v, w, w) forced cutoff input (note 1) _____ input l to sd pin used timers timer a4, a1, a2 (used in the one-shot timer mode) ___ timer a4: u- and u-phase waveform control ___ timer a1: v- and v-phase waveform control ___ timer a2: w- and w-phase waveform control timer b2 (used in the timer mode) carrier wave cycle control dead timer timer (3 eight-bit timer and shared reload register) dead time control output waveform triangular wave modulation, sawtooth wave modification enable to output h or l for one cycle enable to set positive-phase level and negative-phase level respectively carrier wave cycle triangular wave modulation: count source x (m+1) x 2 sawtooth wave modulation: count source x (m+1) m: setting value of tb2 register, 0 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 three-phase pwm output width triangular wave modulation: count source x n x 2 sawtooth wave modulation: count source x n n: setting value of ta4, ta1 and ta2 register (of ta4, ta41, ta1, ta11, ta2 and ta21 registers when setting the inv11 bit to 1 ), 1 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 dead time count source x p, or no dead time p: setting value of dtt register, 1 to 255 count source: f 1 , f 2 , f 1 divided by 2, f 2 divided by 2 active level eable to select h or l positive and negative-phase concurrent positive and negative-phases concurrent active disable function positive and negative-phases concurrent active detect func- tion interrupt frequency for timer b2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis _____ note 1: when three phase motor control function is enabled (inv02=1) p8 5 becomes sd. do not use p8 5 for _____ _____ gpio. if the sd fueature is not needed then p8 5 /sd must always be driven high. _____ __ when sd is driven low, inv03 (three phase output control bit) is cleared, pins u(p8 0 ), u(p8 1 ), __ ___ v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ) pins go back to gpio mode and are controlled by their corresponding _____ port direction and data registers. in addition if bit ivprc1 is set to 1 when sd is driven low pin p8 0 , p8 1 , p7 2 , p7 3, p7 4 , p7 5 tri-state regardless of when function (3 phase, gpio, or uart) is assigned to them. related pins p7 2 /clk 2 /ta1 out /v/rxd 1 _________ _________ ___ p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 p7 4 /ta2 out /w ____ p7 5 /ta2 in /w p8 0 /ta4 out /u ___ p8 1 /ta4 in /u m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 110 of n rej09b0047-0060z d r q 0 in v 12 1 trigger trigger tim er b 2 (timer mode) s ignal to be w ritten to tim er b 2 1 tim er b 2 interrupt request bit d u 1 bit d t q q q u three-phase output shift register (u phase) d ead tim e tim er n = 1 to 255 trigger trigger r eload register n = 1 to 255 trigger trigger u phase output signal u v v v w w w phase output control circuit d q t d q t w d q t d q t v d q t d q t u w v u r eload tim er a1 counter (one-shot timer mode) trigger tq r eload tim er a 2 counter (one-shot timer mode) trigger tq r eload tim er a4 counter (one-shot timer mode) trigger tq transfer trigger (note 1) timer b2 underflow d u 0 bit d u b0 bit ta4 register ta41 register ta1 register ta11 register ta2 register ta21 register timer ai(i = 1, 2, 4) start trigger signal timer a4 reload control signal timer a4 one-shot pulse d u b 1 bit d ead tim e tim er n = 1 to 255 d ead tim e tim er n = 1 to 255 interrupt occurrence set circuit ictb2 register n = 1 to 15 0 inv13 ictb2 counter n = 1 to 15 sd reset inv03 inv14 inv05 inv04 inv00 inv01 inv11 inv11 inv11 inv11 inv06 inv06 inv06 inv07 inv10 1/2 f1 phase output control circuit phase output control circuit phase output signal phase output signal phase output signal phase output signal phase output signal r everse control r everse control r everse control r everse control reverse control d t d t q d t r everse control idw idv idu d q t d q t d q t b2 b0 b1 b its 2 through 0 of p osition-data- retain function control register (address 034e 16 ) pd8_0 pd8_1 pd7_2 pd7_3 pd7_4 pd7_5 s q r reset sd ivprc1 data bus note : if the inv06 bit = "0" (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence o f a timer b2 underflow after writing to the idb0 and idb1 registers. set to "0" when ta2s bit = "0" set to "0" when ta1s bit = "0" set to "0" when ta4s bit = "0" diagram for switching to p8 0 , p81 and p7 2 - p7 5 is not shown. figure 12.3.1. three-phase motor control timer functions block diagram m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 111 of n rej09b0047-0060z three-phase pwm control register 0 (note 1) symbol address after reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit inv02 mode select bit inv04 positive and negative phases concurrent output disable bit inv07 software trigger select bit inv06 modulation mode select bit inv05 positive and negative phases concurrent output detect flag inv03 output control bit 0: ictb2 counter incremented by 1 at odd-numbered occurrences of a timer b2 underflow 1: ictb2 counter incremented by 1 at even-numbered occurrences of a timer b2 underflow 0: ictb2 counter incremented by 1 at a timer b2 underflow 1: selected by inv00 bit 0: three-phase motor control timer function unused 1: three-phase motor control timer function 0: three-phase motor control timer output disabled 1: three-phase motor control timer output enabled 0: simultaneous active output enabled 1: simultaneous active output disabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode setting this bit to 1 generates a transfer trigger. if the inv06 bit is 1 , a trigger for the dead time timer is also generated. the value of this bit when read is 0 . (note 9) (note 3) (note 7) (note 2, note 3) note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: if this bit needs to be set to 1 , set any value in the ictb2 register before writing to it. note 3: effective when the inv11 bit is 1 (three-phase mode 1). if inv11 is 0 (three-phase mode 0), the ictb2 counter is incremented by 1 each time the timer b2 underflows, regardless of whether the inv00 and inv01 bits are set. note 4: setting the inv02 bit to 1 activates the dead time timer, u/v/w-phase output control circuits and ictb2 counter. note 5: when inv03="1"(three-phase motor control timer output enabled) p8 0 , p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 functionas u, u, v, v, w, w note 6: the inv03 bit is set to 0 in the following cases: ? when reset ? when positive and negative go active (inv05="1") simultaneously while inv04 bit is 1 ? when set to 0 in a program ? when input on the sd pin changes state from h to l (the inv03 bit cannot be set to 1 when sd input is l .) inv03 is set to 0 when the sd pin changes from h to l regardless of the value of the invcr1 bit. inv03 is set to "0" when both inv04 bit and inv05 bit are "1". note 7: can only be set by writing 0 in a program, and cannot be set to 1 . note 8: the effects of the inv06 bit are described in the table below. (note 4) rw rw rw rw rw rw rw rw (note 5) (note 8) item mode timing at which transferred from idb0 to idb1 registers to three-phase output shift register timing at which dead time timer trigger is generated when inv16 bit is 0 inv13 bit inv06=0 triangular wave modulation mode transferred only once synchronously with the transfer trigger after writing to the idb0 to idb1 registers synchronous with the falling edge of timer a1, a2, or a4 one-shot pulse effective when inv11 is 1 and inv06 is 0 inv06=1 sawtooth wave modulation mode transferred every transfer trigger synchronous with the transfer trigger and the falling edge of timer a1, a2, or a4 one-shot pulse transfer trigger: timer b2 underflow, write to the inv07 bit or write to the tb2 register when inv10 is 1 note 9: if the inv06 bit is 1 , set the inv11 bit to 0 (three-phase mode 0) and set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). note 10: individual pins can be disabled using pfcr register. (note 6) has no effect (note 10) figure 12.3.2. invc0 register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 112 of n rej09b0047-0060z figure 12.3.3. invc1 register three-phase pwm control register 1 (note 1) symbol address after reset invc1 0349 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer a1, a2, a4 start trigger signal select bit inv10 bit symbol bit name description rw inv11 timer a1-1, a2-1, a4-1 control bit inv12 dead time timer count source select bit inv14 output polarity control bit (b7) reserved bit inv16 dead time timer trigger select bit inv15 dead time invalid bit inv13 carrier wave detect flag 0: timer b2 underflow 1: timer b2 underflow and write to the tb2 register 0: three-phase mode 0 1: three-phase mode 1 0 : f 1 or f 2 1 : f 1 divided by 2 or f 2 divided by 2 0: timer a output at even-numbered occ- urrences (ta11, ta21, ta41 register value counted) 1: timer a output at odd-numbered occ- urrences (ta1, ta2, ta4 register value counted) 0 : output waveform l active 1 : output waveform h active 0: dead time timer enabled 1: dead time timer disabled 0: falling edge of timer a4, a1 or a2 one-shot pulse 1: rising edge of three-phase output shift register (u, v or w phase) output this bit should be set to 0 note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: the effects of the inv11 bit are described in the table below. (note 5) (note 4) rw rw rw rw rw rw rw ro (note 2) item mode ta11, ta21, ta41 registers inv00 bit, inv01 bit inv13 bit inv11=0 three-phase mode 1 three-phase mode 0 not used has no effect. ictb2 counted every time timer b2 underflows regardless of whether the inv00 to inv01 bits are set. has no effect inv11=1 used effect effective when inv11 bit is 1 and inv06 bit is 0 note 3: if the inv06 bit is 1 (sawtooth wave modulation mode), set this bit to 0 (three-phase mode 0). also, if the inv11 bit is 0 , set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). note 4: the inv13 bit is effective only when the inv06 bit is 0 (triangular wave modulation mode) and the inv11 bit is 1 (three-phase mode 1). note 5: if all of the following conditions hold true, set the inv16 bit to 1 (dead time timer triggered by the rising edge of three-phase output shift register output) ? the inv15 bit is 0 (dead time timer enabled) ? when the inv03 bit is set to 1 (three-phase motor control timer output enabled), the dij bit and dibj bit (i:u, v, or w, j: 0 to 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). conversely, if either one of the above conditions holds false, set the inv16 bit to 0 (dead time timer triggered (note 3) 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 113 of n rej09b0047-0060z timer b2 interrupt occurrences frequency set counter symbol address after reset ictb2 034d 16 x? 16 function setting range b7 b0 if the inv01 bit is 0 ? (ictb2 counter counted every time timer b2 underflows), assuming the set value = n, a timer b2 interrupt is generated at every n th occurrence of a timer b2 underflow. if the inv01 bit is 1 ? (ictb2 counter count timing selected by the inv00 bit), assuming the set value = n, a timer b2 interrupt is generated at every n th occurrence of a timer b2 underflow that meets the condition selected by the inv00 bit. 1 to 15 note : use mov instruction to write to this register. if the inv01 bit = 1 ? , make sure the tb2s bit also = 0 ? (timer b2 count stopped) when writing to this register. if the inv01 bit = 0 ? , although this register can be written even when the tb2s bit = 1 ? (timer b2 count start), do not write synchronously with a timer b2 underflow. rw wo (note) nothing is assigned. when write, set to "0". when read, its content is indeterminate. b3 three-phase output buffer register i (i=0, 1) (note) symbol address after reset idb0 034a 16 00 16 idb1 034b 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dui dubi dvi dwi dvbi dwbi u phase output buffer i write the output level 0: active level 1: inactive level when read, these bits show the three-phase output shift register value. v phase output buffer i w phase output buffer i u phase output buffer i v phase output buffer i w phase output buffer i dead time timer (note 1, note 2) symbol address after reset dtt 034c 16 ?? 16 function setting range b7 b0 assuming the set value = n, upon a start trigger the timer starts counting the count source selected by the inv12 bit and stops after counting it n times. the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. 1 to 255 note: the idb0 and idb1 register values are transferred to the three-phase shift register by a transfer trigger. the value written to the idb0 register after a transfer trigger represents the output signal of each phase, and the next value written to the idb1 register at the falling edge of the timer a1, a2 or a4 one-shot pulse represents the output signal of each phase. note 1: use mov instruction to write to this register. note 2: effective when the inv15 bit is 0 (dead time timer enable). if the inv15 bit is 1 , the dead time timer is disabled and has no effect. rw rw rw rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) rw wo figure 12.3.4. idb0 register, idb1register, dtt register, and icctb2 register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 114 of n rej09b0047-0060z figure 12.3.5. ta1, ta2, ta4, ta11, ta21 and ta41 registers symbol address after reset ta1 0389 16 -0388 16 ???? 16 ta2 038b 16 -038a 16 ???? 16 ta4 038f 16 -038e 16 ???? 16 ta11 (note6,7) 0343 16 -0342 16 ???? 16 ta21 (note6,7) 0345 16 -0344 16 ???? 16 ta41 (note6,7) 0347 16 -0346 16 ???? 16 b7 b0 b7 b0 (b15) (b8) rw assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. the positive and negative phases change at the same time timer a, a2 or a4 stops. function setting range timer ai, ai-1 register (i=1, 2, 4) (note 1, note 2, note 3, note 4, note 5) note 1: the register must be accessed in 16 bit units. note 2: when the timer ai register is set to "0000 16 ", the counter does not operate and a timer ai interrupt does not occur. note 3: use mov instruction to write to these registers. note 4: if the inv15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. note 5: if the inv11 bit is "0" (three-phase mode 0), the tai register value is transferred to the reload register by a timer ai (i = 1, 2 or 4) start trigger. if the inv11 bit is "1" (three-phase mode 1), the tai1 register value is transferred to the reload register by a timer ai start trigger first and then the tai register value is transferred to the reload register by the next timer ai start trigger. thereafter, the tai1 register and tai register values are transferred to the reload register alternately. note 6: do not write to tai1 registers synchronously with a timer b2 underflow in three-phase mode 1, do not set tai1 register while the timer b underflows. . . note 7: write to the tai1 register as follows: (1) write a value to the tai1 register (2) wait for one cycle of timer ai count source. (3) write the same value to the tai1 register again. wo 0000 16 to ffff 16 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 115 of n rej09b0047-0060z ivpcr1 bit status of u/v/w pins remarks p8 5 /nmt/sd pin inputs "1" (three-phase output forcrible cutoff enable) "0" (three-phase output forcrible cutoff disable) h l h l high impedance peripheral input/output or input/output port peripheral input/output or input/output port peripheral input/output or input/output port three-phase output forcrible cutoff(note 1) note 1: the three-phase output forcrible cutoff function becomes effective if the inpcr1 bit is "1" (three-phase output forcrible cutoff function enable) even when inv03 bit is "0"(three-phase motor control timer output disalbe) ivpcr1 bit status of u/v/w pins remarks p8 5 /nmt/sd pin inputs (note 3) "1" (three-phase output forcrible cutoff enable) "0" (three-phase output forcrible cutoff disable) h l(note 1) h l(note 1) high impedance three-phase output forcrible cutoff note 1: when "l" is input to the p8 5 /nmi/sd pin, inv03 bit changes in "0" at the same time. note 2: the value of the port register and the port direction register becomes effective. note 3: when sd function isn t used, set to "0"(input) in pd8 5 and pullup to "h" in p8 5 /nmi/sd pin from outside. input/output port(note 2) three-phase pwm output three-phase pwm output the effect of p8 5 /nmi/sd pin input is below. 1.case of inv03 = "1"(three-phase motor control timer output enabled) 2.case of inv03 = "0"(three-phase motor control timer output disabled) pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw tb1en timer b1 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1" (a-d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to " 17.6 digital debounce function " for the sd input (note 2) (note 3, 4, 7) (note 5) (note 5) (note 6) (b6-b5) reserved bits must set to "0" figure 12.3.6. tb2sc registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 116 of n rej09b0047-0060z figure 12.3.7. tb2 register, trgsr register, and tabsr register ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit to use the v-phase output control circuit, set these bits to 01 2 (tb2 underflow). trigger select register bit name function bit symbol b0 to use the w-phase output control circuit, set these bits to 01 2 (tb2 underflow). 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected (note 2) 1 0 : ta2 overflow is selected (note 2) 1 1 : ta4 overflow is selected (note 2) to use the u-phase output control circuit, set these bits to 01 2 (tb2 underflow). timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit rw ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b5 b4 note 1: set the corresponding port direction bit to 0 (input mode). note 2: overflow or underflow. b7 b6 b5 b4 b3 b2 b1 symbol address after reset tabsr 0380 16 00 16 count start flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw symbol address after reset tb2 0395 16 -0394 16 indeterminate b7 b0 b7 b0 (b15) ( b8) rw 0000 16 to ffff 16 function setting rang e timer b2 register (note ) note : the register must be accessed in 16 bit units. rw divide the count source by n + 1 where n = set value. timer a1, a2 and a4 are started at every occurrence of underflow. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 117 of n rej09b0047-0060z bit name timer ai mode register symbol address after reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta4mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit must set to 10 2 (one-shot timer mode) for the three-phase motor control timer function tmod1 tmod0 mr0 pulse output function select bit must set to 0 for the three-phase motor control timer function mr2 mr1 mr3 must set to 0 for the three-phase motor control timer function 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 1 0 0 must set to 1 (selected by event/trigger select register) for the three-phase motor control timer function trigger select bit external trigger select bit rw timer b2 mode register symbol address after reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa aa aa operation mode select bit set to 00 2 (timer mode) for the three- phase motor control timer function tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 when write in three-phase motor control timer function, write 0 . when read, its content is indeterminate. 0 b7 b6 1 0 has no effect for the three-phase motor control timer function rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro has no effect for the three-phase motor control timer function. when write, set to 0 . when read, its content is indeterminate. must set to 0 for the three-phase motor control timer function 0 figure 12.3.8. ta1mr, ta2mr, ta4mr, and tb2mr registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 118 of n rej09b0047-0060z start trigger signal for timer a4* timer b2 u phase c arr i er wave signal wave u phase output signal * m nn p p m u phase u phase u phase inv14 = 0 timer a4 one-shot pulse* inv14 = 1 dead time dead time transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. an example for changing pwm outputs is shown below. (1)when inv11=1(three-phase mode 1) inv01=0, ictb2=2 16 (timer b2 interrupt is generated at every 2 th occurrence of a timer b2 underflow), or inv01=1, inv00=1, ictb2=1 16 (timer b2 interrupt is generated at even-numbered occurrences of a timer b2 underflow). initial timer value: ta41=m, ta4=m. the ta4 and ta41 registers are modified every time a timer b2 interrupt occurs. first time, ta41= n, ta4 = n. second time, ta41 = p, ta4 = p. initial values of idb0 and idb1 registers: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the third time a timer b2 interrupt occurs. (2)when inv11=0(three-phase mode 0) inv01=0, ictb2=1 16 (timer b2 interrupt is generated at every occurrence of a timer b2 underflow) initial timer value: ta4 = m. the ta4 register is modified each time a timer b2 interrupt occurs. first time, ta4 = m. second time, ta4 = n. third time, ta4 = n. fourth time, ta4 = p. fifth time, ta4 = p. initial values of idb0 and idb1 registers: du0=1, dub0=0, du1=0, dub1=1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the sixth time a timer b2 interrupt occurs. tb2s bit of the tabsr register inv13 (inv11=1(three-phase mode 1)) shown here is a typical waveform for the case where invc0 = 00xx11xx 2 (x = set as suitable for the system) and invc1 = 010xxxx0 2 . u phase output signal * ( l active) ( h active) the value written to the ta4 register and ta41 register are inverted at odd-numbered timer a outputs. figure 12.3.9. triangular wave modulation operation the three-phase motor control timer function is enabled by setting the inv02 bit of invc0 register to 1 . when this function is on, timer b2 is used to control the carrier wave, and timers a4, a1 and a2 are used __ ___ ___ to control three-phase pwm outputs (u, u, v, v, w and w). the dead time is controlled by a dedicated dead-time timer. figure 12.3.9 shows the example of triangular modulation waveform, and figure 12.3.10 shows the example of sawtooth modulation waveform. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 119 of n rej09b0047-0060z timer b2 u phase carrier wave signal wave u phase output signal * u phase u phase output signal * u phase u phase inv14 = 0 carrier wave: sawtooth waveform inv14 = 1 transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. shown here is a typical waveform for the case where invc0= 01xx110x 2 (x = set as suitable for the system) and invc1 = 010xxx00 2 . an example for changing pwm outputs is shown below. ? initial values of idb0 and idb1 registers: du0=0, dub0=1, du1=1, dub1=1. the register values are changed to du0=1, dub0=0, du1=1, dub1=1 a timer b2 interrupt occurs. start trigger signal for timer a4* timer a4 one-shot pulse* dead time dead time ( h active) ( l active) figure 12.3.10. sawtooth wave modulation operation m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 120 of n rej09b0047-0060z 12.3.1 position-data-retain function this function is used to retain the position data synchronously with the three-phase waveform output.there are three position-data input pins for u, v, and w phases. a trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address 034e 16 ). this bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge of each positive phase. 12.3.1.1 operation of the position-data-retain function figure 12.3.1.1.1 shows a usage example of the position-data-retain function (u phase) when the retain trigger is selected as the falling edge of the positive signal. (1) at the falling edge of the u-phase waveform ouput, the state at pin idu is transferred to the u- phase position data retain bit ( bit2 at address 034e 16 ). (2) until the next falling edge of the uphase waveform output,the above value is retained. transferred carrier wave u-phase waveform output u-phase waveform output 1 2 transferred transferred transferred pin idu u-phase position data retain bit (bit 2 at address 034e 16 ) note: n o t e : the retain trigger is the falling edge of the positive signal. figure 12.3.1.1.1 usage example of position-data-retain function ( u phase ) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 12.3 three-phase motor control timer function rev.0.60 2004.02.01 page 121 of n rej09b0047-0060z 12.3.1.2 position-data-retain function control register figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register. p osition-data-retain f unction control re g ister (note) symbol address when reset pdrf 034e 16 xxxx 0000 2 ro ro ro rw bit name function bit pdrw pdrv pdru w-phase position data retain bit input level at pin idu is read out. 0: "l" level 1: "h" level note: this register is valid only in the three-phase mode. retain-trigger polarity select bit (b7-b4) rw pdrt v-phase position data retain bit nothing is assigned. when write, set to 0 ? . when read, contents are indeterminate. u-phase position data retain bit input level at pin idv is read out. 0: "l" level 1: "h" level input level at pin idw is read out. 0: "l" level 1: "h" level 0: rising edge of positive phase 1: falling edge of positive phase b 7 b3 b 2b1b0 figure 12.3.1.2.1. structure of position-data-retain function control register 12.3.1.2.1 w-phase position data retain bit (pdrw) this bit is used to retain the input level at pin idw. 12.3.1.2.2 v-phase position data retain bit (pdrv) this bit is used to retain the input level at pin idv. 12.3.1.2.3 u-phase position data retain bit (pdru) this bit is used to retain the input level at pin idu. 12.3.1.2.4 retain-trigger polarity select bit (pdrt) this bit is used to select the trigger polarity to retain the position data. when this bit = "0", the rising edge of each positive phase selected. when this bit = "1", the falling edge of each pocitive phase selected. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 122 of n rej09b0047-0060z 13. timer s (input capture/output compare) the timer s (input capture/output compare : here after, timer s is referred to as "ic/oc".) is a multi- functional i/o port for time measurement and waveform generation. each channel of the ic/oc module provides the capability for time measurement, by input capture, and also provides the capability for wave- form generation, by output comparison. the ic/oc consists of one 16-bit base timer for free-running operation, as well as eight 16-bit registers for time measurement and waveform generation. table 13.1 lists functions and channels of the ic/oc. table 13.1. ic/oc functions and channels function time measurement (note 1) 8 channels digital filter 8 channels trigger input prescaler 2 channels trigger input gate 2 channels waveform generation (note 1) 8 channels single-phase waveform output available phase-delayed waveform output available set/reset waveform output available notes 1 : the time measurement function shares pins with the waveform generation function. the time measurement function or waveform generation function can be selected for each channel. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 123 of n rej09b0047-0060z figure 13.1 shows the block diagram of the ic/oc. figures 13.1. ic/oc block diagram bts: bits in the g1bcr1 register cts1 to cts0, df1 to df0, gt, pr : bits in the g1tmcrj register (j= 0 to 7) pclk0 : bits in the pclkr register g1tm0, g1po0 register g1tm1, g1po1 register g1tm2, g1po2 register g1tm3, g1po3 register g1tm4, g1po4 register g1tm5, g1po5 register g1tm6, g1po6 register g1tm 7, g 1po 7 register pwm output pwm output pwm output pwm output base timer reset (n+1) divider register edge select digital filter gate function edge select digital filter gate function edge select digital filter edge select digital filter inpc1 0 inpc1 1 inpc1 6 (g1dv) gt gt pr pr ch0 to ch7 interrupt request signal outc1 0 outc1 1 outc1 4 outc1 5 prescaler function prescaler function outc1 6 outc1 7 outc1 2 outc1 3 (note 1) base timer f bt1 edge select digital filter inpc1 2 two-phase pulse input bck1 to bck0 : bits in the g1bcr0 register request from int1 pi n bts request by matching g1po0 register and base timer base timer over flow request bck1 to bck0 11 10 00 10:f bt1 11: f 1 or f 2 df1 to df0 cts1 to cts0 cts1 to cts0 cts1 to cts0 00 df1 to df0 00 df1 to df0 00 df1 to df0 00 0 0 1 0 1 0 1 1 df1 to df0 base timer reset register (g1btrr) request by matching g1btrr and base timer 00 cts1 to cts0 df1 to df0 edge select digital filter inpc1 3 df1 to df0 edge select digital filter inpc1 4 cts1 to cts0 df1 to df0 edge select digital filter inpc1 5 cts1 to cts0 inpc1 7 digital debounce base timer reset request base timer interrupt request 00 00 cts1 to cts0 cts1 to cts0 1/2 pclk0=0 pclk0=1 f 1 or f 2 f 1 or f 2 main clock, pll clock, ring oscillator clock 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 10:f bt1 11: f 1 or f 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 124 of n rej09b0047-0060z figures 13.2 to 13.11 show registers associated with the ic/oc base timer, the time measurement function, and the waveform generation function. figure 13.2. g1bt and g1bcr0 registers base timer register (note 1) symbol address when reset g1bt 0321 16 - 0320 16 ???? 16 rw rw function (b7) b0 setting range 0000 16 to ffff 16 b8 b15 b7 (b0) when the base timer is operating: when read, value of the counter can be read. when write, the counter starts counting from the value written. when the base timer is reset, this register is set to "0000 16 ". (note 2) when the base timer is reset: this register is set to "0000 16 " but a value read is indeterminate. no value is written. (note 2) note 1: the value which is written in this register is reflected synchronizing with the base timer count source f bt1 . note 2: this base timer stops only when the bck1 to bck0 bits in the g1bcr0 register are set to "00 2 " (count source clock stop). this base timer operates when the bck1 to bck0 bits are set to other than "00 2 ". when the bts bit in the g1bcr1 register is set to "0", the base timer continues to be held in reset, and remains in a no counting state with a value of "0000 16 ". when the bts bit in the g1bcr1 register is set to "1", this state is cleared and the timer starts counting. base timer control register 0 symbol address when reset g1bcr0 0322 16 0000 0000 2 rw rw rw rw rw rw bit name function bit symbol : clock stop : avoid this setting : two-phase input (note 1) : f 1 or f 2 (note 2) b1 0 0 1 1 b0 0 1 0 1 bck0 bck1 rst4 count source select bit channel 7 input select bit it base timer overflow select bit 0: bit 15 overflow 1: bit 14 overflow ch7insel 0: base timer not reset by matching g1btrr 1: base timer reset by matching g1btrr note 1: this setting can be used when the ud1 to ud0 bits in the g1bcr1 register are set to "10 2 " (two- phase signal processing mode). avoid setting the bck1 to bck0 bits to "10 2 " in other modes. note 2: when the pclk0 bit in the pclkr register is set to "0", the count source is f 2 . and when this bit is set to "1", the count source is f 1 . base timer reset cause select bit 4 0: p2 7 /outc1 7 /inpc1 7 pin 1: p1 7 /int5/inpc1 7 /idu pin reserved bit should be set to 0" (b5-b3) rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 125 of n rej09b0047-0060z figure 13.3. g1dv register divider register symbol address when reset g1dv 032a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 rw rw function setting range divide ratio of f 1 , f 2 or two pulse input by (n+1) for f bt1 . n: this register detemines 00 16 to ff 16 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 126 of n rej09b0047-0060z figure 13.4. g1bcr1 register rst1 0: the base timer is not reset when an input to the int1 pin is "l" level 1: the base timer is reset when an input to the int1 pin is "l" level base timer control register 1 symbol address when reset g1bcr1 0323 16 0000 0000 2 rw rw rw rw rw rw rw rw bit name function bit symbol b6 0 0 1 1 b5 0 1 0 1 (b0) rst2 base timer start bit bts ud0 ud1 base timer reset cause select bit 1 base timer reset cause select bit 2 counter increment/ decrement control bit 0: base timer is reset 1: base timer starts counting : counter increment mode : counter increment/decrement mode : two-phase pulse signal processing mode : avoid this setting note 1: the base timer is reset after two clock cycles of f bt1 when it matches the g1po0 register. (see figure 13.8 about the g1po0 register.) when setting the rst1 bit to "1", values of the g1poj register (j=1 to7) to use for the waveform generation function should be set to smaller value than values of the g1po0 register. reserved bit should set to "0". 0: the base timer is not reset by matching the g1po0 register 1: the base timer is reset by matching the g1po0 register (note 1) reserved bit should set to "0". reserved bit should be set to "0". rw (b3) (b7) 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 127 of n rej09b0047-0060z base timer reset register (note 1) symbol address when reset g1btrr 0329 16 - 0328 16 ???? 16 rw rw function setting range when enabled by the rst4 reset cause bit (bit 2 of g1bcr0), the g1btrr will reset the base timer, g1bt, when g1bt matches g1btrr 0000 16 to ffff 16 b15 b0 b7 b8 (b7) (b0) note 1: the value which is written in this register is reflected synchronizing with the base timer count source f bt1 . figure 13.5. g1btrr register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 128 of n rej09b0047-0060z figure 13.6. g1tmcr0 to g1tmcr7 registers, and g1tpr6 to g1tpr7 registers time measurement control register j (j=0 to 7) symbol g1tmcr0 to g1tmcr3 g1tmcr4 to g1tmcr7 address 0318 16 , 0319 16 , 031a 16 , 031b 16 031c 16 , 031d 16 , 031e 16 , 031f 16 when reset 0000 0000 2 0000 0000 2 rw rw rw rw rw rw rw rw rw bit name function bit symbol cts0 cts1 df0 time measurement trigger select bit df1 gate function select bit (note 2) gt goc pr gsc digital filter function select bit gate function clear select bit (notes 2, 3, 4) 0 : gate function not used 1 : gate function used gate function clear bit (notes 2, 3) prescaler function select bit (note 2) b1 0 0 1 1 b0 0 1 0 1 : no time measurement : rising edge : falling edge : both edges b3 0 0 1 1 b2 0 1 0 1 : no digital filter : avoid this setting : f bt1 : f 1 or f 2 (note 1) 0 : not cleared 1 : the gate is cleared when the base timer matches the g1pok register when setting the gsc bit to "1", the gate is cleared. 0 : not used 1 : used notes : 1. when the pclk0 bit in the pclkr register is set to "0", the count source is f 2 . and when this bit is set to "1", the count source is f 1 . 2. this bit is in the g1tmcr6 and g1tmcr7 registers. all bits 4 to 7 in the g1tmcr0 to g1tmcr5 registers should be set to "0". 3. these bits are available when setting the gt bit to "1". 3. the goc bit is set to "0" after the gate function is cleared. see figure 13.8 about the g1pok register (k=4 when j=6 and k=5 when j=7). b7 b6 b5 b4 b3 b2 b1 b0 time measurement prescale register j (j=6,7) (note 1) symbol address when reset g1tpr6 to g1tpr7 0324 16 , 0325 16 0000 0000 2 rw rw function setting range as the setting value is n, time is measured when- ever a trigger input is counted by n+1 (note 2) 00 16 to ff 16 note 1: the value which is written in this register is reflected synchronizing with the base timer count source f bt1 . note 2: the first prescaler, after the pr bit in the g1tmcrj register changes "0" (prescaler function unused) to "1" (prescaler function used), may be divided by n, not by n+1. subsequent prescalers b7 b0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 129 of n rej09b0047-0060z figure 13.7. g1tm0 to g1tm7 registers, and g1pocr0 to g1pocr7 registers time measurement register j (j=0 to 7) rw ro function setting range b15 (b7) b8 (b0) symbol g1tm0 to g1tm2 g1tm3 to g1tm5 g1tm6 to g1tm7 address 0301 16 - 0300 16, 0303 16 - 0302 16, 0305 16 - 0304 16 0307 16 - 0306 16, 0309 16 - 0308 16, 030b 16 - 030a 16 030d 16 - 030c 16, 030f 16 - 030e 16 when reset ???? 16 ???? 16 ???? 16 value of the base timer is stored every time measurement. b7 b0 waveform generation control register j (j=0 to 7) symbol address when reset g1pocr0 to g1pocr3 0310 16 , 0311 16 , 0312 16 , 0313 16 0x00 xx00 2 g1pocr4 to g1pocr7 0314 16 , 0315 16 , 0316 16 , 0317 16 0x00 xx00 2 rw rw rw rw rw rw bit name function bit symbol mod0 mod1 operation mode select bit output initial value select bit ivl rld inv 0: outputs "l" as an initial value 1: outputs "h" as an initial value inverse output function select bit (note 2) : single waveform output mode : sr waveform output mode (note 1) : phase-delayed waveform output mode : avoid this setting 0: output is not inversed 1: output is inversed b1 0 0 1 1 b0 0 1 0 1 gipoj register value reload timing select bit notes : 1. this setting is enabled only on even channels. in sr waveform output mode, the values written to the corresponding odd channel (next channel after an even channel) are ignored. an even channel outputs waveform. an odd channel outputs no waveform. 2. the inverse output function is performed as a final step on a process of waveform generation. when setting the inv bit to "1" (output inverse), "h" is output with setting the ivl bit to "0" (output "l" as an initial value) and "l" with setting the ivl bit to "1" (output "h" as an initial value). nothing is assigned. when write, should set to "0". when read, its content is indeterminate. nothing is assigned. when write, should set to "0". when read, its content is indeterminate. 0: reloads the g1poj register when the cpu writes to a counter 1: reloads the g1poj register when the base timer is reset (b3-b2) (b6) b7 b6 b5 b4 b3 b2 b1 b0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 130 of n rej09b0047-0060z figure 13.8. g1po0 to g1po7 registers waveform generation register j (j=0 to 7) symbol g1po0 to g1po2 g1po3 to g1po5 g1po6 to g1po7 rw rw function setting range b15 (b7) b8 (b0) address 0301 16 -0300 16, 0303 16 -0302 16, 0305 16 -0304 16 0307 16 -0306 16, 0309 16 -0308 16, 030b 16 -030a 16 030d 16 -030c 16, 030f 16 -030e 16 when reset ???? 16 ???? 16 ???? 16 when the rld bit in the g1pocrj register should be set to "0" value is reloaded into the g1poj register to include it in output waveform, etc. when the rld bit should be set to "1" value is reloaded when the base timer is reset. value written can be read between writing the value and reloaded. b7 b0 0000 16 to ffff 16 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 131 of n rej09b0047-0060z figure 13.9. g1fs and g1fe registers function enable register (note 1) symbol address when reset g1fe 0326 16 0000 0000 2 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol ife0 ife1 ife2 channel 0 function enable bit ife3 ife4 ife5 ife7 function ife6 0 : channel functions disabled 1 : channel functions enabled channel 1 function enable bit channel 2 function enable bit channel 3 function enable bit channel 4 function enable bit channel 5 function enable bit channel 6 function enable bit channel 7 function enable bit note 1: the value which is written in this register is reflected synchronizing with the base timer count source f bt1 . function select register symbol address when reset g1fs 0327 16 0000 0000 2 rw rw rw rw rw rw rw rw rw bit name bit symbol b7 b6 b5 b3 b2 b1 b4 b0 fsc0 fsc1 fsc2 channel 0 time measure- ment/waveform generation function select bit fsc3 fsc4 fsc5 fsc7 function fsc6 0 : select the waveform generation function 1 : select the time measurement function channel 1 time measure- ment/waveform generation function select bit channel 2 time measure- ment/waveform generation function select bit channel 3 time measure- ment/waveform generation function select bit channel 4 time measure- ment/waveform generation function select bit channel 5 time measure- ment/waveform generation function select bit channel 6 time measure- ment/waveform generation function select bit channel 7 time measure- ment/waveform generation function select bit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 132 of n rej09b0047-0060z interrupt request register (notes 1, 2) symbol address when reset g1ir 0330 16 ???? ???? 2 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ir0 g1ir1 g1ir2 interrupt request, ch0 g1ir3 g1ir4 g1ir5 g1ir7 function g1ir6 0 : no request 1 : interrupt requested interrupt request, ch1 interrupt request, ch2 interrupt request, ch3 interrupt request, ch4 interrupt request, ch5 interrupt request, ch6 interrupt request, ch7 notes: 1. interrupt request for base timer is latched by the soft interrupt 7 icr at address 0047h. 2. each g1iri (i = 0 to 7) is anded with its corresponding g1iex (x = 0 to 1) to generate soft interrupt 5 or soft interrupt 6. figure 13.10. g1ir register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 133 of n rej09b0047-0060z interrupt enable register 0 symbol address when reset g1ie0 0331 16 0000 0000 2 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ie00 g1ie01 g1ie02 interrupt enable 0, ch0 g1ie03 g1ie04 g1ie05 g1ie07 function g1ie06 0 : ic/oc interrupt 0 request disable 1 : ic/oc interrupt 0 request enable interrupt enable 0, ch1 interrupt enable 0, ch2 interrupt enable 0, ch3 interrupt enable 0, ch4 interrupt enable 0, ch5 interrupt enable 0, ch6 interrupt enable 0, ch7 interrupt enable register 1 symbol address when reset g1ie1 0332 16 0000 0000 2 b7 b6 b5 b4 b3 b2 b1 b0 rw rw rw rw rw rw rw rw rw bit name bit symbol g1ie10 g1ie11 g1ie12 interrupt enable 1, ch0 g1ie13 g1ie14 g1ie15 g1ie17 function g1ie16 0 : ic/oc interrupt 1 request disable 1 : ic/oc interrupt 1 request enable interrupt enable 1, ch1 interrupt enable 1, ch2 interrupt enable 1, ch3 interrupt enable 1, ch4 interrupt enable 1, ch5 interrupt enable 1, ch6 interrupt enable 1, ch7 figure 13.11. g1ie0 and g1ie1 registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 134 of n rej09b0047-0060z the timer increments a counter on all edges the timer decrements a counter on all edges p8 0 p8 1 13.1 base timer the base timer counts an internally generated count source with free-running. table 13.1.1 lists specifications of the base timer. table 13.1.2 shows registers associated with the base timer. figure 13.1.1 shows a block diagram of the base timer. figure 13.1.2 shows an example of the base timer in counter increment mode. figure 13.1.3 shows an example of the base timer in counter increment/ decrement mode. figure 13.1.4 shows an example of two-phase pulse signal processing mode. table 13.1.1. base timer specifications item specification count source(f bt1 ) f 1 or f 2 divided by (n+1) , two pulse input divided by (n+1) n: the div7 to div0 bits in the g1dv register determines. n=0 to 255 in f 1 and two pulse input when n=0, a count source is not divided counting operation the base timer increments the counter the base timer increments/decrements the counter (see the selectable function) two-phase pulse processing (see the selectable function) count start condition ? the base timer starts counting when the bts bit in the g1bcr1 register is set to "1" count stop condition the bts bit in the g1bcr1 register is set to "0" (base timer reset) base timer reset condition (1) value of the base timer matches value of the g1btrr register (2) value of the base timer matches value of g1po0 register. (3) apply a low-level signal ("l") to external interrupt pin,int1 pin value for base timer reset "0000 16 " interrupt request the base timer interrupt request is asserten: (1) at bit 14 or bit 15 is overflow of the base timer (2) base timer value matches the base timer reset register, and the base timer reset is enable (see figure 13.1.1.) read from timer ? while the base timer is running,the g1bt register indicates a counter value ? when the base timer is reset, a counter value is indeterminate write to timer when a value is written while the base timer is running, the value written is counted first. no value can be written while the base timer is reset. selectable function ? counter increment/decrement mode the base timer starts counting in increment mode until reaching the maximum count value. then the base timer starts in decrement mode until reaching next 0000 16 . (see figure 13.1.3.) ? two-phase pulse processing mode. two-phase pulses from p8 0 and p8 1 pins are counted (see figure 13.1.4.) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 135 of n rej09b0047-0060z table 13.1.2. base timer associated register settings (time measurement function, waveform generation function, communication function) register bit function g1bcr0 bck1 to bck0 select a count source rst4 select base timer reset timing it select the base timer overflow g1bcr1 rst2 to rst1 select base timer reset timing bts used when starting the base timer ud1 to ud0 select how to count g1bt - base timer value to read or to write g1dv - divide ratio of a count source when setting the rst1 bit to "1" (base timer reset when base timer matches g1po0), the following registers require to be setup. g1pocr0 mod1 to mod0 set to "00 2 " (single-phase waveform output mode) g1po0 - set reset cycle g1fs fsc0 set to "0" (waveform generation function) g1fe ife0 set to "1" (channel operation start) (n+1) divider rst4 rst1 rst2 matched with g1btrr matched with g1po0 register base timer b14 b15 base timer overflow request bck1 to bck0 it bts bit in g1bcr1 register two-phase pulse input overflow signal input "l" to int1 pin base timer reset 11 10 0 1 f bt1 notes : 1. divider is reset when setting bts bit to "0". it, rst4, bck1 to bck0 : bits in the g1bcr0 register rst2 to rst1: bits in the g1bcr1 register (note 1) f 1 or f 2 figure 13.1.1. base timer block diagram m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 136 of n rej09b0047-0060z figure 13.1.2. counter increment mode ffff 16 8000 16 0000 16 4000 16 c000 16 state of a counter base timer interrupts "1" "0" b14 overflow signal "1" "0" b15 overflow signal base timer interrupt the above applies to the following conditions. the rst4 bit in the g1bcr0 register is set to "0" (the base timer is not reset by matching the g1btrr register) the rst1 bit in the g1bcr1 register is set to "0" (the base timer is not reset by matching the g1po0 register) the ud1 to ud0 bits in the g1bcr1 register are set to "00 2 " (counter increment mode) it=0 in the g1bcr0 register (base timer interrupt generated by the bit 15 overflow) it=1 in the g1bcr0 register (base timer interrupt generated by the bit 14 overflow) ffff 16 8000 16 4000 16 c000 16 0000 16 state of a counter "1" "0" base timer interrupts b14 overflow signal "1" "0" b15 overflow signal base timer interrupt it=0 in the g1bcr0 register (base timer interrupt generated by the bit 15 overflow) it=1 in the g1bcr0 register (base timer interrupt generated by the bit 14 overflow) figure 13.1.3. counter increment/decrement mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 137 of n rej09b0047-0060z figure 13.1.4. base timer operation in two-phase pulse signal processing mode (1) when the base timer is reset while the base timer increments the counter (2) when the base timer is reset while the base timer decrements the counter ( ) ( ) m when selects no division (n+1) divisor value of counter min 1 s (note 1) min 1 s m+1 1 2 0 set to "0" in this timing base timer starts counting p8 0 (a-phase) p8 1 (b-phase) int1 (z-phase) set to "1" in this timing min 1 s (note 1) min 1 s m input waveform value of counter m-1 ffff 16 fffe 16 0 set to "0" in this timing note 1: more or equal to 1.5 f bt1 clock cycle are required. base timer starts counting p8 0 (a-phase) p8 1 (b-phase) int1 (z-phase) set to "ffff 16 " in this timing input waveform when no selects no division (n+1) divisor f bt1 f bt1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 138 of n rej09b0047-0060z 13.1.1 base timer reset register the base timer reset register(g1btrr) provides the capability to reset the base timer(bt) when the base timer count value matches the value stored in the g1btrr. the g1btrr is enabled by the rst4 reset cause select bit,g1bcr0(2). this function is identical in operation to the g1po0 base timer reset that is enabled by rst1.the base timer reset feature is included to allow all eight chan- nels to be used for waveform generation while providing a base timer reset on match function. it is possible to simultaneously enable both rst1 and rst4, g1po0 and g1btrr base timer resets, although operation of both base timer reset on match functions may cause unexpected behavior. it is recommended that only one of rst1 or rst4 be enabled. figure 13.1.1.1. base timer reset operation by base timer reset register figure 13.1.1.2. base timer reset operation by g1po0 register _______ figure 13.1.1.3. base timer reset operation by int1 base timer base timer reset register base timer interrupt rst4 m-2 m-1 m m+1 0000 16 0001 16 m base timer g1po0 g1ir0 rst1 m-2 m-1 m m+1 0000 16 0001 16 m base timer p8 3 /int1 rst2 m-2 m-1 m m+1 0000 16 0001 16 ________ ________ note1:int1 base timer reset does not generate a base timer interrupt,int1 may generate an interrupt if enabled. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 139 of n rej09b0047-0060z 13.2 interrupt operation the ic/oc interrupt contains several request causes. figure 13.2.1 shows the ic/oc interrupt block dia- gram and table 13.2.1 shows the ic/oc interrupt assignation. when either the base timer reset request or base timer overflow request is generated, the ir bit (bit 3 in the btic register) corresponding to the ic/oc base timer interrupt is set to "1" (with an interrupt request). also when an interrupt request of each eight channels (channel i) is generated, the bit i in the g1ir register is set to "1" (with an interrupt request). at this time, if the bit i in the g1ie0 register is "1" (ic/oc interrupt 0 request enabled), the ir bit (bit 3 in the icoc0ic register) corresponding to the ic/oc interrupt 0 is set to "1" (with an interrupt request). and if the bit i in the g1ie1 register is "1" (ic/oc interrupt 1 request enabled), the ir bit (bit 3 in the icoc1ic register) corresponding to the ic/oc interrupt 1 is set to "1"(with an interrupt request). additionally, because each bit in the g1ir register is not automatically set to "0" even if the interrupt is acknowledged, set to "0" using a program. if these bits are left "1", all ic/oc channel interrupt causes, which are generated after setting the ir bit to "1", will be disabled. figure 13.2.1. ic/oc interrupt and dma request generation table 13.2.1. interrupt assignment interrupt interrupt control register ic/oc base timer interrupt btic(0047 16 ) ic/oc interrupt 0 icoc0ic(0045 16 ) ic/oc interrupt 1 icoc0ic(0046 16 ) 13.3 dma support each of the interrupt sources - the eight ic/oc channel interrupts and the one base timer interrupt - are capable of generating a dma request. aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaa aaaaaa interrupt select logic channel 0 to 7 interrupt requests dma requests (channel 0 to 7) all register are read / write g1ie0 g1ir g1ie1 ic/oc interrupt 1 request ic/oc interrupt 0 request ic/oc base timer interrupt request base timer reset request base timer overflow request base timer interrupt / dma request enable request enable m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 140 of n rej09b0047-0060z 13.4 time measurement function synchronizing with an external trigger input, the value of the base timer is stored into the g1tmj register (j=0 to 7). table 13.4.1 shows specifications of the time measurement function. table 13.4.2 shows regis- ter settings associated with the time measurement function. figures 13.4.1 and 13.4.2 display operational timing of the time measurement function. figure 13.4.3 shows operational timing of the prescaler function and the gate function. table 13.4.1. time measurement function specifications item specification measurement channel channels 0 to 7 selecting trigger input polarity rising edge, falling edge, both edges of the inpc1j pin(note 1) measurement start condition the ifej bit in the g1fe register should be set to "1" (channels j function enabled) when the fscj bit (j=0 to 7) in the g1fs register is set to "1" (time measurement function selected). measurement stop condition the ifej bit should be set to "0" (channel j function disabled) time measurement timing ? no prescaler :every input is a trigger ? prescaler (for channel 6 and channel 7) : every [g1tpr k (k=6,7) +1] th input is a trigger interrupt request generation timing the g1iri bit (i=0 to 7) in the interrupt request register (see figure 13.10) is set to "1" at time measurement timing inpc1j pin function(note 1) trigger input pin selectable function ? digital filter function the digital filter samples a trigger input level every f 1 , f 2 or f bt1 to pass pulses matching a trigger input level three times ? prescaler function (for channel 6 and channel 7) trigger inputs are counted to perform time measurement whenever value of the g1tprk(k=6,7) register + 1 trigger is input ? gate function (for channel 6 and channel 7) when a trigger input is inhibited with setting the goc bit in the g1tmcrk (k=6,7) register to "1" (gate cleared by matching the g1pop register (p=4 when k=6, p=5 when k=7)) after time measurement by first trigger input, a trigger input is enabled to receive again by matching the base timer with the g1pop register ? digital debounce function (for channel7) see section 13.6.2 and 17.6 for details note1: the inpc1 0 to inpc1 7 pins m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 141 of n rej09b0047-0060z table 13.4.2. register settings associated with the time measurement function register bit function g1tmcrj cts1 to cts0 select time measurement trigger df1 to df0 select the digital filter function gt, goc, gsc select the gate function pr select the prescaler function g1tprk - setting value of prescaler g1fs fscj set to "1" (time measurement function) g1fe ifej set to "1" (channel j function enabled) j = 0 to 7 k = 6, 7 bit configuration and function vary depending on which channel is used. registers associated with the time measurement function should be set after setting registers associated with the base time. ffff 16 p p n n m m base timer inpc1j pin input 0000 16 g1tmj register g1irj bit when setting to "0", write "0" by program j=0 to 7 g1irj bit : bits in the g1ir register when the base timer matches the g1po0 register and is set to "0000 16 " (setting the rst1 bit to "1", and the rst4 and rst2 bits to "0"), the base timer is set to "0000 16 " after it reaches a setting value of the g1po0 register+2. the above applies to the following condition. the cts1 to cts0 bits in the g1tmcrj registers are set to "01 2 " (time measurement is trigger on the rising edge). the pr bit is set to "0" (no prescaler used) and the gt bit is set to"0" (no gate function used). bits rts4, rts2, and rts1 of the g1bcr0 and g1bcr1 registers are set to "0" (no base timer reset). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). figure 13.4.1. time measurement function (1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 142 of n rej09b0047-0060z figure 13.4.2. time measurement function (2) 2. no interrupt is generated when the microcomputer receives input when the g1irj bit is in "h". 1. bits in the g1ir register. 2. for an input pulse to the inpc1j pin, more or equal to 1.5 f bt1 clock periods are required. n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n +5 n+8 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n n+2 n+5 n+8 n+12 delayed by 1 clock f bt1 base timer inpc1j pin input or trigger signal after passing the digital filter g1tmj register (a) when selecting the rising edge for timer measurement trigger (the cts1 to cts0 bits in the g1tmcr register (j=0 to 7)=01 2 ) g1irj bit (note 1) when setting to "0", write "0" by program notes : . (note 2) (b) when selecting both edges for timer measurement trigger (the cts1 to cts0 bits=11 2 ) maximum 3.5 clock cycles of f 1 or f 2 or f bt1 (note 1) (c) trigger signal when using digital filter (the df1 to df0 bits in the g1tmcr register =10 2 or 11 2 ) signals, which do not match 3 times, are stripped off f bt1 base timer inpc1j pin input or trigger signal after passing the digital filter g1tmj register (note 2) g1irj bit (note 1) f 1 or f 2 or f bt1 (note 1) inpc1j pin trigger signal after passing the digital filter notes : . 1. bits in the g1ir register. value of the base timer is stored into the g1tmj register . when setting to "0", write "0" by program note 1: f bt1 when the df1 to df0 bits are set to "10 2 ", and f 1 or f 2 when set to "11 2 ". the trigger signal is delayed by the digital filter m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 143 of n rej09b0047-0060z figure 13.4.3. prescaler function and gate function note 1: bits in the g1ir register. g1irj bit (note 1) f bt1 1. this applies to the second period that the g1tprj register decrements after setting the pr bit in the g1tmcrj f bt1 base timer g1irj bit (note 2) g1tmj register internal time measurement trigger prescaler (note 1) (a) when using the prescaler function (when the g1tprj register (j=6, 7) =02 16 , pr bit in the g1tmcrj register (j=6, 7) =1) base timer inpc1j pin input or trigger signal after passing the digital filter internal time measurement trigger ifej bit in g1fe register g1pok register match signal gate control signal g1tmj register value of the g1pok register this trigger input is disabled due to gate function. 21 0 ffff 16 0000 16 n-2 n-1 n n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+14 n+1 n+13 2 notes : register to "1" (prescaler used). 2. bits in the g1ir register. (b) when using the gate function (gate function is cleared by matching the g1pok register and base timer, the gt bit in the g1tmcrj register=1, the goc bit=1) inpc1j pin input or trigger signal after passing the digital filter when setting to "0", write "0" by program . when setting to "0", write "0" by program gate gate gate cleared n+1 +12 n+13 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 144 of n rej09b0047-0060z 13.5 waveform generation function waveforms are generated when value of the base timer matches g1poj register (j=0 to 7). the waveform generation function has the following three modes : ? single-phase waveform output mode ? phase-delayed waveform output mode ? set/reset waveform output (sr waveform output) mode table 13.5.1 lists registers associated with the waveform generation function. table 13.5.1. registers related to the waveform generation function settings register bit function g1pocrj mod1 to mod0 select output waveform mode ivl select default value rld select g1poj register value reload timing inv select inverse output g1poj - select timing to output waveform inverted g1fs fscj set to "0" (waveform generation function) g1fe ifej set to "1" (enables function on channel j) j = 0 to 7 bit configuration and function vary depending on which channel is used. registers associated with the waveform generation function should be set after setting registers associated with the base time. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 145 of n rej09b0047-0060z 13.5.1 single-phase waveform output mode output level of the outc1j pin is inverted when value of the base timer matches that of the g1poj register (j=0 to 7). the inverted output level is returned to a default output level when the base timer reaches "0000 16 ". table 13.5.1.1 lists specifications of single-phase waveform mode. figure 13.5.1.1 lists an example of single-phase waveform mode operation. table 13.5.1.1. single-phase waveform output mode specifications item specification output waveform ? free-running operation (the rst1, rst2, and rst4 bits of the g1bcr1 and g1bcr0 registers are set to "0" (no reset)) cycle : default output level : inverse level : ? the base timer is reset when its value matches that of either register (a) g1po0 (enabled by setting bit rst1 to "1", and bits rst4 and rst2 to "0"), or (b) g1btrr (enabled by setting bit rst4 to "1", and bits rst2 and rst1 to "0") cycle : default output level : inverse level : m : setting value of the g1poj register (j=0 to 7), 0001 16 to fffd 16 n : setting value of the g1po0 register or the g1btrr register, 0001 16 to fffd 16 waveform output start condition the ifej bit in the g1fe register should be set to "1" (channel j function enabled) waveform output stop condition the ifej bit should be set to "0" (channel j function disabled) interrupt request the g1irj bit in the interrupt request register is set to "1" when value of the base timer matches one of the g1poj registers. (see figure 13.10.) outc1j pin(note 1) pulse output selectable function ? default value set function : output level is set when waveform output starts ? inverse output function : waveform level is inverted to output waveform from the outc1j pin note 1: the outc1 0 to outc1 7 pins . m f bt1 65536-m f bt1 n+2 f bt1 m f bt1 n+2-m f bt1 65536 f bt1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 146 of n rej09b0047-0060z figure 13.5.1.1. single-phase waveform output mode ffff 16 m m f bt1 65536-m f bt1 inverse 65536 f bt1 when setting to "0", write "0" by program base timer (1) free-running operation (bits rst4, rst2, and rst1 of the g1bcr0 and g1bcr1 registers are set to "0") (2) the base timer is reset when its value matches that of either register (a) g1po0 (enabled by setting bit rst1 to "1", and bits rst4 and rst2 to "0"), or (b) g1btrr (enabled by setting bit rst4 to "1", and bits rst2 and rst1 to "0") 0000 16 outc1j pin g1irj bit g1irj bit j=0 to 7 m : setting value of the g1poj register g1irj bit : bits in the g1ir register outc1j pin ffff 16 m n+2 base timer 0000 16 inverse m f bt1 n+2-m f bt1 inverse n+2 f bt1 return to initial output level when setting to "0", write "0" by program return to initial output level inverse inverse j=1 to 7 m : setting value of the g1pok register n: setting value of either g1po0 register or g1btrr register g1irj bit : bits in the g1ir register the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value) and the inv bit be set to "0" (no output inverted). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value) and the inv bit is set to "0" (no output inverted). bits rst4, rst2, and rst1 of the g1bcr0 and g1bcr1 registers are set to "0" (no base timer reset), and the ud1 to ud0 bits are set to "00 2 " (counter increment mode). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 147 of n rej09b0047-0060z 13.5.2 phase-delayed waveform output mode output level of the outc1j pin is inverted whenever the value of the base timer matches that of the g1poj register value ( j=0 to 7). table 13.5.2.1 lists specifications of phase-delayed waveform mode. figure 13.5.2.1 lists an example of phase-delayed waveform mode operation. table 13.5.2.1. phase-delayed waveform output mode specifications item specification output waveform ? free-running operation (the rst1, rst2, and rst4 bits of the g1bcr1 and g1bcr0 registers are set to "0" (no reset)) cycle : "h" and "l" width : ? setting bit rst1 to "1", and bits rst4 and rst2 to "0" enables the base timer to be reset when its value matches the g1po0 register. likewise, setting bit rst4 to "1",and bits rst2 and rst1 to "0" enables the base timer to be reset when its value matches the g1btrr register. cycle : "h" and "l" width : n : setting value of either g1po0 register or g1btrr register, 0001 16 to fffd 16 waveform output start condition(note 1) the ifej bit in the g1fe register should be set to "1" (channel j function enabled) waveform output stop condition the ifej bit should be set to "0" (channel j function disabled) interrupt request the g1irj bit in the interrupt request register is set to "1" when value of the base timer matches one of the g1poj registers. (see figure 13.10.) outc1j pin(note 2) pulse output selectable function ? default value set function : output level is set when waveform output starts ? inverse output function : waveform level is inverted to output waveform from the outc1j pin note 1 : the fscj bit in the g1fs register should be set to "0" (waveform generation function selected) in the channels shared by the time measurement function and waveform generation function. note 2 : the outc1 0 to outc1 7 pins. 65536 x 2 f bt1 65536 f bt1 2(n+2) f bt1 n+2 f bt1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 148 of n rej09b0047-0060z figure 13.5.2.1. phase-delayed waveform output mode ffff 16 m 65536 f bt1 65536x2 f bt1 0000 16 ffff 16 m n+2 0000 16 65536 f bt1 m f bt1 n+2 f bt1 n+2 f bt1 2(n+2) f bt1 base timer (1) free-running operation (bits rst4, rst2, and rst1 of the g1bcr0 and g1bcr1 registers are set to "0") outc1j pin g1irj bit j=0 to 7 m : setting value of the g1poj register g1irj bit : bits in the g1ir register inverse when setting to "0", write "0" by program inverse (2) base timer is reset when its value matches that of either register (a) g1po0 (enabled by setting bit rst1 to "1", and bits rst4 and rst2 to "0"), or (b) g1btrr (enabled by setting bit rst4 to "1", and bits rst2 and rst1 to "0") g1irj bit outc1j pin base timer when setting to "0", write "0" by program inverse j=1 to 7 m : setting value of the g1poj register n: setting value of either register g1po0 or g1btrr g1irj bit : bits in the g1ir register the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value). the inv bit is set to "0" (no output inverted). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value). the inv bit is set to "0" (no output inverted). bits rst4, rst2, and rst1 of the g1bcr0 and g1bcr1 registers are set to "0" (no base timer reset). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). inverse inverse m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 149 of n rej09b0047-0060z 13.5.3 set/reset waveform output (sr waveform output) mode output level of the outc1j pin is inverted when the base timer value matches that of the g1poj register value (j=0, 2, 4, 6). it is returned to default output level when the base timer value matches that of the g1pok register (k=j+1). table 13.5.3.1 lists specifications of sr waveform mode. figure 13.5.3.1 lists an example of the sr waveform mode operation. table 13.5.3.1. sr waveform output mode specifications item specification output waveform ? free-running operation (the rst1, rts2, and rst4 bits of the g1bcr1 and g1bcr0 registers are set to "0" (no reset)) cycle : inverse level(note 1) : ? setting bit rst1 to "1", and bits rst4 and rst2 to "0" enables the base timer to be reset when its value matches the g1po0 register(note 2). likewise, setting bit rst4 to "1", and bits rst2 and rst1 to "0" enables the base timer to be reset when its value matches the g1btrr register. cycle : inverse level(note 1) : m : setting value of the g1poj register (j=0, 2, 4, 6 ) n : setting value of the g1pok register (k=j+1) p : setting value of either g1po0 register or g1btrr register all m, n, p: 0001 16 to fffd 16 waveform output start condition(note 3) the ifej bit in the g1fe register should be set to "1" (channel j function enabled) waveform output stop condition the ifej bit should be set to "0" (channel j function disabled) interrupt request the g1irj bit in the interrupt request register is set to "1" when value of the base timer matches one of the g1poj registers. the g1irk bit in the interrupt request register is set to "1 " when value of the base timer matches one of the g1pok registers (see figure 13.10.) outc1j pin(note 3) pulse output selectable function ? default value set function : output level is set when waveform output starts ? inverse output function : waveform level is inverted to output waveform from the outc1j pin note 1 : the waveform generation register of odd channel should have greater value than the one of even channel has. note 2 : when the g1po0 register resets the base timer, the sr waveform generation function with channels 0 and 1 cannot be used. note 3 : t he outc1 0 , outc1 2 , outc14, outc1 6 pins. 65536 f bt1 m-n f bt1 p+2 f bt1 m-n f bt1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 150 of n rej09b0047-0060z ffff 16 m n n-m f bt1 65536 f bt1 0000 16 ffff 16 m p+2 n 0000 16 65536-n+m f bt1 n-m f bt1 p+2-n+m f bt1 p+2 f b t 1 (1) free-running operation (the rst1 bit is set to "1", and both rst4 and rst2 bits are set to "0") j=0, 2, 4, 6 k=j+1 m : setting value of the g1pok register n: setting value of the g1poj register g1irj, g1irk bits: bits in the g1ir register inverse when setting to "0", write "0" by program inverse (2) base timer is reset when its value matches that of either register (a) g1po0 (enabled by setting bit rst1 to "1", and bits rst4 and rst2 to "0"), or (b) g1btrr (enabled by setting bit rst4 to "1", and bits rst2 and rst1 to "0") j=2, 4, 6 k=j+1 m : setting value of the g1pok register n: setting value of the g1poj register p: setting value of either register g1po0 or g1btrr g1irj, g1irk bits: bits in the g1ir register return to initial output level inverse return to initial output level when setting to "0", write "0" by program when setting to "0", write "0" by program base timer outc1j pin g1irj bit g1irk bit base timer outc1j pin g1irj bit g1irk bit the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value). the inv bit is set to "0" (no output inverted). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). the above applies to the following conditions. the ivl bit in the g1pocrj register is set to "0" (output "l" as an initial value). the inv bit is set to "0" (no output inverted). bits rst4, rst2, and rst1 of the g1bcr0 and g1bcr1 registers are set to "0" (no base timer reset). the ud1 to ud0 bits are set to "00 2 " (counter increment mode). figure 13.5.3.1. set/reset waveform output mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 151 of n rej09b0047-0060z pin ife fsc mod1 mod0 port direction port data p2 7 /inpc1 7 / 0 x x x determined by pd2 7 p2 7 outc1 7 1 1 x x determined by pd2 7 , input to inpc1 7 is always active p2 7 or inpc1 7 1 0 0 0 single-phase waveform output outc1 7 1 0 0 1 determined by pd2 7 , s-r pwm mode p2 7 1 0 1 0 phase-delayed waveform output outc1 7 p2 6 /inpc1 6 / 0 x x x determined by pd2 6 p2 6 outc1 6 1 1 x x determined by pd2 6 , input to inpc1 6 is always active p2 6 or inpc1 6 1 0 0 0 single-phase waveform output outc1 6 1 0 0 1 sr waveform output outc1 6 1 0 1 0 phase-delayed waveform output outc1 6 p2 5 /inpc1 5 / 0 x x x determined by pd2 5 p2 5 outc1 5 1 1 x x determined by pd2 5 , input to inpc1 5 is always active p2 5 or inpc1 5 1 0 0 0 single-phase waveform output outc1 5 1 0 0 1 determined by pd2 5 , s-r pwm mode p2 5 1 0 1 0 phase-delayed waveform output outc1 5 p2 4 /inpc1 4 / 0 x x x determined by pd2 4 p2 4 outc1 4 1 1 x x determined by pd2 4 , input to inpc1 4 is always active p2 4 or inpc1 4 1 0 0 0 single-phase waveform output outc1 4 1 0 0 1 sr waveform output outc1 4 1 0 1 0 phase-delayed waveform output outc1 4 p2 3 /inpc1 3 / 0 x x x determined by pd2 3 p2 3 outc1 3 1 1 x x determined by pd2 3 , input to inpc1 3 is always active p2 3 or inpc1 3 1 0 0 0 single-phase waveform output outc1 3 1 0 0 1 determined by pd2 3 , s-r pwm mode p2 3 1 0 1 0 phase-delayed waveform output outc1 3 p2 2 /inpc1 2 / 0 x x x determined by pd2 2 p2 2 outc1 2 1 1 x x determined by pd2 2 , input to inpc1 2 is always active p2 2 or inpc1 2 1 0 0 0 single-phase waveform output outc1 2 1 0 0 1 sr waveform output outc1 2 1 0 1 0 phase-delayed waveform output outc1 2 p2 1 /inpc1 1 / 0 x x x determined by pd2 1 p2 1 outc1 1 1 1 x x determined by pd2 1 , input to inpc1 1 is always active p2 1 or inpc1 1 1 0 0 0 single-phase waveform output outc1 1 1 0 0 1 determined by pd2 1 , s-r pwm mode p2 1 1 0 1 0 phase-delayed waveform output outc1 1 p2 0 /inpc1 0 / 0 x x x determined by pd2 0 p2 0 outc1 0 1 1 x x determined by pd2 0 , input to inpc1 0 is always active p2 0 or inpc1 0 1 0 0 0 single-phase waveform output outc1 0 1 0 0 1 sr waveform output outc1 0 1 0 1 0 phase-delayed waveform output outc1 0 13.6 i/o port function select the m16c/28 will automatically configure the port package pins to be ic/oc inputs or outputs based on the values in the function enable (g1fe) and function select (g1fs) registers. when using pwm s-r mode, two channels are enabled and selected as output, but only one output, the output corresponding to the even numbered channel, is generated. the port package pin corresponding to the odd numbered channel is available for use as general pur- pose input / output. table 13.6.1. pin setting for time measurement and waveform generation functions ife: ifej (j=0 to 7) bits in the g1fe register. fsc: fscj (j=0 to 7) bits in the g1fs register. mod2 to mod1: bits in the g1pocrj (j=0 to 7) register. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 13. timer s (input capture / output compare) rev.0.60 2004.02.01 page 152 of n rej09b0047-0060z 13.6.1 inpc1 7 alternate input pin selection the input capture pin for ic/oc channel 7 can be assigned to one of two package pins. control bit, g1bcr0(6) ch7insel, channel 7 input select, selects ic/oc inpc1 7 to come from p2 7 / ________ outc1 7 /inpc1 7 or p1 7 /int5/inpc1 7 /idu. ________ 13.6.2 digital debounce function for pin p1 7 /int5/inpc1 7 ________ ________ the int5/inpc1 7 input from the p1 7 /int5/inpc1 7 /idu pin has an effective digital debounce function for a noise rejection. refer to " 17.6 digital debounce function " for this detail. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 153 of n rej09b0047-0060z 14. serial i/o serial i/o is configured with five channels: uart0 to uart2, si/o3 and si/o4. si/o4 is not in 64 pin version. 14.1. uarti (i=0 to 2) uarti each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 14.1.1 shows the block diagram of uarti. figures 14.1.2 and 14.1.3 shows the block diagram of the uarti transmit/receive. uarti has the following modes: ? clock synchronous serial i/o mode ? clock asynchronous serial i/o mode (uart mode). ? special mode 1 (i 2 c mode) : uart2 ? special mode 2 : uart2 ? special mode 3 (bus collision detection function, ie mode) : uart2 ? special mode 4 (sim mode) : uart2 figures 14.1.4 to 14.1.9 show the uarti-related registers. refer to tables listing each mode for register setting. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 154 of n rej09b0047-0060z clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clock source selection internal external cts/rts disabled cts/rts selected rxd 0 1 / (n 0 +1) 1/16 1/16 1/2 u0brg register clk 0 cts 0 / rts 0 f 1sio or f 2sio f 8sio f 32sio v cc rts 0 cts 0 txd 0 (uart0) clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 crs=1 crs=0 crd=0 crd=1 rcsp=0 rcsp=1 v cc crd=0 crd=1 uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clk polarity reversing circuit cts/rts disabled cts 0 from uart1 uart reception clock synchronous type rxd 1 txd 1 (uart1) 1 / (n 1 +1) 1/16 1/16 1/2 u1brg register clk 1 f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 v cc crd=0 crd=1 clkmd0=0 clkmd1=0 crs=1 crs=0 rcsp=0 rcsp=1 clkmd0=1 clkmd1=1 clock source selection internal external uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) clk polarity reversing circuit rts1 cts1 clock output pin select cts/rts disabled cts/rts disabled cts/rts selected cts 0 from uart0 cts 1 / rts 1 / cts 0 / clks 1 i = 0 to 2 n i : values set to the uibrg register smd2 to smd0, ckdir: uimr register s bits clk1 to clk0, ckpol, crd, crs: uic0 register s bits clkmd0, clkmd1, rcsp: ucon register s bits rxd 2 clk 2 cts 2 / rts 2 rts 2 cts 2 txd 2 (uart2) 1 / (n 2 +1) 1/16 1/16 1/2 u2brg register f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 crs=1 crs=0 v cc crd=0 crd=1 reception control circuit transmission control circuit uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock rxd polarity reversing circuit internal external clock source selection txd polarity reversing circuit transmit/ receive unit clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selected main clock or ring oscillator clock 1/2 1/8 1/4 f 1sio f 2sio f 8sio f 32sio f 1sio or f 2sio pclk1=1 pclk1=0 figure 14.1.1. block diagram of uarti (i = 0 to 2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 155 of n rej09b0047-0060z sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp stps=0 p a r enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 data bus high-order bits stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 smd2 to smd0, stps, prye, iopol, ckdir : uimr register s bit figure 14.1.2. block diagram of uarti (i = 0, 1) transmit/receive unit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 156 of n rej09b0047-0060z sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uarti transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uarti receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit stps=0 stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 iopol=0 iopol=1 iopol =0 iopol =1 u2ere =0 u2ere =1 smd2 to smd0, stps, prye, iopol, ckdir : u2mr register s bit u2ere : u2c1 register s bit figure 14.1.3. block diagram of uart2 transmit/receive unit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 157 of n rej09b0047-0060z (b15) b7 b0 (b8) b7 b0 uarti transmit buffer register (i=0 to 2)(note) function transmit data nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminate. symbol address after reset u0tb 03a3 16 -03a2 16 indeterminate u1tb 03ab 16 -03aa 16 indeterminate u2tb 037b 16 -037a 16 indeterminate rw note: use mov instruction to write to this register. wo b7 uarti baud rate generation register (i=0 to 2)(notes 1, 2) b0 symbol address after reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, uibrg divides the count source by n + 1 00 16 to ff 16 setting range note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: use mov instruction to write to this register. rw wo note 1: when the uimr register s smd2 to smd0 bits = 000 2 (serial i/o disabled) or the uic1 register s re bit = 0 (reception disabled), all of the sum, per, fer and oer bits are set to 0 (no error). the sum bit is set to 0 (no error) when all of the per, fer and oer bits = 0 (no error). also, the per and fer bits are set to 0 by reading the lower byte of the uirb register. note 2: the abt bit is set to 0 by writing 0 in a program. (writing 1 has no effect.) (b15) symbol address after reset u0rb 03a7 16 -03a6 16 indeterminate u1rb 03af 16 -03ae 16 indeterminate u2rb 037f 16 -037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register (i=0 to 2) function bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found receive data (d 7 to d 0 ) abt arbitration lost detecting flag (note 2) 0 : not detected 1 : detected rw rw ro ro ro ro ro (b7-b0) (b10-b9) receive data (d 8 ) ro (b8) nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . figure 14.1.4. serial i/o-related registers (1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 158 of n rej09b0047-0060z uarti transmit/receive mode register (i=0, 1) symbol address after reset u0mr, u1mr 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw ckdir smd1 smd0 serial i/o mode select bit (note 2) smd2 internal/external clock select bit stps pry prye (b7) parity enable bit 0 : internal clock 1 : external clock (note 1) stop bit length select bit odd/even parity select bit reserve bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long must not be set except above b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity write to "0" function note 1: set the corresponding port direction bit for each clki pin to 0 (input mode). note 2: to receive data, set the corresponding port direction bit for each rxdi pin to 0 (input mode). rw rw rw rw rw rw rw rw uart2 transmit/receive mode register symbol address after reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw ckdir smd1 smd0 serial i/o mode select bit (note 2) smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note 1) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 0 1 0 : i 2 c mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long must not be set except above b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity 0 : no reverse 1 : reverse function note 1: set the corresponding port direction bit for each clk2 pin to 0 (input mode). note 2: to receive data, set the corresponding port direction bit for each rxd2 pin to 0 (input mode). note 3: set the corresponding port direction bit for scl and sda pins to 0 (input mode). rw rw rw rw rw rw rw rw (note 3) figure 14.1.5. serial i/o-related registers (2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 159 of n rej09b0047-0060z figure 14.1.6. serial i/o-related registers (3) uarti transmit/receive control register 0 (i=0 to 2) symbol address after reset u0c0 to u2c0 03a4 16 , 03ac 16 , 037c 16 00001000 2 b7 b6 b5 b4 b3 b2 b1 b0 function txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1sio or f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : must not be set b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 , p6 4 and p7 3 can be used as i/o ports) 0 : txdi/sdai and scli pins are cmos output 1 : txdi/sdai and scli pins are n-channel open-drain output uform transfer format select bit (note 2) effective when crd = 0 0 : cts function is selected (note 1) 1 : rts function is selected bit name bit symbol note 1: set the corresponding port direction bit for each ctsi pin to 0 (input mode). note 2: effective for clock synchronous serial i/o mode, uart mode transfer data 8 bits long and special mode 2. note 3: cts 1 /rts 1 can be used when the ucon register s clkmd1 bit = 0 (only clk 1 output) and the ucon register s rcsp bit = 0 (cts 0 /rts 0 not separated). rw rw rw rw rw rw rw rw ro (note 3) note: when using multiple transfer clock output pins, make sure the following conditions are met: u1mr register s ckdir bit = 0 (internal clock) uart transmit/receive control register 2 symbol address after reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit uart1 clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : clk output is only clk1 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. when write, set 0 . when read, its content is indeterminate. u0irs u1irs u0rrm u1rrm uart1 clk/clks select bit 1 (note) effective when clkmd1 = 1 0 : clock output from clk1 1 : clock output from clks1 rcsp separate uart0 cts/rts bit 0 : cts/rts shared pin 1 : cts/rts separated (cts 0 supplied from the p6 4 pin) rw rw rw rw rw rw rw (b7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 160 of n rej09b0047-0060z uarti transmit/receive control register 1 (i=0, 1) symbol address after reset u0c1, u1c1 03a5 16 ,03ad 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in uitb register 1 : no data present in uitb register 0 : reception disabled 1 : reception enabled 0 : no data present in uirb register 1 : data present in uirb register nothing is assigned. when write, set 0 . when read, these contents are 0 . uart2 transmit/receive control register 1 symbol address after reset u2c1 037d 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : reception disabled 1 : reception enabled u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled data logic select bit 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit 0 : output disabled 1 : output enabled rw rw ro ro rw rw rw rw rw rw rw ro ro (b7-b4) 0 : data present in u2tb register 1 : no data present in u2tb register 0 : no data present in u2rb register 1 : data present in u2rb register figure 14.1.7. serial i/o-related registers (4) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 161 of n rej09b0047-0060z uart2 special mode register symbol address after reset u2smr 0377 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function abscs acse sss i 2 c mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected (busy) bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : other than i 2 c mode 1 : i 2 c mode 0 : update per bit 1 : update per byte iicm abc bbs 0 : not synchronized to r x di 1 : synchronized to r x di (note 2) set to 0 transmit start condition select bit 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision note 1: the bbs bit is set to 0 by writing 0 in a program. (writing 1 has no effect.). note 2: when a transfer begins, the sss bit is set to 0 (not synchronized to r x di). (note1) nothing is assigned. when write, set 0 . when read, its content is indeterminate. rw rw rw rw rw rw rw rw (b7) 0 (b3) reserved bit figure 14.1.8. serial i/o-related registers (5) uart2 special mode register 2 symbol address after reset u2smr2 0376 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function stac swc2 sdhi i c mode select bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart initialization bit clock-synchronous bit refer to table 141.3.4. i 2 c mode functions 0 : disabled 1 : enabled iicm2 csc swc als 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: transfer clock 1: l output 2 nothing is assigned. when write, set 0 . when read, its content is indeterminate. rw rw rw rw rw rw rw (b7) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 162 of n rej09b0047-0060z uart2 special mode register 3 symbol address after reset u2smr3 0375 16 000x0x0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function dl2 sda digital delay setup bit (note 1, note 2) dl0 dl1 0 0 0 : without delay 0 0 1 : 1 to 2 cycle(s) of uibrg count source 0 1 0 : 2 to 3 cycles of uibrg count source 0 1 1 : 3 to 4 cycles of uibrg count source 1 0 0 : 4 to 5 cycles of uibrg count source 1 0 1 : 5 to 6 cycles of uibrg count source 1 1 0 : 6 to 7 cycles of uibrg count source 1 1 1 : 7 to 8 cycles of uibrg count source nothing is assigned. when write, set 0 . when read, its content is indeterminate. b7 b6 b5 0 : without clock delay 1 : with clock delay clock phase set bit 0 : clki is cmos output 1 : clki is n-channel open drain output clock output select bit ckph nodc note 1 : the dl2 to dl0 bits are used to generate a delay in sdai output by digital means during i 2 c mode. in other than i 2 c mode, set these bits to 000 2 (no delay). note 2 : the amount of delay varies with the load on scl2 and sda2 pins. also, when using an external clock, the amount of delay increases by about 100 ns. rw rw rw rw rw rw (b0) nothing is assigned. when write, set 0 . when read, its content is indeterminate. nothing is assigned. when write, set 0 . when read, its content is indeterminate. (b2) (b4) figure 14.1.9. serial i/o-related registers (6) uart2 special mode register 4 symbol address after reset u2smr4 0374 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function ackc sclhi swc9 start condition generate bit (note) stop condition generate bit (note) 0 : clear 1 : start scl,sda output select bit ack data bit restart condition generate bit (note) 0 : clear 1 : start 0 : clear 1 : start stareq rstareq stpreq ackd 0 : start and stop conditions not output 1 : start and stop conditions output scl output stop enable bit ack data output enable bit 0 : disabled 1 : enabled 0 : ack 1 : nack 0 : serial i/o data output 1 : ack data output note: set to 0 when each condition is generated. stspsel 0 : scl l hold disabled 1 : scl l hold enabled scl wait bit 3 rw rw rw rw rw rw rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 163 of n rej09b0047-0060z 14.1.1. clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 14.1.1.1 lists the specifications of the clock synchronous serial i/o mode. table 14.1.1.2 lists the registers used in clock synchronous serial i/o mode and the register values set. item specification transfer data format ? transfer data length: 8 bits transfer clock ? uimr(i=0 to 2) register s ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : input from clki pin transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin = l reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of uic1 register= 1 (reception enabled) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register= 0 (data present in the uitb register) ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 3) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit =1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 7th bit of the next data select function ? clk polarity selection transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? continuous receive mode selection reception is enabled immediately by reading the uirb register ? switching serial data logic (uart2) this function reverses the logic value of the transmit/receive data ? transfer clock output from multiple pins selection (uart1) the output pin can be selected in a program from two uart1 transfer clock pins that have been set _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins note 1: when an external clock is selected, the conditions must be met while if the uic0 register s ckpol bit = 0 interrupt request generation timing (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the uic0 register s ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change. note 3: the u0irs and u1irs bits respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4. table 14.1.1.1. clock synchronous serial i/o mode specifications m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 164 of n rej09b0047-0060z table 14.1.1. 2. registers to be used and settings in clock synchronous serial i/o mode register bit function uitb (note3) 0 to 7 set transmission data uirb (note3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a transfer rate uimr (note3) smd2 to smd0 set to 001 2 ckdir select the internal clock or external clock iopol(i=2)(note 4) set to 0 uic0 clk1 to clk0 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmission/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 1) select the source of uart2 transmit interrupt u2rrm (note 1) set this bit to 1 to use uart2 continuous receive mode u2lch(note 3) set this bit to 1 to use uart2 inverted data logic u2ere(note 3) set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 2 set to 0 nodc select clock output mode 4 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set this bit to 1 to use continuous receive mode clkmd0 select the transfer clock output pin when clkmd1 = 1 clkmd1 set this bit to 1 to output uart1 transfer clock from two pins rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 note 1: set the u0c1 and u1c1 register bit 4 and bit 5 to 0 . the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. note 2: not all register bits are described above. set those bits to 0 when writing to the registers in clock synchronous serial i/o mode. note 3: set the u0c1 and u1c1 register bit 6 and bit 7 to "0". note 4: set the u0mr and u1mr register bit 7 to "0". i=0 to 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 165 of n rej09b0047-0060z table 14.1.1.3 lists the functions of the input/output pins during clock synchronous serial i/o mode. table 14.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese- lected. table 14.1.1.4 lists the p6 4 pin functions during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 14.1.1.3. pin functions ( when not select multiple transfer clock output pin function ) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) uimr register s ckdir bit=0 uimr register s ckdir bit=1 pd6 register s pd6_1 bit=0, pd6_5 bit=0, pd7 register s pd7_2 bit=0 pd6 register s pd6_2 bit=0, pd6_6 bit=0, pd7 register s pd7_1 bit=0 (can be used as an input/output port when performing transmission only) uic0 register s crd bit=0 uic0 register s crs bit=0 pd6 register s pd6_0 bit=0, pd6_4 bit=0, pd7 register s pd7_3 bit=0 uic0 register s crd bit=0 uic0 register s crs bit=1 uic0 register s crd bit=1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 clkmd0 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0 00 0 rts 1 1 00 cts 0 (note1) 0 clks 1 0 0 00 1 0 1(note 2) 1 note 1: in addition to this, set the u0c0 register s crd bit to 0 (cts 0 /rts 0 enabled) and the u0c0 register s crs bit to 1 (rts 0 selected). note 2: when the clkmd1 bit = 1 and the clkmd0 bit = 0, the following logic levels are output: ? high if the u1c0 register s clkpol bit = 0 ? low if the u1c0 register s clkpol bit = 1 table 14.1.1.4. p6 4 pin functions m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 166 of n rej09b0047-0060z d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because the te bit = 0 write data to the uitb register tc = t clk = 2(n + 1) / fj fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) n: value set to uibrg register i: 0 to 2 transfer clock uic1 register te bit uic1 register ti bit clki txdi h l 0 1 0 1 0 1 ctsi 0 1 stopped pulsing because ctsi = h 1 / f ext write dummy data to uitb register uic1 register te bit uic1 register ti bit clki rxdi uic1 register ri bit rtsi h l 0 1 0 1 0 1 uic1 register re bit 0 1 receive data is taken in transferred from uitb register to uarti transmit register read out from uirb register transferred from uarti receive register to uirb register siric register ir bit 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 transferred from uitb register to uarti transmit register make sure the following conditions are met when input to the clki pin before receiving data is high: ? uic0 register te bit = 1 (transmit enabled) ? uic0 register re bit = 1 (receive enabled) ? write dummy data to the uitb register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register ckdir bit = 0 (internal clock) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 0 (cts selected) ? uic0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the tran sfer clock) ? uiirs bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1ir s bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program cleared to 0 when interrupt request is accepted, or cleared to 0 in a program the above timing diagram applies to the case where the register bits are set as follows: ? uimr register ckdir bit = 1 (external clock) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 1 (rts selected) ? uic0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) uic0 register txept bit sitic register ir bit even if the reception is completed, the rts does not change. the rts becomes l when the ri bit changes to 0 from 1 . (1) example of transmit timing (2) example of receive timing figure 14.1.1.1. typical transmit/receive timings in clock synchronous serial i/o mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 167 of n rej09b0047-0060z 14.1.1.1 clk polarity select function use the uic0 register (i = 0 to 2) s ckpol bit to select the transfer clock polarity. figure 14.1.1.1.1 shows the polarity of the transfer clock. figure 14.1.1.1.1. polarity of transfer clock (2) when the uic0 register s ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i (1) when the uic0 register s ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i note 1: this applies to the case where the uic0 register s uform bit = 0 (lsb first) and uic1 register's uilch bit = 0 (no reverse). note 2: when not transferring, the clki pin outputs a high signal. note 3: when not transferring, the clki pin outputs a low signal. i = 0 to 2 (note 2) (note 3) 14.1.1.2 lsb first/msb first select function use the uic0 register (i = 0 to 2) s uform bit to select the transfer format. figure 14.1.1.2.1 shows the transfer format. figure 14.1.1.2.1 transfer format (1) when uic0 register's uform bit = 0 (lsb first) d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i (2) when uic0 register's uform bit = 1 (msb first) d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i note: this applies to the case where the uic0 register s ckpol bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uic1 register s uilch bit = 0 (no reverse). i = 0 to 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 168 of n rej09b0047-0060z 14.1.1.3 continuous receive mode when the uirrm bit (i = 0 to 2) = 1 (continuous receive mode), the uic1 register s ti bit is set to 0 (data present in the uitb register) by reading the uirb register. in this case, i.e., uirrm bit = 1, do not write dummy data to the uitb register in a program. the u0rrm and u1rrm bits are the ucon register bit 2 and bit 3, respectively, and the u2rrm bit is the u2c1 register bit 5. 14.1.1.4 serial data logic switch function (uart2) when the u2c1 register s u2lch bit = 1 (reverse), the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 14.1.1.4.1 shows serial data logic. figure 14.1.1.4.1. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) h l h l txd 2 (reverse) d0 d1 d2 d3 d4 d5 d6 d7 h l (1) when the u2c1 register's u2lch bit = 0 (no reverse) transfer clock h l (2) when the u2c1 register's u2lch bit = 1 (reverse) note: this applies to the case where the u2c0 register s ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uform bit = 0 (lsb first). 14.1.1.5 transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 14.1.1.5.1.) the multiple pins function is valid only when the internal clock is selected for uart1. microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies to the case where the u1mrregister's ckdir bit = 0 (internal clock) and the ucon register's clkmd1 bit = 1 ( transfer clock output from multiple pins). transfer enabled when the ucon register's clkmd0 bit = 0 transfer enabled when the ucon register's clkmd0 bit = 1 figure 14.1.1.5.1 transfer clock output from multiple pins m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 169 of n rej09b0047-0060z _______ _______ 14.1.1.6 cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? u0c0 register's crd bit = 0 (enables uart0 cts/rts) _______ ? u0c0 register's crs bit = 1 (outputs uart0 rts) _______ _______ ? u1c0 register's crd bit = 0 (enables uart1 cts/rts) _______ ? u1c0 register's crs bit = 0 (inputs uart1 cts) _______ ? ucon register's rcsp bit = 1 (inputs cts 0 from the p6 4 pin) ? ucon register's clkmd1 bit = 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. figure 14.1.1.6.1. cts/rts separate function usage microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic clk 0 (p6 1 ) clk m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 170 of n rej09b0047-0060z item specification transfer data format ? character bit (transfer data): selectable from 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable from odd, even, or none ? stop bit: selectable from 1 or 2 bits transfer clock ? uimr(i=0 to 2) register s ckdir bit = 0 (internal clock) : fj/ 16(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : f ext /16(n+1) f ext : input from clki pin. n :setting value of uibrg register 00 16 to ff 16 transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin = l reception start condition ? before reception can start, the following requirements must be met _ the re bit of uic1 register= 1 (reception enabled) _ start bit detection ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 2) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit =1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 1) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the bit one before the last stop bit of the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1 s in parity and character bits does not match the number of 1 s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? serial data logic switch (uart2) this function reverses the logic of the transmit/receive data. the start and stop bits are not reversed. ? t x d, r x d i/o polarity switch (uart2) this function reverses the polarities of hte t x d pin output and r x d pin input. the logic levels of all i/o data is reversed. _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins note 1: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change. note 2: the u0irs and u1irs bits respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4. 14.1.2. clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 14.1.2.1 lists the specifications of the uart mode. interrupt request generation timing table 14.1.2.1. uart mode specifications m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 171 of n rej09b0047-0060z table 14.1.2.2. registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (note 1) uirb 0 to 8 reception data can be read (note 1) oer,fer,per,sum error flag uibrg 0 to 7 set a transfer rate uimr smd2 to smd0 set these bits to 100 2 when transfer data is 7 bits long set these bits to 101 2 when transfer data is 8 bits long set these bits to 110 2 when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even iopol(i=2)(note 4) select the txd/rxd input/output polarity uic0 clk0, clk1 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 2) select the source of uart2 transmit interrupt u2rrm (note 2) set to 0 uilch (note 3) set this bit to 1 to use uart2 inverted data logic uiere (note 3) set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1 set to 0 rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 note 1: the bits used for transmit/receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. note 2: set the u0c1 and u1c1 registers bit 4 to bit 5 to 0 . the u0irs, u1irs, u0rrm and u1rrm bits are included in the ucon register. note 3: set the u0c1 and u1c1 registers bit 6 to bit 7 to 0 . note 4: set the u0mr and u1mr registers bit 7 to 0 . i=0 to 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 172 of n rej09b0047-0060z table 14.1.2.3 lists the functions of the input/output pins during uart mode. table 14.1.2.4 lists the p6 4 pin functions during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 14.1.2.3. i/o pin functions in uart mode pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input input/output port transfer clock input input/output port (outputs "h" when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) uimr register s ckdir bit=0 uimr register s ckdir bit=1 pd6 register s pd6_1 bit=0, pd6_5 bit=0, pd7 register s pd7_2 bit=0 pd6 register s pd6_2 bit=0, pd6_6 bit=0, pd7 register s pd7_1 bit=0 (can be used as an input/output port when performing transmission only) uic0 register s crd bit=0 uic0 register s crs bit=0 pd6 register s pd6_0 bit=0, pd6_4 bit=0, pd7 register s pd7_3 bit=0 uic0 register s crd bit=0 uic0 register s crs bit=1 uic0 register s crd bit=1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) table 14.1.2.4. p6 4 pin functions in uart mode pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0000 rts 1 10 0 cts 0 (note) 0 0 0 00 1 0 note: in addition to this, set the u0c0 register s crd bit to 0 (cts 0 /rts 0 enabled) and the u0c0 register s crs bit to 1 (rts 0 selected). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 173 of n rej09b0047-0060z figure 14.1.2.1. typical transmit timing in uart mode (uart0, uart1) start bit parity bit txdi ctsi 1 0 1 l h 0 1 tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 0 1 txdi 0 1 0 1 0 1 transfer clock tc 0 1 tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stop bit start bit the transfer clock stops momentarily as ctsi is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately ctsi changes to l . d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp stop bit stop bit 0 sp stopped pulsing because the te bit = 0 write data to the uitb register uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 1 (parity enabled) ? uimr register stps bit = 0 (1 stop bit) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 0 (cts selected) ? uiirs bit = 1 (an interrupt request occurs when transmit completed): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program write data to the uitb register transferred from uitb register to uarti transmit register tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 0 (parity disabled) ? uimr register stps bit = 1 (2 stop bits) ? uic0 register crd bit = 1 (cts/rts disabled) ? uiirs bit = 0 (an interrupt request occurs when transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 174 of n rej09b0047-0060z ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 14.1.2.2. receive operation d 0 start bit sampled l uibrg count source rxdi transfer clock rtsi stop bit 1 0 0 1 h l 0 1 reception triggered when transfer clock is generated by falling edge of start bit uic1 register re bit uic1 register ri bit siric register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program receive data taken in d 7 d 1 transferred from uarti receive register to uirb register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 0 (parity disabled) ? uimr register stps bit = 0 (1 stop bit) ? uic0 register crd bit = 0 (ctsi/rtsi enabled), crs bit = 1 (rtsi selected) i = 0 to 2 14.1.2.1. lsb first/msb first select function as shown in figure 14.1.2.1.1, use the uic0 register s uform bit to select the transfer format. this function is valid when transfer data is 8 bits long. figure 14.1.2.1.1. transfer format (1) when uic0 register's uform bit = 0 (lsb first) (2) when uic0 register's uform bit = 1 (msb first) note: this applies to the case where the uic0 register s ckpol bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the uic1 register s uilch bit = 0 (no reverse), uimr register's stps bit = 0 (1 stop bit) and uimr register's prye bit = 1 (parity enabled). d 1 d 2 d 3 d 4 d 5 d 6 sp d0 d 1 d 2 d 3 d 4 d 5 d 6 sp d 0 t x d i r x d i clk i d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i st st d 7 p d 7 p sp sp st st p p d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 st : start bit p : parity bit sp : stop bit i = 0 to 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 175 of n rej09b0047-0060z 14.1.2.3. txd and rxd i/o polarity inverse function (uart2) this function inverses the polarities of the t x d2 pin output and r x d2 pin input. the logic levels of all input/output data (including the start, stop and parity bits) are inversed. figure 14.1.2.3.1 shows the t x d pin output and r x d pin input polarity inverse. figure 14.1.2.3.1. t x d and r x d i/o polarity inverse 14.1.2.2. serial data logic switching function (uart2) the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 14.1.2.2.1 shows serial data logic. figure 14.1.2.2.1. serial data logic switching transfer clock h l d0 d1 d2 d3 d4 d5 d6 d7 p sp st txd 2 (no reverse) h l txd 2 (reverse) sp st d3 d4 d5 d6 d7 p d0 d1 d2 h l (1) when the u2c1 register's u2lch bit = 0 (no reverse) (2) when the u2c1 register's u2lch bit = 1 (reverse) transfer clock h l note: this applies to the case where the u2c0 register s ckpol bit = 0 (transmit data output at the falling edge of the transfer clock), the u2c0 register's uform bit = 0 (lsb first), the u2mr register's stps bit = 0 (1 stop bit) and u2mr register's prye bit = 1 (parity enabled). st : start bit p : parity bit sp : stop bit (1) when the u2mr register's iopol bit = 0 (no reverse) (2) when the u2mr register's iopol bit = 1 (reverse) note: this applies to the case where the u2c0 register's uform bit = 0 (lsb first), the u2mr register's stps bit = 0 (1 stop bit) and the u2mr register's prye bit = 1 (parity enabled). st : start bit p : parity bit sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 d0 d1 d2 d3 d4 d5 d6 d7 p sp st h sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) rxd 2 (no reverse) transfer clock txd 2 (reverse) rxd 2 (reverse) l h l h l h l h l h l m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1 uarti (i=0 to 2) rev.0.60 2004.02.01 page 176 of n rej09b0047-0060z _______ _______ 14.1.2.4. cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? u0c0 register's crd bit = 0 (enables uart0 cts/rts) _______ ? u0c0 register's crs bit = 1 (outputs uart0 rts) _______ _______ ? u1c0 register's crd bit = 0 (enables uart1 cts/rts) _______ ? u1c0 register's crs bit = 0 (inputs uart1 cts) _______ ? ucon register's rcsp bit = 1 (inputs cts 0 from the p6 4 pin) ? ucon register's clkmd1 bit = 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. _______ _______ figure 1.19.6. cts/rts separate function microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 177 of n rej09b0047-0060z 14.1.3 special mode 1 (i 2 c bus mode)(uart2) ii 2 c mode is provided for use as a simplified i 2 c interface compatible mode. table 14.1.3.1 lists the specifications of the i 2 c mode. table 14.1.3.2 and 14.1.3.3 list the registers used in the i 2 c mode and the register values set. table 14.1.3.4 lists the i 2 c mode fuctions. figure 14.1.3.1 shows the block diagram for i 2 c mode. figure 14.1.3.2 shows scl 2 timing. as shown in table 14.1.3.2, the microcomputer is placed in i 2 c mode by setting the smd2 to smd0 bits to 010 2 and the iicm bit to 1 . because sda 2 transmit output has a delay circuit attached, sda output does not change state until scl 2 goes low and remains stably low. table 14.1.3.1. i 2 c bus mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? during master u2mr register s ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? during slave ckdir bit = 1 (external clock) : input from scl pin transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register = 0 (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of u2c1 register= 1 (reception enabled) _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register= 0 (data present in the uitb register) when start or stop condition is detected, acknowledge undetected, and acknowledge detected error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 8th bit of the next data select function ? arbitration lost timing at which the u2rb register s abt bit is updated can be selected ? sda digital delay no digital delay or a delay of 2 to 8 u2brg count source clock cycles selectable ? clock phase setting with or without clock delay selectable note 1: when an external clock is selected, the conditions must be met while the external clock is in the high state. note 2: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit of s2ric register does not change . interrupt request generation timing m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 178 of n rej09b0047-0060z clk control falling edge detection external clock internal clock start/stop condition detection interrupt request start condition detection stop condition detection reception register bus busy transmission register arbitration noise filter sda2 scl2 uart2 d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmit, nack interrupt request uart2 receive, ack interrupt request, dma1 request iicm=1 and iicm2=0 s r q als r s swc iicm=1 and iicm2=0 iicm2=1 iicm2=1 swc2 sdhi dma0, dma1 request (uart1: dma0 only) noise filter iicm : uismr register bit iicm2, swc, als, swc2, sdhi : uismr2 register bit stspsel, ackd, ackc : uismr4 register bit iicm=0 iicm=1 dma0 (uart0, uart2) stspsel=0 stspsel=1 stspsel=1 stspsel=0 sda stsp scl stsp ackc=1 ackc=0 q port register (note) i/o port 9th bit falling edge 9th bit ackd bit delay circuit this diagram applies to the case where the uimr register's smd2 to smd0 bits = 010 2 and the uismr register's iicm bit = 1. note: if the iicm bit = 1, the pin can be read even when the pd7_1 bit = 1 (output mode). start and stop condition generation block figure 14.1.3.1. i 2 c bus mode block diagram m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 179 of n rej09b0047-0060z table 14.1.3.2. registers to be used and settings in i 2 c bus mode (1) (continued) register bit function master slave u2tb 0 to 7 set transmission data set transmission data (note 1) u2rb 0 to 7 reception data can be read reception data can be read (note 1) 8 ack or nack is set in this bit ack or nack is set in this bit abt arbitration lost detection flag invalid oer overrun error flag overrun error flag u2brg 0 to 7 set a transfer rate invalid u2mr smd2 to smd0 set to 010 2 set to 010 2 (note 1) ckdir set to 0 set to 1 iopol set to 0 set to 0 u2c0 clk1, clk0 select the count source for the u2brg invalid register crs invalid because crd = 1 invalid because crd = 1 txept transmit buffer empty flag transmit buffer empty flag crd set to 1 set to 1 nch set to 1 set to 1 ckpol set to 0 set to 0 uform set to 1 set to 1 u2c1 te set this bit to 1 to enable transmission set this bit to 1 to enable transmission ti transmit buffer empty flag transmit buffer empty flag re set this bit to 1 to enable reception set this bit to 1 to enable reception ri reception complete flag reception complete flag u2irs invalid invalid u2rrm, set to 0 set to 0 u2lch, u2ere u2smr iicm set to 1 set to 1 abc select the timing at which arbitration-lost invalid is detected bbs bus busy flag bus busy flag 3 to 7 set to 0 set to 0 u2smr2 iicm2 refer to table "i 2 c mode functions refer to table " i 2 c mode functions csc set this bit to 1 to enable clock set to 0 synchronization swc set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output fixed to l at the falling edge of the 9th fixed to l at the falling edge of the 9 th bit of clock bit of clock als set this bit to 1 to have sda 2 output set to 0 stopped when arbitration-lost is detected stac set to 0 set this bit to 1 to initialize uart2 at start condition detection swc2 set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output forcibly pulled low forcibly pulled low sdhi set this bit to 1 to disable sda 2 output set this bit to 1 to disable sda 2 output 7 set to 0 set to 0 u2smr3 0, 2, 4 and nodc set to 0 set to 0 ckph refer to table "i 2 c mode functions refer to table "i 2 c mode functions dl2 to dl0 set the amount of sda 2 digital delay set the amount of sda 2 digital delay note 1: not all register bits are described above. set those bits to 0 when writing to the registers in i 2 c bus mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 180 of n rej09b0047-0060z u2smr4 stareq set this bit to 1 to generate start set to 0 condition rstareq set this bit to 1 to generate restart set to 0 condition stpreq set this bit to 1 to generate stop set to 0 condition stspsel set this bit to 1 to output each condition set to 0 ackd select ack or nack select ack or nack ackc set this bit to 1 to output ack data set this bit to 1 to output ack data sclhi set this bit to 1 to have scl2 output set to 0 stopped when stop condition is detected swc9 set to 0 set this bit to 1 to set the scl 2 to l hold at the falling edge of the 9th bit of clock register bit function master slave table 14.1.3.3. registers to be used and settings in i 2 c bus mode (2) (continued) note 1: not all register bits are described above. set those bits to 0 when writing to the registers in i 2 c bus mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 181 of n rej09b0047-0060z function i 2 c mode (smd2 to smd0 = 010 2 , iicm = 1) clock synchronous serial i/o mode (smd2 to smd0 = 001 2 , iicm = 0) factor of interrupt number 15 (note 1) (refer to fig. 14.1.3.2.) no acknowledgment detection (nack) rising edge of scl 2 9th bit factor of interrupt number 16 (note 1) (refer to fig. 14.1.3.2.) start condition detection or stop condition detection (refer to fig 14.1.3.4.) uart2 transmission output delay functions of p7 0 pin noise filter width read rxd2 and scl 2 pin levels factor of interrupt number 10 (note 1) (refer to fig. 14.1.3.2.) acknowledgment detection (ack) rising edge of scl 2 9th bit initial value of txd2 and sda 2 outputs uart2 transmission transmission started or completed (selected by u2irs) uart2 reception when 8th bit received ckpol = 0 (rising edge) ckpol = 1 (falling edge) not delayed txd2 output rxd2 input clk2 input or output selected 15ns possible when the corresponding port direction bit = 0 ckpol = 0 (h) ckpol = 1 (l) delayed sda 2 input/output scl 2 input/output (cannot be used in i 2 c mode) initial and end values of scl 2 h 200ns always possible no matter how the corresponding port direction bit is set the value set in the port register before setting i 2 c mode (note 2) timing for transferring data from the uart reception shift register to the u2rb register iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/ receive interrupt) ckph = 1 (clock delay) ckph = 1 (clock delay) uart2 transmission rising edge of scl 2 9th bit uart2 transmission falling edge of scl 2 next to the 9th bit uart2 transmission falling edge of scl 2 9th bit ckpol = 0 (rising edge) ckpol = 1 (falling edge) rising edge of scl 2 9th bit falling edge of scl 2 9th bit falling and rising edges of scl 2 9th bit . . dma1 factor (refer to fig. 14.1.3.2.) uart2 reception acknowledgment detection (ack) uart2 reception falling edge of scl 2 9th bi t store received data 1st to 8th bits are stored in u2rb register bit 0 to bit 7 1st to 8th bits are stored in u2rb register bit 7 to bit 0 1st to 7th bits are stored in u2rb register bit 6 to bit 0, with 8th bit stored in u2rb register bit 8 l read u2rb register bit 6 to bit 0 as bit 7 to bit 1, and bit 8 as bit 0 (note 4) read received data u2rb register status is read directly as is ckph = 0 (no clock delay) ckph = 0 (no clock delay) h l 1st to 8th bits are stored in u2rb register bit 7 to bit 0 (note 3) functions of p7 1 pin functions of p7 2 pin note 1: if the source or cause of any interrupt is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). (refer to notes on interrupts in precautions.) if one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. therefore, always be sure to clear the ir bit to 0 (interrupt not requested) after changing those bits. smd2 smd0 bits in the u2mr register, iicm bit in the u2smr register, iicm2 bit in the u2smr2 register, ckph bit in the u2smr3 register note 2: set the initial value of sda 2 output while the u2mr register s smd2 to smd0 bits = 000 2 (serial i/o disabled). note 3: second data transfer to u2rb register (rising edge of scl 2 9th bit) note 4. first data transfer to u2rb register (falling edge of scl 2 9th bit) table 14.1.3.4. i 2 c bus mode functions m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 182 of n rej09b0047-0060z figure 14.1.3.2. transfer to u2rb register and interrupt timing (3) iicm2= 1 (uart transmit/receive interrupt), ckph= 0 (1) iicm2= 0 (ack and nack interrupts), ckph= 0 (no clock delay) this diagram applies to the case where the following condition is met. ? u2mr re g ister ckdir bit = 0 (slave selected) ack interrupt (dma1 request), nack interrupt transfer to u2rb register receive interrupt (dma1 request) transmit interrupt transfer to u2rb register (4) iicm2= 1, ckph= 1 d 6 d 5 d 4 d 3 d 2 d 1 d7 sda2 scl2 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d7 sda2 scl2 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack, nack) d7 sda2 scl2 d 0 d 8 (ack, nack) d 8 (ack, nack) d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack, nack) d7 sda2 scl2 d 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 u2rb register b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 b15 ??? b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 b15 ??? b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit (2) iicm2= 0, ckph= 1 (clock delay) ack interrupt (dma1 request), nack interrupt transfer to u2rb register u2rb register transmit interrupt transfer to u2rb register receive interrupt (dma1 request) transfer to u2rb register u2rb register u2rb register u2rb register m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 183 of n rej09b0047-0060z 14.1.3.1 detection of start and stop condition whether a start or a stop condition has been detected is determined. a start condition-detected interrupt request is generated when the sda 2 pin changes state from high to low while the scl 2 pin is in the high state. a stop condition-detected interrupt request is generated when the sda 2 pin changes state from low to high while the scl 2 pin is in the high state. because the start and stop condition-detected interrupts share the interrupt control register and vec- tor, check the u2smr register s bbs bit to determine which interrupt source is requesting the inter- rupt. note: when the pclkr register's pclk1 bit = "1", this is the cycle number of f 1sio ; when pclk1 bit = "0", this is the cycle number of f 2sio . 3 to 6 cycles < duration for setting-up (note) 3 to 6 cycles < duration for holding (note) duration for setting up duration for holding scl2 sda2 (start condition) sda2 (stop condition) figure 14.1.3.1.1. detection of start and stop condition 14.1.3.2 output of start and stop condition a start condition is generated by setting the u2smr4 register s stareq bit to 1 (start). a restart condition is generated by setting the u2smr4 register s rstareq bit to 1 (start). a stop condition is generated by setting the u2smr4 register s stpreq bit to 1 (start). the output procedure is described below. (1) set the stareq bit, rstareq bit or stpreq bit to 1 (start). (2) set the stspsel bit in the u2smr4 register to 1 (output). make sure that no interrupts or dma transfers will occur between (1) and (2). the function of the stspsel bit is shown in table 14.1.3.2.1 and figure 14.1.3.2.1. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 184 of n rej09b0047-0060z table 14.1.3.2.1. stspsel bit functions figure 14.1.3.2.1. stspsel bit functions function output of scl2 and sda2 pins start/stop condition interrupt request generation timing stspsel = 0 output of transfer clock and data output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) start/stop condition detection stspsel = 1 output of a start/stop condition according to the stareq, rstareq and stpreq bit finish generating start/stop condi- tion start condition detection interrupt stop condition detection interrupt (1) when slave ckdir="1" (external clock) start condition detection interrupt stop condition detection interrupt (2) when master ckdir="0" (internal clock), ckph="1" (clock delayed) sda2 scl2 set stareq= "1" (start) set stpreq= "1" (start) stpsel bit (= "0") sda2 scl2 stpsel bit set to 1 in a program set to 0 in a program set to 1 in a program set to 0 in a program 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit 14.1.3.3 arbitration unmatching of the transmit data and sda 2 pin input data is checked synchronously with the rising edge of scl 2 . use the u2smr register s abc bit to select the timing at which the u2rb register s abt bit is updated. if the abc bit = 0 (updated bitwise), the abt bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. in cases when the abc bit is set to 1 , if unmatching is detected even once during check, the abt bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. if the abt bit needs to be updated bytewise, clear the abt bit to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte. setting the u2smr2 register s als bit to 1 (sda output stop enabled) causes arbitration-lost to occur, in which case the sda 2 pin is placed in the high-impedance state at the same time the abt bit is set to 1 (unmatching detected). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 185 of n rej09b0047-0060z 14.1.3.4 transfer clock data is transmitted/received using a transfer clock like the one shown in figure 14.1.3.2.1. the u2smr2 register s csc bit is used to synchronize the internally generated clock (internal scl2) and an external clock supplied to the scl 2 pin. in cases when the csc bit is set to 1 (clock synchro- nization enabled), if a falling edge on the scl 2 pin is detected while the internal scl 2 is high, the internal scl 2 goes low, at which time the u2brg register value is reloaded with and starts counting in the low-level interval. if the internal scl 2 changes state from low to high while the scl 2 pin is low, counting stops, and when the scl 2 pin goes high, counting restarts. in this way, the uart2 transfer clock is comprised of the logical product of the internal scl 2 and scl 2 pin signal. the transfer clock works from a half period before the falling edge of the internal scl 2 1st bit to the rising edge of the 9 th bit. to use this function, select an internal clock for the transfer clock. the u2smr2 register s swc bit allows to select whether the scl 2 pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. if the u2smr4 register s sclhi bit is set to 1 (enabled), scl 2 output is turned off (placed in the high- impedance state) when a stop condition is detected. setting the u2smr2 register s swc2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal from the scl 2 pin even while sending or receiving data. clearing the swc2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the scl 2 pin, instead of outputting a low-level signal. if the u2smr4 register s swc9 bit is set to 1 (scl hold low enabled) when the u2smr3 register s ckph bit = 1, the scl 2 pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. setting the swc9 bit = 0 (scl hold low disabled) frees the scl 2 pin from low-level output. 14.1.3.5 sda output the data written to the u2tb register bit 7 to bit 0 (d 7 to d 0 ) is sequentially output beginning with d 7 . the ninth bit (d 8 ) is ack or nack. the initial value of sda 2 transmit output can only be set when iicm = 1 (i 2 c bus mode) and the u2mr register s smd2 to smd0 bits = 000 2 (serial i/o disabled). the u2smr3 register s dl2 to dl0 bits allow to add no delays or a delay of 2 to 8 u2brg count source clock cycles to sda 2 output. setting the u2smr2 register s sdhi bit = 1 (sda output disabled) forcibly places the sda 2 pin in the high-impedance state. do not write to the sdhi bit synchronously with the rising edge of the uart2 transfer clock. this is because the abt bit may inadvertently be set to 1 (detected). 14.1.3.6 sda input when the iicm2 bit = 0, the 1st to 8th bits (d 7 to d 0 ) of received data are stored in the u2rb register bit 7 to bit 0. the 9th bit (d 8 ) is ack or nack. when the iicm2 bit = 1, the 1st to 7th bits (d 7 to d 1 ) of received data are stored in the u2rb register bit 6 to bit 0 and the 8th bit (d 0 ) is stored in the u2rb register bit 8. even when the iicm2 bit = 1, providing the ckph bit = 1, the same data as when the iicm2 bit = 0 can be read out by reading the u2rb register after the rising edge of the corresponding clock pulse of 9th bit. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.3 special mode 1 (i 2 c bus mode) (uart2) rev.0.60 2004.02.01 page 186 of n rej09b0047-0060z 14.1.3.7 ack and nack if the stspsel bit in the u2smr4 register is set to 0 (start and stop conditions not generated) and the ackc bit in the u2smr4 register is set to 1 (ack data output), the value of the ackd bit in the u2smr4 register is output from the sda 2 pin. if the iicm2 bit = 0, a nack interrupt request is generated if the sda 2 pin remains high at the rising edge of the 9th bit of transmit clock pulse. an ack interrupt request is generated if the sda 2 pin is low at the rising edge of the 9th bit of transmit clock pulse. if ack2 is selected for the cause of dma1 request, a dma transfer can be activated by detection of an acknowledge. 14.1.3.8 initialization of transmission/reception if a start condition is detected while the stac bit = 1 (uart2 initialization enabled), the serial i/o operates as described below. - the transmit shift register is initialized, and the content of the u2tb register is transferred to the transmit shift register. in this way, the serial i/o starts sending data synchronously with the next clock pulse applied. however, the uart2 output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. - the receive shift register is initialized, and the serial i/o starts receiving data synchronously with the next clock pulse applied. - the swc bit is set to 1 (scl wait output enabled). consequently, the scl 2 pin is pulled low at the falling edge of the ninth clock pulse. note that when uart2 transmission/reception is started using this function, the ti does not change state. note also that when using this function, the selected transfer clock should be an external clock. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.4 special mode 2 (uart2) rev.0.60 2004.02.01 page 187 of n rej09b0047-0060z 14.1.4 special mode 2 (uart2) multiple slaves can be serially communicated from one master. transfer clock polarity and phase are selectable. table 14.1.4.1 lists the specifications of special mode 2. table 14.1.4.2 lists the registers used in special mode 2 and the register values set. figure 14.1.4.1 shows communication control ex- ample for special mode 2. table 14.1.4.1. special mode 2 specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? master mode u2mr register s ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? slave mode ckdir bit = 1 (external clock selected) : input from clk2 pin transmit/receive control controlled by input/output ports transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register = 0 (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of u2c1 register= 1 (reception enabled) _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register= 0 (data present in the u2tb register) ? for transmission, one of the following conditions can be selected _ the u2irs bit of u2c1 register = 0 (transmit buffer empty): when transferring data from the u2tb register to the uart2 transmit register (at start of transmission) _ the u2irs bit =1 (transfer completed): when the serial i/o finished sending data from the uart2 transmit register ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 7th bit of the next data select function ? clock phase setting selectable from four combinations of transfer clock polarities and phases note 1: when an external clock is selected, the conditions must be met while if the u2c0 register s ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the u2c0 register s ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit of s2ric register does not change. interrupt request generation timing m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.4 special mode 2 (uart2) rev.0.60 2004.02.01 page 188 of n rej09b0047-0060z p1 3 p1 2 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) microcomputer (master) microcomputer (slave) microcomputer (slave) figure 14.1.4.1. serial bus communication control example (uart2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.4 special mode 2 (uart2) rev.0.60 2004.02.01 page 189 of n rej09b0047-0060z table 14.1.4.2. registers to be used and settings in special mode 2 register bit function u2tb (note) 0 to 7 set transmission data u2rb (note) 0 to 7 reception data can be read oer overrun error flag u2brg 0 to 7 set a transfer rate u2mr (note) smd2 to smd0 set to 001 2 ckdir set this bit to 0 for master mode or 1 for slave mode iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch select txd2 pin output format ckpol clock phases can be set in combination with the u2smr3 register's ckph bit uform select the lsb first or msb first u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select uart2 transmit interrupt cause u2rrm, set to 0 u2lch, u2ere u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 ckph clock phases can be set in combination with the u2c0 register's ckpol bit nodc set to 0 0, 2, 4 to 7 set to 0 u2smr4 0 to 7 set to 0 note : not all register bits are described above. set those bits to 0 when writing to the registers in special mode 2. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.4 special mode 2 (uart2) rev.0.60 2004.02.01 page 190 of n rej09b0047-0060z 14.1.4.1 clock phase setting function one of four combinations of transfer clock phases and polarities can be selected using the u2smr3 register s ckph bit and the u2c0 register s ckpol bit. make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate. 14.1.4.1.1 master (internal clock) figure 14.1.4.1.1.1 shows the transmission and reception timing in master (internal clock). 14.1.4.1.2 slave (external clock) figure 14.1.4.1.2.1 shows the transmission and reception timing (ckph=0) in slave (external clock) while figure 14.1.4.1.2.2 shows the transmission and reception timing (ckph=1) in slave (external clock). data output timing data input timing d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 clock output (ckpol=0, ckph=0) "h" "l" clock output (ckpol=1, ckph=0) "h" "l" clock output (ckpol=0, ckph=1) "h" "l" clock output (ckpol=1, ckph=1) "h" "l" "h" "l" figure 14.1.4.1.1.1. transmission and reception timing in master mode (internal clock) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.4 special mode 2 (uart2) rev.0.60 2004.02.01 page 191 of n rej09b0047-0060z figure 14.1.4.1.2.1. transmission and reception timing (ckph=0) in slave mode (external clock) figure 14.1.4.1.2.2. transmission and reception timing (ckph=1) in slave mode (external clock) slave control input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 indeterminate clock input (ckpol=0, ckph=1) clock input (ckpol=1, ckph=1) data output timing data input timing "h" "l" "h " "l" "h " "l " "h " "l" d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 . slave control input m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.5 special mode 3 (ie bus mode) (uart2) rev.0.60 2004.02.01 page 192 of n rej09b0047-0060z 14.1.5 special mode 3 (ie bus mode)(uart2) in this mode, one bit of ie bus is approximated with one byte of uart mode waveform. table 14.1.5.1 lists the registers used in ie bus mode and the register values set. figure 14.1.5.1 shows the functions of bus collision detect function related bits. if the txd2 pin output level and rxd2 pin input level do not match, a uart2 bus collision detect interrupt request is generated. use the ifsr2a register s ifsr26 and ifsr27 bits to enable the uart0/uart1 bus collision detect function. table 14.1.5.1. registers to be used and settings in ie bus mode register bit function u2tb 0 to 8 set transmission data u2rb (note) 0 to 8 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 110 2 ckdir select the internal clock or external clock stps set to 0 pry invalid because prye=0 prye set to 0 iopol select the txd/rxd input/output polarity u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch select txd2 pin output mode ckpol set to 0 uform set to 0 u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select the source of uart2 transmit interrupt u2rrm, set to 0 u2lch, u2ere u2smr 0 to 3, 7 set to 0 abscs select the sampling timing at which to detect a bus collision acse set this bit to 1 to use the auto clear function of transmit enable bit sss select the transmit start condition u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note : not all register bits are described above. set those bits to 0 when writing to the registers in ie bus mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.5 special mode 3 (ie bus mode) (uart2) rev.0.60 2004.02.01 page 193 of n rej09b0047-0060z (2) u2smr register acse bit (auto clear of transmit enable bit) (1) u2smr register abscs bit (bus collision detect sampling clock select) if abscs=0, bus collision is determined at the rising edge of the transfer clock transfer clock timer aj (3) u2smr register sss bit (transmit start condition select) transmission enable condition is met if sss bit = 1, the serial i/o starts sending data at the rising edge (note 1) of rxd2 txd2 clk2 txd2 rxd2 txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp input to taj in if abscs=1, bus collision is determined when timer aj (one-shot timer mode) underflows. txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp timer aj: timer a0 when uart2 transfer clock u2bcnic register ir bit (note) u2c1 register te bit note: bcnic register when uart2. if acse bit = 1 (automatically clear when bus collision occurs), the te bit is cleared to 0 (transmission disabled) when the u2bcnic register s ir bit = 1 (unmatching detected). if sss bit = 0, the serial i/o starts sending data one transfer clock cycle after the transmission enable condition is met. transfer clock (note 2) note 1: the falling edge of rxd2 when iopol=0; the rising edge of rxd2 when iopol = 1. note 2: the transmit condition must be met before the falling edge (note 1) of rxd. this diagram applies to the case where iopol=1 (reversed). figure 14.1.5.1. bus collision detect function-related bits m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.6 special mode 4 (sim mode) (uart2) rev.0.60 2004.02.01 page 194 of n rej09b0047-0060z item specification transfer data format ? direct format ? inverse format transfer clock ? u2mr register s ckdir bit = 0 (internal clock) : fi/ 16(n+1) fi = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : f ext /16(n+1) f ext : input from clk 2 pin. n: setting value of u2brg register 00 16 to ff 16 transmission start condition ? before transmission can start, the following requirements must be met _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register = 0 (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met _ the re bit of u2c1 register= 1 (reception enabled) _ start bit detection ? for transmission when the serial i/o finished sending data from the u2tb transfer register (u2irs bit =1) (note 2) ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (note 1) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the bit one before the last stop bit of the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error during reception, if a parity error is detected, parity error signal is output from the txd 2 pin. during transmission, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered note 1: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit of s2ric register does not change. note 2: a transmit interrupt request is generated by setting the u2c1 register u2irs bit to 1 (transmis- sion complete) and u2ere bit to 1 (error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to 0 (no interrupt request) after setting these bits. 14.1.6 special mode 4 (sim mode) (uart2) based on uart mode, this is an sim interface compatible mode. direct and inverse formats can be implemented, and this mode allows output of a low from the txd2 pin when a parity error is detected. tables 14.1.6.1 lists the specifications of sim mode. table 14.1.6.2 lists the registers used in the sim mode and the register values set. table 14.1.6.1. sim mode specifications interrupt request generation timing m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.6 special mode 4 (sim mode) (uart2) rev.0.60 2004.02.01 page 195 of n rej09b0047-0060z table 14.1.6.2. registers to be used and settings in sim mode register bit function u2tb (note) 0 to 7 set transmission data u2rb (note) 0 to 7 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 101 2 ckdir select the internal clock or external clock stps set to 0 pry set this bit to 1 for direct format or 0 for inverse format prye set to 1 iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch set to 0 ckpol set to 0 uform set this bit to 0 for direct format or 1 for inverse format u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs set to 1 u2rrm set to 0 u2lch set this bit to 0 for direct format or 1 for inverse format u2ere set to 1 u2smr (note) 0 to 3 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note: not all register bits are described above. set those bits to 0 when writing to the registers in sim mode. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.6 special mode 4 (sim mode) (uart2) rev.0.60 2004.02.01 page 196 of n rej09b0047-0060z figure 14.1.6.1. transmit and receive timing in sim mode transfer clock an l level is output from txd 2 due to the occurrence of a parity error read the u2rb register cleared to 0 when interrupt request is accepted, or cleared to 0 in a program u2c1 register te bit d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p 0 1 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p txd 2 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 pin level u2c1 register ti bit parity error signal sent back from receiver (note) u2c0 register txept bit s2tic register ir bit start bit parity bit stop bit write data to u2tb register transferred from u2tb register to uart2 transmit register an l level returns due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. the ir bit is set to 1 at the falling edge of transfer clock note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received. note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the txd 2 output and the parity error signal sent back from receiver. tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg the above timing diagram applies to the case where data is transferred in the direct format. ? u2mr register stps bit = 0 (1 stop bit) ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) ? u2c1 register u2irsch bit = 1 (transmit is completed) start bit parity bit stop bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program read the u2rb register (1) transmission transfer clock u2c1 register re bit rxd 2 pin level transmitter's transmit waveform (note) u2c0 register ri bit s2ric register ir bit (1) reception the above timing diagram applies to the case where data is transferred in the direct format. ? u2mr register stps bit = 0 (1 stop bit) ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) ? u2c1 register u2irsch bit = 1 (transmit is completed) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.6 special mode 4 (sim mode) (uart2) rev.0.60 2004.02.01 page 197 of n rej09b0047-0060z figure 14.1.6.2 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 14.1.6.2. sim interface connection microcomputer sim card txd 2 rxd 2 14.1.6.1 parity error signal output the parity error signal is enabled by setting the u2c1 register s u2ere bit to 1 . ? when receiving the parity error signal is output when a parity error is detected while receiving data. this is achieved by pulling the txd2 output low with the timing shown in figure 14.1.6.1.1. if the r2rb register is read while outputting a parity error signal, the per bit is cleared to 0 and at the same time the txd2 output is returned high. ? when transmitting a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. therefore, whether a parity signal has been returned can be determined by reading the port that shares the rxd2 pin in a transmission-finished interrupt service routine. figure 14.1.6.1.1. parity error signal output timing st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st (note) transfer clock rxd 2 txd 2 u2c1 register ri bit h l h l h l 1 0 this timing diagram applies to the case where the direct format is implemented. note: the output of microcomputer is in the high-impedance state (pulled up externally). m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.1.6 special mode 4 (sim mode) (uart2) rev.0.60 2004.02.01 page 198 of n rej09b0047-0060z 14.1.6.2 format ? direct format set the u2mr register's pry bit to 1 , u2c0 register's uform bit to 0 and u2c1 register's u2lch bit to 0 . ? inverse format set the pry bit to 0 , uform bit to 1 and u2lch bit to 1 . figure 14.1.6.2.1 shows the sim interface format. figure 14.1.6.2.1. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 txd 2 d7 d6 d5 d4 d3 d2 d1 d0 p transfer clcck (1) direct format h l h l (2) inverse format p : odd parity h l h l m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.2 si/o 3 and si/o 4 rev.0.60 2004.02.01 page 199 of n rej09b0047-0060z 14.2 si/o3 and si/o4 si/o3 and si/o4 are exclusive clock-synchronous serial i/os. figure 14.2.1 shows the block diagram of si/o3 and si/o4, and figure 14.2.2 shows the si/o3 and si/o4- related registers. table 14.2.1 shows the specifications of si/o3 and si/o4. figure 14.2.1. si/o3 and si/o4 block diagram data bus si/oi interrupt request note: i = 3, 4. n = a value set in the sibrg register. sitrr register si/o counter i 8 smi5 lsb msb smi2 smi3 smi3 smi6 smi1 to smi0 clk i s outi s ini sibrg register smi6 1/(n+1) 1/2 1/2 main clock, pll clock, or ring oscillator clock f 1sio 1/2 1/8 1/4 f 8sio f 32sio f 2sio pclk1=0 pclk1=1 smi4 00 2 01 2 10 2 clock source select synchronous circuit clk polarity reversing circuit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.2 si/o 3 and si/o 4 rev.0.60 2004.02.01 page 200 of n rej09b0047-0060z si/oi bit rate generator (i = 3, 4) (notes 1, 2) b7 b0 symbol address after reset s3brg 0363 16 ?? 16 s4brg 0367 16 ?? 16 description assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 setting range rw si/oi transmit/receive register (i = 3, 4) (note 1, 2) b7 b0 symbol address after reset s3trr 0360 16 ?? 16 s4trr 0364 16 ?? 16 description transmission/reception starts by writing transmit data to this register. after transmission/reception finishes, reception data can be read by reading this register. note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: to receive data, set the corresponding port direction bit for s in i to 0 (input mode). s i/oi control register (i = 3, 4) (note 1) symbol address after reset s3c 0362 16 0100000 2 s4c 0366 16 0100000 2 b7 b6 b5 b4 b3 b2 b1 b0 description smi5 smi1 smi0 smi3 smi6 smi7 internal synchronous clock select bit transfer direction select bit s i/oi port select bit s out i initial value set bit 0 0 : selecting f 1sio or f 2sio 0 1 : selecting f 8sio 1 0 : selecting f 32sio 1 1 : must not be set. b1 b0 0 : external clock 1 : internal clock effective when smi3 = 0 0 : l output 1 : h output 0 : input/output port 1 : s out i output, clki function bit name bit symbol synchronous clock select bit 0 : lsb first 1 : msb first smi2 s out i output disable bit 0 : s out i output 1 : s out i output disable (high impedance) note 1: make sure register s4c is written to by the next instruction after setting the prcr register's prc2 bit to 1" (write enable). note 2: set the smi3 bit to 1 (s out i output, clki function). note 3: set the smi3 bit to 1 and the corresponding port direction bit to 0 (input mode). note 4: effective when smi3 bit = 1. clk polarity select bit smi4 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge rw rw rw rw rw rw rw rw rw wo rw rw (note 4) (note 2) (note 3) note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: use mov instruction to write to this register. figure 14.2.2. s3c and s4c registers, s3brg and s4brg registers, and s3trr and s4trr registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.2 si/o 3 and si/o 4 rev.0.60 2004.02.01 page 201 of n rej09b0047-0060z item specification transfer data format ? transfer data length: 8 bits transfer clock ? sic (i=3, 4) register s smi6 bit = 1 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n=setting value of sibrg register 00 16 to ff 16 . ? smi6 bit = 0 (external clock) : input from clki pin (note 1) transmission/reception ? before transmission/reception can start, the following requirements must be met start condition write transmit data to the sitrr register (notes 2, 3) ? when sic register's smi4 bit = 0 the rising edge of the last transfer clock pulse (note 4) ? when smi4 = 1 the falling edge of the last transfer clock pulse (note 4) clki pin fucntion i/o port, transfer clock input, transfer clock output s out i pin function i/o port, transmit data output, high-impedance sini pin function i/o port, receive data input select function ? lsb first or msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? function for setting an s out i initial value set function when the sic register's smi6 bit = 0 (external clock), the s out i pin output level while not tranmitting can be selected. ? clk polarity selection whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. note 1: to set the sic register s smi6 bit to 0 (external clock), follow the procedure described below. ? if the sic register s smi4 bit = 0, write transmit data to the sitrr register while input on the clki pin is high. the same applies when rewriting the sic register s smi7 bit. ? if the smi4 bit = 1, write transmit data to the sitrr register while input on the clki pin is low. the same applies when rewriting the smi7 bit. ? because shift operation continues as long as the transfer clock is supplied to the si/oi circuit, stop the transfer clock after supplying eight pulses. if the smi6 bit = 1 (internal clock), the transfer clock automatically stops. note 2: unlike uart0 to uart2, si/oi (i = 3 to 4) is not separated between the transfer register and buffer. there- fore, do not write the next transmit data to the sitrr register during transmission. note 3: when the sic register s smi6 bit = 1 (internal clock), s outi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. however, if transmit data is written to the sitrr register during this period, s outi immediately goes to a high-impedance state, with the data hold time thereby reduced. note 4: when the sic register s smi6 bit = 1 (internal clock), the transfer clock stops in the high state if the smi4 bit = 0, or stops in the low state if the smi4 bit = 1. table 14.2.1. si/o3 and si/o4 specifications interrupt request generation timing m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.2 si/o 3 and si/o 4 rev.0.60 2004.02.01 page 202 of n rej09b0047-0060z 14.2.1 si/oi operation timing figure 14.2.1.1 shows the si/oi operation timing d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 i= 3, 4 1.5 cycle (max) si/oi internal clock clki output signal written to the sitrr register s out i output s in i input siic register ir bit (note 2) note 1: this diagram applies to the case where the sic register bits are set as follows: smi2=0 (s out i output), smi3=1 (s out i output, clki function), smi4=0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), smi5=0 (lsb first) and smi6=1 (internal clock) note 2: when the smi6 bit = 1 (internal clock), the s out i pin is placed in the high-impedance state after the transfer finishes. note 3: if the smi6 bit=0 (internal clock), the serial i/o starts sending or receiving data a maximum of 1.5 transfer clock cycl es after writing to the sitrr register. "h" "l" "h" "l" "h" "l" "h" "l" "h" "l" "1" "0" (note 3) figure 14.2.1.1. si/oi operation timing 14.2.2 clk polarity selection the sic register's smi4 bit allows selection of the polarity of the transfer clock. figure 14.2.2.1 shows the polarity of the transfer clock. figure 14.2.2.1. polarity of transfer clock (2) when sic register's smi4 bit = 1 (note 3) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 s ini s outi clk i (1) when sic register's smi4 bit = 0 note 1: this diagram applies to the case where the sic register bits are set as follows: smi5=0 (lsb first) and smi6=1 (internal clock) note 2: when the smi6 bit=1 (internal clock), a high level is output from the clki pin if not transferring data. note 3: when the smi6 bit=1 (internal clock), a low level is output from the clki pin if not transferring data. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 s ini s outi clk i (note 2) i=3 and 4 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 14.2 si/o 3 and si/o 4 rev.0.60 2004.02.01 page 203 of n rej09b0047-0060z 14.2.3 functions for setting an s out i initial value if the sic register s smi6 bit = 0 (external clock), the s outi pin output can be fixed high or low when not transferring. figure 14.2.3.1 shows the timing chart for setting an s outi initial value and how to set it. figure 14.2.3.1. s out i s initial value setting setting of the initial value of s out i output and starting of transmission/ reception set the smi3 bit to 0 (s out i pin functions as an i/o port) write to the sitrr register serial transmit/reception starts set the smi7 bit to 1 (s out i initial value = h ) set the smi3 bit to 1 (s out i pin functions as s out i output) h level is output from the s out i pin signal written to sitrr register s out i (internal) smi7 bit s out i pin output smi3 bit setting the s out i initial value to h port selection switching (i/o port s out i) d0 (i = 3, 4) initial value = h (note 3) port output d0 (example) when h selected for s out i initial value (note 1) note 1: this diagram applies to the case where the sic register bits are set as follows: smi2=0 (s out i output), smi5=0 (lsb first) and smi6=0 (external clock) note 2: s out i can only be initialized when input on the clki pin is in the high state if the sic register s smi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the smi4 bit = 1 (transmit data output at the rising edge of the transfer clock). note 3: if the smi6 bit = 1 (internal clock) or if the smi2 bit = 1 (s out output disabled), this output goes to the high-impedance state. (note 2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 204 of n rej09b0047-0060z 15. a-d converter the microcomputer contains one a-d converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. the analog inputs share the pins with p10 0 to p10 7 (an 0 to ____________ an 7 ), p0 0 to p0 7 (an 00 to an 07 ), and p1 0 to p1 3 , p9 3 , p9 5 to p9 7 (an 20 to an 27 ). similarly, ad trg input shares the pin with p1 5 . therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (= input mode). note that p1 0 to p1 3 , p9 3 , p9 5 to p9 7 (an 20 to an 27 ) are available only in the 80-pin package. when not using the a-d converter, set the vcut bit to 0 (= v ref unconnected), so that no current will flow from the v ref pin into the resistor ladder, helping to reduce the power consumption of the chip. the a-d conversion result is stored in the adi register bits for an i , an 0i , and an 2i pins (i = 0 to 7). table 15.1 shows the a-d converter performance. figure 15.1 shows the a-d converter block diagram and figures 15.2 to 15.4 show the a-d converter associated with registers. item performance a-d conversion method successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) f ad /divided-by-2 or f ad /divided-by-3 or f ad /divided-by-4 or f ad /divided-by-6 or f ad /divided-by-12 or f ad resolution 8-bit or 10-bit (selectable) integral nonlinearity error when av cc = v ref = 5v ? with 8-bit resolution: 2lsb ? with 10-bit resolution - an 0 to an 7 input : 3lsb - an 00 to an 07 input and an 20 to an 27 input : 7lsb when av cc = v ref = 3.3v ? with 8-bit resolution: 2lsb ? with 10-bit resolution - an 0 to an 7 input : 5lsb - an 00 to an 07 input and an 20 to an 27 input : 7lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1 analog input pins 8 pins (an 0 to an 7 ) + 8 pins (an 00 to an 07 ) + 8 pins (an 20 to an 27 ) (80pin-ver.) 8 pins (an 0 to an 7 ) + 4 pins (an 00 to an 03 ) + 1 pin (an 24 ) (64pin-ver.) conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles table 15.1 a-d converter performance note 1: not dependent on use of sample and hold function. note 2: set the fad frequency to 10 mhz or less. without sample-and-hold function, set the fad frequency to 250kh z or more. with the sample and hold function, set the fad frequency to 1mh z or more. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 205 of n rej09b0047-0060z figure 15.1 a-d converter block diagram =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 00 an 01 an 02 an 03 an 04 an 05 an 06 an 07 v ref v in ch2 to ch0 decoder for channel selection a-d register 0(16) data bus low-order v ref av ss vcut=0 vcut=1 data bus high-order port p10 group port p1/port p9 group adgsel1 to adgsel0=10 2 adgsel1 to adgsel0=00 2 an 20 an 21 an 22 an 23 an 24 an 25 an 26 an 27 adgsel1 to adgsel0=11 2 f ad cks0=1 cks0=0 cks1=1 cks1=0 1/3 cks2=0 cks2=1 1/2 1/2 ? ad a-d conversion rate selection (03c1 16 to 03c0 16 ) (03c3 16 to 03c2 16 ) (03c5 16 to 03c4 16 ) (03c7 16 to 03c6 16 ) (03c9 16 to 03c8 16 ) (03cb 16 to 03ca 16 ) (03cd 16 to 03cc 16 ) (03cf 16 to 03ce 16 ) resistor ladder successive conversion register adcon0 register (address 03d6 16 ) adcon1 register (address 03d7 16 ) comparator 0 addresses decoder for a-d register a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) adcon2 register (address 03d4 16 ) port p0 group =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 ch2 to ch0 ch2 to ch0 (note) sse = 1 ch2 to ch0=001 2 comparator 1 adgsel1 to adgsel0=00 2 adgsel1 to adgsel0=10 2 adgsel1 to adgsel0=11 2 v in 1 note: port p1/port p9 group is available for only 80-pin package. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 206 of n rej09b0047-0060z figure 15.2 adcon0 to adcon2 registers a-d control register 0 (note) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode or delayed trigger mode 0,1 0 1 : repeat mode 1 0 : single sweep mode or simultaneous sample sweep mode 1 1 : repeat sweep mode 0 or repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : hardware trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 see table 15.2 a-d conversion frequency select cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 2) a-d operation mode select bit 1 0 : other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : v ref not connected 1 : v ref connected b4 b3 note: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. frequency select bit 1 cks1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw function varies with each operation mode function varies with each operation mode see table 15.2 a-d conversion frequency select note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before startinga-d conversion. nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) rw trg1 trigger select bit see table 15.2 a-d conversion frequency select function varies with each operation mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 207 of n rej09b0047-0060z a-d trigger control register (note 1, 2) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d operation mode select bit 2 0 : other than simultaneous sample sweep mode or delayed trigger mode 0,1 1 : simultaneous sample sweep mode or delayed trigger mode 0,1 bit symbol bit name function rw sse a-d operation mode select bit 3 hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) 0 : other than delayed trigger mode 0,1 1 : delayed trigger mode 0,1 note 1: if the adtrgcon register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: set 00 16 in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. an1 trigger select bit an0 trigger select bit function varies with each operation mode function varies with each operation mode figure 15.3 adtrgcon register note: set the ? ad frequency to 10 mhz or less. the selected ? ad frequency is determined by a combination of the cks0 bit in the adcon0 register, cks1 bit in the adcon1 register and the cks2 bit in the adcon2 register. cks2 cks1 cks0 ? ad 000 001 010 100 101 110 111 divided-by-4 of f ad divided-by-2 of f ad f ad divided-by-12 of f ad 011 divided-by-6 of f ad divided-by-3 of f ad table 15.2 a-d conversion frequency select m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 208 of n rej09b0047-0060z figure 15.4 adstat0 register and ad0 to ad7 registers a-d register i (i=0 to 7) symbol address after reset ad0 03c1 16 to 03c0 16 indeterminate ad1 03c3 16 to 03c2 16 indeterminate ad2 03c5 16 to 03c4 16 indeterminate ad3 03c7 16 to 03c6 16 indeterminate ad4 03c9 16 to 03c8 16 indeterminate ad5 03cb 16 to 03ca 16 indeterminate ad6 03cd 16 to 03cc 16 indeterminate ad7 03cf 16 to 03ce 16 indeterminate eight low-order bits of a-d conversion result function (b15) b7 b7 b0 b0 (b8) when the bits bit in the adcon1 register is 1 (10-bit mode) nothing is assigned. when write, set to 0 . when read, its content is 0 . when read, its content is indeterminate rw ro ro two high-order bits of a-d conversion result when the bits bit in the adcon1 register is 0 (8-bit mode) a-d conversion result a-d conversion status register 0 (note 1) symbol address after reset adstat0 03d3 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 an1 trigger status flag 0 : without an1 trigger during an0 conversion 1 : with an1 trigger during an0 conversion bit symbol bit name function rw aderr0 conversion termination flag an0 conversion status flag adstt0 aderr1 adtcsf rw ro rw ro ro nothing is assigned. when write, set to 0 . when read, its content is 0 . (b2) adstrt0 an0 conversion completion status flag 0 : conversion not terminated 1 : conversion terminated by timer b0 underflow delayed trigger sweep status flag 0 : sweep not in progress 1 : sweep in progress 0 : an0 conversion not in progress 1 : an0 conversion in progress adstt1 rw 0 : an0 conversion not completed 1 : an0 conversion completed adstrt1 rw an1 conversion status flag 0 : an1 conversion not in progress 1 : an1 conversion in progress an1 conversion completion status flag 0 : an1 conversion not completed 1 : an1 conversion completed note 1: adstat0 register is valid only when the dte bit in the adtrgcon register is set to 1 . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 209 of n rej09b0047-0060z figure 15.5 tb2sc register pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw tb1en timer b1 operation mode select bit 0 : other than a-d trigger mode 1 : a-d trigger mode rw note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1" (a-d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to " 17.6 digital debounce function " for the sd input (note 2) (note 3, 4, 7) (note 5) (note 5) (note 6) (b6-b5) reserved bits must set to "0" m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 210 of n rej09b0047-0060z 15.1 operation modes 15.1.1 one-shot mode in one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. table 15.1.1.1 shows the one-shot mode specifications. figure 15.1.1.1 shows the operation example in one- shot mode. figure 15.1.1.2 shows the adcon0 to adcon2 registers in one-shot mode. table 15.1.1.1 one-shot mode specifications item specification function the ch2 to ch0 bits in the adcon0 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to a selected pin is once converted to a digital code a-d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a-d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) a-d conversion stop ? a-d conversion completed (if a software trigger is selected, the adst bit is condition set to 0 (a-d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a-d conversion completed analog input pin select one pin from an 0 to an 7 , an 00 to an 07 , an 20 to an 27 readout of a-d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin figure 15.1.1.1 operation example in one-shot mode ? example when selecting an 2 to an analog input pin (ch2 to ch0="010 2 ") an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d conversion started a-d interrupt request generated a-d pin input voltage sampling a-d pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 211 of n rej09b0047-0060z a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (note 2, 3) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 (note 3) md0 md1 trigger select bit trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 2) a-d operation mode select bit 1 1 : v ref connected 0 0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see table 15.2 a-d conversion frequency select refer to table 15.2 a-d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) rw trg1 trigger select bit 1 b2 b1 b0 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel 0 bits in the adcon2 register to select the desired pin. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using an another instruction. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in one-shot mode nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in one-shot mode see table 15.2 a-d conversion frequency select 0 figure 15.1.1.2 adcon0 to adcon2 registers in one-shot mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 212 of n rej09b0047-0060z 15.1.2 repeat mode in repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. table 15.1.2.1 shows the repeat mode specifications. figure 15.1.2.1 shows the operation example in repeat mode. figure 15.1.2.2 shows the adcon0 to adcon2 registers in repeat mode. item specification function the ch2 to ch0 bits in the adcon0 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to a selected pin is repeatedly converted to a digital code a-d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a-d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) a-d conversion stop condition set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated analog input pin select one pin from an 0 to an 7 , an 00 to an 07 and an 20 to an 27 readout of a-d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin table 15.1.2.1 repeat mode specifications figure 15.1.2.1 operation example in repeat mode ? example when selecting an 2 to an analog input pin (ch2 to ch0="010 2 ") a-d conversion started an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d pin input voltage sampling a-d pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 213 of n rej09b0047-0060z a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (note 2, 3) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 (note 3) md0 md1 trigger select bit trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 2) a-d operation mode select bit 1 1 : v ref connected 0 0 0 1 : repeat mode b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select refer to table 15.2 a-d conversion frequency select (b7-b6) 1 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) see table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 b2 b1 b0 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using an another instruction. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in repeat mode nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in repeat mode 0 figure 15.1.2.2 adcon0 to adcon2 registers in repeat mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 214 of n rej09b0047-0060z 15.1.3 single sweep mode in single sweep mode, analog voltage is applied to the selected pins are converted one-by-one to a digital code. table 15.1.3.1 shows the single sweep mode specifications. figure 15.1.3.1 shows the operation example in single sweep mode. figure 15.1.3.2 shows the adcon0 to adcon2 registers in single sweep mode. item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code a-d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a-d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) a-d conversion stop condition ? a-d conversion completed(when selecting a software trigger, the adst bit is set to 0 (a-d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a-d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note 1 ) readout of a-d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin table 15.1.3.1 single sweep mode specifications note 1. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.1.3.1 operation example in single sweep mode ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") a-d conversion started a-d interrupt request generated an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d pin input voltage sampling a-d pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 215 of n rej09b0047-0060z a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 1 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select refer to table 15.2 a-d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) nothing is assigned. when write, set to 0 . when read, its content is 0 . 0 : without sample and hold 1 : with sample and hold set to "0" in single sweep mode invalid in single sweep mode 1 0 : single sweep mode or simultaneous sample sweep mode b4 b3 when selecting single sweep mode 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. 0 figure 15.1.3.2 adcon0 register to adcon2 registers in single sweep mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 216 of n rej09b0047-0060z item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is repeatedly converted to a digital code a-d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a-d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) a-d conversion stop condition set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note 1) readout of a-d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin 15.1.4 repeat sweep mode 0 in repeat sweep mode 0, analog voltage is applied to the selected pins are repeatedly converted to a digital code. table 15.1.4.1 shows the repeat sweep mode 0 specifications. figure 15.1.4.1 shows the operation example in repeat sweep mode 0. figure 15.1.4.2 shows the adcon0 to adcon2 registers in repeat sweep mode 0. table 15.1.4.1 repeat sweep mode 0 specifications note 1. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.1.4.1 operation example in repeat sweep mode 0 ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") a-d conversion started an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d pin input voltage sampling a-d pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 217 of n rej09b0047-0060z a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select (b7-b6) nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. when selecting repeat sweep mode 0 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 0 : without sample and hold 1 : with sample and hold set to "0" in repeat sweep mode 0 0 a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit tr g adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw 1 rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select 1 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in repeat sweep mode 0 1 1 : repeat sweep mode 0 or repeat sweep mode 1 b4 b3 figure 15.1.4.2 adcon0 to adcon2 registers in repeat sweep mode 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 218 of n rej09b0047-0060z 15.1.5 repeat sweep mode 1 in repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. table 15.1.5.1 shows the repeat sweep mode 1 specifications. figure 15.1.5.1 shows the operation example in repeat sweep mode 1. figure 15.1.5.2 shows the adcon0 to adcon2 registers in repeat sweep mode 1. table 15.1.5.1 repeat sweep mode 1 specifications item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register mainly select pins. analog voltage applied to the all selected pins is repeatedly converted to a digital code example : when selecting an 0 analog voltage is converted to a digital code in the following order an 0 an 1 an 0 an 2 an 0 an 3 , and so on. a-d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a-d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) a-d conversion stop condition set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated analog input pins mainly select from an 0 (1 pins), an 0 to an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to used in a-d conversions an 3 (4 pins) (note 1) readout of a-d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin note1. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 15.1.5.1 operation example in repeat sweep mode 1 ? example when selecting an 0 to a-d sweep pins (scan1 to scan0="00 2 ") an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d conversion started a-d pin input voltage sampling a-d pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 219 of n rej09b0047-0060z a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 1 1 1 frequency select bit 1 cks1 1 : repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select refer to table 15.2 a-d conversion frequency select (b7-b6) 1 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in repeat sweep mode 1 invalid in repeat sweep mode 1 1 1 : repeat sweep mode 0 or repeat sweep mode 1 b4 b3 when selecting repeat sweep mode 1 0 0 : an 0 (1 pin) 0 1 : an 0 to an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 figure 15.1.5.2 adcon0 to adcon2 registers in repeat sweep mode 1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 220 of n rej09b0047-0060z item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code. at this time, the input voltage of an 0 and an 1 are sampled simultaneously. a-d conversion start condition when the trg bit in the adcon0 register is "0" (software trigger) set the adst bit in the adcon0 register to 1 (a-d conversion started) when the trg bit in the adcon0 register is "1" (hardware trigger) the trigger is selected by trg1 and hptrg0 bits (see table 15.1.6.2 ) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a-d conversion started) timer b0, b2 or timer b2 interrupt generation frequency setting counter underflow after setting the adst bit to 1 (a-d conversion started) a-d conversion stop condition a-d conversion completed (if selecting software trigger, the adst bit is auto- matically set to "0" ). set the adst bit to "0" (a-d conversion halted) interrupt generation timing a-d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins),an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) (note 1) readout of a-d conversion result readout one of the an0 to an7 registers that corresponds to the selected pin note 1. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 07 . however, all input pins need to belong to the same group. 15.1.6 simultaneous sample sweep mode in simultaneous sample sweep mode, analog voltage is applied to the selected pins are converted one- by-one to a digital code. at this time, the input voltage of an0 and an1 are sampled simultaneously using two circuits of sample and hold circuit. table 15.1.6.1 shows the simultaneous sample sweep mode specifications. figure 15.1.6.1 shows the operation example in simultaneous sample sweep mode. fig- ure 15.1.6.2 shows adcon0 to adcon2 registers and figure 15.1.6.3 shows adtrgcon registers in simultaneous sample sweep mode. table 15.1.6.2 shows the trigger select bit setting in simultaneous sample sweep mode. in simultaneous sample sweep mode, timer b0 underflow can be selected as a trigger by combining software trigger, ad trg trigger, timer b2 underflow, timer b2 interrupt generation frequency setting counter underflow or a-d trigger mode of timer b. ? example when selecting an 0 to an 3 to a-d pins for sweep (scan1 to scan0="01 2 ") a-d conversion started a-d interrupt request generated an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a-d pin input voltage sampling a-d pin conversion figure 15.1.6.1 operation example in simultaneous sample sweep mode table 15.1.6.1 simultaneous sample sweep mode specifications m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 221 of n rej09b0047-0060z figure 15.1.6.2 adcon0 to adcon2 registers for simultaneous sample sweep mode a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit trg adst a-d conversion start fag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 1 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select refer to table 15.2 a-d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. refer to table 15.1.6.2 trigger select bit setting in simultaneous sample sweep mode note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. invalid in simultaneous sample sweep mode 1 0 : single sweep mode or simultaneous sample sweep mode b4 b3 when selecting simultaneous sample sweep mode 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 00 reserved bit set to "0" rw 1 refer to table 15.1.6.2 trigger select bit setting in simultaneous sample sweep mode set to 1 in simultaneous sample sweep mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 222 of n rej09b0047-0060z figure 15.1.6.3 adtrgcon register in simultaneous sample sweep mode a-d trigger control register (note 1) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d operation mode select bit 2 bit symbol bit name function rw sse a-d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) an0 trigger select bit note 1: if adtrgcon register is rewritten during a-d conversion, the conversion result will be indeterminate. 0 0 : any mode other than delayed trigger mode 0,1 1 : simultaneous sample sweep mode or delayed trigger mode 0, 1 1 0 refer to table 15.1.6.2 trigger select bit setting in simultaneous sample sweep mode set to "0" in simultaneous sample sweep mode table 15.1.6.2 trigger select bit setting in simultaneous sample sweep mode trg hptrg0 trg1 trigger 0 1 1 1 - 1 0 0 software trigger timer b0 underflow (note 1) timer b2 or timer b2 interrupt generation frequency setting counter underflow (note 2) ad trg - - 1 0 note 1. a count can be started for timer b2, timer b2 interrupt generation frequency setting counter underflow or the int5 pin falling edge as count start conditions of timer b0. note 2. select timer b2 or timer b2 interrupt generation frequency setting counter using the tb2sel bit in the tb2sc register. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 223 of n rej09b0047-0060z note 1. set the larger value than the value of the timer b0 register to the timer b1 register. note 2. do not write 1 (a-d conversion started) to the adst bit in delayed trigger mode 0. when write 1 , unexpected interrupts may be generated. note 3. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 15.1.7 delayed trigger mode 0 in delayed trigger mode 0, analog voltage applied to the selected pins are converted one-by-one to a digital code. the delayed trigger mode 0 used in combination with a-d trigger mode of timer b. the timer b0 underflow starts a single sweep conversion. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted until the timer b1 underflow is generated. when the timer b1 under- flow is generated, the single sweep conversion is restarted after the an 1 pin. table 15.1.7.1 shows the delayed trigger mode 0 specifications. figure 15.1.7.1 shows the operation example in delayed trigger mode 0. figure 15.1.7.2 to figure 15.1.7.3 show each flag operation in the adstat0 register that corre- sponds to the operation example. figure 15.1.7.4 shows the adcon0 to adcon2 registers in delayed trigger mode 0. figure 15.1.7.5 shows the adtrgcon register in delayed trigger mode 0 and table 15.1.7.2 shows the trigger select bit setting in delayed trigger mode 0. item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the input voltage of the selected pins are converted one-by-one to the digital code. at this time, timer b0 under flow generation starts an 0 pin conversion. timer b1 underflow generation starts con- version after the an 1 pin. (note 1) a-d conversion start an 0 pin conversion start condition ? after timer b0 underflow is generated if timer b0 underflow is generated again before timer b1 underflow is generated , the conversion is not affected ? when timer b0 underflow is generated during a-d conversion of pins after the an 1 pin, conversion is halted and the sweep is restarted from the an 0 pin again an 1 pin conversion start condition ? when timer b1 underflow is generated during a-d conversion of the an 0 pin, the input voltage of the an 1 pin is sampled. the an 1 conversion and the rest of the sweep start when an 0 conversion is completed. a-d conversion stop ? when single sweep conversion from the an 0 pin is completed condition ? set the adst bit to "0" (a-d conversion halted)(note 2) interrupt request a-d conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins)(note 3) readout of a-d conversion result readout one of the an0 to an7 registers that corresponds to the selected pins table 15.1.7.1 delayed trigger mode 0 specifications m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 224 of n rej09b0047-0060z an 0 an 1 an 2 an 3 timer b0 underflow a-d pin input voltage sampling a-d pin conversion an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a-d conversion) timer b0 underflow timer b1 underflow timer b1 underflow ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") example 1: when timer b1 underflow is generated during an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow timer b1 underflow example 2: when timer b1 underflow is generated after an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion) timer b0 underflow timer b1 under flow timer b1 underflow example 3: when timer b0 underflow is generated during a-d conversion of any pins except an 0 pin example 4: when timer b0 underflow is generated again before timer b1 underflow is generated after timer b0 underflow generation figure 15.1.7.1 operation example in delayed trigger mode 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 225 of n rej09b0047-0060z figure 15.1.7.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (1) an 0 an 1 an 2 an 3 timer b0 underflow "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" an 0 an 1 an 2 an 3 "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" a-d pin input voltage sampling a-d pin conversion do not set to "1" by program do not set to "1" by program set to "0" by an interrupt request acknowledgement or a program set to "0" by an interrupt request acknowledgement or a program set to 0" by program set to "0" by program adst flag: bit 6 in the adcon0 register aderr0 aderr1 adtcsf adstt0 adstt1 adstrt0 a n d adstrt1 fl ag:bits013456a n d7i n t h e adstat0 register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b1 underflow timer b1 underflow ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") example 1: when timer b1 underflow is generated during an 0 pin conversion example 2: when timer b1 underflow is generated after an 0 pin conversion m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 226 of n rej09b0047-0060z an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion ) "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a-d conversion) "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" a-d pin input voltage sampling a-d pin conversion a-d pin input voltage sampling a-d pin conversion do not set to "1" by program do not set to "1" by program set to "0" by interrupt request acknowledgement or a program set to "0" by interrupt request acknowledgement or a program set to "0" by program set to "0" by program adst flag: bit 6 in the adcon0 register aderr 0, aderr1 , adt cs f , ad s tt 0, ad s tt1 , ad s trt 0 a n d ad s trt1 fl ag : b i ts 0, 1 , 3, 4 , 5, 6 a n d 7 in t h e ad s tat 0 r eg i ste r adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b0 underflow timer b1 underflow timer b1 underflow timer b1 underflow example 3: when timer b0 underflow is generated during a-d pin conversion of any pins except an 0 pin example 4: after timer b0 underflow is generated and when timer b0 underflow is generated again before timer b1 underflow is genetaed figure 15.1.7.3 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 227 of n rej09b0047-0060z figure 15.1.7.4 adcon0 to adcon2 registers in delayed trigger mode 0 a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit refer to table 15.1.7.2 trigger select bit setting in delayed trigger mode 0 trg adst a-d conversion start flag (note 2) 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 01 when selecting delayed trigger sweep mode 0 0 1 1 1 : set to "111b" in delayed trigger mode 0 b2 b1 b0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: do not write 1 in delayed trigger mode 0. when write, set to "0". note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. refer to table 15.2 a-d conversion frequency select (b7-b6) 1 1 0 00 b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) reserved bit set to "0" rw note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: set to 1 in delayed trigger mode 0. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit (note 2) 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 1 refer to table 15.1.7.2 trigger select bit setting in delayed trigger mode 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 228 of n rej09b0047-0060z figure 15.1.7.5 adtrgcon register in delayed trigger mode 0 a-d trigger control register (note 1) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d operation mode select bit 2 bit symbol bit name function rw sse a-d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) an0 trigger select bit note 1: if adtrgcon reigster is rewritten during a-d conversion, the conversion result will be indeterminate. 1 delayed trigger mode 0, 1 simultaneous sample sweep mode or delayed trigger mode 0,1 1 0 refer to table 15.1.7.2 trigger select bit setting in delayed trigger mode 0 refer to table 15.1.7.2 trigger select bit setting in delayed trigger mode 0 trigger timer b0, b1 underflow trg 0 hptrg0 1 trg1 0 hptrg1 1 table 15.1.7.2 trigger select bit setting in delayed trigger mode 0 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 229 of n rej09b0047-0060z ___________ note 1. when a third ad trg pin falling edge is generated again during a-d conversion, its trigger is ignored. ___________ note 2. the ad trg pin falling edge is detected synchronized with the operation clock ad. therefore, when the ___________ ___________ ad trg pin falling edge is generated in shorter periods than ad, the second ad trg pin falling edge may not ___________ be detected. do not generate the ad trg pin falling edge in shorter periods than ad. note 3. do not write 1 (a-d conversion started) to the adst bit in delayed trigger mode 1. when write 1 ,unexpected interrupts may be generated. note 4. an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 15.1.8 delayed trigger mode 1 in delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a digital code. when the input of the ad trg pin (falling edge) changes state from h to l , a single sweep conversion is started. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted until the second ad trg pin falling edge is generated. when the second ad trg falling edge is generated, the single sweep conversion of the pins after the an 1 pin is restarted. table 15.1.8.1 shows the delayed trigger mode 1 specifications. figure 15.1.8.1 shows the operation example of delayed trigger mode 1. figure 15.1.8.2 to figure 15.1.8.3 show each flag operation in the adstat0 register that corresponds to the operation example. figure 15.1.8.4 shows the adcon0 to adcon2 registers in delayed trigger mode 1. figure 15.1.8.5 shows the adtrgcon register in delayed trigger mode 1 and table 15.1.8.2 shows the trigger select bit setting in delayed trigger mode 1. table 15.1.8.1 delayed trigger mode 1 specifications item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltages applied to the selected pins are converted one-by-one to a digital code. at this time, the ad trg pin falling edge starts an 0 pin conversion and the second ad trg pin falling edge starts conversion of the pins after an 1 pin a-d conversion start an 0 pin conversion start condition condition the ad trg pin input changes state from h to l (falling edge)(note 1) an 1 pin conversion start condition (note 2) the ad trg pin input changes state from h to l (falling edge) ? when the second ad trg pin falling edge is generated during a-d conversion of the an 0 pin, input voltage of an 1 pin is sampled or after at the time of ad trg falling edge. the conversion of an 1 and the rest of the sweep starts when an 0 conversion is completed. ? when the ad trg pin falling edge is generated again during single sweep conver sion of pins after the an 1 pin, the conversion is not affected a-d conversion stop ? a-d conversion completed condition ? set the adst bit to "0" (a-d conversion halted)(note 3) interrupt request single sweep conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins) (note 4) readout of a-d conversion result readout one of the an0 to an7 registers that corresponds to the selected pins m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 230 of n rej09b0047-0060z ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") a-d pin input voltage sampling a-d pin conversion an 0 an 1 an 2 an 3 ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion ad trg pin input example 3: when ad trg pin falling edge is generated more than two times after an 0 pin conversion an 0 an 1 an 2 an 3 (invalid) (valid after single sweep conversion) ad trg pin input figure 15.1.8.1 operation example in delayed trigger mode1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 231 of n rej09b0047-0060z ? example when selecting an 0 to an 3 to a-d sweep pins (scan1 to scan0="01 2 ") a-d pin input voltage sampling a-d pin conversion an 0 an 1 an 2 an 3 an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" set to "0" by interrupt request acknowledgement or a program adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register set to "0" by program set to "0" by interrupt request acknowledgment or a program set to "0" by program do not set to "1" by program do not set to "1" by program ad trg pin input figure 15.1.8.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 232 of n rej09b0047-0060z example 3: when ad trg input falling edge is generated more than two times after an 0 pin conversion an 0 an 1 an 2 an 3 (invalid) (valid after single sweep conversion) adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" set to "0" when interrupt request acknowledgement or a program set to "0" by program do not set to "1" by program a-d pin input voltage sampling a-d pin conversion adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 a n d adstrt1 fl ag:bits0,1,3,4,5,6a n d7i n t h e adstat0 register ad trg pin input figure 15.1.8.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 233 of n rej09b0047-0060z a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit refer to table 15.1.8.2 trigger select bit setting in delayed trigger mode 1 tr g adst a-d conversion start flag (note 2) 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a-d operation mode select bit 1 1 : v ref connected 01 when selecting delayed trigger mode 1 0 1 1 1 : set to "111b" in delayed trigger mode 1 b2 b1 b0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 15.2 a-d conversion frequency select note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: do not write 1 in delayed trigger mode 1. when write, set to "0". note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a-d conversion. refer to table 15.2 a-d conversion frequency select (b7-b6) 1 1 0 00 b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) reserved bit set to "0" rw note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: set to 1 in delayed trigger mode 1. a-d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit (note 2) 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a-d input group select bit 0 0 : select port p10 group (an i ) 0 1 : do not set 1 0 : select port p0 group (an 0i ) 1 1 : select port p1/p9 group (an 2i ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 15.2 a-d conversion frequency select rw trg1 trigger select bit 1 1 refer to table 15.1.8.2 trigger select bit setting in delayed trigger mode 1 figure 15.1.8.4 adcon0 to adcon2 registers in delayed trigger mode 1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 234 of n rej09b0047-0060z a-d trigger control register (note 1) symbol address after reset adtrgcon 03d2h 00h b7 b6 b5 b4 b3 b2 b1 b0 a-d operation mode select bit 2 bit symbol bit name function rw sse a-d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) an0 trigger select bit note 1: if adtrgcon is rewritten during a-d conversion, the conversion result will be indeterminate. 1 delayed trigger mode 0, 1 simultaneous sample sweep mode or delayed trigger mode 0,1 1 0 refer to table 15.1.8.2 trigger select bit setting in delayed trigger mode 1 refer to table 15.1.8.2 trigger select bit setting in delayed trigger mode 1 figure 15.1.8.5 adtrgcon register in delayed trigger mode 1 trigger trg 0 hptrg0 0 trg1 1 ad trg hptrg1 0 table 15.1.8.2 trigger select bit setting in delayed trigger mode 1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 235 of n rej09b0047-0060z 15.2 resolution select function the bits bit in the adcon1 register determines the resolution. when the bits bit is set to 1 (10-bit precision), the a-d conversion result is stored into bits 0 to 9 in the adi register (i=0 to 7). when the bits bit is set to 0 (8-bit precision), the a-d conversion result is stored into bits 0 to 7 in the adi register. 15.3 sample and hold when the smp bit in the adcon 2 register is set to 1 (with the sample and hold function), a-d conver- sion rate per pin increases to 28 ad cycles for 8-bit resolution or 33 ad cycles for 10-bit resolution. the sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. in these modes, start a-d conversion after selecting whether the sample and hold circuit is to be used or not. 15.4 current consumption reducing function when the a-d converter is not used, the vcut bit in the adcon1 register isolates the resistor ladder of the a-d converter from the reference voltage input pin (v ref ). power consumption is reduced by shutting off any current flow into the resistor ladder from the v ref pin. when using the a-d converter, set the vcut bit to 1 (v ref connected) before setting the adst bit in the adcon0 register to 1 (a-d conversion started). do not set the adst bit and vcut bit to 1 simul- taneously, nor set the vcut bit to 0 (v ref unconnected) during a-d conversion. 15.5 analog input pin and external sensor equivalent circuit example figure 15.5.1 shows an example of the analog input pin and external sensor equivalent circuit. figure 15.5.1 analog input pin and external sensor equivalent circuit r 0 r (7.8k ? ) c (1.5pf) v in v c sampling time : 3 f ad microcomputer sensor equivalent circuit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 15. a-d converter rev.0.60 2004.02.01 page 236 of n rej09b0047-0060z microcomputer notes 1. c1 0.47f, c2 0.47f, c3 100pf, c4 0.1f (reference) 2. use thick and shortest possible wiring to connect capacitors. av cc av ss v ref an i c4 c1 c2 c3 v cc v ss an i : an i (i=0 to 7), an 0i (i=0 to 7 for 80-pin version, and i=0 to 3 for 64-pin version) an 2i (i=0 to 7 for 80-pin version, i=4 for 64-pin version) 15.6 precautions of using a-d converter (1) set the bit in the port direction register, which corresponds to the pin being used as the analog input, to 0 (input mode) set the bit in the port direction register, which corresponds to pin ad trg , to 0 (input mode) if the external trigger is used. (2) when using a key input interrupt, do not use pins an 4 to an 7 as analog input pins (key input interrupt request is generated when the a-d input voltage is l ). (3) insert capacitors between pins av cc , v ref , analog input pin (an i (i=0 to 7), an 0i and an 2i ) and av ss to prevent latch-ups and malfunctions due to noise, and to minimize conversion errors. the same applies to pins v cc and v ss . figure 15.6.1 shows the procedure of each pin. (4) incorrect values are stored in the adi register (i=0 to 7) if the cpu reads the adi register while the adi register is storing results from a completed a-d conversion. this occurs when a divided main clock or a sub clock is selected as the cpu clock. ? in one-shot mode or single sweep mode, simultaneous sample sweep mode and delayed trigger mode 0, 1 , read the corresponding adi register after verifying that the a-d conversion has been completed. (the completion of the a-d conversion can be determined by the ir bit in the adic register). ? in repeat mode, repeat sweep mode 0 and repeat sweep mode 1, use an undivided main clock as the cpu clock. (5) conversion results of the a-d converter are indeterminate, if the adst bit in the adcon0 register is set to 0 (a-d conversion halted) and the conversion is forcibly terminated, by program during a-d conversion. adi registers not operating a-d conversion may also be indeterminate. if the adst bit is changed to 0 by program, during the a-d conversion, do not use any values obtained from the adi registers. figure 15.6.1 vcc, vss, avcc, avss, vref and ani connections m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 237 of n rej09b0047-0060z item function based on philips i 2 c bus standard: format 7-bit addressing format high-speed clock mode standard clock mode based on philips i 2 c bus standard: master transmit communication mode master receive slave transmit slave receive scl clock frequency 16.1khz to 400khz (at v iic (note 1) = 4mhz) 16. multi-master i 2 c bus interface the multi-master i 2 c bus interface is a serial communication circuit based on philips i 2 c bus data transfer format. 2 independent channels, with both arbitration lost detection and synchronous functions, are built in for the multi-master serial communication. figure 16.1 shows a block diagram of the multi-master i 2 c bus interface and table 16.1 lists the multi-master i 2 c bus interface functions. the multi-master i 2 c bus interface consists of the i 2 c0 address register, the i 2 c0 data shift register, the i 2 c0 clock control register, the i 2 c0 control register 1, i 2 c0 control register 2, the i 2 c0 status register, the i 2 c0 start/stop condition control register and other control circuits. figure 16.2 to 16.8 show the registers associated with the multi-master i 2 c bus. table 16.1 multi-master i 2 c bus interface functions note 1. v iic =i 2 c system clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 238 of n rej09b0047-0060z figure 16.1 block diagram of multi-master i 2 c bus interface noise elimination circuit serial data (sda) data control circui t bb circui t clock control circui t noise elimination circuit (scl) b7 b0 ack ack bit fast mode ccr4 ccr 3ccr 2ccr 1 ccr 0 internal data bu s clock divisi on s20 al circui t b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 address comparat or b7 b0 s 0 s0d0 interrupt generation circuit interrupt request signal (sclsdairq) b7 b0 ick1 ick0 sclm sdam wit sim s3d0 interrupt generation circuit interrupt request sign al b7 mst tr x bb p i n al aas ad0 lr b b0 s10 b7 b0 tiss als bc2 bc1 bc 0 es0 f1 i 2 c system clock (viic) t imeout dete c tion circui t tof to e ick4 ick3 ick2 tosel system clock select circut s5d0 s6d0 b7 b0 aas0 aas1 aas2 s30 i 2 c0 control register 1 i 2 c0 start/stop condition control register s2d0 stsp sel sis sip ssc4 ssc3 ssc2 ssc1 ssc0 i 2 c0 address registers i 2 c0 data shift registers i 2 c0 control registers 2 s4d0 i 2 c0 clock control registers i 2 c0 status registers i 2 c0 control registers 0 s1d0 i 2 c0 status registers 1 i 2 c-bus interface bit count (i 2 c irq) serial clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 239 of n rej09b0047-0060z figure 16.2 i 2 c0 address register, i 2 c0 address register 2 sad6 sad5 sad4 sad3 sad2 sad1 sad0 reserved bit function bit name bit symbol address after reset symbol c 0 a d d r e s s r e g i s t e r s0d0 02e2 16 00 16 b 7 b6 b5 b 4 b3 b 2b1b0 i 2 slave address set to 0 comparing with received address data rw rw rw rw rw rw rw rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 240 of n rej09b0047-0060z figure 16.3 i 2 c0 data shift register, i 2 c0 clock control register 0: standard clock mode 1: high-speed clock mode 0: ack is returned 1: ack is not returned 0: no ack clock 1: with ack clock ack clock bit ack bit s cl mode specification bit s cl frequency control bits ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack function bit name bit symbol 00 16 after reset 02e4 16 address symbol s20 b 7 b6 b5 b 4 b3 b2 b1 b0 c 0 clock control re g ister i 2 rw see table 16.3 set values of i c0 clock control register and s cl frequency 2 rw rw rw rw rw rw rw rw symbol address when reset s00 02e0 16 xx 16 b7 b6 b5 b4 b3 b2 b1 b0 aaaaaa aaaaaa i c0 data shift register 2 rw transmit/receive data are stored. in the master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to section 16.9 start condition generation method and section16.11 stop condition generation method) . the transmit/receive are started synchronized with s cl . note 1: the write is only enabled when the bus interface enable bit (es0 bit) is "1". because the register is used both for storing transmit/receive data, write the transmit data after the receive data is read out when transmittin g . function rw (note 1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 241 of n rej09b0047-0060z figure 16.4 i 2 c0 control register 0 0: disabled 1: enabled 0: addressing format 1: free data format set to "0" 0: reset release (auto) 1: reset note 1: in the following status, the bit counter is cleared automatically ? start condition/stop condition are detected ? immediately after the completion of 1-byte data transmit ? immediately after the completion of 1-byte data receive i c bus interface pin input level select bit 2 i c bus interface reset bit 2 reserved bit data format select bit i c bus interface enable bit 2 bit counter (number of transmit/receive bits) bc2 tiss ihr (b5) als es0 bc1 bc0 function bit name bit symbol 00 16 after reset 02e3 16 address symbol s1d0 c 0 control re g ister 0 i 2 b 7 b6 b5 b 4 b3 b 2 b 1b0 b2 b1 b0 (note 1) 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 rw 0: i c bus input 1: smbus input 2 rw rw rw rw rw rw rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 242 of n rej09b0047-0060z figure 16.5 i 2 c0 status register note 1: this bit is read only if it is used for the status check. to write to this bit, refer to sections 16.9 start condition generation method and 16.11 stop condition generation method . note 2: this bit is read only, when write, set to 0 . note 3: to write to these bits, refer to sections 16.9 start condition generation method and 16.11 stop condition generation method. 0 0: slave receive mode 0 1: slave transmit mode 1 0: master receive mode 1 1: master transmit mode 0: bus free 1: bus busy 0: interrupt request issued 1: no interrupt request issued 0: not detected 1: detected 0: no address matched 1: address matched 0: no general call detected 1: general call detected 0: last bit = 0 1: last bit = 1 communication mode specification bits bus busy flag i c bus interface interrupt request bit 2 arbitration lost detection flag slave address comparison flag general call detecting flag last receive bit mst trx bb pin al aas adr0 lrb function bit name bit symbol 0001000x 2 after reset 02e8 16 address symbol s10 c 0 status re g ister i 2 rw b7 b6 b 7 b6 b5 b 4 b3 b 2b1b0 ro (note 1) ro (note 1) ro (note 1) ro (note 2) ro (note 1) ro (note 2) ro (note 3) ro (note 3) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 243 of n rej09b0047-0060z figure 16.6 i 2 c0 control register 1 0: s cl output logic value = 0 1: s cl output logic value = 1 0: s da output logic value = 0 1: s da output logic value = 1 0: s cl i/o pin (enable es0 = 1) 1: port output pin (enable es0 = 1) 0: s da i/o pin (enable es0 = 1) 1: port output pin (enable es0 = 1) 0: disable the i 2 c bus interface interrupt of data receive completion 1: enable the i 2 c bus interface interrupt of data receive completion when setting nack (ack bit = 0), write "0" 0: disable the i 2 c bus interface interrupt of stop condition detection 1: enable the i 2 c bus interface interrupt of stop condition detection i c system clock selection bits, if ick4 to ick2 bits in the s4d0 register is "000 2 " 2 the logic value monitor bit of s cl output the logic value monitor bit of s da output s cli /port function switch bit s dai /port function switch bit the interrupt enable bit for data receive completion the interrupt enable bit for stop condition detection ick1 ick0 sclm sdam pec ped wit sim function bit name bit symbol 00110000 2 when reset 02e6 16 address symbol s3d0 c 0 control re g ister 1 i 2 b 7 b6 b5 b 4 b3 b 2b1b0 rw b7 b6 0 0 : 0 1 : 1 0 : v iic =1/2 f 1 =1/4f 1 ? f 1 =f(x in ) =1/8f 1 1 1 : reserved v iic v iic rw rw rw rw ro ro rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 244 of n rej09b0047-0060z figure 16.7 i 2 c0 control register 2 scpin reserved bit ick4 ick3 ick2 tosel tof toe function bit name bit symbol 00 16 when reset 02e7 16 address symbol s4d0 c 0 control re g ister 2 i 2 rw b 7 b6 b5 b 4 b3 b 2b1b0 0 : long time 1 : short time stop condition detection interrupt request bit set to "0" b5 b4 b3 0 0 0 v iic set by ick1 and ick0 bits in s3d0 register 0 0 1 v iic = 1/2.5 f1 0 1 0 v iic = 1/3 f1 0 1 1 v iic = 1/5 f1 1 0 0 v iic = 1/6 f1 time out detection time select bit time out detection flag time out detection function enable bit i 2 c system clock select bits 0 : no i 2 c bus interface interrupt request 1 : i 2 c bus interface interrupt request 0 : not detected 1 : detected 0 : disabled 1 : enabled rw ro rw rw rw rw rw rw (b6) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 245 of n rej09b0047-0060z figure 16.8 i 2 c0 start/stop condition control register note: do not set odd values or 00000 2 to start/stop condition setting bits(ssc4 to ssc0) oscillation i 2 c bus system i 2 c bus system ssc4-ssc0 s cl release setup time hold time f1 (mhz) clock select clock(mhz) time(cycle) (cycle) (cycle) 10 1 / 2f1 5 xxx11110 6.2 s (31) 3.2 s (16) 3.0 s (15) 8 1 / 2 f1 4 xxx11010 6.75 s(27) 3.5 s (14) 3.25 s(13) xxx11000 6.25 s(25) 3.25 s (13) 3.0 s (12) 8 1 / 8f1 1 xxx00100 5.0 s (5) 3.0 s (3) 2.0 s (2) 4 1 / 2 f1 2 xxx01100 6.5 s (13) 3.5 s (7) 3.0 s (6) xxx01010 5.5 s (11) 3.0 s (6) 2.5 s (5) 2 1 / 2 f1 1 xxx00100 5.0 s (5) 3.0 s (3) 2.0 s (2) table 16.2 recommended setting value (ssc4 - ssc0) start/stop condition at each oscillation frequency 0: setup/hold time short mode 1: setup/hold time long mode 0: s da enabled 1: s cl enabled 0: active in falling edge 1: active in rising edge setting for detection condition of start/stop condition. see table 16.2 recommended setting value (ssc4 - ssc0) start/stop condition at each oscillation frequency . start/stop condition generation select bit s cl /s da interrupt pin select bit s cl /s da interrupt pin polarity select bit start/stop condition setting bits(note 1) stsp sel sis sip ssc4 ssc3 ssc2 ssc1 ssc0 function bit name bit symbol 00011010 2 when reset 02e5 16 address symbol s2d0 c 0 s t a r t / s t o p c o n d i t i o n c o n t r o l r e g i s t e r i 2 rw b 7 b6 b5 b 4 b3 b 2b1b0 note 1: disable the setting of "00000 2 " and odd values. rw rw rw rw rw rw rw rw m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 246 of n rej09b0047-0060z 16.2 i 2 c0 address register (s0d0 register) this register consists of 7 bits of sad6 to sad0. at the addressing format which detects the slave address automatically, the contents of sad6 to sad0 are compared with the address data to be received. 16.1 i 2 c0 data shift register (s00 register) the i 2 c0 data shift register (address 02e0 16 ) is the 8-bit shift register to store the receive data and the write transmit data. when the transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the s cl clock, and each time one-bit data is output, the data of this register is shifted by one bit to the left. when the data is received, it is input to this register from the bit 0 in synchro- nization with the s cl clock, and each time the one-bit data is input, the data of this register is shifted by one bit to the left. figure 16.9 shows the timing which stores the receive data to this register. the i 2 c0 data shift register is in a write enable status only when the i 2 c bus interface enable bit (es0 bit : bit 3 of address 02e3 16 ) of the i 2 c0 control register 0 is 1 . the bit counter is reset by a write instruction to the i 2 c0 data shift register. when both the es0 bit and the mst bit in the i 2 c0 status register (address 02e8 16 ) are 1 , the scl is output by a write instruction to the i 2 c0 data shift register. reading data from the i 2 c0 data shift register is always enabled regardless of the es0 bit value. figure 16.9 the timing of receiving data stored to i 2 c0 data shift register s cl s da internal s cl internal s da shift clock t dfil : noise elimination circuit delay time 1 to 2 v iic cycle tdfil tdfil tdsft storing data at shift clock rising edge. t dsf : shift clock delay time 1 v iic cycle m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 247 of n rej09b0047-0060z 16.3 i 2 c0 clock control register (s20 register) the i 2 c0 clock control register (address 02e4 16 ) is used to set theack control, s cl mode and the s cl frequency. 16.3.1 bits 0 to 4: s cl frequency control bits (ccr0 ccr4) these bits control the s cl frequency. see table 16.3 set values of i 2 c0 clock control register and scl frequency . 16.3.2 bit 5: s cl mode specification bit (fast mode) this bit specifies s cl mode. when this bit is set to 0 , standard clock mode is selected. when the bit is set to 1 , high-speed clock mode is selected. when connecting to the bus with high-speed mode i 2 c bus standard (maximum 400 kbits/s), set 4 mhz or more to the i 2 c system clock(v iic ). 16.3.3 bit 6: ack bit (ack bit) this bit sets the s da status when an ack clock (note 1) is generated. when this bit is set to 0 , ack return mode is selected and the s da goes to l at the ack clock generation. when the bit is set to 1 , ack non- return mode is selected. the s da is held in the h status at the ack clock generation. however, when the address data is received at the ack bit=0 and the slave address matches with the address data, the s da is automatically set to l (ack is returned). if the slave address does not match with the address data, the s da is automatically set to h (ack is not returned). note 1. ack clock: clock for acknowledgment 16.3.4 bit 7: ack clock bit (ack) this bit specifies mode of acknowledgment for responses to transfer data. when this bit is set to 0 , no ack clock mode is selected. in this case, the ack clock is not generated after the data transmit. when the bit is set to 1 , ack clock mode is selected and the master generates an ack clock at the completion of each 1-byte data transfer. the device for transmitting the address data and the control data releases the s da at the ack clock generation (set the s da to h ) and receives the ack bit generated by the data receive device. note . do not rewrite the data into the i 2 c0 clock control register other than the ack bit (ackbit) during the transfer. if data is written during the transfer, the i 2 c bus clock circuit is reset and the data can not be transferred normally. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 248 of n rej09b0047-0060z setting value of ccr4 to ccr0 s cl frequency (at v iic =4mhz, unit : khz) (note 1) ccr4 ccr3 ccr2 ccr1 ccr0 standard clock mode high-speed clock mode 0 0 0 0 0 setting disabled setting disabled 0 0 0 0 1 setting disabled setting disabled 0 0 0 1 0 setting disabled setting disabled 0 0 0 1 1 - (note 2) 333 0 0 1 0 0 - (note 2) 250 0 0 1 0 1 100 400 (note 3) 0 0 1 1 0 83.3 166 500 / ccr value 1000 / ccr value (note 3) (note 3) 1 1 1 0 1 17.2 34.5 1 1 1 1 0 16.6 33.3 1 1 1 1 1 16.1 32.3 note 1: the duty of the s cl clock output is 50 %. the duty becomes 35 to 45 % only when high-speed clock mode is selected and the ccr value = 5 (400 khz, at viic = 4 mhz). h duration of the clock fluctuates from C 4 to +2 i 2 c system clock cycles in standard clock mode, and fluctu- ates from C 2 to +2 i 2 c system clock cycles in high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because the l is extended instead of h reduc tion. these are the values when the s cl clock synchronization by the synchronous function is not performed. the ccr value is the decimal notation value of the s cl frequency control bits ccr4 to ccr0. note 2: each value of the s cl frequency exceeds the limit at v iic = 4 mhz or more. when using these setting values, use v iic = 4 mhz or less. refer to figure 16.6 i 2 c system clock select bits (bit 6 and 7 of i 2 c control register 1) on v iic . note 3: the data formula of s cl frequency is described below: v iic /(8 ccr value) standard clock mode v iic /(4 ccr value) high-speed clock mode (ccr value 5) v iic /(2 ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as the ccr value regardless of the viic frequency. set 100 khz (max.) in standard clock mode and 400 khz (max.) in high-speed clock mode to the s cl frequency by setting the s cl frequency control bits ccr4 to ccr0. table 16.3 set values of i 2 c0 clock control register and s cl frequency m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 249 of n rej09b0047-0060z 16.4 i 2 c0 control register 0 (s1d0 register) the i 2 c0 control register 0 (address 02e3 16 ) controls the data communication format. 16.4.1 bits 0 to 2: bit counter (bc0 bc2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c bus interface interrupt request signal is generated immediately after the number of count specified with these bits (the ack clock is added to the number of count when the ack clock is selected by the ack bit (bit 7 of address 02e4 16 )) have been transferred, and the bc0 to bc2 are returned to 000 2 . also when a start condition is detected, these bits become 000 2 and the address data is always transmitted and received in 8 bits. 16.4.2 bit 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c bus interface. when this bit is set to 0 , the interface is disabled and the s da and the s cl become high-impedance. when the bit is set to 1 , the interface is enabled. when the es0 bit is set to 0 , the following is performed. 1)set mst = 1, trx = 0, pin = 1, bb = 0, al = 0, aas = 0, and adr0 = 0, of the i 2 c0 status register (address : 02e8 16 ) 2)writing the data into the i 2 c0 data shift register (address : 02e0 16 ) is disabled. 3)the tof bit in the i 2 c0 control register (address : 02e7 16 ) is cleared to 0 4)the i 2 c system clock (v iic ) is stopped and the internal counter, flags are initialized. 16.4.3 bit 4: data format select bit (als) this bit decides if the recognition of the slave address is processed or not. when this bit is set to 0 , the addressing format is selected and the address data is recognized. the transfer will be processed only when a comparison is matched between the slave address and the address data or a general call is received (refer to figure 16.5 i 2 c0 status register: the item of bit 1, general call detection flag ). when this bit is set to 1 , the free data format is selected and the slave address is not recognized. 16.4.4 bit 6: i 2 c bus interface reset bit (ihr) the bit is used to reset the i 2 c bus interface circuit when the abnormal communication occurs. when the es0 bit is 1 (i 2 c bus interface is enabled), writing 1 to the ihr bit resets h/w. flags are processed as follows: 1)set mst = 0, trx = 0, pin = 1, bb = 0, al = 0, aas = 0, and adr0 = 0, of i 2 c0 status register (address : 02e8 16 ) 2)the tof bit of the i 2 c0 control register 2 (address : 02e7 16 ) is cleared to 0 3)the internal counter, flags are initialized. after writing 1 to the ihr bit, the circuit reset processing is finished in max. 2.5 v iic cycles and the ihr bit is automatically cleared to 0 . figure 16.10 shows the reset timing. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 250 of n rej09b0047-0060z figure 16.10 the timing of reset to the i 2 c bus interface circuit 2.5 v iic cycles the signal of writing "1" to ihr bit ihr bit the reset signal to i c-bus interface circuit 2 16.4.5 bit 7: i 2 c bus interface pin input level select bit (tiss) this bit selects the input level of the s cl and s da pins of the multi-master i 2 c bus interface. when this bit is set to 1 , the p2 0 and p2 1 become the smbus input level. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 251 of n rej09b0047-0060z 16.5 i 2 c0 status register (s10 register) the i 2 c0 status register (address 02e8 16 ) controls the i 2 c bus interface status. use the lower-6 bit as read only if it is used for a status check. 16.5.1 bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for an ack receive confirmation. if the ack is returned when the ack clock is generated, the lrb bit is set to 0 . if the ack is not returned, this bit is set to 1 . except in ack mode, the last bit value of the received data is input. the bit is 0 by executing a write instruction to the i 2 c0 data shift register (address 02e0 16 ). 16.5.2 bit 1: general call detection flag (adr0) when the als bit is 0 , this bit is set to 1 when a general call (note 1) ,whose address data is all 0 , is received in slave mode. by a general call of the master device, every slave device receives control data after the general call. the adr0 bit is set to 0 by detecting the stop condition, start condition and when the es0 is 0 , or reset. note 1. general call: the master transmits the general call address 00 16 to all slaves. 16.5.3 bit 2: slave address comparison flag (aas) this flag indicates a comparison result of the address data when the als bit in the s1d0 register is 0 . in slave receive mode, this bit is set to 1 in one of the following conditions: ? 7 bit of the address data matches the slave address stored in the s0d0 register. ? a general call is received. the aas flag is set to 0 in one of the following conditions: ? when the es0 bit is set to 1 , excute to write an instruction to the s00 register ? when the es0 bit is set to 0 . ? excute to reset by the ihr bit in the s1d0 register. 16.5.4 bit 3: arbitration lost detection flag (al) (note 1) when devices other than the microcomputer set the s da to l in master transmit mode, the arbitration is judged to be lost and the al bit is set to 1 . at the same time, the trx bit is set to 0 . immediately after the bute transmist, whose arbitration is lost, is completed, the mst bit is set to 0 . the arbitration lost can be detected only in master transmit mode. when the arbitration is lost during the slave address transmit, the trx bit is set to 0 and the receive mode is set. consequently, it is possible to detect the match between its own slave address and address data transmitted by another master devices. the bit becomes 0 if writing to the i 2 c0 data shift register (address 02e0 16 ) when the es0 bit is 1 . the bit also becomes 0 when the es0 bit is set to 0 or when reset. note 1. arbitration lost: the status is that communication as a master is disabled. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 252 of n rej09b0047-0060z 16.5.5 bit 4: i 2 c bus interface interrupt request bit (pin) this bit generates an i 2 c bus interface interrupt request signal. after each byte data is transmitted, the pin bit is changed from 1 to 0 . at the same time, an i 2 c bus interface interrupt request signal is generated to the cpu. the pin bit is set to 0 synchronized with the falling edge of the last internal transmit clock (the ack clock in ack clock enable mode, the 8th clock in ack clock disable mode) and an interrupt request signal is generated synchronized with the falling edge of the pin bit. when the pin bit is 0 , s cl is kept in the 0 state and the clock generation is disabled. in ack clock enable mode, and when the wit bit in the s3d0 register is set to 1 , synchronized with the falling edge of the last bit clock and the ack clock, the pin bit becomes to 0 and the i 2 c bus interface interrupt request is generated (refer to section 16.6.2 bit1: interrupt enable bit at the completion of data receive (wit) . figure 16.11 shows the timing of the i 2 c bus interface interrupt request generation. the pin bit is set to 1 in one of the following conditions: ? executing a write instruction to the s00 register (address 02e0 16 ). ? executing a write instruction to the s20 register (address : 02e4 16 ) (only when the wit is 1 and the internal wait flag is 1 ) ? when the es0 bit is 0 ? at reset the pin bit is set to 0 in one of the following conditions: ? immediately after the completion of the 1-byte data transmit (including arbitration lost is detected) ? immediately after the completion of the 1-byte data receive ? in slave receive mode, with the als = 0 and immediately after the completion of the slave address match or the general call address receive ? in slave receive mode, with the als = 1 and immediately after the completion of the address data receive 16.5.6 bit 5: bus busy flag (bb) this bit indicates the operating conditions of the bus system. when this bit is set to 0 , the bus system is not used and a start condition can be generated. the bb flag is set/reset by the s cl and the s da pins input the signal regardless of master or slave mode. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detections is followed by the start/ stop condition setting bits (ssc4 C ssc0) of the s2d0 register (address 02e5 16 ). when the es0 bit of the s1d0 register (address 02e3 16 ) is 0 or reset, the bb flag is set to 0 . for the writing function to the bb flag, refer to section 16.9 start condition generation method and 16.11 stop condi- tion generation method as described later. figure 16.11 interrupt request signal generation timing s cl pin flag i 2 cirq m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 253 of n rej09b0047-0060z 16.5.8 bit 7: communication mode select bit (master/slave select bit: mst) this bit is used for the master/slave select bit for the data communication. when this bit is 0 , the slave is specified, so that a start condition and a stop condition are generated by the master are received. the data communication is performed synchronized with the clock generated by the master. when this bit is 1 , the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for the data communication are generated on the s cl . this bit is set to 0 by hardware in one of the following conditions. ? immediately after the completion of 1-byte data transfer,which lost the arbitration, when arbitration lost is detected. ? when a stop condition is detected. ? when a start condition is detected. ? writing a start condition is disabled by the start condition duplicate protect function (note 1) . ? at reset note 1. start condition duplicate protect function the mst, trx, and bb bits are set to 1 at the same time after confirming that the bb flag is 0 in the procedure of a start condition generation. however, when a start condition generation by other master devices and the bb flag is set to 1 immediately after the contents of the bb flag are confirmed, the start condition duplicate protect function makes the writing to the mst and trx bits invalid. the duplicate protect function becomes valid from the rising of the bb flag to receive completion of the slave address. refer to section 16.9 start condition generation method for details. 16.5.7 bit 6: communication mode select bit (transfer direction select bit: trx) this bit decides a transfer direction for the data communication. when this bit is 0 , receive mode is selected and the data from a transmit device is received. when the bit is 1 , transmit mode is selected and the address data and the control data are output onto the s da synchronized with the clock gener- ated on the s cl . this bit can be set/reset by software or hardware. this bit is set to 1 by hardware in the following condition: ? in slave mode with the als = 0, if the aas flag is set to 1 after the address data receive and the ___ received r/w bit is 1 . this bit is set to 0 by hardware in one of the following conditions: ? when an arbitration lost is detected. ? when a stop condition is detected. ? when a start condition is detected. ? when a start condition is disabled by the start condition duplicate protect function (1) . ? when a start condition is detected with mst = 0. ? when ack non-return is detected with mst = 0. ? es0 = 0. ? at reset m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 254 of n rej09b0047-0060z 16.6 i 2 c0 control register 1 (s3d0 register) i 2 c0 control register 1 (address 02e6 16 ) controls i 2 c bus interface circuit. 16.6.1 bit 0 : interrupt enable bit by stop condition (sim ) this bit enables the i 2 c bus interface to request an i 2 c bus interface interrupt by detecting a stop condition. if the bit set to 1 , an interrupt request from the i 2 c bus interface is generated by detecting a stop condition ( there is no change for the pin flag) 16.6.2 bit 1: interrupt enable bit at the completion of data receive (wit) when with ack mode (ack bit = 1) is specified, by the interrupt enable (wit bit = 1) at the completion of data receive, the i 2 c bus interface interrupt request is generated and the pin bit becomes 0 synchro- nized with the falling edge of the last data bit clock. the scl becomes l and the ack clock generation is suppressed. table 16.4 and figure 16.12 show the i 2 c bus interrupt request timing and the communication restart method. after the communication restart, synchronized with the falling edge of ack clock, the pin bit becomes 0 again and the i 2 c bus interface interrupt request is generated. table16.4 timing of interrupt generation in data receive i 2 c bus interrupt generation timing communication restart method 1) synchronized with the falling edge of the the execution of writing to ack bit of i 2 c0 clock control last data bit clock register. follow this by a register write to set pin bit = 1. (do not write to the i 2 c0 data shift register. the ack clock operation can be incorrect.) 2) synchronized with the falling edge of the the execution of writing to the i 2 c0 data shift register ack clock the state of the internal wait flag can be read out by reading the wit bit. the internal wait flag is set after writing to the i 2 c0 data shift register, and it is reset after writing to the i 2 c0 clock control register. conse- quently, the i 2 c bus interface interrupt request generated by the timing 1) or 2) can be determined. (see figure 16.12 the timing of the interrupt generation at the competion of data receive .) in the cases of transmit and the address data receive immediately after the start condition, the i 2 c bus interface interrupt request is only generated at the falling edge of the ack clock regardless of the value of the wit bit and the wait flag remains the reset state. write 0 to the wit bit when in nack is specified. (ack bit = 0) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 255 of n rej09b0047-0060z figure 16.12 the timing of the interrupt generation at the completion of the data receive in receive mode, ack bit = 1 wit bit = 0 7 clock 8 clock ack clock 1 clock 1 bit 7 bit 8 bit ack bit s cl s da ackbit pin flag internal wait flag i 2 c bus interface interrupt request signal the writing signal of i 2 c0 data shift register 7 clock 8 clock ack clock 1 bit 7 bit 8 bit s cl s da ackbit pin flag internal wait flag i 2 c bus interface interrupt request signal the writing signal of i 2 c0 data shift register the writing signal of i 2 c0 clock control register 1) note: do not write to the i 2 c0 clock control register except the bit ackbit. in receive mode, ack bit = 1 wit bit = 1 2) 16.6.3 bits 2,3 : port function select bits ped, pec when the es0 bit of the i 2 c0 control register 0 is set to 1 , p2 1 and p2 0 functions as s cl and s da pins respectively. however, if the ped is set to 1 , the s da functions as the output port so as to the s cl if the pec is set to 1 . in this case, if 0 or 1 is written to the port register, the data can be output onto the i 2 c bus regardless of the internal s cl /s da output signals. the functions of s cl /s da are returned back by setting the ped to 1 again. if the ports are set in input mode, the values on the i 2 c bus can be known by reading the port register regardless of the values of the ped and pec.table 16.5 shows the port specification. table 16.5 port specifications pin name p2 0 p2 1 es0 bit 0 1 1 es0 bit 0 1 1 ped bit - 0 1 pec bit - 0 1 0/1 - - 0/1 - - p2 0 port direction register p2 1 port direction register function port i/o function s da i/o function s da input function, port output function function port i/o function s cl i/o function s cl input function, port output function m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 256 of n rej09b0047-0060z 16.6.6 the address receive in stop mode/wait mode the i 2 c bus interface circuit enables to receive the address data in wait mode when setting the cm02 bit in the cm0 register to "0" (do not stop the peripheral function clock in wait mode) and entering wait mode. however, the i 2 c bus interface circuit is not operated in stop mode or in low power consumption mode, because the i 2 c bus system clock v iic is not supplied. 16.6.4 bits 4,5 : s da /s cl logic output value monitor bits s dam /s clm these bits enableto monitor the logic value of the s da and s cl output signals from the i 2 c bus interface circuit. the s dam bit monitors the s da output logic value. the s clm bit monitors the s cl output logic value. the bits are read-only. when write, set to 0 . 16.6.5 bits 6,7 : i 2 c system clock select bits ick0, ick1 these bits and ick4 to ick2 bits in the s4d0 register select the system clock (v iic ) of the i 2 c bus interface circuit. these bits enable to select the i 2 c bus system clock v iic among divisions by 2, 2.5, 3, 4, 5, 6 or 8 of the main clock f(x in ). i3ck4[s4d0] ick3[s4d0] ick2[s4d0] ick1[s3d0] ick0[s3d0] i 2 c system clock 00000v iic = 1/2 f(x in ) 00001v iic = 1/4 f(x in ) 00010v iic = 1/8 f(x in ) 001xxv iic = 1/2.5 f(x in ) 010xxv iic = 1/3 f(x in ) 011xxv iic = 1/5 f(x in ) 100xxv iic = 1/6 f(x in ) table 16.6 i 2 c system clock select bits ( do not set the combination which is not indicated here) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 257 of n rej09b0047-0060z 16.7 i 2 c0 control register 2 (s3d0 register) i 2 c0 control register 2 (address: 02e7 16 ) controls the abnormal communication detection. in the i 2 c bus communication, the data transfer is controlled by the s cl clock signal. the devices are stoped in the commu- nication state if the s cl clock is stopped during the transfer. to avoid that, if the s cl clock is stopped in h state for a period of time, the i 2 c bus interface circuit has the function to detect the time out and generate an i 2 c bus interface interrupt request. please see figure 16.13 the timing of time out detection . figure 16.13 the timing of time out detection 1 clock 1 bit s cl s da bb flag internal counter start signal internal counter stop, reset signal internal counter overflow signal i 2 c-bus interface interrupt request signal 2 bit 3 bit 2 clock 3 clock s cl clock stop ( h ) the time of timeout detection m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 258 of n rej09b0047-0060z 16.7.1 bit0: time out detection function enable bit (toe) the bit enables a time out detection function. when setting this bit to 1 , the i 2 c bus interface interrupt request signal is generated if the s cl clock is stopped in h state for a period of time during the bus busy (bb flag =1). the time out detection period is measured by the internal counter and selected from long time mode or short time mode by the time out detection period select bit (tosel). when time out is detected, set the es0 bit to 0 and then process initialization. 16.7.2 bit1: time out detection flag (tof ) the bit is the flag showing the time out detection status. if the internal counter which measures the time out period overflows, the time out detection flag (tof) becomes to 1 , and at the same time the i 2 c bus interface interrupt request signal is generated. 16.7.3 bit2: time out detection period select bit (tosel) the bit selects time out detection period from long time and short time mode. if the tosel = 0, the long time mode and tosel = 1, the short time mode is selected respectively. the long time is counted by 16- bit counters and the short time is counted by 14-bit counters based on the i 2 c system clock (v iic ). table 16.7 shows examples of the time out detection period. table 16.7 examples of time out detection period (unit: ms) 16.7.4 bits 3,4,5: i 2 c system clock select bits (ick2-4) ick4 to 2 bits, ick1 and ick0 bits of the s3d0 register select the system clock (v iic ) of the i 2 c bus interface circuit.table 16.6 shows the i 2 c system clock setting for the setting values. 16.7.5 bit7: stop condition detection interrupt request bit (scpin) the bit monitors the stop condition detection interrupt. the bit becomes to 1 when the i 2 c bus interface interrupt is generated by detecting of the stop condition. writing 0 clears the bit and 1 can not be written. v iic (mhz) long time mode short time mode 4 16.4 4.1 2 32.8 8.2 1 65.6 16.4 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 259 of n rej09b0047-0060z 16.8 i 2 c0 start/stop condition control registers (s2d0 register) the i 2 c0 start/stop condition control register(address 02e5 16 ) controls the detection of the start/ stop condition. 16.8.1 bit0-bit4: start/stop condition setting bits (ssc0-ssc4) because the release time, the set up time and the hold time of the s cl are measured on the base of the i 2 c bus system clock(v iic ). the detecting condition changes depending on the oscillation frequency (x in ) and the i 2 c bus system clock select bits. it is necessary to set the appropriate value of start/stop condition setting bits (ssc4-ssc0) and set the release time, the set up time and the hold time by the system clock frequency. refer to table 16.10 start/stop condition detect conditions . do not set odd numbers or 00000 2 to start/stop condition setting bits. table 16.2 shows the recommended setting value to start/ stop condition setting bits (ssc4-ssc0) at each oscillation frequency under standard clock mode. the detection of the start/stop condition starts immediately after setting the es0 bit to "1". 16.8.2 bit5: s cl /s da interrupt pin polarity select bit (sip) the s cl /s da interrupt can be generated by detecting the rising edge or the falling edge of the s cl pin or the s da pin. the s cl /s da interrupt pin polarity select bit selects the polarity of the s cl pin or the s da pin for interrupt. 16.8.3 bit6 : s cl /s da interrupt pin select bit (sis) the s cl /s da interrupt pin select bit selects either the s cl pin or the s da pin as the s cl /s da interrupt enable pin. notes: the s cl /s da interrupt request may be set when the setting of the s cl /s da interrupt pin polarity se lect bit, s cl /s da interrupt pin select bit and i 2 c bus interface enable bit es0 are changed. when using the s cl /s da interrupt, write 0 to the s cl /s da interrupt request bit after setting the above bits, and enable the s cl /s da interrupt. 16.8.4 bit7: start/stop condition generation select bit (stspsel) the bit selects the length of the set up and the hold time when the start/stop condition is generated. the length of the set up and hold time is based on the i 2 c system clock cycles. refer to table 16.8 start/stop generation timing table . set the bit to 1 if the i 2 c bus system clock frequency is over 4mhz. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 260 of n rej09b0047-0060z 16.9 start condition generation method when the es0 bit of the i 2 c0 control register is 1 and the bb flag of the i 2 c0 status register is 0 , writing 1 to the mst, trx, and bb bits and 0 to the pin and low-order bits of the i 2 c0 status register (s10 register) simultaneously enters the standby status to generate the start condition. the start condition is generated after writing the slave address data to the i 2 c0 data shift register. after that, the bit counter becomes 000 2 and 1-byte s cl are output. the start condition generation timing is different in standard clock mode and high-speed clock mode. refer to figure 16.16 start condition generation timing dia- gram, and table 16.8 start/stop generation timing table . figure 16.14 start condition generation flow chart interrupt disable bb=0? s10=e0 16 s00=data interrupt enable no yes start condition standby status setting start condition trigger generation *data=slave address data m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 261 of n rej09b0047-0060z 16.11 stop condition generation method when the es0 bit in the i 2 c0 control register is 1 , writing 1 to the mst and the trx bits in the i 2 c0 status register, and 0 to the bb, pin and low-order 4 bits in the i 2 c0 status register simultaneously enters the standby status to generate the stop condition. the stop condition is generated after writing the dummy data to the i 2 c0 data shift register. the stop condition generation timing is different in standard clock mode and high-speed clock mode. refer to figure 16.17 stop condition generation timing diagram , and table 16.8 start/stop generation timing table . do not write data to the i 2 c0 status register and the i 2 c0 data shift register, before the bb flag becomes 0 after executing the instruction to generate the stop condition. otherwise, the stop condition waveform may not be operated normally. 16.10 start condition duplicate protect function it is necessary to verify that the bus is not in use via the bb flag before the start condition is generated. however,when the bb flag is set to 1 because a start condition is generated by another master devices immediately after the bb flag is verified, the start condition is suspended by the start condition duplicate protect function. when the function starts, it works as follows: ? the start condition standby setting is disabled. if the start condition standby has been set, release it and resets the mst and trx bits. ? writing to the i 2 c0 data shift register is disabled. (the start condition trigger generation is disabled) ? when the start condition generation is interrupted, sets the al flag. the start condition duplicate protect function is valid from the s da falling edge of the start condition to the slave receive completion. figure16.15 shows the duration of the start condition duplicate protect function. figure 16.15 the duration of the start condition duplicate protect function 1 clock 1 bit s cl s da bb flag 2 bit 3 bit 2 clock 3 clock 8 bit ack bit the duration of start condition duplicate protect 8 clock ack clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 262 of n rej09b0047-0060z the value of the data writing to status register function mst trx bb pin al aas as0 lrb 1 1 1 0 0 0 0 0 setting up the start condition stand by in master transmit mode 1 1 0 0 0 0 0 0 setting up the stop condition stand by in master transmit mode 0/1 0/1 - 0 1 1 1 1 setting up each communication mode (refer to chapter 16.5 i 2 c status register ) item start/stop condition generation standard clock mode high-speed clock mode select bit setup 0 5.0 s (20 cycles) 2.5 s (10 cycles) time 1 13.0 s (52 cycles) 6.5 s (26 cycles) hold 0 5.0 s (20 cycles) 2.5 s (10 cycles) time 1 13.0 s (52 cycles) 6.5 s (26 cycles) figure 16.16 start condition generation timing diagram figure 16.17 stop condition generation timing diagram table 16.8 start/stop generation timing table as mentioned above, writing 1 to mst and trx bits. writing 1 or 0 to the bb bit, writing 0 to the pin and low-order 4 bits, simultaneously set up the start or stop condition standby. it releases the s da in the start condition standby, sets the s da to l in the stop condition standby. the signal writing to data shift register triggers the generation of start/stop conditions. in the case of setting the mst, and the trx to 1 without generating a start/stop condi- tion. write 1 to the low-order 4 bits simultaneously. table16.9 shows the function of writing to the status register. note 1. actual time at the time of v iic = 4mhz, the contents in () denote cycle numbers. table 16.9 the function of writing to status register i 2 c0 data shift register write signal s cl s da aa aa hold time setup time i 2 c0 data shift register write signal s cl s da aa aa setup time aa aa hold time m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 263 of n rej09b0047-0060z 16.12 start/stop condition detect operation figure 16.18, figure 16.19 and table 16.10 show start/stop condition detect operations. the start/ stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the s cl and s da pins satisfied with three conditions: the s cl release time, the setup time, and the hold time (see table.16.10 start/stop condition detect conditions ). the bb flag is set to 1 by detecting the start condition and is set to 0 by detecting the stop condition. the bb flag set and reset timing are different in standard clock mode and high-speed clock mode. see table.16.10 start/ stop condition detect conditions . figure 16.18 start condition detection timing diagram figure 16.19 stop condition detection timing diagram standard clock mode high-speed clock mode s cl release time ssc value + 1 cycle (6.25 s) 4 cycles (1.0 s) setup time ssc value + 1 cycle < 4.0 s (3.25 s) 2 cycles (0.5 s) 2 hold time ssc value cycle < 4.0 s (3.0 s) 2 cycles (0.5 s) 2 bb flag set/reset ssc value - 1 +2 cycles (3.375 s) 3.5 cycles (0.875 s) time 2 table 16.10 start/stop detection timing table note 1. unit : cycle numbers of i 2 c system clock v iic the ssc value is the decimal notation value of the start/stop condition set bits ssc4 to ssc0. do not set 0 or odd numbers to the ssc value. the values in () are examples when the i 2 c0 start/stop condition control register is set to 18 16 at v iic = 4 mhz. bb flag aaa hold time s cl s cl release time setup time aa bb flag set time s da bb flag aaa hold time s cl s da s cl release time setup time aa bb flag reset time m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 264 of n rej09b0047-0060z 16.13 address data communication 16.13.1 example of master transmit an example of master transmit in standard clock mode, at the s cl frequency of 100 khz and in ack return mode is shown below. 1)set the slave address in the upper 7-bit of i 2 c0 address registers (s0d0). 2)set ack return mode and the scl = 100 khz by setting 00 16 in the i 2 c0 control register 1(s3d0), 000 2 in the ick4 to ick2 bits of the i 2 c0 control register 2(s4d0) and 85 16 in the i 2 c0 clock control register (s20) respectively. (f 1 =8mhz) 3)set 00 16 in the i 2 c0 status register (s10) so that transmit/receive mode is initialized. 4)set a communication enable status by setting 08 16 in the i 2 c0 control register 0 (s1d0). 5)confirm the bus free condition by the bb flag of the i 2 c0 status register (s10). 6)set e0 16 in the i 2 c0 status register (s10) to set the start condition standby. 7 )set the destination address data for transmit in high-order 7 bit in the i 2 c0 data shift register (s00) and set 0 in the least significant bit. and then a start condition is generated. at this time, s cl for 1 byte and an ack clock are automatically generated. 8)set transmit data in the i 2 c0 data shift register (s00). at this time, an s cl and an ack clock are automaticall generated. 9)when transmitting more than 1-byte control data, repeat step 7). 10)set c0 16 in the i 2 c0 status register (s10) to set a stop condition if ack is not returned from the slave receive side or the transmit end. 11)a stop condition is generated when writing the dummy data to the i 2 c0 data shift register (s00). figure 16.20 (1) shows the master transmit format. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 265 of n rej09b0047-0060z 16.13.2 example of slave receive an example of the slave receive in high-speed clock mode, at the s cl frequency of 400 khz, in ack return mode and using the addressing format is shown below. 1)set a slave address in the high-order 7 bits in the i 2 c0 address register (s0d0). 2)set ack clock mode and s cl = 400 khz by setting 00 16 in the i 2 c0 control register 1 (s3d0), 000 2 in the ick4 to ick2 bits in the i 2 c0 control register 2 (s4d0) and a5 16 in the i 2 c0 clock control register (s20) respectively. (f 1 =8mhz) 3)set 00 16 in the i 2 c0 status register (s10) so that transmit/receive mode is initialized. 4)set a communication enable status by setting 08 16 in the i 2 c0 control register 0 (s1d0). 5)when a start condition is received, an address comparison is performed. 6) ? when all transmitted addresses are 0 (general call): adr0 in the i 2 c0 status register (s10) is set to 1 and an i 2 c bus interface interrupt request signal is generated. ? when the transmitted addresses match with the address set in 2): ass in the i 2 c0 status register (s10) is set to 1 and an i 2 c bus interface interrupt request signal occurs. ? in the cases other than the above adr0 and aas of the i 2 c0 status register are set to 0 and no i 2 c bus interface interrupt request signal occurs. 7)set dummy data in the i 2 c0 data shift register (s00). 8)after receiving 1-byte data, an ack is automatically returned and an i 2 c bus interface interrupt request signal is generated. 9)after receiving 1-byte data, an i 2 c bus interface interrupt request signal is generated, set the ackbit to 1 or 0 by reading the contents in the data shift register (s00). and the ack bit is returned or not returned. 10)when receiving more than 1-byte control data, repeat step 7) 8) or 7) 9). 11)when a stop condition is detected, the communication ends. refer to figure 16.20 address data communication format, (2) . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 266 of n rej09b0047-0060z figure 16.20 address data communication format s slave address r/w a data a a/a p 7 bits 0 1 - 8 bits s r/w a a a p 1 (1) a master transmit device transmits data to a receive device (2) a master receive device receives data from a transmit device data data data slave address 1 - 8 bits 7 bits 1 - 8 bits 1 - 8 bits s: start condition p : stop condition a: ack bit r/w : read/write bit m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 267 of n rej09b0047-0060z 16.14 usage precautions (1) a ccess to the registers of i 2 c bus interface circuit the precaution of read/write to the control registers of i 2 c bus interface circuit is as follows. ? i 2 c0 data shift register (s00 : 02e0 16 ) do not write the register during the data transfer. the transfer bit counter is reset and the data may not be transfered normally. ? i 2 c0 control register 0 (s1d0 : address 02e3 16 ). after the start condition detection or the 1-byte transfer completion, the bit counter (bits bc2 to bc0) is reset by hardware. do not read/write the register at this time, because the data may be undetermined. figure 16.22 and figure 16.23 show the bit counter reset timing by hardware. ? i 2 c0 clock control register (s20 : address 02e4 16 ) do not write to this register except the ackbit during the transfer. the i 2 c clock generator is reset and the data may not be transfered normally. ? i 2 c0 control register 1 (s3d0 : address 02e6 16 ) write i 2 c system clock select bits when i 2 c bus interface enable bit (es0)is disabled. when the data receive completion interrupt enable bit (wit) reads out, the internal wait flag is read.do not use the bit managing instrustion (read-modify-write instruction) to access the register. ? i 2 c0 status register (s10 : address 02e8 16 ) do not use the bit managing instruction (read-modify-write instruction) to access the register be cause all bits of this register are changed by h/w. do not read/write during the timing when the mst and the trx bits for the communication mode setting are changed. the data may be undetermined. figure16.21 to figure 16.23 show the timing when the mst and the trx bits are changed by h/w. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 268 of n rej09b0047-0060z figure 16.21 the bit reset timing (the stop condition detection) figure 16.22 the bit reset timing (the start condition detection) bb flag s cl bit reset signal aaaa mst trx aaa aaa 1.5v iic cycle s da related bits bb flag s cl bit reset signal aaaaa bc0 - bc2 trx(slave mode) s da related bits figure 16.23 bit set/reset timing ( at the completion of data transfer) s cl bit set signal aaa 1v iic c y cle pin bit aa 2v iic cycle bit reset signal aaaaa aaaaa bc0 - bc2 mst(when in arbitration lost) trx(when in nack receive in slave transmit mode) the bits referring to reset aaaaa aaaaa trx(als=0 meanwhile the slave receive r/w bit = 1 the bits referring to set m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 16. multi-master i 2 c bus interface rev.0.60 2004.02.01 page 269 of n rej09b0047-0060z (2) generation of restart condition after 1-byte data transfer and a restart condition is generated, write e0 16 to i 2 c0 status register, set the start condition standby and the s da pin will be released. writing to the i 2 c0 data shift register gener- ates the start condition trigger after waiting in software until the s da becomes h . figure 16.24 shows the restart condition generation timing. figure 16.24 the time of generation of restart condition 8 clock ack clock s cl s da s1i writing signal ( start condition setting standby) insert software wait s0i writing signal (start condition trigger generation) (3) iimitation of cpu clock the registers of i 2 c bus interface circuit can not be read from or written to if the cpu clock is selected to the sub clock (x cin , x cout ) by the system clock select bit (system clock control register 0, address 0006h, cm07 bit). select the main clock (x in , x out ) or the ring oscillator clock in read/write. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 270 of n rej09b0047-0060z 17. programmable i/o ports the programmable input/output ports (hereafter referred to simply as i/o ports ) consist of 71 lines p0, p1,p2, p3, p6, p7, p8, p9, p10 (except p9 4 ) for the 80-pin version, or 55 lines p0 0 to p0 3 , p1 5 to p1 7 , p2, p3 0 to p3 3 , p6, p7, p8, p9 0 to p9 3 , p10 for the 64-pin version. each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high in sets of 4 lines. figures 17.1 to 17.5 show the i/o ports. figure 17.6 shows the i/o pins. each pin functions as an i/o port, a peripheral function input/output. for details on how to set peripheral functions, refer to each functional description in this manual. if any pin is used as a peripheral function input, set the direction bit for that pin to 0 (input mode). any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 17.1 port pi direction register (pdi register, i = 0 to 3, 6 to 10) figure 17.1.1 shows the direction registers. this register selects whether the i/o port is to be used for input or output. the bits in this register corre- spond one for one to each port. 17.2 port pi register (pi register, i = 0 to 3, 6 to 10) figure 17.2.1 shows the pi registers. data input/output to and from external devices are accomplished by reading and writing to the pi register. the pi register consists of a port latch to hold the output data and a circuit to read the pin status. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. the bits in the pi register correspond one for one to each port. 17.3 pull-up control register 0 to pull-up control register 2 (pur0 to pur2 regis- ters) figure 17.3.1 shows the pur0 to pur2 registers. the pur0 to pur2 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. the port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. 17.4 port control register figure 17.4.1 shows the port control register. when the p1 register is read after setting the pcr register s pcr0 bit to 1 , the corresponding port latch can be read no matter how the pd1 register is set. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 271 of n rej09b0047-0060z 17.5 pin assignment control register (pacr) figure 17.5.1 shows the pacr. after reset set pacr2 to pacr0 bit in the pacr register before you input and output to each pin. when the pacr register isn t set up, the input and output function of some of the pins doesn t work. pacr2 to pacr0 : control the number of pins enabled for use. at reset these bits equal 000 2 . when using the 80 pin version of the m16c/28 set these bits to 011 2 . when using the 64 pin version of the m16c/28 set these bits to 010 2 . u1map : controls the assignment of uart1 pins. if u1map = 0 (default at reset) the uart1 functions are assigned to p6 4 /cts 1 /rts 1 , p6 5 /clk 1 , p6 6 /rxd 1 , and p6 7 /txd 1 . if u1map = 1 the uart1 functions are assigned to p7 0 /cts 1 /rts 1 , p7 1 /clk 1 , p7 2 /rxd 1 , and p7 3 /txd 1 . pacr is write protected by prc2 bit of prcr (protect register). prc2 bit of prcr must be set immedi- ately before the write to pacr. 17.6 digital debounce function two digital debounce function circuits are provided. level is determined when level is held, after applying either a falling edge or rising edge to the pin, longer than the programmed filter width time. this enables noise reduction. ________ _______ _____ this function is assigned to int5/inpc17 and nmi/sd. digital filter width is set in the nddr register and the p17ddr register respectively.figure 17.6.1 shows the nddr register and the p17ddr register. additionally, a digital debounce function is disabled to the port p1 7 input and the port p8 5 input. filter width : f8 1 / (n+1) n: count value set in the nddr register and p17ddr register the nddr register and the p17ddr register decrement count value with f8 as the count source. the nddr register and the p17ddr register indicate count time. count value is reloaded if a falling edge or a rising edge is applied to the pin. the nddr register and the p17ddr register can be set 00 16 to ff 16 when using the digital debounce function. setting to ff 16 disables the digital filter. see figure 17.6.2 for details. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 272 of n rej09b0047-0060z figure 17.1. i/o ports (1) p1 0 to p1 3 p1 5 to p1 6 p2 2 to p2 7 , p3 0 , p6 0 , p6 1 , p6 4 , p6 5 , p7 3 , p7 5 , p8 1 p0 0 to p0 7 , p9 3 p3 0 to p3 7 (inside dotted-line included) (inside dotted-line not included) data bus data bus (note 1) analog input pull-up selection direction register port latch note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. p1 4 (inside dotted-line not included) (inside dotted-line included) p1 7 (inside dotted-line not included) (inside dotted-line included) p3 2 , p7 4 , p7 6 , p8 0 (inside dotted-line not included) (inside dotted-line included) data bus direction register port latch pull-up selection (note 1) port p1 control register analog input direction register port latch pull-up selection (note 1) port p1 control register input to respective peripheral functions digital debounce inpc1 7 /int5 "1" output data bus direction register port latch pull-up selection (note 1) input to respective peripheral functions m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 273 of n rej09b0047-0060z figure 17.2. i/o ports (2) p8 2 to p8 4 (note 1) p3 1 , p7 7 , p9 0 to p9 2 data bus pull-up selection direction register port latch data bus pull-up selection direction register port latch input to respective peripheral functions input to respective peripheral functions (note 1) p2 0 , p2 1 , p7 1 , p7 2 "1" output data bus direction register port latch pull-up selection (note 1) input to respective peripheral functions note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. switching between cmos and nch m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 274 of n rej09b0047-0060z figure 17.3. i/o ports (3) p6 2 , p6 6 data bus pull-up selection direction register port latch input to respective peripheral functions (note 1) p8 5 p6 3 , p6 7 output 1 data bus pull-up selection direction register port latch (note 1) switching between cmos and nch note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. switching between cmos and nch data bus pull-up selection direction register port latch nmi interrupt input nmi enable digital debounce nmi enable sd (note 1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 275 of n rej09b0047-0060z figure 17.4. i/o ports (4) data bus direction register pull-up selection port latch analog input input to respective peripheral functions p10 0 to p10 3 (inside dotted-line not included) p9 7 , p10 4 to p10 7 (inside dotted-line included) (note 1) note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. p9 5 , p9 6 1 output direction register data bus port latch analog input pull-up selection (note 1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 276 of n rej09b0047-0060z figure 17.6. i/o pins figure 17.5. i/o ports (5) cnv ss cnv ss signal input reset reset signal input (note 1) (note 1) note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch direction register pull-up selection port latch data bus (note) (note) note: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 277 of n rej09b0047-0060z figure 17.1.1. pd0, pd1, pd2, pd3, pd6, pd7, pd8, pd9, and pd10 registers port pi direction register (i=0 to 3, 6 to 8, and 10) (note) symbol address after reset pd0 to pd3 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 00 16 pd6 to pd8 03ee 16 , 03ef 16 , 03f2 16 00 16 pd10 03f6 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction bit pdi_1 port pi 1 direction bit pdi_2 port pi 2 direction bit pdi_3 port pi 3 direction bit pdi_4 port pi 4 direction bit pdi_5 port pi 5 direction bit pdi_6 port pi 6 direction bit pdi_7 port pi 7 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 3, 6 to 8, and 10) port p9 direction register (note 1,2) symbol address after reset pd9 03f3 16 00000000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pd9_0 port p9 0 direction bit pd9_1 port p9 1 direction bit pd9_2 port p9 2 direction bit pd9_3 port p9 3 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note: ports must be enabled using the pacr in 80 pin version set pacr2, pacr1, pacr0 to "011 2 " in 64 pin version set pacr2, pacr1, pacr0 to "010 2 " rw rw rw rw rw rw rw rw rw rw rw rw rw pd9_5 port p9 5 direction bit rw pd9_6 port p9 6 direction bit rw pd9_7 port p9 7 direction bit rw nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (b4) note 1: make sure the pd9 register is written to by the next instruction after setting the prcr register's prc2 bit to "1"(write enabled). note 2: ports must be enabled using the pacr in 80 pin version set pacr2, pacr1, pacr0 to "011 2 " in 64 pin version set pacr2, pacr1, pacr0 to "010 2 " m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 278 of n rej09b0047-0060z port pi register (i=0 to 3, 6 to 8 and 10) (note) symbol address after reset p0 to p3 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 indeterminate p6 to p8 03ec 16 , 03ed 16 , 03f0 16 indeterminate p10 03f4 16 indeterminate bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 bit pi_1 port pi 1 bit pi_2 port pi 2 bit pi_3 port pi 3 bit pi_4 port pi 4 bit pi_5 port pi 5 bit pi_6 port pi 6 bit pi_7 port pi 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level (note 1) (i = 0 to 3, 6 to 8 and 10) port p9 register (note1) symbol address after reset p9 03f1 16 indeterminate bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 p9_0 port p9 0 bit p9_1 port p9 1 bit p9_2 port p9 2 bit p9_3 port p9 3 bit (b4) nothing is assigned (note 2) p9_5 port p9 5 bit p9_6 port p9 6 bit p9_7 port p9 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for p8 5 ) 0 : l level 1 : h level rw rw rw rw rw rw rw rw rw rw rw rw - rw rw rw rw note: ports must be enabled using the pacr in 80 pin version set pacr2, pacr1, pacr0 to "011 2 " in 64 pin version set pacr2, pacr1, pacr0 to "010 2 " note1: ports must be enabled using the pacr in 80 pin version set pacr2, pacr1, pacr0 to "011 2 " in 64 pin version set pacr2, pacr1, pacr0 to "010 2 " note2: nothing is assigned. in an attempt to write t o this bit, write "0". the value if read turns out to be "0". figure 17.2.1. p0, p1, p2, p3, p6, p7, p8, p9, and p10 registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 279 of n rej09b0047-0060z pull-up control register 0 (note) symbol address after reset pur0 03fc 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up 0 : not pulled high 1 : pulled high (note) pull-up control register 1 symbol address after reset(note 5) pur1 03fd 16 00000000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up pu17 p7 4 to p7 7 pull-up 0 : not pulled high 1 : pulled high (note) note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. rw rw rw rw rw rw rw rw rw rw rw rw rw note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. pull-up control register 2 symbol address after reset pur2 03fe 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up pu22 p9 0 to p9 3 pull-up pu23 p9 5 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . 0 : not pulled high 1 : pulled high (note) rw rw rw rw rw rw rw (b7-b6) note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . (b3-b0) figure 17.3.1. pur0 to pur2 registers m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 280 of n rej09b0047-0060z figure 17.4.1. pcr register port control register symbpl address after reset pcr 03ff 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control bit nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . rw (b7-b1) operation performed when the p1 register is read 0: when the port is set for input, the input levels of p10 to p17 pins are read. when set for output, the port latch is read. 1: the port latch is read regardless of whether the port is set for input or output. figure 17.5.1. pacr register pin assignment control register (note) symbpl address after reset pacr 025d 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pin enabling bit nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . rw (b6-b3) 010 : 64 pin 011 : 80 pin all other values are reserved. do not use. pacr0 pacr1 pacr2 rw rw reserved bits u1map uart1 pin remapping bit uart1 pins assigned to 0 : p6 7 to p6 4 1 : p7 3 to p7 0 rw note : set bit 2 of protect register (address 000a 16 ) to "1" before writing to pacr. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 281 of n rej09b0047-0060z figure 17.6.1. nddr and p17ddr registers nmi digital debounce register (note) symbol address after reset nddr 033e 16 ff 16 rw b7 b0 function rw note : set bit 2 of protect register (address 000a 16 ) to "1" before writing to nddr. setting range 00 16 ~ff 16 assuming that set value =n, for n = 0 to feh, nmi / sd pulse whose width is greater than (v1/8) / ( n + 1) will be input. for n = ffh, the digital debounce filter is disabled. all signals are input p1 7 digital debounce register symbol address after reset p17ddr 033f 16 ff 16 rw b7 b0 function rw setting range 00 16 ~ff 16 assuming that set value =n, for n = 0 to feh, inpc17 / int5 pulse whose width is greater than (v1/8) / ( n + 1) will be input. for n = ffh, the digital debounce filter is disabled. all signals are input m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 282 of n rej09b0047-0060z figure 17.6.2. functioning of digital debounce filter f 8 p8 5 / p1 7 data bus 1. (condition after reset). reload = ff, port in = signal out continuosly. 2. reload = 03. at edge of port in != signal out, counter gets reload value and stats counting down. 3. port in = signal out, counting stops. 4. at edge of port in != signal out, counter gets reload value and starts counting. 5. counter underflows, stops, and port in is driven to signal out. 6. at edge of port in != signal out, counter gets reload value and starts counting. 7. counter underflows, stops, and port in is driven to signal out. 8. at edge of port in != signal out, counter gets reload value and starts counting. 9. ff is written to reload value. counter is stopped and loaded with ff. port in = signal out continuously. clock port in reload value (write) digital debounce filter signal out count value (read) to nmi and sd / int5 and inpc17 data bus f 8 reload value port in signal out count value reload value (continued) port in (continued) signal out (continued) count value (continued) ff 03 ff 03 02 01 03 02 01 00 ff 03 ff 03 02 01 00 ff ff 03 02 ff 1 2 3 4 5 6 7 8 9 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 17. programmable i/o ports rev.0.60 2004.02.01 page 283 of n rej09b0047-0060z pin name connection ports p0 to p3, p6 to p10 x out (note 3) av ss , v ref av cc after setting for input mode, connect every pin to v ss via a resistor(pull-down); or after setting for output mode, leave these pins open. (note 1, note 2, note 4) open connect to v cc connect to v ss note 1: when setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. for this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. futhermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the directionregisters be periodically reset in software, for the increased reliability of the program. note 2: make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). note 3: with external clock or v cc input to x in pin. note 4: when using the 80pin version, set pacr2, pacr1, pacr0 to "011 2 ". when using the 64pin version, set pacr2, pacr1, pacr0 to "010 2 ". connect via resistor to v cc (pull-up) xin table 17.1. unassigned pin handling in single-chip mode figure 17.7. unassigned pins handling (input mode) (input mode) (output mode) x out av cc av ss v ref microcomputer v cc v ss in single-chip mode open open note : when using the 64pin version, set pacr2, pacr1, pacr0 to "010 2 ". (note) port p0 to p3, p6 to p10 x in m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 284 of n rej09b0047-0060z 18. electrical characteristics 18.1. normal version table 18.1. absolute maximum ratings o p e r a t i n g a m b i e n t t e m p e r a t u r e p a r a m e t e ru n i t i n p u t v o l t a g e a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e o u t p u t v o l t a g e v o -0.3 to v cc +0.3 -0.3 to v cc +0.3 p d p o w e r d i s s i p a t i o n s t o r a g e t e m p e r a t u r e rated value v v v condition v i a v c c v c c t s t g t o p r s y m b o l m w v p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , v r e f , r e s e t , c n v s s v cc =av cc v cc =av cc -0.3 to 6.5 -0.3 to 6.5 - 6 5 t o 1 5 0 3 0 0 - 2 0 t o 8 5 / - 4 0 t o 8 5 c t o p r = 2 5 c c p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x o u t m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 285 of n rej09b0047-0060z table 18.2. recommended operating conditions (note 1) 2.7 5 . 5 typ. m a x . u n i t p a r a m e t e r v c c s u p p l y v o l t a g e s y m b o l m i n . s t a n d a r d a n a l o g s u p p l y v o l t a g e v c c a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h i o h ( a v g ) h i g h a v e r a g e o u t p u t c u r r e n t m a m a v s s a v s s 0.7v cc v v v v c c 0 . 3 v c c 0 l o w i n p u t v o l t a g e i o h ( p e a k ) h i g h p e a k o u t p u t c u r r e n t h i g h i n p u t v o l t a g e - 5 . 0 - 1 0 . 0 l o w p e a k o u t p u t c u r r e n t 10.0 5.0 m a f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y ( n o t e 4 ) l o w a v e r a g e o u t p u t c u r r e n t i o l ( p e a k ) ma i ol (avg) v v i l 3 3 x v c c - 8 0 v cc =3.0 to 5.5v v cc =2.7 to 3.0v 0 0 mhz mhz 20 f ( x c i n )s u b - c l o c k o s c i l l a t i o n f r e q u e n c y khz 50 32.768 note 1: referenced to v cc = 2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: the mean output current is the mean value within 100ms. note 3: the total i ol(peak) for all ports must be 80ma max. the total i oh(peak) for all ports must be -80ma max. note 4: relationship between main clock oscillation frequency, pll clock oscillation frequency and supply voltage. f 1 ( r o c )r i n g o s c i l l a t i o n f r e q u e n c y 1 mhz 1 f ( p l l )p l l c l o c k o s c i l l a t i o n f r e q u e n c y ( n o t e 4 ) v cc =3.0 to 5.5v v cc =2.7 to 3.0v 10 10 mhz mhz 33 x v cc -80 f (bclk) cpu operation clock 0 mhz 2 0 t s u ( p l l )p l l f r e q u e n c y s y n t h e s i z e r s t a b i l i z a t i o n w a i t t i m e v cc =5.0v v cc =3.0v 50 20 ms ms p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 f 2 (roc) ring oscillation frequency 2 f 3 ( r o c )r i n g o s c i l l a t i o n f r e q u e n c y 3 mhz 2 mhz 16 20 main clock input oscillation frequency 20.0 0.0 f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa 33.3 x v cc -80mh z pll clock oscillation frequency 20.0 0.0 f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 5.5 10.0 2.7 aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa 3.0 33.3 x v cc -80mh z m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 286 of n rej09b0047-0060z table 18.3. a-d conversion characteristics (note 1) standard min. t y p .m a x . C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r b i t s v ref =v cc 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t l s b 3 l s b v ref =v cc =3.3v an 0 to an 7 input 8 b i t 2 r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e ( 1 0 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e reference voltage analog input voltage k ? s v v i a v r e f v 0 2 . 0 10 v c c v ref 40 3 . 3 conversion time(8bit), s a m p l e & h o l d f u n c t i o n a v a i l a b l e s 2.8 t c o n v t s a m p s a m p l i n g t i m e0 . 3 s v ref =v cc v ref =v cc =5v, ? ad =10mhz v ref =v cc =5v, ? ad =10mhz dnl d i f f e r e n t i a l n o n - l i n e a r i t y e r r o r o f f s e t e r r o r g a i n e r r o r C C l s b l s b l s b 1 3 3 note 1: referenced to v cc =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: ad operation clock frequency ( ? ad frequency) must be 10 mhz or less. and divide the f ad if v cc is less than 4.2v, and make ? ad frequency equal to or lower than f ad /2. note 3: a case without sample & hold function turn ? ad frequency into 250 khz or more in addition to a limit of note 2. a case with sample & hold function turn ? ad frequency into 1mhz or more in addition to a limit of note 2. 1 0 b i t l s b 5 l s b 3 l s b v ref =v cc =3.3v an 0 to an 7 input 8 b i t 2 l s b 5 C a b s o l u t e a c c u r a c y v ref =v cc =3.3v v ref =v cc =5v a n 0 t o a n 7 i n p u t a n 0 0 t o a n 07 , a n 20 t o a n 27 i n p u t a n 0 t o an 7 input a n 0 0 t o a n 07 , a n 20 t o a n 27 i n p u t l s b 7 l s b 7 1 0 b i t v ref =v cc =3.3v v ref =v cc =5v a n 0 t o an 7 input a n 0 0 t o an 07 , an 20 t o an 27 input a n 0 t o an 7 input a n 0 0 t o a n 07 , a n 20 t o a n 27 i n p u t l s b 7 l s b 7 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 287 of n rej09b0047-0060z table 18.4. flash memory version electrical characteristics (note 1) note 1: when not otherwise specified, vcc = 2.7 to5.5v; topr = 0 to 60 c. note 2: vcc = 5v; topr = 25 c. note 3: definition of e/w cycle: each block may be written to a variable number of times - up to a maximum of the total number of distinct word addresses - for every block erase. performing multiple writes to the same address before an erase operation is prohibited. note 4: maximum number of e/w cycles for which opration is guaranteed. note 5: topr = 55 c. note 6: when not otherwise specified, vcc = 2.7 to 5.5v; topr = -20 to 85 c / -40 to 85 c (option). note 7: table18.5 applies for block a or b e/w cycles > 1000. otherwise, use table 18.4. note 8: to reduce the number of e/w cycles, a block erase should ideally be performed after writing as many different word addresses (only one time each) as possible. it is important to track the total number of block erases. note 9: should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. note 10: when block a or b e/w cycles exceed 100 (option), select one wait state per block access. when fmr17 is set to "1", one wait state is inserted per access to block a or b - regardless of the value of pm17. wait state insertion durin g access to all other blocks, as well as to internal ram, is controlled b y pm17 - re g ardless of the settin g of word program time (vcc=5.0v, topr=25 c) block erase time 75 0.2 600 9 s s parameter standard min. typ. (note 2) max unit symbol C C 0.4 9 s 0.7 9s 1.2 9s 2kbyte block 8kbyte block 16kbyte block 32kbyte block C erase/write cycle (note 3) 100(note 4) cycle td(sr-es) C time delay from suspend request until erase suspend data retention time (note 5) ms year 20 20 word program time (vcc=5.0v, topr=25 c) block erase time(vcc=5.0v, topr=25 c) 100 s parameter standard min. typ. (note 2) max unit symbol C C 0.3 9 s (2kbyte block) C erase/write cycle (note 3, 8, 9) 10000 (note 4,10) cycle td(sr-es) time delay from suspend request until erase suspend ms 20 table 18.5. flash memory version electrical characteristics (note 6) 10000 e/w cycle products (option) [blocka and block b(note 7)] erase suspend request (interrupt request) fmr46 td(sr-es) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 288 of n rej09b0047-0060z table 18.6. low voltage detection circuit electrical characteristics (note 1, note 3 ) table 18.7. power supply circuit timing characteristics symbol standard typ. unit measuring condition min. max. parameter vdet4 voltage down detection voltage (note 1) v v cc =0.8 to 5.5v note 1: vdet4 > vdet3 note 2: vdet3s is the min voltage at which "hardware reset 2" is maintained. note 3: the low voltage detection circuit is designed to use when v cc is set to 5v. t.b.d vdet3 reset level detection voltage (notes 1) v v symbol standard typ. unit measuring condition min. max. parameter 2 v cc =2.7 to 5.5v note 1: when v cc = 5v note 2: this is the time between interrupt for (stop/wait) mode release and resumption of cpu clock operation. note 3: after enabling low voltage detection, this time is required before proper detection can occur. 2 6 (note 1) 50 td(r-s) stop release time (note 2) 20 td(m-l) time for internal power supply stabilization when main clock oscillation starts 20 td(s-r) hardware reset 2 release wait time s ms vdet3s low voltage reset retention voltage (note 2) vdet3r low voltage reset release voltage v td(p-r) time for internal power supply stabilization during powering-on td(e-a) low voltage detection circuit operation start time (note 3) ms s ms v cc =2.7 to 5.5v v cc =vdet3r to 5.5v td(w-s) low power dissipation mode wait mode release time (note 2) 150 s t.b.d t.b.d td(roc) time for internal ring oscillator stabilization during powering-on ms t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d interrupt for stop mode release cpu clock td(r-s) td(s-r) vdet3r v cc cpu clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 289 of n rej09b0047-0060z table 18.8. electrical characteristics (note 1 ) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l low output voltage l o w o u t p u t v o l t a g e v o l v o l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v v v x o u t v 2 . 0 0 . 4 5v v x o u t 2 . 0 2 . 0 m i n .m a x . p a r a m e t e r i o h = - 1 m a i o h = - 0 . 5 m a i o l = 1 m a i o l = 0 . 5 m a highpower lowpower highpower lowpower highpower lowpower h i g h o u t p u t v o l t a g e x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2 . 5 1 . 6 v h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h low input current i i l v r a m r a m r e t e n t i o n v o l t a g e v t + - v t - v t + - v t - c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , 0.2 1 . 0v 0.2 2.5 v 5 . 0 a a a t s t o p m o d e2.0v reset t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , a d t r g , c t s 0 t o c t s 2 , s c l , s d a , v i = 5 v v i = 0 v - 5 . 0 r f x i n r fxcin f e e d b a c k r e s i s t a n c ex i n feedback resistance x cin 15 1 . 5m ? m ? p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7, x in , reset, cnvss p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7, x in , reset, cnvss r pullup p u l l - u p r e s i s t a n c e 5 0k ? i n t 0 t o i n t 5 , n m i , v x c o u t 0 0 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d h i g h p o w e r l o w p o w e r v i =0v 3 0 170 k i 0 t o k i 3 , r x d 0 t o r x d 2 , s i n 3 , s i n 4 v c c - 2 . 0 v c c - 2 . 0 note 1: referenced to v cc =4.2 to 5.5v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=20mhz unless otherwise specified. i o h = - 5 m a i o h = - 2 0 0 a v c c - 2 . 0 v c c - 0 . 3 v c c v c c v c c v c c i o l = 5 m a i o l = 2 0 0 a l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 v cc = 5v m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 290 of n rej09b0047-0060z v cc = 5v table 18.9. electrical characteristics (2) (note 1 ) symbol standard typ. unit measuring condition min. max. parameter i cc power supply current (v cc =3.0 to 5.5v) the output pins are open and other pins are v ss no division ma 16 f(x in )=20mhz, flash memory ma flash memory program v cc =5.0v f(bclk)=10mhz, ma flash memory erase v cc =5.0v f(bclk)=10mhz, t opr =25 c 3a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high a 0.8 a flash memory note 1: referenced to v cc =3.0 to 5.5v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(x in )=20mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit of vcr2 register idet3: vc26 bit of vcr2 register i det 2: v c 2 5 b i t o f v c r2 r eg i ste r ma wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a flash memory ring oscillation, f(bclk)=32khz, wait mode(note 2), oscillation capacity low idet4 voltage down detection dissipation current (note 4) a idet3 reset area detection dissipation current (note 4) a idet2 ram retention limit detection dissipation current (note 4) a no division, ring oscillation 19 1 t.b.d t.b.d 25 500 t.b.d 12 t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 291 of n rej09b0047-0060z v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.10. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 20 20 9 9 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 292 of n rej09b0047-0060z v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.12. timer a input (gating input in timer mode) table 18.13. timer a input (external trigger input in one-shot timer mode) table 18.14. timer a input (external trigger input in pulse width modulation mode) table 18.15. timer a input (counter increment/decrement input in event counter mode) table 18.11. timer a input (counter input in event counter mode) table 18.16. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 293 of n rej09b0047-0060z timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.17. timer b input (counter input in event counter mode) table 18.18. timer b input (pulse period measurement mode) table 18.19. timer b input (pulse width measurement mode) table 18.20. a-d trigger input table 18.21. serial i/o _______ table 18.22. external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 294 of n rej09b0047-0060z table 18.23. multi-master i 2 c-bus line v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 295 of n rej09b0047-0060z v cc = 5v tai in input tai out input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) figure 18.1. timing diagram (1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 296 of n rej09b0047-0060z v cc = 5v figure 18.2. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda figure 18.3. timing diagram (3) v cc = 5v m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 297 of n rej09b0047-0060z v cc = 3v table 18.24. electrical characteristics ( note 1) s y m b o l v o h high output voltage v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e standard t y p . unit measuring condition v v x out v v x o u t 0 . 5 0 . 5 min. m a x . v c c - 0 . 5 p a r a m e t e r i oh = - 1ma i oh = - 0.1ma i oh = - 50a i ol =1ma i ol =0.1ma i ol =50a highpower lowpower highpower lowpower highpower lowpower x cout with no load applied with no load applied 2 . 5 1 . 6 v h y s t e r e s i s h y s t e r e s i s high input current i ih l o w i n p u t c u r r e n t i i l v r a m ram retention voltage v t + - v t - v t + - v t - 0 . 20 . 8v 0 . 21 . 8v 4 . 0 a a at stop mode 2.0 v r e s e t x i n , r e s e t , c n v s s v i =3v v i =0v - 4 . 0 r f x i n r fxcin f e e d b a c k r e s i s t a n c ex i n feedback resistance x cin 25 3 . 0m ? m ? r p u l l u p pull-up resistance 100 k ? v x c o u t 0 0 with no load applied with no load applied highpower lowpower v i =0v 50 500 c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , a d t r g , c t s 0 t o c t s 2 , s c l , s d a , i n t 0 t o i n t 5 , n m i , k i 0 t o k i 3 , r x d 0 t o r x d 2 , s i n 3 , s i n 4 x i n , r e s e t , c n v s s v c c - 0 . 5 v c c - 0 . 5 n o t e 1 : r e f e r e n c e d t o v c c = 2 . 7 t o 3 . 3 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . v c c v c c v c c 0.5 0 . 7 high output voltage low output voltage low output voltage p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 298 of n rej09b0047-0060z table 18.25. electrical characteristics (2) ( note 1) v cc = 3v symbol standard typ. unit measuring condition min. max. parameter the output pins are open and other pins are v ss no division ma f(bclk)=10mhz, t.b.d flash memory i cc power supply current (v cc =2.7 to 3.6v) t opr =25 c t.b.d a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high a 0.7 a flash memory note 1: referenced to v cc =2.7 to 3.3v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=10mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit of vcr2 register idet3: vc26 bit of vcr2 register idet2: vc25 bit o f vcr2 register wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz, a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a flash memory ring oscillation, f(bclk)=32khz, wait mode (note 2), oscillation capacity low idet4 voltage down detection dissipation current (note 4) a t.b.d idet3 reset level detection dissipation current (note 4) a idet2 ram retention limit detection dissipation current (note 4) a 8 vcc=3.0v ma flash memory f(bclk)=10mhz, program vcc=3.0v ma flash memory f(bclk)=10mhz, erase t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 299 of n rej09b0047-0060z v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.26. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 300 of n rej09b0047-0060z v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.27. timer a input (counter input in event counter mode) table 18.28. timer a input (gating input in timer mode) table 18.29. timer a input (external trigger input in one-shot timer mode) table 18.30. timer a input (external trigger input in pulse width modulation mode) table 18.31. timer a input (counter increment/decrement input in event counter mode) table 18.32. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 301 of n rej09b0047-0060z v cc = 3v table 18.33. timer b input (counter input in event counter mode) table 18.34. timer b input (pulse period measurement mode) table 18.35. timer b input (pulse width measurement mode) table 18.36. a-d trigger input table 18.37. serial i/o _______ table 18.38. external interrupt inti input timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 50 90 160 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 302 of n rej09b0047-0060z v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.39. multi-master i 2 c-bus line high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 303 of n rej09b0047-0060z v cc = 3v figure 18.4. timing diagram (1) tai in input tai out input during event counter mode tbi in input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (normal-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 304 of n rej09b0047-0060z v cc = 3v figure 18.5. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda figure 18.6. timing diagram (3) v cc = 3v m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 305 of n rej09b0047-0060z 18.2. t version table 18.40. absolute maximum ratings o p e r a t i n g a m b i e n t t e m p e r a t u r e p a r a m e t e ru n i t i n p u t v o l t a g e a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e output voltage v o -0.3 to v cc +0.3 -0.3 to v cc +0.3 p d p o w e r d i s s i p a t i o n storage temperature rated value v v v condition v i a v c c v c c t stg t o p r s y m b o l m w v p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , v r e f , r e s e t , c n v s s v cc =av cc v cc =av cc -0.3 to 6.5 -0.3 to 6.5 -65 to 150 3 0 0 -40 to 85 c t o p r = 2 5 c c p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x o u t m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 306 of n rej09b0047-0060z table 18.41. recommended operating conditions (note 1) 3.0 5 . 5 typ. m a x . unit p a r a m e t e r v cc s u p p l y v o l t a g e s y m b o l m i n . standard a n a l o g s u p p l y v o l t a g e v c c avcc v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v ih i o h ( a v g ) h i g h a v e r a g e o u t p u t c u r r e n t m a m a vss avss 0.7v cc v v v v c c 0 . 3 v c c 0 l o w i n p u t v o l t a g e i o h ( p e a k ) h i g h p e a k o u t p u t c u r r e n t h i g h i n p u t v o l t a g e - 5 . 0 - 1 0 . 0 l o w p e a k o u t p u t c u r r e n t 10.0 5.0 m a f (x in ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y ( n o t e 3 ) l o w a v e r a g e o u t p u t c u r r e n t i o l ( p e a k ) ma i o l ( a v g ) v v il 0 m h z 20 f (x cin ) sub-clock oscillation frequency k h z 50 3 2 . 7 6 8 n o t e 1 : r e f e r e n c e d t o v c c = 3 . 0 t o 5 . 5 v a t t o p r = - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : t h e m e a n o u t p u t c u r r e n t i s t h e m e a n v a l u e w i t h i n 1 0 0 m s . n o t e 3 : r e l a t i o n s h i p b e t w e e n m a i n c l o c k o s c i l l a t i o n f r e q u e n c y , p l l c l o c k o s c i l l a t i o n f r e q u e n c y a n d s u p p l y v o l t a g e . n o t e 4 : t h e t o t a l i o l ( p e a k ) f o r a l l p o r t s m u s t b e 8 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r a l l p o r t s m u s t b e - 8 0 m a m a x . f 1 (roc) ring oscillation frequency 1 m h z 1 f ( p l l )p l l c l o c k o s c i l l a t i o n f r e q u e n c y ( n o t e 3 ) 10 mhz 20 f ( b c l k )c p u o p e r a t i o n c l o c k 0 m h z 20 t su (pll) pll frequency synthesizer stabilization wait time v c c = 5 . 0 v v cc =3.0v 50 20 m s ms p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 , x in , reset, cnv ss p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 , x in , reset, cnv ss p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 f 2 ( r o c )r i n g o s c i l l a t i o n f r e q u e n c y 2 f 3 ( r o c )r i n g o s c i l l a t i o n f r e q u e n c y 3 mhz 2 mhz 16 main clock input oscillation frequency 20.0 0.0 f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa 20mh z pll clock oscillation frequency 20.0 0.0 f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 5.5 10.0 aaaaa aaaaa aaaaa aaaaa aaaaa 3.0 20mh z m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 307 of n rej09b0047-0060z table 18.42. a-d conversion characteristics (note 1) standard min. typ. max. C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r b i t s v ref =v cc 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nu n i t l s b 3 l s b v ref =v cc =3.3v an 0 to an 7 input 8 b i t 2 r l a d d e r t c o n v l a d d e r r e s i s t a n c e conversion time(10bit), s a m p l e & h o l d f u n c t i o n a v a i l a b l e reference voltage a n a l o g i n p u t v o l t a g e k ? s v v ia v ref v 0 2.0 10 v cc v ref 4 0 3.3 c o n v e r s i o n t i m e ( 8 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e s 2 . 8 t c o n v t samp sampling time 0.3 s v ref =v cc v ref =v cc =5v, ? ad =10mhz v ref =v cc =5v, ? ad =10mhz dnl d i f f e r e n t i a l n o n - l i n e a r i t y e r r o r o f f s e t e r r o r g a i n e r r o r C C l s b l s b l s b 1 3 3 n o t e 1 : r e f e r e n c e d t o v c c = a v c c = v r e f = 3 . 3 t o 5 . 5 v , v s s = a v s s = 0 v a t t o p r = - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : a d o p e r a t i o n c l o c k f r e q u e n c y ( ? a d f r e q u e n c y ) m u s t b e 1 0 m h z o r l e s s . a n d d i v i d e t h e f a d i f v c c i s l e s s t h a n 4 . 2 v , a n d m a k e ? a d f r e q u e n c y e q u a l t o o r l o w e r t h a n f a d / 2 . n o t e 3 : a c a s e w i t h o u t s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 2 5 0 k h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 3 . a c a s e w i t h s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 1 m h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 3 . 1 0 b i t l s b 5 l s b 3 l s b v ref =v cc =3.3v an 0 to an 7 input 8 b i t 2 l s b 5 C a b s o l u t e a c c u r a c y v ref =v cc =3.3v v ref =v cc =5v a n 0 t o a n 7 i n p u t a n 0 0 t o a n 07 , a n 20 t o a n 27 i n p u t a n 0 t o a n 7 i n p u t a n 0 0 t o an 07 , an 20 t o an 27 input l s b 7 l s b 7 1 0 b i t v ref =v cc =3.3v v ref =v cc =5v a n 0 t o a n 7 i n p u t a n 0 0 t o a n 07 , a n 20 t o a n 27 i n p u t a n 0 t o an 7 input a n 0 0 t o an 07 , an 20 t o an 27 input l s b 7 l s b 7 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 308 of n rej09b0047-0060z table 18.43. flash memory version electrical characteristics (note 1) for 100 e/w cycle products note 1: when not otherwise specified, vcc = 2.7 to5.5v; topr = 0 to 60 c. note 2: vcc = 5v; topr = 25 c. note 3: definition of e/w cycle: each block may be written to a variable number of times - up to a maximum of the total number of distinct word addresses - for every block erase. performing multiple writes to the same address before an erase operation is prohibited. note 4: maximum number of e/w cycles for which opration is guaranteed. note 5: topr = 55 c. note 6: when not otherwise specified, vcc = 2.7 to 5.5v; topr = -40 to 85 c. note 7: table18.44 applies for block a or b e/w cycles > 1000. otherwise, use table 18.43. note 8: to reduce the number of e/w cycles, a block erase should ideally be performed after writing as many different word addresses (only one time each) as possible. it is important to track the total number of block erases. note 9: should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. note 10: when block a or b e/w cycles exceed 100 (option), select one wait state per block access. when fmr17 is set to "1", one wait state is inserted per access to block a or b - regardless of the value of pm17. wait state insertion durin g access to all other blocks, as well as to internal ram, is controlled b y pm17 - re g ardless of word program time (vcc=5.0v, topr=25 c) block erase time 75 0.2 600 9 s s parameter standard min. typ. (note 2) max unit symbol C C 0.4 9 s 0.7 9s 1.2 9s 2kbyte block 8kbyte block 16kbyte block 32kbyte block C erase/write cycle (note 3) 100(note 4) cycle td(sr-es) C time delay from suspend request until erase suspend data retention time (note 5) ms year 20 20 word program time (vcc=5.0v, topr=25 c) block erase time(vcc=5.0v, topr=25 c) 100 s parameter standard min. typ. (note 2) max unit symbol C C 0.3 9 s (2kbyte block) C erase/write cycle (note 3, 8, 9) 10000 (note 4,10) cycle td(sr-es) time delay from suspend request until erase suspend ms 20 table 18.44. flash memory version electrical characteristics (note 6) for 10000 e/w cycle products (option) [block a and block b (note 7)] erase suspend request (interrupt request) fmr46 td(sr-es) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 309 of n rej09b0047-0060z table 18.45. low voltage detection circuit electrical characteristics (note 1, note 3 ) table 18.46. power supply circuit timing characteristics symbol standard typ. unit measuring condition min. max. parameter vdet4 voltage down detection voltage (note 1) v v cc =0.8 to 5.5v note 1: vdet4 > vdet3 note 2: vdet3s is the min voltage at which "hardware reset 2" is maintained. below this voltage. note 3: the low voltage detection circuit is designed to use when v cc is set to 5v. t.b.d vdet3 reset level detection voltage (notes 1) v v symbol standard typ. unit measuring condition min. max. parameter 2 v cc =3.0 to 5.5v note 1: when v cc = 5v note 2: this is the time between interrupt for (stop/wait) mode release and resumption of cpu clock operation. note 3: after enabling low voltage detection, this time is required before proper detection can occur. 2 6 (note 1) 50 td(r-s) stop release time (note 2) 20 td(m-l) time for internal power supply stabilization when main clock oscillation starts 20 td(s-r) hardware reset 2 release wait time s ms vdet3s low voltage reset retention voltage (note 2) vdet3r low voltage reset release voltage v td(p-r) time for internal power supply stabilization during powering-on td(e-a) low voltage detection circuit operation start time (note 3) ms s ms v cc =3.0 to 5.5v v cc =vdet3r to 5.5v td(w-s) low power dissipation mode wait mode release time (note 2) 150 s t.b.d t.b.d td(roc) time for internal ring oscillator stabilization during powering-on ms t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d interrupt for stop mode release cpu clock td(r-s) td(s-r) vdet3r v cc cpu clock m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 310 of n rej09b0047-0060z v cc = 5v table 18.47. electrical characteristics (note 1 ) symbol v oh v oh high output voltage v oh v ol low output voltage low output voltage v ol v ol high output voltage high output voltage standard typ. unit measuring condition v v v x out v 2.0 0.45 v v x out 2.0 2.0 min. max. parameter i oh =-1ma i oh =-0.5ma i ol =1ma i ol =0.5ma highpower lowpower highpower lowpower highpower lowpower high output voltage x cout with no load applied with no load applied 2.5 1.6 v hysteresis hysteresis high input current i ih low input current i il v ram ram retention voltage v t+- v t- v t+- v t- clk 0 to clk 2 ,ta2 out to ta4 out , 0.2 1.0 v 0.2 2.5 v 5.0 a a at stop mode 2.0 v reset ta0 in to ta4 in , tb0 in to tb2 in , ad trg , cts 0 to cts 2 , scl, sda, v i =5v v i =0v -5.0 r fxin r fxcin feedback resistance x in feedback resistance x cin 15 1.5 m m p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7, x in , reset, cnvss p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7, x in , reset, cnvss r pullup pull-up resistance 50 k int 0 to int 5 , nmi, v x cout 0 0 with no load applied with no load applied highpower lowpower v i =0v 30 170 ki 0 to ki 3 , rxd 0 to rxd 2 , s in3 , s in4 v cc -2.0 v cc -2.0 note 1: referenced to v cc =4.2 to 5.5v, v ss =0v at topr = -40 to 85 c, f(bclk)=20mhz unless otherwise specified. i oh =-5ma i oh =-200a v cc -2.0 v cc -0.3 v cc v cc v cc v cc i ol =5ma i ol =200a low output voltage low output voltage p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 311 of n rej09b0047-0060z v cc = 5v table 18.48. electrical characteristics (2) (note 1 ) symbol standard typ. unit measuring condition min. max. parameter i cc power supply current (v cc =3.0 to 5.5v) the output pins are open and other pins are v ss no division ma 16 f(x in )=20mhz, flash memory ma flash memory program v cc1 =5.0v f(bclk)=10mhz, ma flash memory erase v cc1 =5.0v f(bclk)=10mhz, t opr =25 c 3a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high a 0.8 a flash memory note 1: referenced to v cc =3.0 to 5.5v, v ss =0v at topr = -40 to 85 c, f(x in )=20mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit of vcr2 register idet3: vc26 bit of vcr2 register idet2: vc25 bit o f vcr2 register ma wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a flash memory ring oscillation, f(bclk)=32khz, wait mode(note 2), oscillation capacity low idet4 voltage down detection dissipation current (note 4) a idet3 reset area detection dissipation current (note 4) a idet2 ram retention limit detection dissipation current (note 4) a no division, ring oscillation 19 1 t.b.d t.b.d 25 500 t.b.d 12 t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 312 of n rej09b0047-0060z v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.49. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 20 20 9 9 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 313 of n rej09b0047-0060z v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.51. timer a input (gating input in timer mode) table 18.52. timer a input (external trigger input in one-shot timer mode) table 18.53. timer a input (external trigger input in pulse width modulation mode) table 18.54. timer a input (counter increment/decrement input in event counter mode) table 18.50. timer a input (counter input in event counter mode) table 18.55. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 314 of n rej09b0047-0060z timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.56. timer b input (counter input in event counter mode) table 18.57. timer b input (pulse period measurement mode) table 18.58. timer b input (pulse width measurement mode) table 18.59. a-d trigger input table 18.60. serial i/o _______ table 18.61. external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 315 of n rej09b0047-0060z timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.62. multi-master i 2 c-bus line v cc = 5v high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 316 of n rej09b0047-0060z v cc = 5v tai in input tai out input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) figure 18.7. timing diagram (1) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 317 of n rej09b0047-0060z v cc = 5v figure 18.8. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda figure 18.9. timing diagram (3) v cc = 5v m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 318 of n rej09b0047-0060z v cc = 3v table 18.63. electrical characteristics ( note) s y m b o l v o h high output voltage v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e standard t y p . unit measuring condition v v x out v v x o u t 0 . 5 0 . 5 min. m a x . v c c - 0 . 5 p a r a m e t e r i oh = - 1ma i oh = - 0.1ma i oh = - 50a i ol =1ma i ol =0.1ma i ol =50a highpower lowpower highpower lowpower highpower lowpower x cout with no load applied with no load applied 2 . 5 1 . 6 v h y s t e r e s i s h y s t e r e s i s high input current i ih l o w i n p u t c u r r e n t i i l v r a m ram retention voltage v t + - v t - v t + - v t - 0 . 20 . 8v 0 . 21 . 8v 4 . 0 a a at stop mode 2.0 v r e s e t x i n , r e s e t , c n v s s v i =3v v i =0v - 4 . 0 r f x i n r fxcin f e e d b a c k r e s i s t a n c ex i n feedback resistance x cin 25 3 . 0m ? m ? r p u l l u p pull-up resistance 100 k ? v x c o u t 0 0 with no load applied with no load applied highpower lowpower v i =0v 50 500 c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , a d t r g , c t s 0 t o c t s 2 , s c l , s d a , i n t 0 t o i n t 5 , n m i , k i 0 t o k i 3 , r x d 0 t o r x d 2 , s i n 3 , s i n 4 x i n , r e s e t , c n v s s v c c - 0 . 5 v c c - 0 . 5 n o t e 1 : r e f e r e n c e d t o v c c = 3 . 0 t o 3 . 3 v , v s s = 0 v a t t o p r = - 4 0 t o 8 5 c , f ( b c l k ) = 2 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . v c c v c c v c c 0.5 0 . 7 high output voltage low output voltage low output voltage p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 9 5 t o p 9 7 , p 1 0 0 t o p 1 0 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p9 5 to p9 7 , p10 0 to p10 7 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 319 of n rej09b0047-0060z table 18.64. electrical characteristics (2) ( note 1) v cc = 3v symbol standard typ. unit measuring condition min. max. parameter the output pins are open and other pins are v ss no division ma f(bclk)=10mhz, t.b.d flash memory i cc power supply current (v cc =2.7 to 3.6v) t opr =25 c t.b.d a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high a 0.7 a flash memory note 1: referenced to v cc =3.0 to 3.3v, v ss =0v at topr = -40 to 85 c, f(bclk)=20mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit of vcr2 register idet3: vc26 bit of vcr2 register idet2: vc25 bit o f vcr2 register wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz, a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a flash memory ring oscillation, f(bclk)=32khz, wait mode (note 2), oscillation capacity low idet4 voltage down detection dissipation current (note 4) a t.b.d idet3 reset level detection dissipation current (note 4) a idet2 ram retention limit detection dissipation current (note 4) a 8 vcc=3.0v ma flash memory f(bclk)=10mhz, program vcc=3.0v ma flash memory f(bclk)=10mhz, erase t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d t.b.d m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 320 of n rej09b0047-0060z timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.65. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 321 of n rej09b0047-0060z v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.66. timer a input (counter input in event counter mode) table 18.67. timer a input (gating input in timer mode) table 18.68. timer a input (external trigger input in one-shot timer mode) table 18.69. timer a input (external trigger input in pulse width modulation mode) table 18.70. timer a input (counter increment/decrement input in event counter mode) table 18.71. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 322 of n rej09b0047-0060z v cc = 3v table 18.72. timer b input (counter input in event counter mode) table 18.73. timer b input (pulse period measurement mode) table 18.74. timer b input (pulse width measurement mode) table 18.75. a-d trigger input table 18.76. serial i/o _______ table 18.77. external interrupt inti input timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 50 90 160 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 323 of n rej09b0047-0060z v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.78. multi-master i 2 c-bus line high-speed clock mode max. min. bus free time the hold time in start condition the hold time in scl clock "0" status s s s tbuf thd;sta tlow parameter symbol unit tr thigh thd;dat ns s s data hold time the hold time in scl clock "1" status scl, sda signals' rising time 1.3 0.6 1.3 0 0.6 20+0.1cb tf scl, sda signals' falling time t su ;dat data setup time t su ;sta the setup time in restart condition t su ;sto stop condition setup time standard clock mode max. min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 100 0.6 20+0.1cb 0.6 300 300 0.9 ns ns s s m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 324 of n rej09b0047-0060z v cc = 3v figure 18.10. timing diagram (1) tai in input tai out input during event counter mode tbi in input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(t in C up) t su(up C t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 18. electrical characteristics (t-version) these standards are not final and focused only normal-version. should be used as a reference. rev.0.60 2004.02.01 page 325 of n rej09b0047-0060z v cc = 3v figure 18.11. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda figure 18.12. timing diagram (3) v cc = 3v m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 326 of n rej09b0047-0060z table 19.1. flash memory version specifications 19. flash memory version 19.1 flash memory performance the flash memory version is functionally the same as the mask rom version except that it internally con- tains flash memory. in the flash memory version, the flash memory can perform in three mode : cpu rewrite mode, standard serial i/o mode and parallel i/o mode. table 19.1 shows the flash memory version specifications. (refer to table 1.2.1 performance outline of m16c/28 group (80-pin device) for the items not listed in table 19.1. or table 1.2.2 performance outline of m16c/28 group (64-pin device) ). item flash memory operating mode erase block program method erase method program, erase control method protect method number of commands program/erase endurance(note1) rom code protection specification 3 modes (cpu rewrite, standard serial i/o, parallel i/o) see figure 19.2.1 to19.2.3 flash memory block diagram in units of word block erase program and erase controlled by software command all user blocks are write protected by bit fmr16. in addition, the block 0 and block 1 are write protected by bit fmr02. 5 commands 100 times 1,000 times (option) 100 times 10,000 times (option) parallel i/o and standard serial i/o modes are supported. note 1: program and erase endurance definition program and erase endurance are the erase endurance of each block. if the program and erase endurance are n times (n=100,1,000,10,000), each block can be erased n times. for example, if a 2-kbyte block a is erased after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure. however, data cannot be written to the same address more than once without erasing the block. (rewrite disabled) note 2: to use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. erase block only after all possible address are used. for example, an 8-word program can be written 128 times before erase is necessary. maintaining an equal number of erasure between block a and b will also improve efficiency. we recommend keeping track of the number of times erasure is used. data retention 10 years block 0 to 4 (program area) block a and b (data are) (note2) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 327 of n rej09b0047-0060z table 19.2. flash memory rewrite modes overview flash memory cpu rewrite mode standard serial i/o mode parallel i/o mode rewrite mode function areas which user rom area user rom area user rom area can be rewritten operation single chip mode boot mode parallel i/o mode mode rom none serial programmer parallel programmer programmer the user rom area is rewrit- ten when the cpu executes software command. ew0 mode: rewrite in area other than flash memory ew1 mode: rewrite in flash memory the user rom area is rewrit- ten using a dedicated serial programmer. standard serial i/o mode 1: clock synchronous serial i/o standard serial i/o mode 2: uart the user rom areas are re- written using a dedicated parallel programmer. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 328 of n rej09b0047-0060z 19.2 memory map the flash memory contains the user rom area and the boot rom area (reserved area). figures 19.2.1 to 19.2.3 show the flash memory block diagram. the user rom area has space to store the microcomputer operation program in single-chip mode and a separate 2-kbyte space as the block a and b. the user rom area is divided into several blocks. the user rom area can be rewritten in cpu rewrite, standard serial input/output, and parallel input/output modes. however, if block 0 and 1 are rewritten in cpu rewrite mode, setting the fmr02 bit in the fmr0 register to 1 (block 0, 1 rewrite enabled) and the fmr16 bit in the fmr1 register to 1 (blocks 0 to 4 rewrite enabled) enable rewriting. also, if blocks 2 to 4 are rewritten in cpu rewrite mode, setting the fmr16 bit in the fmr1 register to 1 (blocks 0 to 4 rewrite enabled) enables writing. setting the pm10 bit in the pm1 register to 1 (data area access enabled) for block a and b enables to use. figure 19.2.1. flash memory block diagram (rom capacity 48k byte) 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled for use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erasure when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 and 3 are enabled for programs and erasure when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 0fbfff 16 0f7fff 16 0f4000 16 0fffff 16 user rom area block 2 : 16k bytes (note 5) block a :2k bytes (note 2) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) block 3 : 16k bytes (note 5) 00f7ff 16 00f800 16 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 329 of n rej09b0047-0060z the m16c/28 (flash memory version) contains the flash memory that can be rewritten with a single voltage. for this flash memory, three flash memory modes area available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a program- mer and a cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). each mode is detailed in the follwing sections. the flash memory is divided into several blocks as shown in figures 19.2.1 to 19.2.3, so that memory can be erased one block at time. in addition to the user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o mode. this boot rom area has a standard serial i/o mode control program stored in it when shipped from the factory, which can be rewritten with a rewrite control program, to suit the user's application system. when the cpu is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. it is reconnected automatically when cpu operation is restored. 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 block 2 : 16k bytes 0fbfff 16 0f7fff 16 0f0000 16 0fffff 16 user rom area block a :2k bytes (note 2) block 2 : 16k bytes (note 5) block 3 : 32k bytes (note 5) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) 00f7ff 16 00f800 16 note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled for use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erasure when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 and 3 are enabled for programs and erasure when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) figure 19.2.2. flash memory block diagram (rom capacity 64k byte) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 330 of n rej09b0047-0060z 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 block 2 : 16k bytes 0fbfff 16 0f7fff 16 0f0000 16 0effff 16 0fffff 16 user rom area 0e8000 16 block a :2k bytes (note 2) block 2 : 16k bytes (note 5) block 4 : 32k bytes (note 5) block 3 : 32k bytes (note 5) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) 00f7ff 16 00f800 16 note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled for use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erasure when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 to 4 are enabled for programs and erasure when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) figure 19.2.3. flash memory block diagram (rom capacity 96k byte) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 331 of n rej09b0047-0060z 19.3 functions to prevent flash memory from rewriting the flash memory has a built-in rom code protect function for parallel i/o mode and a built-in id code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 19.3.1 rom code protect function the rom code protect function prevents the flash memory from reading and rewriting in parallel input/ output mode. figure 19.3.1.1 shows the romcp register. the romcp register is located in the user rom area. the romcp1 bit consists of two bits. the rom code protect function is enabled and reading and rewriting flash memory is disabled when setting either or both of two romcp1 bits to 0 other than the romcr bit is 00 2 . however, when setting the romcr bit to 00 2 , the flash memory can be read or rewritten. once the rom code protect function is enabled, the romcr bits can not be changed in paral- lel input/output mode. therefore, use the standard serial input/output or other modes to rewrite the flash memory. 19.3.2 id code check function use the id code check function in standard serial input/output mode. unless the flash memory is blank, the id codes sent from the programmer and the seven bytes id codes written in the flash memory are compared to see if they match. if the id codes do not match, the commands sent from the programmer are not acknowledged. the id code consists of 8-bit data, starting with the first byte, into addresses, 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . the flash memory has a program with the id code set in these addresses. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 332 of n rej09b0047-0060z figure 19.3.1.1. romcp register figure 19.3.2.1. address for id code stored symbol address factory setting romcp 0fffff 16 ff 16 (note 4) rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: disables protect 01: 10: 11: 00: 01: 10: 11: disables protect rom code protect reset bit (note 2, note 4) rom code protect level 1 set bit (note 1, note 3, note 4) romcr romcp1 b5 b4 b7 b6 1 1 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 enables romcp1 bit } enables protect } note 1: when the romcr bits are set to other than 00 2 and the romcp1 bits are set to other than 11 2 (rom code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode. note 2: when the romcr bits are set to 00 2 , the rom code protect level 1 is reset. because the romcr bits can not be modified in parallel input/output mode, modify in standard serial input/ output mode. note 3: the romcp1 bits are valid when the romcr bits are 01 2 , 10 2 or 11 2 . note 4: this bit can not be set to 1 once it is set to 0 . the romcp register is set to ff 16 when a block, including the romcp register, is erased. 1 1 rw rw rw rw rw rw rw rw rw reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address romcp m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 333 of n rej09b0047-0060z table 19.4.1. ew0 mode and ew1 mode item ew0 mode ew1 mode(note 2) operation mode single chip mode single chip mode areas in which a user rom area user rom area rewrite control program can be located areas where the rewrite control program must be the rewrite control program can be rewrite control transferred to any other than the flash excuted in the user rom area program can be memory (e.g., ram) before being executed executed areas which can be user rom area user rom area rewritten however, this excludes blocks with the rewrite control program software command none ? program, block erase command restrictions cannot be executed in a block having the rewite control program ? read status register command cannot be executed mode after programming read status register mode read array mode or erasing cpu state during auto- operating hold state (i/o ports retain the state write and auto-erase before the command is excuted (note 1) flash memory status ? read the fmr0 register's fmr00, read the fmr0 register's fmr00, detection(note 2) fmr06, and fmr07 bits in the fmr06, and fmr07 bits in a program fmr0 register by program ? execute the read status register command to read the sr7, sr5, and sr4 bits. condition for transferring set the fmr40 and fmr41 bits in the fmr40 bit in the fmr4 register is to erase-suspend(note 3) the fmr4 register to "1" by program. set to "1" and the interruput request of 19.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewritten when the cpu executes software commands. in cpu rewrite mode, only the user rom area shown in figure 19.2.1 to 19.2.3 can be rewritten and the boot rom area cannot be rewritten. verify the program and the block erase commands are executed only on blocks in the user rom area. therefore, the user rom area can be rewritten directly while the microcom- puter is mounted on-board without using a rom programmer, etc. for interrupts requested during an erasing operation in cpu rewrite mode, the m16c/28 flash module offers an erase-suspend function which the erasing operation to be suspended, and access made available to the flash. erase-write 0 (ew0) mode and erase-write 1 (ew1) mode are provided as cpu rewrite mode. table 19.4.1 shows the differences between erase-write 0 (ew0) and erase-write 1 (ew1) modes. 1 wait is required for the cpu erase-write control. note 1: do not generate a dma transfer. note 2: block 1 and block 0 are enabled for rewrite by setting fmr02 bit in the fmr0 register to "1" and setting fmr16 bit in the fmr1 register to "1". block 2 to block 4 are enabled for rewrite by setting fmr16 bit in the fmr1 register to "1". note 3: the time, until entering erase suspend and reading flash is enabled, is maximum td(sr-es) after satisfying the conditions m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 334 of n rej09b0047-0060z 19.4.1 ew0 mode the microcomputer enters cpu rewrite mode by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled) and is ready to acknowledge the software commands. ew0 mode is selected by setting the fmr11 bit in the fmr1 register to 0 . when setting the fmr01 bit to 1 , set to 1 after first writing 0 . the software commands control programming and erasing. the fmr0 register or the status register indicates whether a programming or erasing operations is completed. when entering the erase- suspend during the auto-erasing, set the fmr40 bit to 1 (erase-suspend enabled) and the fmr41 bit to 1 (suspend request). and wait for td(sr-es). after verifying the fmr46 bit is set to 1 (auto-erase stop), access to the user rom area. when setting the fmr41 bit to 0 (erase restart), auto-erasing is restarted. 19.4.2 ew1 mode ew1 mode is selected by setting the fmr11 bit to 1 after the fmr01 bit is set to 1 . (set to 1 after first writing 0 ). the fmr0 register indicates whether or not a programming or an erasing operation is com- pleted. do not execute the software commands of read status register in ew1 mode. when enabling an erase suspend function, set the fmr40 bit to 1 (erase suspend enabled) and execute block erase commands. also, preliminarily set an interrupt to enter the erase-suspend to an interrupt enabled status. after td(sr-es) from an interrupt request and entering erase suspend, an interrupt can be acknowl- edged. when an interrupt request is generated, the fmr41 bit is automatically set to 1 (suspend re- quest) and an auto-erasing is halted. if an auto-erasing is not completed (the fmr00 bit is 0 ) after an interrupt process completed, set the fmr41 bit to 0 (erase restart) and execute block erase commands again. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 335 of n rej09b0047-0060z 19.5 register description figure 19.5.1 shows the flash memory control register 0 and flash memory control register 1. figure 19.5.2 shows the flash memory control register 4. 19.5.1 flash memory control register 0 (fmr0): fmr 00 bit this bit indicates the operation status of the flash memory. the bit is 0 during programming, erasing, or erase-suspend mode; otherwise, the bit is 1 . fmr01 bit the microcomputer enables to acknowledge commands by setting the fmr01 bit to 1 (cpu rewrite mode). to set this bit to 1 , it is necessary to set to 0 after first setting to 1 . to set this bit to 0 by only writing 0 . fmr02 bit the combined setting of the fmr02 bit and the fmr16 bit enable to program and erase in the user rom area. see table 19.5.2.1 for setting details. to set this bit to 1 , it is necessary to set to 0 after first setting to 1 . to set this bit to 0 by only writing 0 . this bit is enabled only when the fmr01 bit is 1 (cpu rewrite mode enable). fmstp bit this bit resets the flash memory control circuits and minimizes power consumption in the flash memory. access to the flash memory is disabled when the fmstp bit is set to 1 . set the fmstp bit by a program in a space other than the flash memory. set the fmstp bit to 1 if one of the following occurs: ? a flash memory access error occurs during erasing or programming in ew0 mode (fmr00 bit does not switch back to 1 (ready)). ? low-power consumption mode or ring oscillator low-power consumption mode is entered. figure 19.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after enter- ing low power mode. follow the procedure on this flow chart. fmr06 bit this is a read-only bit indicating an auto-program operation status. this bit is set to 1 when a pro- gram error occurs; otherwise, it is set to 0 . for details, refer to the description of the full status check. fmr07 bit this is a read-only bit indicating an auto-erase operation status. the bit is set to 1 when an erase error occurs; otherwise, it is set to 0 . for details, refer to the description of the full status check. figure 19.5.1.1 shows a ew0 mode set/reset flowchart, figure 19.5.1.2 shows a ew1 mode set/reset flowchart. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 336 of n rej09b0047-0060z 19.5.2 flash memory control register 1 (fmr1): fmr11 bit ew1 mode is entered by setting the fmr11 bit to 1 (ew1 mode). this bit is enabled only when the fmr01 bit is 1 . fmr16 bit the combined setting of the fmr02 bit and the fmr16 bit enables to program and erase in the user rom area. to set this bit to 1 , it is necessary to set to 0 after first setting to 1 . to set this bit to 0 by only writing 0 . this bit is enabled only when the fmr01 bit is 1 . fmr17 bit fmr17 bit is 1 (with wait state), regardless of the content of the pm17 bit, 1 wait is inserted at the access to block a and block b. regardless of the content of the fmr17 bit, access to other block and the internal ram becomes the pm17 bit setting. set this bit to 1 (with wait state) when rewriting more than 100 times (option). table 19.5.2.1. protection using fmr16 and fmr02 fmr16 fmr02 block a, block b block 0, block 1 other user block 0 0 write allowed write protected write protected 0 1 write allowed write protected write protected 1 0 write allowed write protected write allowed 1 1 write allowed write allowed write allowed 19.5.3 flash memory control register 4 (fmr4): fmr40 bit the erase-suspend function is enabled by setting the fmr40 bit is set to 1 (enabled). fmr41 bit when setting the fmr41 bit to 1 in a program during auto-erasing in ew0 mode the flash module enters erase suspend mode. in ew1 mode, the fmr41 bit is automatically set to 1 (suspend re- quest) when an interrupt request of an enabled interrupt is generated, the fmr41 bit is automatically set to 1 (suspend request) and when an auto-erasing operation is restarted, set the fmr41 bit to 0 (erase restart). fmr46 bit the fmr46 bit is set to 0 during auto-erasing execution and set to 1 during erase-suspend mode. do not access to flash memory while this bit is 0 . m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 337 of n rej09b0047-0060z note 1: when setting this bit to 1 , set to 1 immdediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set this bit while the p8 5 /nmi/sd pin is h when selecting the nmi function. set by program in a space other than the flash memory in ew0 mode. set this bit to read alley mode and 0 note 2: set this bit to 1 immediately after setting it first to 0 while the fmr01 bit is set to 1 . do not generate an interrupt or a dma transfer between setting this bit to 0 and setting it to 1 . note 3: set this bit by a program in a space other than the flash memory. note 4: this bit is set to 0 by executing the clear status command. note 5: this bit is enabled when the fmr01 bit is set to 1 (cpu rewrite mode). this bit can be set to 1 when the fmr01 bit is set to 1 . however, the flash memory does not enter low-power consumption status and it is not initialized. flash memory control register 0 symbol address after reset fmr0 01b7 16 xx000001 2 b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (during writing or erasing) 1: ready cpu rewrite mode select bit (note1) 0: disables cpu rewrite mode (disables software command) 1: enables cpu rewrite mode (enables software commands) fmr01 block 0, 1 rewrite enable bit (note 2) set write protection for user rom area (see table 19.5.2.1) flash memory stop bit (note 3, 5) fmr02 fmstp 0 ry/by status flag reserved bit set to 0 0: terminated normally 1: terminated in error program status flag fmr06 0: terminated normally 1: terminated in error erase status flag fmr07 rw rw rw rw ro ro ro (b5-b4) 0: starts flash memory operation 1: stops flash memory operation (enters low-power consumption state and flash memory reset) 0 (note 4) (note 4) flash memory control register 1 symbol address after reset fmr1 01b5 16 000xxx0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function ew1 mode select bit (note1) 0: ew0 mode 1: ew1 mode fmr11 block a, b access wait bit ( note 3) reserved bit when read, its content is indeterminate reserved bit set to 0 nothing is assigned. when write, set to 0 . when read, its contect is indeterminate. 0 rw ro rw rw rw (b0) (b4) reserved bit (b3-b2) ro note 1: set this bit to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set this bit while the p8 5 /nmi/sd pin is h when the nmi function is selected. if the fmr01 bit is set to 0 , the fmr01 bit and fmr11 bit are both set to 0 note 2: set this bit to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer after setting to 0 . note 3: when rewriting more than 100 times, set this bit to 1 (with wait state). when the fmr17 bit is 1 (with wait state), regardless of the content of the pm17 bit, 1 wait is inserted at the access to the block a and b. (b5) fmr16 rw block 0 to 3 rewrite enable bit (note2) fmr17 set write protection for user rom area (see table 19.5.2.1) 0: disable 1: enable 0: pm17 enabled 1: with wait state (1 wait) when read, its content is indeterminate figure 19.5.1. flash memory control register 0,1 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 338 of n rej09b0047-0060z flash memory control register 4 symbol address after reset fmr4 01b3 16 01000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function erase suspend request bit (note 2) 0: erase restart 1: suspend request fmr41 0 reserved bit set to 0 erase suspend function enable bit (note 1) 0: disabled 1: enabled reserved bit set to 0 0 0 rw rw rw ro rw fmr40 (b5-b2) (b7) ro note 1: when setting this bit to 1 , set to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set by a program in a space other than the flash memory in ew0 mode. note 2: this bit is valid only when the erase-suspend enable bit (fmr40) is 1 . writing is enabled only between executing an erase command and completing erase (this bit is set to 1 other than the above duration). this bit can be set to 0 or 1 by a program in ew0 mode. in ew1 mode, this bit is automatically set to 1 when the fmr40 bit is 1 and a maskable interrupt is generated during erasing. do not write to 1 by a program (writing 0 is enabled). fmr46 00 erase status 0: during auto-erase operation 1: auto-erase stop (erase suspend mode) figure 19.5.2. flash memory control register 4 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 339 of n rej09b0047-0060z execute the read array command (note 3) single-chip mode set cm0, cm1, and pm1 registers (note 1) execute software commands jump to the rewrite control program transfered to an internal ram area (in the following steps, use the rewrite control program internal ram area) transfer a rewrite control program to internal ram area write 0 to the fmr01 bit (cpu rewrite mode disabled) set the fmr01 bit to 1 after writing 0 ( cpu rewrite mode enabled) (note 2) ew0 mode operation procedure rewrite control program jump to a specified address in the flash memory note 1: select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and cm17 to 16 bits in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). note 2: set the fmr01 bit to 1 immediately after setting it to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set the fmr01 bit in a space other than the internal flash memory. also, set only when the p8 5 /nmi/sd pin is h at the time of the nmi function selected. note 3: disables the cpu rewrite mode after executing the read array command. figure 19.5.1.1. setting and resetting of ew0 mode single-chip mode (note 1) set cm0, cm1, and pm1 registers (note 2) set the fmr01 bit to 1 (cpu rewrite mode enabled) after writing 0 set the fmr11 bit to 1 (ew1 mode) after writing 0 (note 3) program in rom ew1 mode operation procedure execute software commands set the fmr01 bit to 0 (cpu rewrite mode disabled) note 1: in ew1 mode, do not set boot mode. note 2: select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and cm17 to 16 bits. in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). note 3: set the fmr01 bits to 1 immediately after setting it to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting the bit to 1 . set the fmr01 bit in a space other than the internal flash memory. set only when the p8 5 /nmi/sd pin is h at the time of the nmi function selected. figure 19.5.1.2. setting and resetting of ew1 mode m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 340 of n rej09b0047-0060z figure 19.5.1.3. processing before and after low power dissipation mode start main clock oscillation transfer a low power internal consumption mode program to ram area switch the clock source of cpu clock. turn main clock off. (note 2) jump to the low power consumption mode program transferred to internal ram area. (in the following steps, use the low-power consumption mode program or internal ram area) wait until the flash memory circuit stabilizes (10 s) (note 3) set the fmstp bit to 0 (flash memory operation) set the fmstp bit to 1 (flash memory stopped. low power consumption state)(note 1) process of low power consumption mode or ring oscillator low power consumption mode switch the clock source of the cpu clock (note 2) low power consumption mode program set the fmr01 bit to 0 (cpu rewrite mode disabled) set the fmr01 bit to 1 after setting 0 ( cpu rewrite mode enabled) (note 2) jump to a desired address in the flash memory wait until oscillation stabilizes note 1: set the fmrstp bit to 1 after setting the fmr01 bit to 1 (cpu rewrite mode). note 2: wait until the clock stabilizes to switch the clock source of the cpu clock to the main clock or the sub clock. note 3: add a 10 s wait time by a program. do not access the flash memory during this wait time. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 341 of n rej09b0047-0060z 19.6 precautions in cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. 19.6.1 operation speed when cpu clock source is the main clock, before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. also, when selecting f 3 (roc) of a ring oscillator as a cpu clock source, before entering cpu rewrite mode (ew0 or ew1 mode), the rocr3 to rocr2 bits in the rocr register set the cpu clock division rate to divide-by-4 or divide-by-8 . on both cases, set the pm17 bit in the pm1 register to 1 (with wait state). 19.6.2 prohibited instructions the following instructions cannot be used in ew0 mode because the cpu tries to read data in the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk in- struction 19.6.3 interrupts ew0 mode ? to use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the ram area. _______ ? the nmi and watchdog timer interrupts can be used since the fmr0 and fmr1 registers are forcibly reset when either interrupt is generated. however, the jump addresses for each interrupt service routines to the fixed vector table are set and interrupt programs are required. flash memory rewrite operation is halted when the nmi or watchdog timer interrupt is generated. set the fmr01 bit to 1 and execute the rewrite and erase program again after exiting the interrupt rou- tine. ? the address match interrupt can not be used since the cpu tries to read data in the flash memory. ew1 mode ? do not acknowledge any interrupts with vectors in the relocatable vector table or the address match interrupt during the auto-program or erase-suspend function. 19.6.4 how to access to set the fmr01, fmr02, or fmr11 bit to 1 , write 1 after first setting the bit to 0 . do not generate an interrupt or a dma transfer between the instruction to set the bit to 0 and the instruction to set it to 1 . set the bit while an h signal is applied to the nmi pin. 19.6.5 writing in the user rom space 19.6.5.1 ew0 mode ? if the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit- ten. if this error occurs, rewrite the user rom area in standard serial i/o mode or parallel i/o mode. 19.6.5.2 ew1 mode ? do not rewrite the block where the rewrite control program is stored. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 342 of n rej09b0047-0060z 19.6.6 dma transfer in ew1 mode, do not perform a dma transfer while the fmr00 bit in the fmr0 register is set to 0 . (the auto-programming or auto-erasing duration ). 19.6.7 writing command and data write the command code and data to even addresses in the user rom area. 19.6.8 wait mode when entering wait mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) before executing the wait instruction. 19.6.9 stop mode when entering stop mode, the following settings are required: ? set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable the dma transfer before setting the cm10 bit to 1 (stop mode). ? execute the instruction to set the cm10 bit to 1 (stop mode) and the jmp.b instruction. program example bset 0, cm1 ; stop mode jmp.b l1 l1: program after exiting stop mode 19.6.10 low power consumption mode and ring oscillator-low power consumption mode if the cm05 bit is set to 1 (main clock stopped), do not execute the following commands. ? program ? block erase m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 343 of n rej09b0047-0060z 19.7 software commands read or write 16-bit commands and data from or to even addresses in the user rom area. when writing a command code, 8 high-order bits (d 15 C d 8 ) are ignored. table 19.7.1. software commands 19.7.1 read array command (ff 16 ) this command reads the flash memory. by writing command code xxff 16 in the first bus cycle, read array mode is entered. content of a specified address can be read in 16-bit unit after the next bus cycle. the microcomputer remains in read array mode until an another command is written. therefore, contents of multiple addresses can be read consecutively. 19.7.2 read status register command (70 16 ) this command reads the status register. by writing command code xx70 16 in the first bus cycle, the status register can be read in the second bus cycle (refer to status register ). read an even address in the user rom area. do not execute this command in ew1 mode. command program clear status register read array read status register first bus cycle second bus cycle block erase write write write write write mode read write write mode x wa ba address srd wd xxd0 16 data (d 15 to d 0 ) xxff 16 xx70 16 xx50 16 xx40 16 xx20 16 data (d 15 to d 0 ) x x x wa x address srd: status register data (d 7 to d 0 ) wa : write address (however,even address) wd : write data (16 bits) ba : highest-order block address (however,even address) x : any even address in the user rom area xx : 8 high-order bits of command code (ignored) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 344 of n rej09b0047-0060z start program completed yes no note 1: write the command code and data at even address. note 2: refer to "figure 19.8.4.1. full status check and handling procedure for each error" write command code xx40 16 to the write address (note 1) write data to the write address (note 1) fmr00=1? full status check (note 2) figure 19.7.4.1. flow chart of program command 19.7.3 clear status register command (50 16 ) this command clears the status register to 0 . by writing xx50 16 in the first bus cycle, and the fmr06 to fmr07 bits in the fmr0 register and sr4 to sr5 bits in the status register are set to 0 . 19.7.4 program command (40 16 ) the program command writes 2-byte data to the flash memory. by writing xx40 16 in the first bus cycle and data to the write address specified in the second bus cycle, the auto-programming/erasing (data prorgramming and verify) start. set the address value specified in the first bus cycle to same and even address as the write address specified in the second bus cycle. the fmr00 bit in the fmr0 register indicates whether an auto-programming operation has been completed. the fmr00 bit is set to 0 during the auto-programming and 1 when the auto-programming operation is completed. after the auto-programming operation is completed, the fmr06 bit in the fmr0 register indicates whether or not the auto-programming operation has been completed as expected. (refer to full status check ). also, each block disables writing (refer to table 19.5.2.1 ). do not write additions to the address which is already programmed. when commands other than a program command are executed imme- diately after a program command, set the same address as the write address specified in the second bus cycle of the program command, to the specified address value in the first bus cycle of the following command. in ew1 mode, do not execute this command on the blocks where the rewrite control pro- gram is allocated. in ew0 mode, the microcomputer enters read status register mode as soon as the auto-programming operation starts and the status register can be read. the sr7 bit in the status register is set to 0 as soon as the auto-programming operation starts. this bit is set to 1 when the auto-programming operation is completed. the microcomputer remains in read status register mode until the read array command is written. after completion of the auto-programming operation, the status register indicates whether or not the auto-programming operation has been completed as ex- pected. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 345 of n rej09b0047-0060z note 1: write the command code and data at even address. note 2: refer to "figure 19.8.4.1. full status check and handling porcedure for each error". note 3: execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. write xxd0 16 to the highest-order block address (note 1) start block erase completed yes no write command code xx20 16 ( note 1) fmr00=1? full status check (note 2,3) figure 19.7.5.1. flow chart of block erase command (when not using erase suspend function) 19.7.5 block erase by writing xx20 16 in the first bus cycle and xxd0 16 in the second bus cycle to the highest-order (even addresse of a block) and the auto-programming/erasing (erase and erase verify) start. the fmr00 bit in the fmr0 register indicates whether the auto-programming operation has been completed. the fmr00 bit is set to 0 during the auto-erasing operation and 1 when the auto-erasing operation is completed. when using the erase-suspend function in ew0 mode, the fmr46 bit in the fmr4 register indicates whether a flash memory has entered erase-suspend mode. the fmr46 bit is set to 0 during auto-erasing operation and 1 when the auto-erasing operation is completed (entering erase- suspend). after the completion of an auto-erasing operation, the fmr07 bit in the fmr0 register indicates whether or not the auto erasing-operation has been completed as expected. (refer to full status check ). also, each block disables erasing. (refer to table 19.5.2.1 ). figure 19.7.5.1 shows a flow chart of the block erase command programming when not using the erase-suspend function. figure 19.7.5.2 shows a flow chart of the block erase command programming when using an erase- suspend function. in ew1 mode, do not execute this command on the block where the rewrite control program is allocated. in ew0 mode, the microcomputer enters read status register mode as soon as the auto-erasing operation starts and the status register can be read. the sr7 bit in the status register is set to 0 as soon as the auto-erasing operation starts. this bit is set to 1 when the auto-erasing operation is completed. the microcomputer remains in read status register mode until the read array command is written. also, execute the clear status register command and the block erase command at least 3 times until the erase error is not generated when an erase error is not generated. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 346 of n rej09b0047-0060z note 1: write the command code and data to even address. note 2: execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. note 3: in ew0 mode, allocate an interrupt vector table of an interrupt, to be used, to a ram area note 4: refer to "figure 19.8.4.1. full status check and handling porcedure for each error". start block erase completed write the command code xx20 16 (note 1) write xxd0 16 to the highest-order block address (note 1) yes no fmr00=1? full status check (note 2,4) fmr40=1 interrupt service routine (note 3) fmr41=1 yes no fmr46=1? access flash memory return (interrupt service routine end) fmr41=0 (ew0 mode) (ew1 mode) start block erase completed write the command code xx20 16 (note 1) write xxd0 16 to the highest-order block address (note 1) yes no fmr00=1? full status check (note 2,4) fmr40=1 fmr41=0 interrupt service routine (note 3) access flash memory return (interrupt service routine end) figure 19.7.5.2. block erase command (at use erase suspend) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 347 of n rej09b0047-0060z bits in the srd register sr4 (d 4 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) status name contents sr1 (d 1 ) sr2 (d 2 ) sr3 (d 3 ) sr0 (d 0 ) program status erase status sequence status reserved reserved reserved reserved "1" ready terminated by error terminated by error - - - - - "0" busy completed normally completed normally - - - - - reserved bits in the fmr0 register fmr00 fmr07 fmr06 value after reset 1 0 0 table 19.8.1. status register 19.8 status register the status register indicates the operating status of the flash memory and whether an erasing or a pro- gramming operates normally and an error ends. the fmr00, fmr06, and fmr07 bits in the fmr0 register indicate the status of the status register. table 19.8.1 shows the status register. in ew0 mode, the status register can be read in the following cases: (1) when a given even address in the user rom area is read after writing the read status register command (2) when a given even address in the user rom area is read after executing the program or block erase command but before executing the read a rray command. 19.8.1 sequence status (sr7 and fmr00 bits ) the sequence status indicates the operating status of the flash memory. this bit is set to 0 (busy) during an auto-programming and auto-erasing and 1 (ready) as soon as these operations are com- pleted. this bit indicates 0 (busy) in erase-suspend mode. 19.8.2 erase status (sr5 and fmr07 bits) refer to full status check. 19.8.3 program status (sr4 and fmr06 bits) refer to full status check. ? d 7 to d 0 : indicates the data bus which is read out when executing the read status register command. ? the fmr07 bit (sr5) and fmr06 bit (sr4) are set to 0 by executing the clear status register command. ? when the fmr07 bit (sr5) or fmr06 bit (sr4) is 1, the program, and block erase command are not acknowledged. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 348 of n rej09b0047-0060z 19.8.4 full status check when an error occurs, the fmr06 to fmr07 bits in the fmr0 register are set to 1 , indicating occur- rence of each specific error. therefore, execution results can be verified by checking these status bits (full status check). table 19.8.4.1 shows errors and the status of fmr0 register. figure 19.8.4.1 shows a flow chart of the full status check and handling procedure for each error. table 19.8.4.1. errors and fmr0 register status fmr00 register (srd register) status error error occurrence condition fmr07 fmr06 (sr5) (sr4) 1 1 command ? when any commands are not written correctly sequence error ? a value other than xxd0 16 or xxff 16 is written in the second bus cycle of the block erase command (note 1) ? when the block erase command is executed on protected blocks ? when the program command is executed on protected blocks 1 0 erase error ? when the block erase command is executed on unprotected blocks but the blocks are not automatically erased correctly 0 1 program error ? when the program command is executed on unprotected blocks but the blocks are not automatically programmed correctly. note 1: the flash memory enters read array mode by writing command code xxff 16 in the second bus cycle of these commands. the command code written in the first bus cycle becomes invalid. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 349 of n rej09b0047-0060z full status check fmr06 =1 and fmr07=1? no command sequence error yes fmr07= 0? yes erase error no (1) execute the clear status register command and set the status flag to 0 whether the command is entered. (2) reexecute the command after checking that it is entered correctly or the program command or the block erase command is not executed for the blocks which are protected. (1) execute the clear status register command and set the erase status flag to 0 . (2) reexecute the block erase command. (3) execute (1) and (2) at least 3 times until an erase error is not generated. note 4: if the fmr06 or fmr07 bits is 1 , any of the program or block erase command can not be aknowledged. execute the clear status register command before executing those commands. fmr06= 0? yes program error no full status check completed note 1: if the error still occurs, the block can not be used. (1) execute the clear status register command and set the program status flag to 0 . (2) reexecute the program command. note 2: if the error still occurs, the block can not be used. [during programming] figure 19.8.4.1. full status check and handling procedure for each error m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 350 of n rej09b0047-0060z 19.9 standard serial i/o mode in standard serial input/output mode, the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for the m16c/28 group. for more information about serial programmers, contact the manufacturer of your serial programmer. for details on how to use the serial programmer, refer to the user s manual included with your serial programmer. table 19.9.1 shows pin functions (flash memory standard serial input/output mode). figures 19.9.1 and 19.9.2 show pin connections for standard serial input/output mode. 19.9.1 id code check function this function determines whether the id codes sent from the serial programmer and those written in the flash memory match. (refer to "19.3 functions to prevent flash memory from rewriting".) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 351 of n rej09b0047-0060z pin description v cc ,v ss apply the voltage guaranteed for program and erase to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad conversion. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 standard serial i/o mode 1: busy signal output pin standard serial i/o mode 2: monitor signal output pin for boot program operation check p6 5 p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 4 , p8 7 input "h" or "l" level signal or open. p9 0 to p9 3 , p9 5 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input input port p0 input port p1 input port p3 input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i i i i i o i i o i i i i p8 5 rp input i connect this pin to vss while reset pin is l . (note 2) standard serial i/o mode 1: serial clock input pin standard serial i/o mode 2: input "l". reset input pin. while reset pin is "l" level, wait for td(roc). (note 1) p2 0 to p2 7 input port p2 input "h" or "l" level signal or open. i p8 6 ce input i connect this pin to vcc while reset pin is l . (note 2) table 19.9.1. pin functions (flash memory standard serial i/o mode) note 1: when using standard serial input/output mode 1, to input h to the txd pin is necessary while the ___________ reset pin is l . therefore, connect this pin to v cc via a resistor. adjust the pull-up resistor value on a system not to affect a data transfer after reset, because this pin changes to a data-output pin _____ _____ note 2: set either the rp pin or the ce pin. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 352 of n rej09b0047-0060z figure 19.9.1. pin connections for serial i/o mode (1) m16c/28 group (flash memory version) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 2 2 2 3 2 4 2 5 2 6 2 7 28 2 9 3 0 3 1 3 2 33 34 35 36 37 38 39 40 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 48 47 46 45 44 43 42 41 64 6 3 6 2 6 1 1 7 1 8 1 9 2 0 busy sclk rxd txd vcc vss reset connect oscillator circuit mode setup method signal cnvss reset value vcc vss to vcc package: 64p6q-a ce note note: in serial i/o mode, it is necessary to connect the ce pin to "h" or the rp pin to "l" while the reset pin is "l". rp note m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 353 of n rej09b0047-0060z figure 19.9.2. pin connections for serial i/o mode (2) m16c/28 group (flash memory version) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 mode setup method signal cnvss reset value vcc vss to vcc package: 80p6q-a busy sclk rxd txd connect oscillator circuit vcc vss reset ce note note: in serial i/o mode, it is necessary to connect the ce pin to "h" or the rp pin to "l" while the reset is "l" rp note m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 354 of n rej09b0047-0060z 19.9.2 example of circuit application in standard serial i/o mode figure 19.9.2.1 shows an example of a circuit application in standard serial i/o mode 1 and figure 19.9.2.2 shows an example of a circuit application in standard serial i/o mode 2. refer to the user's manual for a serial writer to handle pins controlled by the serial writer. figure 19.9.2.1. circuit application in standard serial i/o mode 1 sclk input busy output txd output rxd input busy sclk t x d cnvss p8 6 (ce) reset rxd reset input user reset singnal microcomputer (1) controlling pins and external circuits vary with the serial programmer. for more information, refer to the user's manual included with the serial programmer. (2) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. (3) in standard serial input/output mode 1, if the user reset signal becomes l while the microcomputer is communicating with the serial programmer, break the connection between the user reset signal and the reset pin using a jumper switch. p8 5 (rp) (note 1) (note 1) note 1. set either the p8 6 (ce) pin or the p8 5 (rp) pin. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 355 of n rej09b0047-0060z monitor output rxd input txd output busy sclk txd cnvss p8 6 (ce) rxd microcomputer (1) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. note 1. set either the p8 6 (ce) pin or the p8 5 (rp) pin. p8 5 (rp) (note 1) (note 1) figure 19.9.2.2. circuit application in standard serial i/o mode 2 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 19. flash memory version rev.0.60 2004.02.01 page 356 of n rej09b0047-0060z 19.10 parallel i/o mode in parallel input/output mode, the user rom can be rewritten using a parallel programmer which is appli- cable for the m16c/28 group. for more information about the parallel programmer, contact your parallel programmer manufacturer. for details on how to use the parallel programmer, refer to the user s manual of the parallel programmer. 19.10.1 rom code protect function the rom code protect function prevents the flash memory from being read or rewritten. (refer to the description of the functions to inhibit rewriting flash memory version.) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 20. package rev.0.60 2004.02.01 page 357 of n rej09b0047-0060z 20. package lqfp64-p-1010-0.50 weight(g) jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 ? 10mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 10.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 64 49 48 33 32 17 16 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e recommended lqfp80-p-1212-0.5 weight(g) 0.47 jedec code eiaj package code lead material cu alloy 80p6q-a plastic 80pin 12 ? 12mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 12.4 m e 12.4 10 0 0.1 1.0 0.7 0.5 0.3 14.2 14.0 13.8 14.2 14.0 13.8 0.5 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e a f e h d e h e d 1 20 21 40 41 60 61 80 y lp 0.45 0.6 0.25 0.75 0.08 x a3 m d l 2 b 2 m e e recommended mount pad b x m a 1 a 2 l 1 l detail f lp a3 c recommended rev.0.60 2004.02.01 page 358 of n rej09b0047-0060z m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. register index register index a ad0 to ad7 208 adcon0 206 adcon1 206 adcon2 206 adic 60 adstat0 208 adtrgcon 207 aier 72 b bcnic 60 btic 60 c cm0 33 cm1 34 cm2 35 cpsrf 89,102 d d4int 26 dar0 79 dar1 79 dm0con 78 dm0ic 60 dm0sl 78 dm1con 78 dm1ic 60 dm1sl 78 dtt 113 f fmr0 351 fmr1 351 fmr4 352 g g1bcr0 124 g1bcr1 126 g1bt 124 g1btrr 127 g1dv 125 g1fe 131 g1fs 131 g1ie0 133 g1ie1 133 g1ir 132 g1po0 to g1po7 130 g1pocr0 to g1pocr7 129 g1tm0 to g1tm7 129 g1tmcr0 to g1tmcr7 128 g1tpr6 128 g1tpr7 128 i i2cic 60 icoc0ic 60 icoc1ic 60 ictb2 113 idb0 113 idb1 113 ifsr 61, 69 ifsr2a 61 int0ic to int5ic 60 invc0 111 invc1 112 k kupic 60 m n nddr 282 o onsf 89 p p0 to p3,p6 to p10 279 p17ddr 282 pacr 281 pclkr 36 pcr 281 pd0 to pd3,pd6 to pd10 278 pdrf 121 plc0 37 pm0 30 pm1 30 pm2 36 rev.0.60 2004.02.01 page 359 of n rej09b0047-0060z m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. register index prcr 53 pur0 to pur2 280 r rmad0 72 rmad1 72 rocr 34 s s00 241 s0d0 240 s0tic 60 s0ric 60 s10 243 s1d0 242 s1tic 60 s1ric 60 s20 241 s2d0 246 s2tic 60 s2ric 60 s3brg 200 s3c 200 s3d0 244 s3ic 60 s3trr 200 s4brg 200 s4c 200 s4d0 245 s4ic 60 s4trr 200 sar0 79 sar1 79 scldaic 60 t ta0 88 ta0ic 60 ta0mr 87 ta1 88,114 ta11 114 ta1ic 60 ta1mr 87,117 ta2 88,114 ta21 114 ta2ic 60 ta2mr 87,117 ta3 88 ta3ic 60 ta3mr 87 ta4 88,114 ta41 114 ta4ic 60 ta4mr 87,117 tabsr 88,102,116 tb0 102 tb0ic 60 tb0mr 101 tb1 102 tb1ic 60 tb1mr 101 tb2 102,116 tb2ic 60 tb2mr 101,117 tb2sc 108,115 tcr0 79 tcr1 79 trgsr 89,116 u u0brg 157 u0c0 159 u0c1 160 u0mr 158 u0rb 157 u0tb 157 u1brg 157 u1c0 159 u1c1 160 u1mr 158 u1rb 157 u1tb 157 u2brg 157 u2c0 159 u2c1 160 u2mr 158 u2rb 157 u2smr 161 rev.0.60 2004.02.01 page 360 of n rej09b0047-0060z m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. register index u2smr2 161 u2smr3 162 u2smr4 162 u2tb 157 ucon 159 udf 88 v vcr1 26 vcr2 26 w wdc 25,74 wdts 74 renesas 16-bit cmos single-chip microcomputer hardware manual m16c/28 group rev.0.60 editioned by committee of editing of renesas semiconductor hardware manual this book, or parts thereof, may not be reproduced in any form without permission of renesas technology corporation. copyright ? 2003. renesas technology corporation, all rights reserved. m16c/28 group hardware manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan rene s a s 1 6 -bit s in g le- c hip mi c r oco mp u te r m16 c family / m16 c /tin y s erie s m16c/28 group 16 rev. 0.60 revision date: february. 01. 2004 usage notes reference book www.renesas.com before using this material, please visit our website to confirm that this is the most current document available. rej09b0170-0060z for the most current usage notes reference book , please visit our website. keep safety first in your circuit designs! notes regarding these materials ? renesas technology corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. ? these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. ? renesas technology corporation assumes no responsibility for any damage, or infringe- ment of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that custom- ers contact renesas technology corporation or an authorized renesas technology cor- poration product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any dam- age, liability or other loss resulting from the information contained herein. ? renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten- tially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product con- tained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. ? please contact renesas technology corporation for further details on these materials or t he products contained therein. preface the usage notes reference book is a compilation of usage notes from the hardware manual as well as technical news related to this product. a-1 table of contents 1. usage precaution .............................................................. 1 1.1 precautions for sfr ................................................................................. 1 1.1.1 precaution for 80 pin version .................................................................................. 1 1.1.2 precaution for 64 pin version .................................................................................. 1 1.2 precautions for pll frequency synthesizer ......................................... 2 1.3 precautions for power control .................................................................3 1.4 precautions for protect ............................................................................ 4 1.5 precautions for interrupts .........................................................................5 1.5.1 reading address 00000 16 ............................................................................................................................... .......................... 5 1.5.2 setting the sp ........................................................................................................... 5 _______ 1.5.3 the nmi interrupt ..................................................................................................... 5 1.5.4 changing the interrupt generate factor ................................................................ 6 ______ 1.5.5 int interrupt ............................................................................................................ .. 6 1.5.6 rewrite the interrupt control register ................................................................... 7 1.5.7 watchdog timer interrupt ....................................................................................... 8 1.6 precautions for dmac ...............................................................................9 1.6.1 write to dmae bit in dmicon register ................................................................. 9 1.7 precautions for timers ............................................................................10 1.7.1 timer a .................................................................................................................. .. 10 1.7.1.1 timer a (timer mode) .................................................................................................. 1 0 1.7.1.2 timer a (event counter mode)..................................................................................... 11 1.7.1.3 timer a (one-shot timer mode) .................................................................................. 12 1.7.1.4 timer a (pulse width modulation mode) ................................................................... 13 1.7.2 timer b .................................................................................................................. .. 14 1.7.2.1 timer b (timer mode) .................................................................................................. 1 4 1.7.2.2 timer b (event counter mode) ................................................................................... 15 1.7.2.3 timer b (pulse period/pulse width measurement mode) ....................................... 16 1.7.3 timer s .................................................................................................................. .. 17 1.7.3.1 rewrite the g1ir register ............................................................................................ 17 a-2 1.8 precautions for serial i/o (clock-synchronous serial i/o) ..................18 1.8.1 transmission/reception ......................................................................................... 18 1.8.2 transmission .......................................................................................................... 19 1.8.3 reception ................................................................................................................ 20 1.9 precautions for serial i/o (uart mode) ................................................21 1.9.1 special mode 2 ...................................................................................................... 21 1.9.2 special mode 4 (sim mode) .................................................................................. 21 1.10 precautions for a-d converter .............................................................22 1.11 precautions for programmable i/o ports .............................................24 1.12 electric characteristic differences between mask rom and flash memory version microcomputers ..............25 1.13 precautions for flash memory version ...............................................26 1.13.1 precautions for functions to inhibit rewriting flash memory rewrite .......... 26 1.13.2 precautions for stop mode ................................................................................. 26 1.13.3 precautions for wait mode .................................................................................. 26 1.13.4 precautions for low power dissipation mode, ring oscillator low power dissipation mode ......................... 26 1.13.5 writing command and data ................................................................................. 26 1.13.6 precautions for program command .................................................................. 26 1.13.7 operation speed ................................................................................................... 27 1.13.8 instructions inhibited against use ...................................................................... 27 1.13.9 interrupts .............................................................................................................. 27 1.13.10 how to access .................................................................................................... 27 1.13.11 writing in the user rom area ............................................................................ 28 1.13.12 dma transfer ....................................................................................................... 28 1.13.13 regarding programming/erasure times and execution time ...................... 28 m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 1 of n rej09b0170-0060z 1. usage precaution 1.1 precautions for sfr 1.1.1 precaution for 80 pin version set the ifsr20 bit in the ifsr2a register to "1" after reset and set the pacr2 to pacr0 bits in the pacr register to "011 2 ". 1.1.2 precaution for 64 pin version set the ifsr20 bit in the ifsr2a register to "1" after reset and set the pacr2 to pacr0 bits in the pacr register to "010 2 ". m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 2 of n rej09b0170-0060z 1.2 precautions for pll frequency synthesizer make the supply voltage stable to use the pll frequency synthesizer. for ripple with the supply voltage 5v, keep below 10khz as frequency, below 0.5v (peak to peak) as voltage fluctuation band and below 1v/ms as voltage fluctuation rate. for ripple with the supply voltage 3v, keep below 10khz as frequency, below 0.3v (peak to peak) as voltage fluctuation band and below 0.6v/ms as voltage fluctuation rate. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 3 of n rej09b0170-0060z 1.3 precautions for power control 1. when exiting stop mode by hardware reset, the device will startup using the ring oscillator. 2. insert more than four nop instructions after an wait instruction or a instruction to set the cm10 bit of cm1 register to 1 . when shifting to wait mode or stop mode, an instruction queue reads ahead to the next instruction to halt a program by an wait instruction and an instruction to set the cm10 bit to 1 (all clocks stopped). the next instruction may be executed before entering wait mode or stop mode, de- pending on a combination of instruction and an execution timing. 3. wait until the t d(m-l) elapses or main clock oscillation stabilization time, whichever is longer, before switching the clock source for cpu clock to the main clock. similarly, wait until the sub clock oscillates stably before switching the clock source for cpu clock to the sub clock. 4. suggestions to reduce power consumption (a) ports the processor retains the state of each i/o port even when it goes to wait mode or to stop mode. a current flows in active i/o ports. a pass current flows in input ports that high-impedance state. when entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) a-d converter when a-d conversion is not performed, set the vcut bit of adicon1 register to 0 (no v ref connec- tion). when a-d conversion is performed, start the a-d conversion at least 1 s or longer after setting the vcut bit to 1 (v ref connection). (c) stopping peripheral functions use the cm0 register cm02 bit to stop the unnecessary peripheral functions during wait mode. however, because the peripheral function clock (f c32 ) generated from the sub-clock does not stop, this measure is not conducive to reducing the power consumption of the chip. if low speed mode or low power dissipation mode is to be changed to wait mode, set the cm02 bit to 0 (do not peripheral function clock stopped when in wait mode), before changing wait mode. (d) switching the oscillation-driving capacity set the driving capacity to low when oscillation is stable. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 4 of n rej09b0170-0060z 1.4 precautions for protect set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 5 of n rej09b0170-0060z 1.5 precautions for interrupts 1.5.1 reading address 00000 16 do not read the address 00000 16 in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. at this time, the ir bit for the accepted interrupt is cleared to 0 . if the address 00000 16 is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0 . this causes a problem that the interrupt is canceled, or an unexpected interrupt request is generated. 1.5.2 setting the sp set any value in the sp(usp, isp) before accepting an interrupt. the sp(usp, isp) is cleared to 0000 16 after reset. therefore, if an interrupt is accepted before setting any value in the sp(usp, isp), the pro- gram may go out of control. _______ especially when using nmi interrupt, set a value in the isp at the beginning of the program. for the first _______ and only the first instruction after reset, all interrupts including nmi interrupt are disabled. _______ 1.5.3 the nmi interrupt _______ _______ 1. the nmi interrupt is invalid after reset. the nmi interrupt becomes effective by setting to 1 the pm24 bit of the pm2 register. once enabled, it stays enabled until a reset is applid. _______ 2. the input level of the nmi pin can be read by accessing the p8 register s p8_5 bit. note that the p8_5 _______ bit can only be read when determining the pin level in nmi interrupt routine. _______ _______ 3. when selecting nmi function, stop mode cannot be entered into while input on the nmi pin is low. this _______ is because while input on the nmi pin is low the cm1 register s cm10 bit is fixed to 0 . _______ _______ 4. when selecting nmi function, do not go to wait mode while input on the nmi pin is low. this is because _______ when input on the nmi pin goes low, the cpu stops but cpu clock remains active; therefore, the current consumption in the chip does not drop. in this case, normal condition is restored by an interrupt gener- ated thereafter. _______ _______ 5. when selecting nmi function, the low and high level durations of the input signal to the nmi pin must each be 2 cpu clock cycles + 300 ns or more. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 6 of n rej09b0170-0060z ______ 1.5.5 int interrupt 1. either an l level of at least t w ( inh ) or an h level of at least t w ( inl ) width is necessary for the signal input to pins int 0 through int 5 regardless of the cpu operation clock. 2. if the pol bit in the int0ic to int5ic registers or the ifsr7 to ifsr0 bits in the ifsr register are changed, the ir bit may inadvertently set to 1 (interrupt requested). be sure to clear the ir bit to 0 (interrupt not requested) after changing any of those register bits. 1.5.4 changing the interrupt generate factor if the interrupt generate factor is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). if you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested). changing the interrupt generate factor referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested) after making such changes. refer to the description of each peripheral function for details about the interrupts from peripheral functions. figure 1.5.1 shows the procedure for changing the interrupt generate factor. figure 1.5.1. procedure for changing the interrupt generate factor changing the interrupt source disable interrupts (note 2, note 3) use the mov instruction to clear the ir bit to 0 (interrupt not requested) (note 3) change the interrupt generate factor (including a mode change of peripheral function) enable interrupts (note 2, note 3) end of change ir bit: a bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed note 1: the above settings must be executed individually. do not execute two or more settings simultaneously (using one instruction). note 2: use the i flag for the inti interrupt (i = 0 to 5). for the interrupts from peripheral functions other than the inti interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. in this case, if the maskable interrupts can all be disabled without causing a problem, use the i flag. otherwise, use the corresponding ilvl2 to ilvl0 bit for the interrupt whose interrupt generate factor is to be changed. note 3: refer to section 1.1.6, rewrite the interrupt control register for details about the instructions to use and the notes to be taken for instruction execution. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 7 of n rej09b0170-0060z 1.5.6 rewrite the interrupt control register (1) the interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. otherwise, disable the interrupt before rewriting the interrupt control register. (2) to rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. changing any bit other than the ir bit if while executing an instruction, a request for an interrupt controlled by the register being modified occurs, the ir bit in the register may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. if such a situation presents a problem, use the instructions shown below to modify the register. usable instructions: and, or, bclr, bset changing the ir bit depending on the instruction used, the ir bit may not always be cleared to 0 (interrupt not re- quested). therefore, be sure to use the mov instruction to clear the ir bit. (3) when using the i flag to disable an interrupt, refer to the sample program fragments shown below as you set the i flag. (refer to (2) for details about rewrite the interrupt control registers in the sample program fragments.) examples 1 through 3 show how to prevent the i flag from being set to 1 (interrupts enabled) before the interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer. example 1:using the nop instruction to keep the program waiting until the interrupt control register is modified int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . nop ; nop fset i ; enable interrupts. example 2:using the dummy read to keep the fset instruction waiting int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3:using the popc instruction to changing the i flag int_switch3: pushc flg fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . popc flg ; enable interrupts. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 8 of n rej09b0170-0060z 1.5.7 watchdog timer interrupt initialize the watchdog timer after the watchdog timer interrupt occurs. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 9 of n rej09b0170-0060z 1.6 precautions for dmac 1.6.1 write to dmae bit in dmicon register when both of the conditions below are met, follow the steps below. conditions ? the dmae bit is set to 1 again while it remains set (dmai is in an active state). ? a dma request may occur simultaneously when the dmae bit is being written. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously (*1) . step 2: make sure that the dmai is in an initial state (*2) in a program. if the dmai is not in an initial state, the above steps should be repeated. notes: *1. the dmas bit remains unchanged even if 1 is written. however, if 0 is written to this bit, it is set to 0 (dma not requested). in order to prevent the dmas bit from being modified to 0 , 1 should be written to the dmas bit when 1 is written to the dmae bit. in this way the state of the dmas bit immediately before being written can be maintained. similarly, when writing to the dmae bit with a read-modify-write instruction, 1 should be written to the dmas bit in order to maintain a dma request which is generated during execution. *2. read the tcri register to verify whether the dmai is in an initial state. if the read value is equal to a value which was written to the tcri register before dma transfer start, the dmai is in an initial state. (if a dma request occurs after writing to the dmae bit, the value written to the tcri register is 1 .) if the read value is a value in the middle of transfer, the dmai is not in an initial state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 10 of n rej09b0170-0060z 1.7 precautions for timers 1.7.1 timer a 1.7.1.1 timer a (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register and the tai register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register is modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the counter is read at the same time it is reloaded, the value ffff 16 is read. also, if the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. _____ 3. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 11 of n rej09b0170-0060z 1.7.1.2 timer a (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the udf register, the onsf register tazie, ta0tgl and ta0tgh bits and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the udf register, the onsf register tazie, ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, ffff 16 can be read in underflow, while reloading, and 0000 16 in overflow. when setting tai register to a value during a counter stop, the setting value can be read before a counter starts counting. also, if the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. _____ 3. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 12 of n rej09b0170-0060z 1.7.1.3 timer a (one-shot timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the onsf register ta0tgl and ta0tgh bits and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the onsf register ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. when setting tais bit to 0 (count stop), the followings occur: ? a counter stops counting and a content of reload register is reloaded. ? tai out pin outputs l . ? after one cycle of the cpu clock, the ir bit of taiic register is set to 1 (interrupt request). 3. output in one-shot timer mode synchronizes with a count source internally generated. when an external trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to tai in pin and output in one-shot timer mode. 4. the ir bit is set to 1 when timer operation mode is set with any of the following procedures: ? select one-shot timer mode after reset. ? change an operation mode from timer mode to one-shot timer mode. ? change an operation mode from event counter mode to one-shot timer mode. to use the timer ai interrupt (the ir bit), set the ir bit to 0 after the changes listed above have been made. 5. when a trigger occurs, while counting, a counter reloads the reload register to continue counting after generating a re-trigger and counting down once. to generate a trigger while counting, gener- ate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source. _____ 6. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 13 of n rej09b0170-0060z 1.7.1.4 timer a (pulse width modulation mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the onsf register ta0tgl and ta0tgh bits and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the onsf register ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. the ir bit is set to 1 when setting a timer operation mode with any of the following procedures: ? select the pwm mode after reset. ? change an operation mode from timer mode to pwm mode. ? change an operation mode from event counter mode to pwm mode. to use the timer ai interrupt (interrupt request bit), set the ir bit to 0 by program after the above listed changes have been made. 3. when setting tais register to 0 (count stop) during pwm pulse output, the following action occurs: ? stop counting. ? when tai out pin is output h , output level is set to l and the ir bit is set to 1 . ? when tai out pin is output l , both output level and the ir bit remains unchanged. _____ 4. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 14 of n rej09b0170-0060z 1.7.2 timer b 1.7.2.1 timer b (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr or the tbsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. 2. a value of a counter, while counting, can be read in tbi register at any time. ffff 16 is read while reloading. setting value is read between setting values in tbi register at count stop and starting a counter. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 15 of n rej09b0170-0060z 1.7.2.2 timer b (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr or the tbsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. 2. the counter value can be read out on-the-fly at any time by reading the tbi register. however, if this register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tbi register is read after setting a value in it while not counting but before the counter starts count- ing, the read value is the one that has been set in the register. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 16 of n rej09b0170-0060z 1.7.2.3 timer b (pulse period/pulse width measurement mode) 1. the timer remains idle after reset. set the mode, count source, etc. using the tbimr (i = 0 to 2) register before setting the tbis bit in the tabsr or the tbsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. to clear the mr3 bit to 0 by writing to the tbimr register while the tbis bit = 1 (count starts), be sure to write the same value as previously written to the tm0d0, tm0d1, mr0, mr1, tck0 and tck1 bits and a 0 to the mr2 bit. 2. the ir bit of tbiic register (i=0 to 2) goes to 1 (interrupt request), when an effective edge of a measurement pulse is input or timer bi is overflowed. the factor of interrupt request can be deter- mined by use of the mr3 bit of tbimr register within the interrupt routine. 3. if the source of interrupt cannot be identified by the mr3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times timer b has overflowed. 4. to set the mr3 bit to 0 (no overflow), set tbimr register with setting the tbis bit to 1 and counting the next count source after setting the mr3 bit to 1 (overflow). 5. use the ir bit of tbiic register to detect only overflows. use the mr3 bit only to determine the interrupt factor within the interrupt routine. 6. when a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. 7. a value of the counter is indeterminate at the beginning of a count. mr3 may be set to 1 and timer bi interrupt request may be generated between a count start and an effective edge input. 8. for pulse width measurement, pulse widths are successively measured. use program to check whether the measurement result is an h level width or an l level width. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 17 of n rej09b0170-0060z 1.7.3 timer s 1.7.3.1 rewrite the g1ir register when write "0" (without interrupt request) to each bit in the g1ir register, use the following instructions. usable instructions: and, bclr m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 18 of n rej09b0170-0060z 1.8 precautions for serial i/o (clock-synchronous serial i/o) 1.8.1 transmission/reception _______ ________ 1. with an external clock selected, and choosing the rts function, the output level of the rtsi pin goes to l when the data-receivable status becomes ready, which informs the transmission side that the ________ reception has become ready. the output level of the rtsi pin goes to h when reception starts. so if ________ ________ the rtsi pin is connected to the ctsi pin on the transmission side, the circuit can transmission and _______ reception data with consistent timing. with the internal clock, the rts function has no effect. _____ 2. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the rts 2 and clk 2 pins go to a high-impedance state. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 19 of n rej09b0170-0060z 1.8.2 transmission when an external clock is selected, the conditions must be met while if the uic0 register s ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the uic0 register s ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. ? the te bit of uic1 register= 1 (transmission enabled) ? the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ ? if cts function is selected, input on the ctsi pin = l m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 20 of n rej09b0170-0060z 1.8.3 reception 1. in operating the clock-synchronous serial i/o, operating a transmitter generates a shift clock. fix set- tings for transmission even when using the device only for reception. dummy data is output to the outside from the txdi pin when receiving data. 2. when an internal clock is selected, set the uic1 register (i = 0 to 2) s te bit to 1 (transmission enabled) and write dummy data to the uitb register, and the shift clock will thereby be generated. when an external clock is selected, set the uic1 register (i = 0 to 2) s te bit to 1 and write dummy data to the uitb register, and the shift clock will be generated when the external clock is fed to the clki input pin. 3. when successively receiving data, if all bits of the next receive data are prepared in the uarti receive register while the uic1 register (i = 0 to 2) s re bit = 1 (data present in the uirb register), an overrun error occurs and the uirb register oer bit is set to 1 (overrun error occurred). in this case, because the content of the uirb register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit- ted. note that when an overrun error occurred, the siric register ir bit does not change state. 4. to receive data in succession, set dummy data in the lower-order byte of the uitb register every time reception is made. 5. when an external clock is selected, the conditions must be met while if the ckpol bit = 0 , the external clock is in the high state; if the ckpol bit = 1 , the external clock is in the low state. ? the re bit of uic1 register= 1 (reception enabled) ? the te bit of uic1 register= 1 (transmission enabled) ? the ti bit of uic1 register= 0 (data present in the uitb register) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 21 of n rej09b0170-0060z 1.9 precautions for serial i/o (uart mode) 1.9.1 special mode 2 _____ if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase output _____ forcible cutoff by input on sd pin enabled), the rts 2 and clk 2 pins go to a high-impedance state. 1.9.2 special mode 4 (sim mode) a transmit interrupt request is generated by setting the u2c1 register u2irs bit to 1 (transmission complete) and u2ere bit to 1 (error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to 0 (no interrupt request) after setting these bits. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 22 of n rej09b0170-0060z 1.10 precautions for a-d converter 1. set adcon0 (except bit 6), adcon1, adcon2 and adtrgcon registers when a-d conversion is stopped (before a trigger occurs). 2. when the vcut bit of adcon1 register is changed from 0 (vref not connected) to 1 (vref con- nected), start a-d conversion after passing 1 s or longer. 3. to prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the av cc , v ref , and analog input pins (an i , an 0i , an 2i (i=0 to 7)) each and the av ss pin. similarly, insert a capacitor between the v cc1 pin and the v ss pin. figure 1.10.1 is an ex- ample connection of each pin. 4. make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode). also, if the adcon0 register s tgr bit = 1 (external trigger), make sure the port direction bit for ___________ the ad trg pin is set to 0 (input mode). 5. when using key input interrupts, do not use any of the four an 4 to an 7 pins as analog inputs. (a key input interrupt request is generated when the a-d input voltage goes low.) 6. the ad frequency must be 10 mhz or less. without sample-and-hold function, limit the ad frequency to 250kh z or more. with the sample and hold function, limit the ad frequency to 1mh z or more. 7. when changing an a-d operation mode, select analog input pin again in the ch2 to ch0 bits of adcon0 register and the scan1 to scan0 bits of adcon1 register. figure 1.10.1. use of capacitors to reduce noise microcomputer notes 1. c1 0.47f, c2 0.47f, c3 100pf, c4 0.1f (reference) 2. use thick and shortest possible wiring to connect capacitors. av cc av ss v ref an i c4 c1 c2 c3 v cc v ss an i : an i (i=0 to 7), an 0i (i=0 to 7 for 80-pin version, and i=0 to 3 for 64-pin version) an 2i (i=0 to 7 for 80-pin version, i=4 for 64-pin version) m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 23 of n rej09b0170-0060z 8. if the cpu reads the adi register (i = 0 to 7) at the same time the conversion result is stored in the adi register after completion of a-d conversion, an incorrect value may be stored in the adi register. this problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for cpu clock. ? when operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed trigger mode 0 or delayed trigger mode 1 check to see that a-d conversion is completed before reading the target adi register. (check the adic register s ir bit to see if a-d conversion is completed.) ? when operating in repeat mode or repeat sweep mode 0 or 1 use the main clock for cpu clock directly without dividing it. 9. if a-d conversion is forcibly terminated while in progress by setting the adcon0 register s adst bit to 0 (a-d conversion halted), the conversion result of the a-d converter is indeterminate. the contents of adi registers irrelevant to a-d conversion may also become indeterminate. if while a-d conversion is underway the adst bit is cleared to 0 in a program, ignore the values of all adi registers. 10. when setting the adst bit in the adcon register to "0" and terminating forcefully by a program in single sweep conversion mode, a-d delayed trigger mode 0 and a-d delayed trigger mode 1 during a-d converting operation, the a-d interrupt request may be generated. if this causes a problemm, set the adst bit to "0" after an interrupt is disabled. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 24 of n rej09b0170-0060z 1.11 precautions for programmable i/o ports _____ 1. if a low-level signal is applied to the sd pin when the tb2sc register ivpcr1 bit = 1 (three-phase _____ output forcible cutoff by input on sd pin enabled), the p7 2 to p7 5 , p8 0 and p8 1 pins go to a high- impedance state. 2. setting the sm32 bit in the s3c register to 1 causes the p3 2 pin to go to a high-impedance state. similarly, setting the sm42 bit in the s4c register to 1 causes the p9 6 pin to go to a high-impedance state. 3. when the inv03 bit of the invc0 register is "1"(three-phase motor control timer output enabled), it _____ _______ _____ becomes the following by the sd function when "l" is input to the p8 5 /nmi/sd pin. _____ ? when the tb2sc register ivpcr1 bit = 1 (three-phase output forcible cutoff by input on sd pin __ __ ___ enabled), the u/ u/ v/ v/ w/ w pins go to a high-impedance state. _____ ? when the tb2sc register ivpcr1 bit = 0 (three-phase output forcible cutoff by input on sd pin __ __ ___ disabled), the u/ u/ v/ v/ w/ w pins go to a normal port. _____ _______ _____ when the sd function isn't used, set to "0" (input) in pd8 5 and pullup to "h" in the p8 5 /nmi/sd pin from outside. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 25 of n rej09b0170-0060z 1.12 electric characteristic differences between mask rom and flash memory version microcomputers flash memory version and mask rom version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal rom, different layout pattern, etc. when switching to the mask rom version, conduct equivalent tests as system evaluation tests con- ducted in the flush memory version. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 26 of n rej09b0170-0060z 1.13 precautions for flash memory version 1.13.1 precautions for functions to inhibit rewriting flash memory rewrite id codes are stored in addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . if wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial i/o mode. the romcp register is mapped in address 0fffff 16 . if wrong data is written to this address, the flash memory cannot be read or written in parallel i/o mode. in the flash memory version of microcomputer, these addresses are allocated to the vector addresses (h) of fixed vectors. 1.13.2 precautions for stop mode when shifting to stop mode, the following settings are required: ? set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable dma transfers before setting the cm10 bit to 1 (stop mode). ? execute the jmp.b instruction subsequent to the instruction which sets the cm10 bit to 1 (stop mode) example program bset 0, cm1 ; stop mode jmp.b l1 l1: program after returning from stop mode 1.13.3 precautions for wait mode when shifting to wait mode, set the fmr01 bit to 0 (cpu rewrite mode diabled) before executing the wait instruction. 1.13.4 precautions for low power dissipation mode, ring oscillator low power dissipation mode if the cm05 bit is set to 1 (main clock stop), the following commands must not be executed. ? program ? block erase ? erase all unlocked blocks ? lock bit program 1.13.5 writing command and data write the command code and data at even addresses. 1.13.6 precautions for program command write xx40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 27 of n rej09b0170-0060z 1.13.7 operation speed before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or less for cpu clock using the cm0 register s cm06 bit and cm1 register s cm17 C 6 bits. also, set the pm1 register s pm17 bit to 1 (with wait state). 1.13.8 instructions inhibited against use the following instructions cannot be used in ew0 mode because the flash memory s internal data is referenced: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction 1.13.9 interrupts ew0 mode ? any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the ram area. _______ ? the nmi and watchdog timer interrupts can be used because the fmr0 register and fmr1 regis- ter are initialized when one of those interrupts occurs. the jump addresses for those interrupt service routines should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. ? the address match interrupt cannot be used because the flash memory s internal data is refer- enced. ew1 mode ? make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. ? avoid using watchdog timer interrupts. _______ ? the nmi interrupt can be used because the fmr0 register and fmr1 register are initialized when this interrupt occurs. the jump address for the interrupt service routine should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. 1.13.10 how to access to set the fmr01, fmr02, or fmr11 bit to 1 , write 0 and then 1 in succession. this is necessary to ensure that no interrupts or dma transfers will occur before writing 1 after writing 0 . also only when _______ nmi pin is h level. m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. rev.0.60 2004.02.01 page 28 of n rej09b0170-0060z 1.13.11 writing in the user rom area ew0 mode ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter. in this case, standard serial i/o or parallel i/o mode should be used. ew1 mode ? avoid rewriting any block in which the rewrite control program is stored. 1.13.12 dma transfer in ew1 mode, make sure that no dma transfers will occur while the fmr0 register s fmr00 bit = 0 (during the auto program or auto erase period). 1.13.13 regarding programming/erasure times and execution time as the number of programming/erasure times increases, so does the execution time for software com- mands (program, block erase, erase all unlock blocks, and lock bit program). especially when the number of programming/erasure times exceeds 1,000, the software command execution time is notice- ably extended. therefore, the software command wait time that is set must be greater than the maximum rated value of electrical characteristics. _______ the software commands are aborted by hardware reset 1, hardware reset 2, nmi interrupt, and watchdog timer interrupt. if a software command is aborted by such reset or interrupt, the block that was in process must be erased before reexecuting the aborted command. renesas 16-bit single-chip microcomputer usage notes reference book m16c/28 group rev.0.60 editioned by committee of editing of renesas semiconductor usage notes reference book this book, or parts thereof, may not be reproduced in any form without permission of renesas technology corporation. copyright ? 2003. renesas technology corporation, all rights reserved. m16c/28 group usage notes reference book 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan |
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