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mos integrated circuits pd703037a, 703037ay, 70f3037a, 70f3037ay v850/sb2 tm 32-bit single-chip microcontrollers document no. u14894ej2v0ds00 (2nd edition) date published february 2002 j cp(k) printed in japan data sheet ? 2000 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. description the pd703037a, 703037ay, 70f3037a, and 70f3037ay (v850/sb2) are 32-bit single-chip microcontrollers of the v850 series tm for av equipment. 32-bit cpu, rom, ram, timer/counters, serial interfaces, a/d converter, dma controller, and so on are integrated on a single chip. the pd70f3037a and 70f3037ay have flash memory in place of the internal mask rom of the pd703037a and 703037ay. because flash memory allows the program to be written and erased electrically with the device mounted on the board, these products are ideal for the evaluation stages of system development, small-scale production, and rapid development of new products. the pd703034a, 703034ay, 703035a, 703035ay, 70f3035a, and 70f3035ay products with a different rom/ram size are also available. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850/sb1 tm , v850/sb2 user?s manual hardware: u13850e v850 series user?s manual architecture: u10243e features { number of instructions: 74 { minimum instruction execution time: 76.9 ns (@ internal 13 mhz operation) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { memory space: 16 mb linear address space { internal memory rom: 512 kb ( pd703037a, 703037ay: mask rom) 512 kb ( pd70f3037a, 70f3037ay: flash memory) ram: 24 kb ( pd703037a, 703037ay, 70f3037a, 70f3037ay) { interrupt/exception: pd703037a, 70f3037a (external: 8, internal: 33 sources, exception: 1 source) pd703037ay, 70f3037ay (external: 8, internal: 34 sources, exception: 1 source) { i/o lines total: 83 { timer/counters: 16-bit timer (2 channels: tm0, tm1) 8-bit timer (6 channels: tm2 to tm7) { watch timer: 1 channel { watchdog timer: 1 channel { iebus tm controller: 1 channel
data sheet u14894ej2v0ds 2 pd703037a, 703037ay, 70f3037a, 70f3037ay { serial interface ? asynchronous serial interface (uart0, uart1) ? clocked serial interface (csi0 to csi3) ? 3-wire variable length serial interface (csi4) ? i 2 c bus interface (i 2 c0, i 2 c1) ( pd703037ay, 70f3037ay only) { 10-bit resolution a/d converter: 12 channels { dma controller: 6 channels { real-time output port: 8 bits 1 channel or 4 bits 2 channels { rom correction: 4 places can be corrected { power-saving function: halt/idle/stop modes { packages: 100-pin plastic qfp (14 20) { pd70f3037a, 70f3037ay ? can be replaced with pd703037a and 703037ay (internal mask rom) in mass production applications { av equipment (audio, car audio, vcr, tv, etc.) ordering information part number package internal rom pd703037agf- -3ba pd703037aygf- -3ba pd70f3037agf-3ba pd70f3037aygf-3ba 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) 100-pin plastic qfp (14 20) mask rom (512 kb) mask rom (512 kb) flash memory (512 kb) flash memory (512 kb) remarks 1. indicates rom code suffix. 2. romless versions are not provided.
data sheet u14894ej2v0ds 3 pd703037a, 703037ay, 70f3037a, 70f3037ay pin configuration (top view) 100-pin plastic qfp (14 20) ? pd703037agf- -3ba ? pd70f3037agf-3ba ? pd703037aygf- -3ba ? pd70f3037aygf-3ba p13/si1/rxd0 p12/sck0/scl0 note 2 p11/so0 p10/si0/sda0 note 2 p07/intp6 p06/intp5/rtptrg p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p111/a2 p112/a3 p113/a4 reset xt1 xt2 regc x2 x1 v ss v dd clkout p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq p40/ad0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ref av ss av dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p14/so1/txd0 p15/sck1/asck0 p20/si2/sda1 note 2 p21/so2 p22/sck2/scl1 note 2 p23/rxd1/si3 p24/txd1/so3 p25/asck1/sck3 ev dd ev ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p32/ti10/si4 p33/ti11/so4 p34/to0/a13/sck4 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 ic/v pp note 1 p100/rtp0/kr0/a5 p101/rtp1/kr1/a6 p102/rtp2/kr2/a7 p103/rtp3/kr3/a8 p104/rtp4/kr4/a9/ierx p105/rtp5/kr5/a10/ietx p106/rtp6/kr6/a11 p107/rtp7/kr7/a12 p110/wait/a1 notes 1. ic: connect directly to v ss ( pd703037a, 703037ay). v pp : connect to v ss in normal operation mode ( pd70f3037a, 70f3037ay). 2. scl0, scl1, sda0, and sda1 are available only in the pd703037ay and 70f3037ay.
data sheet u14894ej2v0ds 4 pd703037a, 703037ay, 70f3037a, 70f3037ay pin identification a1 to a21: address bus p70 to p77: port 7 ad0 to ad15: address/data bus p80 to p83: port 8 adtrg: a/d trigger input p90 to p96: port 9 ani0 to ani11: analog input p100 to p107: port 10 asck0, asck1: asynchronous serial clock p110 to p113: port 11 astb: address strobe rd: read av dd : analog power supply regc: regulator control av ref : analog reference voltage reset: reset av ss : analog ground rtp0 to rtp7: real-time output port bv dd : power supply for bus interface rtptrg: rtp trigger input bv ss : ground for bus interface r/w: read/write status clkout: clock output rxd0, rxd1: receive data dstb: data strobe sck0 to sck4: serial clock ev dd : power supply for port scl0, scl1: serial clock ev ss : ground for port sda0, sda1: serial data hldak: hold acknowledge si0 to si4: serial input hldrq: hold request so0 to so4: serial output ic: internally connected ti00, ti01, ti10, : timer i nput ierx: iebus receive data ti11, ti2 to ti5 ietx: iebus transmit data to0 to to5: timer output intp0 to intp6: interrupt request from peripherals txd0, txd1: transmit data kr0 to kr7: key return uben: upper byte enable lben: lower byte enable v dd : power supply nmi: non-maskable interrupt request v pp : programming power supply p00 to p07: port 0 v ss : ground p10 to p15: port 1 wait: wait p20 to p27: port 2 wrh: write strobe high level data p30 to p37: port 3 wrl: write strobe low level data p40 to p47: port 4 x1, x2: crystal for main clock p50 to p57: port 5 xt1, xt2: crystal for sub-clock p60 to p65: port 6
data sheet u14894ej2v0ds 5 pd703037a, 703037ay, 70f3037a, 70f3037ay internal block diagram rom cpu pc rom correction hldrq (p96) hldak (p95) a13 to a15 (p34 to p36) a16 to a21 (p60 to p65) a1 to a12 (p100 to p107, p110 to p113) ad0 to ad15 (p40 to p47, p50 to p57) clkout x1 x2 xt1 xt2 reset v dd v ss bv dd bv ss ev dd ev ss v pp note 4 ic note 5 rtp0 to rtp7 rtptrg regc av dd av ref av ss ani0 to ani11 adtrg p110 to p113 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 astb (p94) dstb/rd (p93) r/w/wrh (p92) uben (p91) lben/wrl (p90) wait (p110) multiplier 16 16 32 32-bit barrel shifter system registers general-purpose registers 32 bits 32 note 1 note 2 ram intc sio csi0/i 2 c0 note 3 csi2/i 2 c1 note 3 csi1/uart0 csi3/uart1 variable length csi4 key return function dmac: 6ch so0 si0/sda0 note 3 sck0/scl0 note 3 watch timer watchdog timer nmi intp0 to intp6 ti00, ti01, ti10, ti11 to0, to1 ti2/to2 ti3/to3 ti4/to4 ti5/to5 so2 si2/sda1 note 3 sck2/scl1 note 3 so1/txd0 si1/rxd0 sck1/asck0 so3/txd1 si3/rxd1 sck3/asck1 so4 si4 sck4 kr0 to kr7 alu ports rtp cg 3.0 v regulator a/d converter instruction queue bcu timer/counters 16-bit timer : tm0, tm1 8-bit timer : tm2 to tm7 iebus ietx ierx notes 1. pd703037a, 703037ay: 512 kb (mask rom) pd70f3037a, 70f3037ay: 512 kb (flash memory) 2. pd703037a, 703037ay, 70f3037a, 70f3037ay: 24 kb 3. i 2 c bus interface and sdan and scln pins (n = 0, 1) are available only in the pd703037ay and 70f3037ay. 4. pd70f3037a, 70f3037ay 5. pd703037a, 703037ay
data sheet u14894ej2v0ds 6 pd703037a, 703037ay, 70f3037a, 70f3037ay contents 1. differences among products................................................................................................7 2. pin functions ............................................................................................................... ...................8 2.1 port pins ................................................................................................................... ..................................8 2.2 non-port pins ............................................................................................................... ............................10 2.3 pin i/o circuits and recommended connection of unused pins........................................................14 3. electrical specifications ................................................................................................... ...18 3.1 flash memory programming mode ( pd70f3037a, 70f3037ay only) ................................................42 4. package drawing............................................................................................................. ...........43 5. recommended soldering conditions ................................................................................44 appendix notes on target system design...........................................................................46
data sheet u14894ej2v0ds 7 pd703037a, 703037ay, 70f3037a, 70f3037ay 1. differences among products rom product name incorporated i 2 c type size ram size flash memory programming pin package pd703034a no pd703034ay yes mask rom 128 kb 12 kb no 100-pin qfp (14 20) 100-pin lqfp (14 14) pd703035a no pd703035ay yes mask rom 256 kb 16 kb no pd70f3035a no pd70f3035ay yes flash memory yes (v pp ) 100-pin qfp (14 20) 100-pin lqfp (14 14) pd703037a no pd703037ay yes mask rom 512 kb 24 kb no pd70f3037a no pd70f3037ay yes flash memory yes (v pp ) 100-pin qfp (14 20) cautions 1. there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. 2. when replacing the flash memory versions with mask rom versions, write the same code in the empty area of the internal rom.
data sheet u14894ej2v0ds 8 pd703037a, 703037ay, 70f3037a, 70f3037ay 2. pin functions 2.1 port pins (1/2) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 i/o yes port 0 8-bit i/o port input/output can be specified in 1-bit units. intp6 p10 si0/sda0 note p11 so0 p12 sck0/scl0 note p13 si1/rxd0 p14 so1/txd0 p15 i/o yes port 1 6-bit i/o port input/output can be specified in 1-bit units. sck1/asck0 p20 si2/sda1 note p21 so2 p22 sck2/scl1 note p23 si3/rxd1 p24 so3/txd1 p25 sck3/asck1 p26 ti2/to2 p27 i/o yes port 2 8-bit i/o port input/output can be specified in 1-bit units. ti3/to3 p30 ti00 p31 ti01 p32 ti10/si4 p33 ti11/so4 p34 to0/a13/sck4 p35 to1/a14 p36 ti4/to4/a15 p37 i/o yes port 3 8-bit i/o port input/output can be specified in 1-bit units. ti5/to5 p40 to p47 i/o no port 4 8-bit i/o port input/output can be specified in 1-bit units. ad0 to ad7 p50 to p57 i/o no port 5 8-bit i/o port input/output can be specified in 1-bit units. ad8 to ad15 note pd703037ay, 70f3037ay only. remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 9 pd703037a, 703037ay, 70f3037a, 70f3037ay (2/2) pin name i/o pull function alternate function p60 to p65 i/o no port 6 6-bit i/o port input/output can be specified in 1-bit units. a16 to a21 p70 to p77 input no port 7 8-bit input port ani0 to ani7 p80 to p83 input no port 8 4-bit input port ani8 to ani11 p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output can be specified in 1-bit units. hldrq p100 rtp0/a5/kr0 p101 rtp1/a6/kr1 p102 rtp2/a7/kr2 p103 rtp3/a8/kr3 p104 rtp4/a9/kr4/ierx p105 rtp5/a10/kr5/ietx p106 rtp6/a11/kr6 p107 i/o yes port 10 8-bit i/o port input/output can be specified in 1-bit units. rtp7/a12/kr7 p110 a1/wait p111 a2 p112 a3 p113 i/o yes port 11 4-bit i/o port input/output can be specified in 1-bit units. a4 remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 10 pd703037a, 703037ay, 70f3037a, 70f3037ay 2.2 non-port pins (1/4) pin name i/o pull function alternate function a1 p110/wait a2 p111 a3 p112 a4 p113 a5 p100/rtp0/kr0 a6 p101/rtp1/kr1 a7 p102/rtp2/kr2 a8 p103/rtp3/kr3 a9 p104/rtp4/kr4/ierx a10 p105/rtp5/kr5/ietx a11 p106/rtp6/kr6 a12 p107/rtp7/kr7 a13 p34/to0/sck4 a14 p35/to1 a15 output yes lower address bus used for external memory expansion p36/to4/ti4 a16 to a21 output no higher address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p50 to p57 adtrg input yes a/d converter external trigger input p05/intp4 ani0 to ani7 p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 baud rate clock input for uart0 p15/sck1 asck1 input yes baud rate clock input for uart1 p25/sck3 astb output no external address strobe output p94 av dd ?? positive power supply for a/d converter and alternate port ? av ref input ? reference voltage input for a/d converter ? av ss ?? ground potential for a/d converter and alternate port ? bv dd ?? positive power supply for bus interface and alternate port ? bv ss ?? ground potential for bus interface and alternate port ? clkout output ? internal system clock output ? dstb output no external data strobe output p93/rd ev dd ?? positive power supply for i/o ports and alternate-function pins (except bus interface alternate port) ? ev ss ?? ground potential for i/o ports and alternate-function pins (except bus interface alternate port) ? hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 ic ?? internally connected ( pd703037a, 703037ay only) ? remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 11 pd703037a, 703037ay, 70f3037a, 70f3037ay (2/4) pin name i/o pull function alternate function ierx input iebus data input p104/rtp4/a9/kr4 ietx output yes iebus data output p105/rtp5/a10/kr5 intp0 p01 intp1 p02 intp2 p03 intp3 input yes external interrupt request input (analog noise elimination) p04 intp4 p05/adtrg intp5 input yes external interrupt request input (digital noise elimination) p06/rtptrg intp6 input yes external interrupt request input (digital noise elimination supporting remote controller) p07 kr0 p100/rtp0/a5 kr1 p101/rtp1/a6 kr2 p102/rtp2/a7 kr3 p103/rtp3/a8 kr4 p104/rtp4/a9/ierx kr5 p105/rtp5/a10/ietx kr6 p106/rtp6/a11 kr7 input yes key return input p107/rtp7/a12 lben output no external data bus?s lower byte enable output p90/wrl nmi input yes non-maskable interrupt request input p00 rd output no read strobe output p93/dstb regc ?? regulator output stabilization capacitance connection ? reset input ? system reset input ? rtp0 p100/kr0/a5 rtp1 p101/kr1/a6 rtp2 p102/kr2/a7 rtp3 p103/kr3/a8 rtp4 p104/kr4/a9/ierx rtp5 p105/kr5/a10/ietx rtp6 p106/kr6/a11 rtp7 output yes real-time output port p107/kr7/a12 rtptrg input yes real-time output port external trigger input p06/intp5 r/w output no external read/write status output p92/wrh rxd0 p13/si1 rxd1 input yes serial receive data input for uart0 and uart1 p23/si3 remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 12 pd703037a, 703037ay, 70f3037a, 70f3037ay (3/4) pin name i/o pull function alternate function sck0 p12/scl0 note sck1 p15/asck0 sck2 p22/scl1 note sck3 i/o yes serial clock i/o (3-wire type) for csi0 to csi3 p25/asck1 sck4 i/o yes serial clock i/o (3-wire type) for variable length csi4 p34/to0/a13 scl0 p12/sck0 scl1 i/o yes serial clock i/o for i 2 c0 and i 2 c1 ( pd703037ay, 70f3037ay only) p22/sck2 sda0 p10/si0 sda1 i/o yes serial transmit/receive data i/o for i 2 c0 and i 2 c1 ( pd703037ay, 70f3037ay only) p20/si2 si0 p10/sda0 note si1 p13/rxd0 si2 p20/sda1 note si3 input yes serial receive data input (3-wire type) for csi0 to csi3 p23/rxd1 si4 input yes serial receive data input (3-wire type) for variable length csi4 p32/ti10 so0 p11 so1 p14/txd0 so2 p21 so3 output yes serial transmit data output (3-wire type) for csi0 to csi3 p24/txd1 so4 output yes serial transmit data output (3-wire type) for variable length csi4 p33/ti11 ti00 external count clock input for tm0/external capture trigger input for tm0 p30 ti01 external capture trigger input for tm0 p31 ti10 external count clock input for tm1/external capture trigger input for tm1 p32/si4 ti11 input yes external capture trigger input for tm1 p33/so4 ti2 p26/to2 ti3 p27/to3 ti4 p36/to4/a15 ti5 input yes external count clock input for tm2 to tm5 p37/to5 to0 p34/a13/sck4 to1 output yes pulse signal output for tm0 and tm1 p35/a14 to2 p26/ti2 to3 p27/ti3 to4 p36/ti4/a15 to5 output yes pulse signal output for tm2 to tm5 p37/ti5 txd0 p14/so1 txd1 output yes serial transmit data output for uart0 and uart1 p24/so3 uben output no higher byte enable output for external data bus p91 v dd ?? positive power supply pin ? note pd703037ay, 70f3037ay only. remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 13 pd703037a, 703037ay, 70f3037a, 70f3037ay (4/4) pin name i/o pull function alternate function v pp ?? high voltage apply pin for program write/verify ( pd70f3037a, 70f3037ay only) ? v ss ?? ground potential ? wait input yes control signal input for inserting wait in bus cycle p 110/a1 wrh output no higher byte write strobe signal output for external data bus p92/r/w wrl output no lower byte write strobe signal output for external data bus p90/lben x1 input ? x2 ? no resonator connection for main clock ? xt1 input ? xt2 ? no resonator connection for sub system clock ? remark pull: on-chip pull-up resistor
data sheet u14894ej2v0ds 14 pd703037a, 703037ay, 70f3037a, 70f3037ay 2.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are show in table 2-1. for the input/output schematic circuit diagram of each type, refer to figure 2-1. table 2-1. types of pin i/o circuits and recommended connection of unused pins (1/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection of unused pins p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 intp6 8-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. p10 si0/sda0 10-a p11 so0 26 p12 sck0/scl0 10-a p13 si1/rxd0 8-a p14 so1/txd0 26 p15 sck1/asck0 10-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. p20 si2/sda1 10-a p21 so2 26 p22 sck2/scl1 10-a p23 si3/rxd1 8-a p24 so3/txd1 26 p25 sck3/asck1 10-a p26 ti2/to2 p27 ti3/to3 8-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. p30 ti00 p31 ti01 p32 ti10/si4 p33 ti11/so4 p34 to0/a13/sck4 8-a p35 to1/a14 5-a p36 ti4/to4/a15 p37 ti5/to5 8-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. p40 to p47 ad0 to ad7 5 bv dd p50 to p57 ad8 to ad15 5 bv dd p60 to p65 a16 to a21 5 bv dd input state: independently connect to bv dd or bv ss via a resistor. output state: leave open.
data sheet u14894ej2v0ds 15 pd703037a, 703037ay, 70f3037a, 70f3037ay table 2-1. types of pin i/o circuits and recommended connection of unused pins (2/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection of unused pins p70 to p77 ani0 to ani7 9 av dd p80 to p83 ani8 to ani11 9 av dd independently connect to av dd or av ss via a resistor. p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq 5bv dd input state: independently connect to bv dd or bv ss via a resistor. output state: leave open. p100 rtp0/a5/kr0 p101 rtp1/a6/kr1 p102 rtp2/a7/kr2 p103 rtp3/a8/kr3 p104 rtp4/a9/kr4/ierx p105 rtp5/a10/kr5/ietx p106 rtp6/a11/kr6 p107 rtp7/a12/kr7 10-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. p110 a1/wait p111 a2 p112 a3 p113 a4 5-a ev dd input state: independently connect to ev dd or ev ss via a resistor. output state: leave open. clkout ? 4 bv dd leave open. reset ? 2 ev dd ? xt1 ? 16 ? connect to v ss via a resistor. xt2 ? 16 ? leave open. av ref ? ? ? connect to av ss via a resistor. ic note 1 ? ? ? connect directly to v ss . v pp note 2 ? ? ? connect to v ss . notes 1. pd703037a, 703037ay 2. pd70f3037a, 70f3037ay caution three power supply systems are available to supply power to the i/o buffers of the v850/sb2?s pins: ev dd , bv dd , and av dd . the voltage ranges that can be used for these i/o buffer power supplies are shown below. ev dd , bv dd : 3.0 to 5.5 v av dd : 4.5 to 5.5 v the electrical specifications differ depending on whether the power supply voltage range is 3.0 to under 4.0 v, or 4.0 to 5.5 v.
data sheet u14894ej2v0ds 16 pd703037a, 703037ay, 70f3037a, 70f3037ay figure 2-1. pin input/output circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics push-pull output that can be set for high-impedance output (both p-ch and n-ch off) in data output disable p-ch out v dd n-ch data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable data output disable p-ch in/out v dd n-ch p-ch v dd pull-up enable in comparator + ? v ref (threshold voltage) p-ch n-ch input enable type 4 type 5 type 9 type 8-a type 5-a caution v dd in the circuit diagrams can be read as ev dd , bv dd , or av dd , as appropriate.
data sheet u14894ej2v0ds 17 pd703037a, 703037ay, 70f3037a, 70f3037ay figure 2-1. pin input/output circuits (2/2) data output disable p-ch in/out v dd n-ch p-ch v dd pull-up enable open drain p-ch feedback cutoff xt1 xt2 data output disable open drain p-ch in/out v dd n-ch p-ch v dd pull-up enable type 10-a type 26 type 16 caution v dd in the circuit diagrams can be read as ev dd , bv dd , or av dd , as appropriate.
data sheet u14894ej2v0ds 18 pd703037a, 703037ay, 70f3037a, 70f3037ay 3. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol conditions ratings unit v dd v dd pin ?0.5 to +7.0 v v pp v pp pin ( pd70f3037a, 70f3037ay only) ? 0.5 to +8.5 v av dd av dd pin ?0.5 to +7.0 v bv dd bv dd pin ?0.5 to +7.0 v ev dd ev dd pin ?0.5 to +7.0 v av ss av ss pin ?0.5 to +0.5 v bv ss bv ss pin ?0.5 to +0.5 v supply voltage ev ss ev ss pin ?0.5 to +0.5 v v i1 note 1 (bv dd pin) ?0.5 to bv dd + 0.5 note 4 v input voltage v i2 note 2 , reset (ev dd pin) ?0.5 to ev dd + 0.5 note 4 v analog input voltage v ian note 3 (av dd pin) ?0.5 to av dd + 0.5 note 4 v analog reference input voltage av ref av ref pin ?0.5 to av dd + 0.5 note 4 v per pin 4.0 ma total for p00 to p07, p10 to p15, p20 to p25 25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 25 ma total for p40 to p47, p90 to p96, clkout 25 ma output current, low i ol total for p50 to p57, p60 to p65 25 ma per pin ?4.0 ma total for p00 to p07, p10 to p15, p20 to p25 ?25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 ?25 ma total for p40 to p47, p90 to p96, clkout ?25 ma output current, high i oh total for p50 to p57, p60 to p65 ?25 ma v o1 note 1 , clkout (bv dd pin) ?0.5 to bv dd + 0.5 note 4 v output voltage v o2 note 2 (ev dd pin) ?0.5 to ev dd + 0.5 note 4 v normal operation mode ?40 to +85 c operating ambient temperature t a flash memory programming mode ( pd70f3037a, 70f3037ay only) ?20 to +85 c pd703037a, 703037ay ?65 to +150 c storage temperature t stg pd70f3037a, 70f3037ay ?40 to + 125 c notes 1. ports 4, 5, 6, 9, and their alternate-function pins 2. ports 0, 1, 2, 3, 10, 11, and their alternate-function pins 3. ports 7, 8, and their alternate-function pins 4. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage.
data sheet u14894ej2v0ds 19 pd703037a, 703037ay, 70f3037a, 70f3037ay cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. capacitance (t a = 25 c, v dd = av dd = bv dd = ev dd = v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions (1) operating frequency av dd operating frequency (f xx )v dd note 1 note 2 bv dd ev dd remark 2 to 13 mhz 4.0 to 5.5 v 4.5 to 5.5 v 4.0 to 5.5 v 3.0 to 5.5 v 3.0 to 5.5 v note 3 other than idle mode 4.0 to 5.5 v 4.5 to 5.5 v 4.0 to 5.5 v 3.0 to 5.5 v 3.0 to 5.5 v ? 32.768 khz idle mode 3.5 to 5.5 v ? 4.0 to 5.5 v 3.0 to 5.5 v 3.0 to 5.5 v note 4 notes 1. when a/d converter is used 2. when a/d converter is not used 3. during stop mode (when only watch timer is operating), v dd = 3.5 to 5.5 v. shifting to stop mode or restoring from stop mode must be performed at v dd = 4.0 v min. 4. shifting to idle mode or restoring from idle mode must be performed at v dd = 4.0 v min. (2) cpu operating frequency parameter symbol conditions min. typ. max. unit main clock operation 0.25 13 mhz cpu operating frequency f cpu subclock operation 32.768 khz
data sheet u14894ej2v0ds 20 pd703037a, 703037ay, 70f3037a, 70f3037ay recommended oscillator (1) main clock oscillator (t a = ?40 to +85 c) (a) connection of ceramic resonator or crystal resonator x2 x1 c2 rf rd c1 parameter symbol conditions min. typ. max. unit oscillation frequency f xx 213mhz ? upon reset release 2 19 /f xx s oscillation stabilization time ? upon stop mode release note s note the typ. value differs depending on the setting of the oscillation stabilization time select register (osts). cautions 1. the main clock oscillator operates on the output voltage of the on-chip regulator (3.0 v). external clock input is prohibited. 2. when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. sufficiently evaluate the matching between the pd703037a, 703037ay, 70f3037a, 70f3037ay and the resonator.
data sheet u14894ej2v0ds 21 pd703037a, 703037ay, 70f3037a, 70f3037ay (b) ceramic resonator (t a = ?40 to +85 c) recommended circuit constant oscillation voltage range manufacturer part number oscillation frequency f xx (mhz) c1 (pf) c2 (pf) rf (k ? )rd (k ? ) min. (v) max. (v) cstls6m29g53-b0 6.290 on-chip on-chip ? 04.05.5 cstcr6m29g53-r0 on-chip on-chip ? 04.05.5 cstla12m5t55001-b0 12.583 on-chip on-chip ? 04.05.5 murata mfg. co., ltd. cstcv12m5t54j01-r0 on-chip on-chip ? 04.05.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use. (2) subclock oscillator (t a = ?40 to +85 c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32 32.768 35 khz oscillation stabilization time ? 10 s cautions 1. the subclock oscillator operates on the output voltage of the on-chip regulator (3.0 v). external clock input is prohibited. 2. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? ? ? ? keep the wiring length as short as possible. ? ? ? ? do not cross the wiring with the other signal lines. ? ? ? ? do not route the wiring near a signal line through which a high fluctuating current flows. ? ? ? ? always make the ground point of the oscillator capacitor the same potential as v ss . ? ? ? ? do not ground the capacitor to a ground pattern through which a high current flows. ? ? ? ? do not fetch signals from the oscillator. 3. sufficiently evaluate the matching between the pd703037a, 703037ay, 70f3037a, 70f3037ay and the resonator.
data sheet u14894ej2v0ds 22 pd703037a, 703037ay, 70f3037a, 70f3037ay dc characteristics (t a = ?40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, av dd = 4.5 to 5.5 v (when a/d converter is used), av dd = 4.0 to 5.5 v (when a/d converter is not used), v ss = av ss = bv ss = ev ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit 4.0 v bv dd 5.5 v 0.7bv dd bv dd v v ih1 note 1 3.0 v bv dd < 4.0 v 0.8bv dd bv dd v 4.0 v ev dd 5.5 v 0.7ev dd ev dd v v ih2 note 2 3.0 v ev dd < 4.0 v 0.8ev dd ev dd v 4.0 v ev dd 5.5 v 0.7ev dd ev dd v v ih3 note 3 , reset 3.0 v ev dd < 4.0 v 0.8ev dd ev dd v input voltage, high v ih4 note 4 0.7av dd av dd v v il1 note 1 bv ss 0.3bv dd v v il2 note 2 ev ss 0.3ev dd v v il3 note 3 , reset ev ss 0.3ev dd v input voltage, low v il4 note 4 av ss 0.3av dd v 3.0 v bv dd 5.5 v, i oh = ? 100 a bv dd ? 0.5 v v oh1 note 1 , clkout 4.0 v bv dd 5.5 v, i oh = ? 3 ma bv dd ? 1.0 v 3.0 v ev dd 5.5 v, i oh = ? 100 a ev dd ? 0.5 v output voltage, high v oh2 notes 2, 3 4.0 v ev dd 5.5 v, i oh = ? 3 ma ev dd ? 1.0 v i ol = 3 ma, 3.0 v bv dd , ev dd 5.5 v 0.5 v output voltage, low v ol i ol = 3 ma, 4.0 v bv dd , ev dd 5.5 v 0.4 v v pp power supply voltage v pp1 normal operation 0 0.54 v input leakage current, high i lih v i = v dd = bv dd = ev dd = av dd 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = bv dd = ev dd = av dd 5 a output leakage current, low i lol v o = 0 v ? 5 a notes 1. ports 4, 5, 6, 9, and their alternate-function pins 2. p11, p14, p21, p24, p34, p35, p110 to p113, and their alternate-function pins 3. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, p100 to p107, and their alternate-function pins 4. ports 7, 8, and their alternate-function pins
data sheet u14894ej2v0ds 23 pd703037a, 703037ay, 70f3037a, 70f3037ay dc characteristics (t a = ?40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, av dd = 4.5 to 5.5 v (when a/d converter is used), av dd = 4.0 to 5.5 v (when a/d converter is not used), v ss = av ss = bv ss = ev ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i dd1 in normal operation mode note 1 15 25 ma i dd2 in halt mode note 1 613ma i dd3 in idle mode note 2 watch timer operating 1 4 ma watch timer, subclock oscillator operating 13 70 a i dd4 in stop mode subclock oscillator stopped, xt1 = v ss 870 a i dd5 in normal operation mode (subclock operation) note 3 50 150 a pd703037a, pd703037ay i dd6 in idle mode (subclock operation) note 3 13 70 a i dd1 in normal operation mode note 1 30 58 ma i dd2 in halt mode note 1 920ma i dd3 in idle mode note 2 watch timer operating 1 4 ma watch timer, subclock oscillator operating 13 100 a i dd4 in stop mode subclock oscillator stopped, xt1 = v ss 8 100 a i dd5 in normal operation mode (subclock operation) note 3 300 900 a supply current pd70f3037a, pd70f3037ay i dd6 in idle mode (subclock operation) note 3 170 340 a pull-up resistance r l v in = 0 v 10 30 100 k ? notes 1. f cpu = f xx = 13 mhz, all peripheral functions operating 2. f xx = 13 mhz 3. f cpu = f xt = 32.768 khz, main clock oscillator stopped remark typ. values are reference values for when t a = 25 c, v dd = bv dd = ev dd = av dd = 5.0 v. the current consumed by the output buffer is not included.
data sheet u14894ej2v0ds 24 pd703037a, 703037ay, 70f3037a, 70f3037ay data retention characteristics (t a = ?40 to +85 c, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode (all functions not operating) 2.7 note 5.5 v pd703037a, pd703037ay 870 a data retention current i dddr v dd = v dddr , xt1 = v ss (subclock stopped) pd70f3037a, pd70f3037ay 8 100 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time (from stop mode setting) t hvd 0ms stop mode release signal input time t drel 0ms data retention high-level input voltage v ihdr all input ports 0.9v dddr v dddr v data retention low-level input voltage v ildr all input ports 0 0.1v dddr v note during stop mode (when only watch timer is operating), v dd = 3.5 to 5.5 v. shifting to stop mode or restoring from stop mode must be performed at v dd = 4.0 v min. remark typ. values are reference values for when t a = 25 c. t hvd v dddr t drel v ihdr v ihdr t fvd t rvd v dd stop mode release interrupt (nmi, etc.) (release by falling edge) stop mode release interrupt (nmi, etc.) (release by rising edge) setting stop mode reset (input) v ildr 4.0 v note note v dd = 4.0 v indicates the minimum operating voltage of the v850/sb2.
data sheet u14894ej2v0ds 25 pd703037a, 703037ay, 70f3037a, 70f3037ay ac characteristics (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, av dd = 4.5 to 5.5 v (when a/d converter is used), av dd = 4.0 to 5.5 v (when a/d converter is not used), v ss = av ss = bv ss = ev ss = 0 v) ac test input test point (v dd : ev dd , bv dd , av dd ) v dd 0 v v ih v il v ih v il measurement points input signal ac test output test points (v dd : ev dd , bv dd ) v oh v ol v oh v ol measurement points output signal v dd 0 v load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
data sheet u14894ej2v0ds 26 pd703037a, 703037ay, 70f3037a, 70f3037ay (1) clock timing (a) t a = ? 40 to +85 c, v dd = bv dd = 4.0 to 5.5 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 76.9 ns 31.2 s clkout high-level width <2> t wkh 0.4t cyk ? 12 ns clkout low-level width <3> t wkl 0.4t cyk ? 12 ns clkout rise time <4> t kr 12 ns clkout fall time <5> t kf 12 ns (b) t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = 3.0 to 4.0 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v parameter symbol conditions min. max. unit clkout output cycle <1> t cyk 76.9 ns 31.2 s clkout high-level width <2> t wkh 0.4t cyk ? 15 ns clkout low-level width <3> t wkl 0.4t cyk ? 15 ns clkout rise time <4> t kr 15 ns clkout fall time <5> t kf 15 ns clkout (output) <2> <4> <5> <3> <1>
data sheet u14894ej2v0ds 27 pd703037a, 703037ay, 70f3037a, 70f3037ay (2) output waveform (other than port 4, port 5, port 6, port 9, and clkout) (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit output rise time <6> t or 20 ns output fall time <7> t of 20 ns <7> <6> output signal (3) reset timing (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit reset pin high-level width <8> t wrsh 500 ns reset pin low-level width <9> t wrsl 500 ns <8> <9> reset (input)
data sheet u14894ej2v0ds 28 pd703037a, 703037ay, 70f3037a, 70f3037ay (4) bus timing (a) clock asynchronous (t a = ? 40 to +85 c, v dd = bv dd = 4.0 to 5.5 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 16 ns address hold time (from astb ) <11> t hsta 0.5t ? 15 ns address float delay time from dstb <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 40 ns data input setup time from dstb <14> t sdid (1 + n)t ? 40 ns delay time from astb to dstb <15> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <16> t hdid 0ns address output time from dstb <17> t dda (1 + i)t ? 15 ns delay time from dstb to astb <18> t ddst1 0.5t ? 15 ns delay time from dstb to astb <19> t ddst2 (1.5 + i)t ? 15 ns dstb low-level width <20> t wdl (1 + n)t ? 22 ns astb high-level width <21> t wsth t ? 15 ns data output time from dstb <22> t ddod 10 ns data output setup time (to dstb ) <23> t sodd (1 + n)t ? 25 ns data output hold time (from dstb ) <24> t hdod t ? 20 ns <25> t sawt1 n 1 1.5t ? 40 ns wait setup time (to address) <26> t sawt2 n 1 (1.5 + n)t ? 40 ns <27> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <28> t hawt2 n 1 (1.5 + n)t ns <29> t sstwt1 n 1t ? 32 ns wait setup time (to astb ) <30> t sstwt2 n 1 (1 + n)t ? 32 ns <31> t hstwt1 n 1ntns wait hold time (from astb ) <32> t hstwt2 n 1 (1 + n)t ns hldrq high-level width <33> t whqh t + 10 ns hldak low-level width <34> t whal t ? 15 ns bus output delay time from hldak <35> t dhac ? 6ns delay time from hldrq to hldak <36> t dhqha1 (2n + 7.5)t + 25 ns delay time from hldrq to hldak <37> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle states inserted after a read cycle (0 or 1). 4. the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1.
data sheet u14894ej2v0ds 29 pd703037a, 703037ay, 70f3037a, 70f3037ay (b) clock asynchronous (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = 3.0 to 4.0 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit address setup time (to astb ) <10> t sast 0.5t ? 20 ns address hold time (from astb ) <11> t hsta 0.5t ? 22 ns address float delay time from dstb <12> t fda 0ns data input setup time from address <13> t said (2 + n)t ? 50 ns data input setup time from dstb <14> t sdid (1 + n)t ? 50 ns delay time from astb to dstb <15> t dstd 0.5t ? 15 ns data input hold time (from dstb ) <16> t hdid 0ns address output time from dstb <17> t dda (1 + i)t ? 15 ns delay time from dstb to astb <18> t ddst1 0.5t ? 15 ns delay time from dstb to astb <19> t ddst2 (1.5 + i)t ? 15 ns dstb low-level width <20> t wdl (1 + n)t ? 35 ns astb high-level width <21> t wsth t ? 15 ns data output time from dstb <22> t ddod 10 ns data output setup time (to dstb ) <23> t sodd (1 + n)t ? 35 ns data output hold time (from dstb ) <24> t hdod t ? 25 ns <25> t sawt1 n 1 1.5t ? 55 ns wait setup time (to address) <26> t sawt2 n 1 (1.5 + n)t ? 55 ns <27> t hawt1 n 1 (0.5 + n)t ns wait hold time (from address) <28> t hawt2 n 1 (1.5 + n)t ns <29> t sstwt1 n 1t ? 45 ns wait setup time (to astb ) <30> t sstwt2 n 1 (1 + n)t ? 45 ns <31> t hstwt1 n 1ntns wait hold time (from astb ) <32> t hstwt2 n 1 (1 + n)t ns hldrq high-level width <33> t whqh t + 10 ns hldak low-level width <34> t whal t ? 25 ns bus output delay time from hldak <35> t dhac ? 6ns delay time from hldrq to hldak <36> t dhqha1 (2n + 7.5)t + 25 ns delay time from hldrq to hldak <37> t dhqha2 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle states inserted after a read cycle (0 or 1). 4. the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1.
data sheet u14894ej2v0ds 30 pd703037a, 703037ay, 70f3037a, 70f3037ay (c) clock synchronous (t a = ? 40 to +85 c, v dd = bv dd = 4.0 to 5.5 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit delay time from clkout to address <38> t dka 019ns delay time from clkout to address float <39> t fka ? 12 10 ns delay time from clkout to astb <40> t dkst 019ns delay time from clkout to dstb <41> t dkd 019ns data input setup time (to clkout ) <42> t sidk 20 ns data input hold time (from clkout ) <43> t hkid 5ns data output delay time from clkout <44> t dkod 19 ns wait setup time (to clkout ) <45> t swtk 20 ns wait hold time (from clkout ) <46> t hkwt 5ns hldrq setup time (to clkout ) <47> t shqk 20 ns hldrq hold time (from clkout ) <48> t hkhq 5ns delay time from clkout to address float (during bus hold) <49> t dkf 19 ns delay time from clkout to hldak <50> t dkha 19 ns remark the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1. (d) clock synchronous (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = 3.0 to 4.0 v, ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit delay time from clkout to address <38> t dka 022ns delay time from clkout to address float <39> t fka ? 16 10 ns delay time from clkout to astb <40> t dkst 019ns delay time from clkout to dstb <41> t dkd 022ns data input setup time (to clkout ) <42> t sidk 20 ns data input hold time (from clkout ) <43> t hkid 5ns data output delay time from clkout <44> t dkod 22 ns wait setup time (to clkout ) <45> t swtk 24 ns wait hold time (from clkout ) <46> t hkwt 5ns hldrq setup time (to clkout ) <47> t shqk 24 ns hldrq hold time (from clkout ) <48> t hkhq 5ns delay time from clkout to address float (during bus hold) <49> t dkf 19 ns delay time from clkout to hldak <50> t dkha 19 ns remark the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1.
data sheet u14894ej2v0ds 31 pd703037a, 703037ay, 70f3037a, 70f3037ay (e) read cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) astb (output) t1 t2 tw <38> < 15 > < 20 > < 45 > dstb, rd (output) wait (input) ad0 to ad15 (i/o) < 39 > < 10 > < 43 > < 40 > t3 < 42 > < 13 > < 21 > < 16 > < 14 > < 19 > < 17 > < 18 > < 41 > < 12 > < 29 > < 31 > < 25 > < 27 > < 26 > < 28 > < 30 > < 46 > < 45 > < 46 > data address < 40 > < 11 > < 41 > < 32 > a1 to a15 (output) a16 to a21 (output) note (output) note r/w, uben, lben remarks 1. the broken lines indicate high impedance. 2. wrl and wrh are high level.
data sheet u14894ej2v0ds 32 pd703037a, 703037ay, 70f3037a, 70f3037ay (f) write cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) astb (output) t1 t2 tw <38> < 15 > < 20 > < 45 > a1 to a15 (output) a16 to a21 (output) note (output) dstb, wrl, wrh (output) wait (input) ad0 to ad15 (i/o) < 44 > < 10 > < 40 > t3 < 21 > < 23 > < 24 > < 18 > < 41 > < 22 > < 29 > < 31 > < 25 > < 27 > < 26 > < 28 > < 30 > < 46 > < 45 > < 46 > data address < 40 > < 11 > < 41 > < 32 > note r/w, uben, lben remarks 1. the broken lines indicate high impedance. 2. rd is high level.
data sheet u14894ej2v0ds 33 pd703037a, 703037ay, 70f3037a, 70f3037ay (g) bus hold timing clkout (output) th a1 to a15 (output) < 47 >< 48 > th th th ti < 47 > < 36 > < 50 >< 50 > <34> < 37 > <33> <49> <35> a16 to a21 (output) note (output) hldrq (input) hldak (output) astb (output) dstb, rd (output) wrl, wrh (output) ad0 to ad15 (i/o) data note r/w, uben, lben remark the broken lines indicate high impedance.
data sheet u14894ej2v0ds 34 pd703037a, 703037ay, 70f3037a, 70f3037ay (5) interrupt timing (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit nmi high-level width <51> t wnih 500 ns nmi low-level width <52> t wnil 500 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn high-level width <53> t with n = 6, digital noise elimination 3tsmp + 20 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn low-level width <54> t witl n = 6, digital noise elimination 3tsmp + 20 ns remarks 1. t = 1/f xx 2. tsmp = noise elimination sampling clock cycle <51> <52> nmi (input) <53> <54> intpn (input) remark n = 0 to 6
data sheet u14894ej2v0ds 35 pd703037a, 703037ay, 70f3037a, 70f3037ay (6) rpu timing (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit tin0, tin1 high-level width <55> t tihn n = 0, 1 2t sam + 20 note ns tin0, tin1 low-level width <56> t tiln n = 0, 1 2t sam + 20 note ns tim high-level width <57> t tihm m = 2 to 5 3t + 20 ns tim low-level width <58> t tilm m = 2 to 5 3t + 20 ns note t sam can select the following count clocks by setting the prmn2 to prmn0 bits of prescaler mode registers n0, n1 (prmn0, prmn1). when n = 0 (tm0), t sam = 2t, 4t, 16t, 64t, 256t, or 1/intwtni cycle when n = 1 (tm1), t sam = 2t, 4t, 16t, 32t, 128t, or 256t however, when the tin0 valid edge is selected as the count clock, t sam = 4t. remark t = 1/f xx <55> <56> tin0, tin1 (input) <57> <58> tim (input) remark n = 0, 1 m = 2 to 5 (7) asynchronous serial interface (uart0, uart1) timing (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit asckn cycle time <59> t kcy13 200 ns asckn high-level width <60> t kh13 80 ns asckn low-level width <61> t kl13 80 ns remark n = 0, 1 <60> <61> <59> asckn (input) remark n = 0, 1
data sheet u14894ej2v0ds 36 pd703037a, 703037ay, 70f3037a, 70f3037ay (8) 3-wire serial interface (csi0 to csi3) timing (a) master mode (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit sckn cycle <62> t kcy1 400 ns sckn high-level width <63> t kh1 140 ns sckn low-level width <64> t kl1 140 ns sin setup time (to sckn ) <65> t sik1 50 ns sin hold time (from sckn ) <66> t ksi1 50 ns delay time from sckn to son output <67> t kso1 60 ns remark n = 0 to 3 (b) slave mode (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit sckn cycle <62> t kcy2 400 ns sckn high-level width <63> t kh2 140 ns sckn low-level width <64> t kl2 140 ns sin setup time (to sckn ) <65> t sik2 50 ns sin hold time (from sckn ) <66> t ksi2 50 ns 4.0 v ev dd 5.5 v 70 ns delay time from sckn to son output <67> t kso2 3.0 v ev dd < 4.0 v 100 ns remark n = 0 to 3 <66> <67> <65> <62> <63> <64> remarks 1. the broken lines indicate high impedance. 2. n = 0 to 3 sckn (i/o) sin (input) son (output) input data output data
data sheet u14894ej2v0ds 37 pd703037a, 703037ay, 70f3037a, 70f3037ay (9) 3-wire variable length serial interface (csi4) timing (a) master mode (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit 4.0 v ev dd 5.5 v 200 ns sck4 cycle <68> t kcy1 3.0 v ev dd < 4.0 v 400 ns 4.0 v ev dd 5.5 v 60 ns sck4 high-level width <69> t kh1 3.0 v ev dd < 4.0 v 140 ns 4.0 v ev dd 5.5 v 60 ns sck4 low-level width <70> t kl1 3.0 v ev dd < 4.0 v 140 ns 4.0 v ev dd 5.5 v 25 ns si4 setup time (to sck4 ) <71> t sik1 3.0 v ev dd < 4.0 v 50 ns si4 hold time (from sck4 ) <72> t ksi1 20 ns delay time from sck4 to so4 output <73> t kso1 55 ns (b) slave mode (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. max. unit 4.0 v ev dd 5.5 v 200 ns sck4 cycle <68> t kcy2 3.0 v ev dd < 4.0 v 400 ns 4.0 v ev dd 5.5 v 60 ns sck4 high-level width <69> t kh2 3.0 v ev dd < 4.0 v 140 ns 4.0 v ev dd 5.5 v 60 ns sck4 low-level width <70> t kl2 3.0 v ev dd < 4.0 v 140 ns 4.0 v ev dd 5.5 v 25 ns si4 setup time (to sck4 ) <71> t sik2 3.0 v ev dd < 4.0 v 50 ns si4 hold time (from sck4 ) <72> t ksi2 20 ns 4.0 v ev dd 5.5 v 55 ns delay time from sck4 to so4 output <73> t kso2 3.0 v ev dd < 4.0 v 100 ns
data sheet u14894ej2v0ds 38 pd703037a, 703037ay, 70f3037a, 70f3037ay <68> <70> <69> <71> <72> <73> si4 (input) so4 (output) sck4 (i/o) output data input data remark the broken lines indicate high impedance.
data sheet u14894ej2v0ds 39 pd703037a, 703037ay, 70f3037a, 70f3037ay (10) i 2 c bus mode ( pd703037ay, 70f3037ay only) (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scln clock frequency ? f clk 0 100 0 400 khz bus-free time (between stop/start conditions) <74> t buf 4.7 ? 1.3 ? s hold time note 1 <75> t hd:sta 4.0 ? 0.6 ? s scln clock low-level width <76> t low 4.7 ? 1.3 ? s scln clock high-level width <77> t high 4.0 ? 0.6 ? s setup time for start/restart conditions <78> t su:sta 4.7 ? 0.6 ? s cbus compatible master 5.0 ??? s data hold time i 2 c mode <79> t hd:dat 0 note 2 ? 0 note 2 0.9 note 3 s data setup time <80> t su:dat 250 ? 100 note 4 ? ns sdan and scln signal rise time <81> t r ? 1000 20 + 0.1cb note 5 300 ns sdan and scln signal fall time <82> t f ? 300 20 + 0.1cb note 5 300 ns stop condition setup time <83> t su:sto 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter <84> t sp ?? 050ns capacitance load of each bus line ? cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sdan signal (at v ihmin. . of scln signal) in order to occupy the undefined area at the falling edge of scln. 3. if the system does not extend the scln signal ? s low-level width (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scln signal ? s low-level width: t su : dat 250 ns ? if the system extends the scln signal ? s low-level width: transmit the following data bit to the sdan line prior to the scln line release (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0, 1
data sheet u14894ej2v0ds 40 pd703037a, 703037ay, 70f3037a, 70f3037ay stop condition start condition restart condition stop condition scln (i/o) sdan (i/o) <75> <74> <76> <77> <81> <82> <79> <80> <78> <75> <84> <83> <81> <82> remark n = 0, 1 a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = av ref = 4.5 to 5.5 v, v ss = av ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution ? 10 10 10 bit adm2 = 00h 0.6 %fsr overall error note 1 ? adm2 = 01h 1.0 %fsr conversion time t conv 510 s zero-scale error note 1 ? 0.4 %fsr adm2 = 00h 0.4 %fsr full-scale error note 1 ? adm2 = 01h 0.6 %fsr adm2 = 00h 4.0 lsb integral linearity error note 2 ? adm2 = 01h 6.0 lsb adm2 = 00h 4.0 lsb differential linearity error note 2 ? adm2 = 01h 6.0 lsb analog reference voltage av ref av ref = av dd 4.5 5.5 v analog power supply voltage av dd 4.5 5.5 v analog input voltage v ian av ss av ref v av ref input current ai ref 12ma adm2 = 00h 3 6 ma av dd power supply current ai dd adm2 = 01h 4 8 ma notes 1. excluding quantization error ( 0.05 %fsr) 2. excluding quantization error ( 0.5 lsb) remarks 1. lsb: least significant bit fsr: full scale range 2. adm2: a/d converter mode register 2
data sheet u14894ej2v0ds 41 pd703037a, 703037ay, 70f3037a, 70f3037ay iebus controller characteristics (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, bv dd = ev dd = 3.0 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit 6.0 note 1 mhz iebus system clock frequency f s communication mode: fixed to mode 1 6.29 notes 1, 2 mhz notes 1. 6.0 mhz and 6.29 mhz can not be used together for the iebus system clock frequency 2. although the system clock frequency specified in the iebus specification is 6.0 mhz, operation is guaranteed at 6.29-mhz system clock in the v850/sb2. regulator (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit output stabilization time t reg stabilization capacitance c = 1 f (connected to regc pin) 1ms cautions 1. be sure to start inputting supply voltage v dd when reset = v ss = ev ss = bv ss = 0 v (the above state), and make reset high level after the t reg period has elapsed. 2. if supply voltage bv dd or ev dd is input before the t reg period has elapsed following the input of supply voltage v dd , note that data may be driven from the pins until the t reg period has elapsed because the i/o buffers ? power supply was turned on while the circuit was in an undefined state.
data sheet u14894ej2v0ds 42 pd703037a, 703037ay, 70f3037a, 70f3037ay 3.1 flash memory programming mode ( pd70f3037a, 70f3037ay only) write/erase characteristics (t a = ? ? ? ? 20 to +85 c, v dd = av dd = bv dd = ev dd = 4.5 to 5.5 v, v ss = av ss = bv ss = ev ss = 0 v) parameter symbol conditions min. typ. max. unit v pp power supply voltage v pp2 during flash memory programming 7.5 7.8 8.1 v v dd power supply current i dd when v pp = v pp2 , f xx = 13 mhz 61 ma v pp power supply current i pp v pp = v pp2 100 ma step erase time t er note 1 0.2 s overall erase time per area t era when the step erase time = 0.2 s, note 2 20 s/area write-back time t wb note 3 1ms number of write-backs per write-back command c wb when the write-back time = 1 ms, note 4 300 count/write- back command number of erase/write-backs c erwb 16 count step writing time t wr note 5 20 s overall writing time per word t wrw when the step writing time = 20 s (1 word = 4 bytes), note 6 20 200 s/word number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite, note 7 100 count/area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. the recommended setting value of the write-back time is 1 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is counted as one rewrite for both ? erase to write ? and ? write only ? . example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. when the pg-fp3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified. 2. area 0 = 000000h to 01ffffh area 2 = 040000h to 05ffffh area 1 = 020000h to 03ffffh area 3 = 060000h to 07ffffh
data sheet u14894ej2v0ds 43 pd703037a, 703037ay, 70f3037a, 70f3037ay 4. package drawing 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 ? 0.05 c d a b s
data sheet u14894ej2v0ds 44 pd703037a, 703037ay, 70f3037a, 70f3037ay 5. recommended soldering conditions the pd703037a, 703037ay, 70f3037a, and 70f3037ay should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 5-1. surface mounting type soldering conditions (1/2) (1) pd703037agf- -3ba: 100-pin plastic qfp (14 20) pd703037aygf- -3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir35-207-2 vps package peak temperature: 215 c, time: 25 to 40 seconds (at 200 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) vp15-207-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once preheating temperature: 120 c max. (package surface temperature) exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ws60-207-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u14894ej2v0ds 45 pd703037a, 703037ay, 70f3037a, 70f3037ay table 5-1. surface mounting type soldering conditions (2/2) (2) pd70f3037agf-3ba: 100-pin plastic qfp (14 20) pd70f3037aygf-3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125 c for 20 to 72 hours) ir35-203-2 vps package peak temperature: 215 c, time: 25 to 40 seconds. (at 200 c or higher), count: two times or less exposure limit: 3 days note (after that, prebake at 125 c for 20 to 72 hours) vp15-203-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once preheating temperature: 120 c max. (package surface temperature) exposure limit: 3 days note (after that, prebake at 125 c for 20 to 72 hours) ws60-203-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u14894ej2v0ds 46 pd703037a, 703037ay, 70f3037a, 70f3037ay appendix notes on target system design the following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. appendix-1. 100-pin plastic qfp (14 20) side view target system nqpack100rb yqpack100rb nexb-100-sd/rb 178 mm note in-circuit emulator option board conversion connector ie-703037-mc-em1 in-circuit emulator ie-703002-mc yqguide note yqsocket100sdn (included with ie-703002-mc) to this portion for adjusting the height (height: 3.2 mm). top view target system yqpack100rb, nqpack100rb, yqguide ie-703037-mc-em1 ie-703002-mc nexb-100-sd/rb 8 mm 20 mm pin 1 position connection condition diagram 33.2 mm 28 mm 18.5 mm 20 mm 38 mm target system nqpack100rb yqpack100rb ie-703037-mc-em1 connect to ie-703002-mc. nexb-100-sd/rb 75 mm pin 1 position
data sheet u14894ej2v0ds 47 pd703037a, 703037ay, 70f3037a, 70f3037ay notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. related document pd703034a, 703034ay, 703035a, 703035ay, 70f3035a, 70f3035ay data sheet (u14780e) the related documents in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850/sb1, v850/sb2, v850 series, and iebus are trademarks of nec corporation.
data sheet u14894ej2v0ds 48 pd703037a, 703037ay, 70f3037a, 70f3037ay regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci n en espa ? a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
data sheet u14894ej2v0ds 49 pd703037a, 703037ay, 70f3037a, 70f3037ay [memo]
data sheet u14894ej2v0ds 50 pd703037a, 703037ay, 70f3037a, 70f3037ay [memo]
data sheet u14894ej2v0ds 51 pd703037a, 703037ay, 70f3037a, 70f3037ay [memo]
pd703037a, 703037ay, 70f3037a, 70f3037ay the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: pd70f3037a, 70f3037ay the customer must judge the need for license: pd703037a, 703037ay m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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