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200 mhz spread spectrum clock synthesizer/driver with differential cpu outputs w320-03 ........................ document #: 38-07248 rev. *c page 1 of 16 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? compliant with intel ? ck-titan clock synthe- sizer/driver specifications ? multiple output clocks at different frequencies ? three pairs of differential cpu outputs, up to 200 mhz ? ten synchronous pci cl ocks, three free-running ? six 3v66 clocks ? two 48 mhz clocks ? one reference clock at 14.318 mhz ? one vch clock ? spread spectrum clocking (down spread) ? power-down features (pci_stop#, cpu_stop# pwr_dwn#) ? three select inputs (mode select & ic frequency select) ? oe and test mode support ? 56-pin ssop package and 56-pin tssop package benefits ? supports next-generation pentium ? processors using differential clock drivers ? motherboard clock generator ? support multiple cpus and a chipset ? support for pci slots and chipset ? supports agp, drcg reference and hub link ? supports usb host controller and graphic controller ? supports isa slots and i/o chip ? enables reduction of electromagnetic interference (emi) and overall system cost ? enables acpi-compliant designs ? supports up to four cpu clock frequencies ? enables ate and ?bed of nails? testing ? widely available, standard package enables lower cost logic block diagram ssop & tssop top view 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 36 35 vdd_ref 34 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 xtal_in xtal_out gnd_ref 25 26 27 28 49 52 51 50 53 56 55 54 pci0 pci5 66buff2/3v66_4 gnd_3v66 pci_stop# s2 gnd_cpu cpu_stop# pci_f2 gnd_pci gnd_3v66 vdd_core vdd_ 48 mhz mult0 vdd_cpu ref pci_f0 pci_f1 vdd_pci gnd_pci pci1 pci2 pci3 vdd_pci pci4 pci6 vdd_3v66 66buff0/3v66_2 66buff1/3v66_3 66in/3v66_5 pwr_dwn# 3v66_0 vdd_3v66 3v66_1/vch gnd_ 48 mhz dot usb gnd_iref iref cpu#2 cpu2 vdd_cpu cpu#1 cpu1 cpu#0 cpu0 s0 s1 gnd_core pwr_gd# sclk sdata w320-03 pin configurations vdd_ref cpu0:2 cpu#0:2 pci_f0:2 xtal pll ref freq x2 x1 ref vdd_pci usb (48mhz) vch_clk/ 3v66_1 osc vdd_cpu cpu_stop# sclk pci0:6 pci_stop# stop clock control stop clock control pll 1 smbus logic dot (48mhz) pwr_dwn# s0:2 vdd_48mhz sdata vdd_3v66 3v66_0 3v66_2:4/ divider network 3v66_5/ 66in pwr pwr pwr pwr pwr pll 2 pwr 66buff0:2 gate pwr_gd# /2
w320-03 ............... .........document #: 38-07248 rev. *c page 2 of 16 pin summary name pins description ref 56 3.3v 14.318 mhz clock output xtal_in 2 14.318 mhz crystal input xtal_out 3 14.318 mhz crystal input cpu, cpu# [0:2] 44, 45, 48, 49, 51, 52 differential cpu clock outputs 3v66_0 33 3.3v 66 mhz clock output 3v66_1/vch 35 3.3v selectable through smbus to be 66 mhz or 48 mhz 66in/3v66_5 24 66 mhz input to buffered 66buff and pci or 66 mhz clock from internal vco 66buff [2:0] /3v66 [4:2] 21, 22, 23 66 mhz buffered outputs from 66input or 66 mhz clocks from internal vco pci_f [0:2] 5, 6, 7, 33 mhz clocks divided down from 66input or divided down from 3v66 pci [0:6] 10, 11, 12, 13, 16, 17, 18 pci clock outputs divided down from 66input or divided down from 3v66 usb 39 fixed 48 mhz clock output dot 38 fixed 48 mhz clock output s2 40 special 3.3v 3 level input for mode selection s1, s0 54, 55 3.3v lvttl inputs for cpu frequency selection iref 42 a precision resistor is attached to this pin which is connected to the internal current reference mult0 43 3.3v lvttl input for selecting the cu rrent multiplier for the cpu outputs pwr_dwn# 25 3.3v lvttl input for power_down# (active low) pci_stop# 34 3.3v lvttl input for pci_stop# (active low) cpu_stop# 53 3.3v lvttl input for cpu_stop# (active low) pwrgd# 28 3.3v lvttl input is a level sensitive strobe used to determine when s[2:0] and multi0 inputs are valid and ok to be sampled (active low) . once pwrgd# is sampled low, the status of this output will be ignored. sdata 29 smbus compatible sdata sclk 30 smbus compatible sclk vdd_ref, vdd_pci, vdd_3v66, vdd_cpu 1, 8, 14, 19, 32, 46, 50 3.3v power supply for outputs vdd_48 mhz 37 3.3v power supply for 48 mhz vdd_core 26 3.3v power supply for pll gnd_ref, gnd_pci, gnd_3v66, gnd_iref, vdd_cpu 4, 9, 15, 20, 31, 36, 41, 47 ground for outputs gnd_core 27 ground for pll
w320-03 ............... .........document #: 38-07248 rev. *c page 3 of 16 function table [1] s2 s1 s0 cpu (mhz) 3v66[0:1] (mhz) 66buff[0:2]/3 v66[2:4] (mhz) 66in/3v66_5 (mhz) pci_f/pci (mhz) ref0(mhz) usb/dot (mhz) notes 1 0 0 66 mhz 66 mhz 66 in 66 mhz input 66 in/2 14.318 mhz 48 mhz 2, 3, 4 1 0 1 100 mhz 66 mhz 66 in 66 mhz input 66 in/2 14.318 mhz 48 mhz 2, 3, 4 1 1 0 200 mhz 66 mhz 66 in 66 mhz input 66 in/2 14.318 mhz 48 mhz 2, 3, 4 1 1 1 133 mhz 66 mhz 66 in 66 mhz input 66 in/2 14.318 mhz 48 mhz 2, 3, 4 0 0 0 66 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 2, 3, 4 0 0 1 100 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 2, 3, 4 0 1 0 200 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 2, 3, 4 0 1 1 133 mhz 66 mhz 66 mhz 66 mhz 33 mhz 14.318 mhz 48 mhz 2, 3, 4 mid 0 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 1, 5 mid 0 1 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 6, 7, 8 mid 1 0 reserved reserved reserved reserved reserved reserved reserved ? mid 1 1 reserved reserved reserved reserved reserved reserved reserved ? swing select functions mult0 board target trace/term z reference r, iref = v dd /(3*rr) output current v oh @ z 060 ? rr = 221 1%, iref = 5.00 ma i oh = 4*iref 1.0v @ 50 150 ? rr = 475 1%, iref = 2.32 ma i oh = 6*iref 0.7v @ 50 clock driver impedances buffer name v dd range buffer type impedance minimum ? typical ? maximum ? cpu, cpu# type x1 50 ref 3.135?3.465 type 3 20 40 60 pci, 3v66, 66buff 3.135?3.465 type 5 12 30 55 usb 3.135?3.465 type 3a 12 30 55 dot 3.135?3.465 type 3b 12 30 55 clock enable configuration pwr_dwn# cpu_stop# pci_stop# cpu cpu# 3v66 66buff pci_f pci usb/dot vcos/ osc 0 x x iref*2 float low low low low low off 1 0 0 iref*2 float on on on off on on 1 0 1 iref*2 float on on on on on on 1 1 0 on on on on on off on on 111onononononononon notes: 1. tclk is a test clock driven in on the xtalin input in test mode. 2. ?normal? mode of operation. 3. range of reference frequency allowed is min. = 14.316 nominal = 14.31818 mhz, max = 14.32 mhz. 4. frequency accuracy of 48 mhz must be +167ppm to match usb default. 5. mid is defined a voltage level between 1.0v and 1.8v for 3 level input functionality. low is below 0.8v. high is above 2.0v. 6. tclk is a test clock over driven on the xtal_in input during test mode. 7. required for dc output impedance verification. 8. these modes are to use the same internal dividers as the cpu = 200-mhz mode. the only change is to slow down the internal vco to allow under clock margining.
w320-03 ............... .........document #: 38-07248 rev. *c page 4 of 16 serial data interface (smbus) to enhance the flexibility and functi on of the clock synthesizer, a two signal smbus interface is provided according to the smbus specification. through th e serial data interface (sdi), various device functions such as individual clock output buffers, etc can be individually enabled or disabled. w320-03 support both block read and block write operations. the registers associated with the sdi initialize to their default setting upon power-up, and theref ore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the ability to stop after any complete byte has been transferred. indexed bytes are not allowed. a block write begins with a slave address and a write condition. the r/w bit is used by the smbus controller as a data direction bit. a zero indicates a write condition to the clock device. the slave receiver address is 11010010 (d2h). a command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. after the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. for example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count byte is required to be a minimum of one byte and a maximum of 32 bytes it may not be 0. figure 1 shows an example of a block write. a transfer is considered valid after the acknowledge bit corre- sponding to the byte count is read by the controller. data byte configuration map start bit slave address 1 1 0 1 0 0 1 0 r/w 0/1 a command code 0 0 0 0 0 0 0 0 a byte count = n a data byte 0 a . . . data byte n-1 a stop bit 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit figure 1. an example of a block write from master to slave from slave to master data byte 0: control regist er (0 = enable, 1 = disable) bit affected pin# name description type power on default bit 7 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 pci [0:6] cpu[2:0] 3v66[1:0] spread spectrum enable 0 = spread off, 1 = spread on r/w 0 bit 6 ? tbd tbd r 0 bit 5 35 3v66_1/vch vch select 66 mhz/48 mhz 0 = 66 mhz, 1 = 48 mhz r/w 0 bit 4 44, 45, 48, 49, 51, 52 cpu [2:0] cpu# [2:0] cpu_stop# reflects the current value of the external cpu_stop# pin rn/a bit 3 10, 11, 12, 13, 16, 17, 18 pci [6:0] pci_stop# (does not affect pci_f [2:0] pins) r/w n/a bit 2 ? ? s2 reflects the value of the s2 pin sampled on power-up rn/a bit 1 ? ? s1 reflects the value of the s1 pin sampled on power-up rn/a bit 0 ? ? s0 reflects the value of the s1 pin sampled on power-up rn/a
w320-03 ............... .........document #: 38-07248 rev. *c page 5 of 16 data byte 1 bit pin# name description type power on default bit 7 ? n/a cpu mult0 value r n/a bit 6 ? n/a tbd r 0 bit 5 44, 45 cpu2 cpu2# allow control of cpu2 with assertion of cpu_stop# 0 = not free running; 1 = free running r/w 0 bit 4 48, 49 cpu1 cpu1# allow control of cpu1 with assertion of cpu_stop# 0 = not free running;1 = free running r/w 0 bit 3 51, 52 cpu0 cpu0# allow control of cpu0 with assertion of cpu_stop# 0= not free running; 1 = free running r/w 0 bit 2 44, 45 cpu2 cpu2# cpu2 output enable 1 = enabled; 0 = disabled r/w 1 bit 1 48, 49 cpu1 cpu1# cpu1output enable 1 = enabled; 0= disabled r/w 1 bit 0 51, 52 cpu0 cpu0# cpu0 output enable 1 = enabled; 0 = disabled r/w 1 data byte 2 bit pin# name pin description type power on default bit 7 ? n/a n/a r 0 bit 6 18 pci6 pci6 output enable 1 = enabled; 0 = disabled r/w 1 bit 5 17 pci5 pci5 output enable 1 = enabled; 0 = disabled r/w 1 bit 4 16 pci4 pci4 output enable 1 = enabled; 0 = disabled r/w 1 bit 3 13 pci3 pci3 output enable 1 = enabled; 0 = disabled r/w 1 bit 2 12 pci2 pci2 output enable 1 = enabled; 0 = disabled r/w 1 bit 1 11 pci1 pci1 output enable 1 = enabled; 0 = disabled r/w 1 bit 0 10 pci0 pci0 output enable 1 = enabled; 0 = disabled r/w 1 data byte 3 bit pin# name pin description type power on default bit 7 38 dot dot 48-mhz output enable r/w 1 bit 6 39 usb usb 48-mhz output enable r/w 1 bit 5 7 pci_f2 allow control of pci_ f2 with assertion of pci_stop# 0 = free running; 1 = stopped with pci_stop# r/w 0 bit 4 6 pci_f1 allow control of pci_ f1 with assertion of pci_stop# 0 = free running; 1 = stopped with pci_stop# r/w 0 bit 3 5 pci_f0 allow control of pci_ f0 with assertion of pci_stop# 0 = free running; 1 = stopped with pci_stop# r/w 0 bit 2 7 pci_f2 pci_f2 output enable r/w 1 bit 1 6 pci_f1 pci_f1output enable r/w 1 bit 0 5 pci_f0 pci_f0 output enable r/w 1
w320-03 ............... .........document #: 38-07248 rev. *c page 6 of 16 data byte 4 bit pin# name pin description type power on default bit 7 -- tbd n/a r 0 bit 6 -- tbd n/a r 0 bit 5 33 3v66_0 3v66_0 output enable 1 = enabled; 0 = disabled r/w 1 bit 4 35 3v66_1/vch 3v66_1/vch output enable 1 = enabled; 0 = disabled r/w 1 bit 3 24 66in/3v66_5 3v66_5 output enable 1 = enable; 0 = disable note: this bit should be used when pin 24 is configured as 3v66_5 output. do not clear this bit when pin 24 is configured as 66in input. r/w 1 bit 2 23 66buff2 66-mhz buffered 2 output enable 1 = enabled; 0 = disabled r/w 1 bit 1 22 66buff1 66-mhz buffered 1 output enable 1 = enabled; 0 = disabled r/w 1 bit 0 21 66buff0 66-mhz buffered 0 output enable 1 = enabled; 0 = disabled r/w 1 data byte 5 bit pin# name pin description type power on default bit 7 n/a n/a r 0 bit 6 n/a n/a r 0 bit 5 66buff [2:0] tpd 66in to 66buff propagation delay control r/w 0 bit 4 66buff [2:0] r/w 0 bit 3 dot dot edge rate control r/w 0 bit 2 dot r/w 0 bit 1 usb usb edge rate control r/w 0 bit 0 usb r/w 0 byte 6: vendor id bit description type power on default bit 7 revision code bit 3 r 0 bit 6 revision code bit 2 r 0 bit 5 revision code bit 1 r 0 bit 4 revision code bit 0 r 1 bit 3 vendor id bit 3 r 0 bit 2 vendor id bit 2 r 1 bit 1 vendor id bit 1 r 0 bit 0 vendor id bit 0 r 0
w320-03 ............... .........document #: 38-07248 rev. *c page 7 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage.......... .............. ............ ..............?0.5 to +7.0v input voltage.............................................. ?0.5v to v dd +0.5 storage temperature (non-condensing)............. ............ ...............?65 ? c to +150 ? c max. soldering temperature (10 sec) ....................... +260 ? c junction temperature................................................ +150 ? c package power dissipation....... ........................................ 1 ? static discharge voltage (per mil-std-883, method 3 015) ........... ................ > 2000v operating conditions over which electrical parameters are guaranteed [9] parameter description min. max. unit v dd_ref , v dd_pci ,v dd_core , v dd_3v66, v dd_cpu, 3.3v supply voltages 3.135 3.465 v v dd_48 mhz 48-mhz supply voltage 2.85 3.465 v t a operating temperature, ambient 0 70 ? c c in input pin capacitance 5 pf c xtal xtal pin capacitance 22.5 pf c l max. capacitive load on usbclk, ref pciclk, 3v66 20 30 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz electrical characteristics over the operating range parameter description test conditions min. max. unit v ih high-level input voltage except crystal pads. threshold voltage for crystal pads = v dd /2 2.0 v v il low-level input voltage except crystal pads 0.8 v v oh high-level output voltage usb, ref, 3v66 i oh = ?1 ma 2.4 v pci i oh = ?1 ma 2.4 v v ol low-level output voltage usb, ref, 3v66 i ol = 1 ma 0.4 v pci i ol = 1 ma 0.55 v i ih input high current 0 < v in < v dd ?5 5 ma i il input low current 0 < v in < v dd ?5 5 ma i oh high-level output current cpu for i oh =6*iref configuration type x1, v oh = 0.65v 12.9 ma type x1, v oh = 0.74v 14.9 ref, dot, usb type 3, v oh = 1.00v ?29 type 3, v oh = 3.135v ?23 3v66, dot, pci type 5, v oh = 1.00v ?33 type 5, v oh = 3.135v ?33 i ol low-level output current ref, dot, usb type 3, v ol = 1.95v 29 ma type 3, v ol = 0.4v 27 3v66, pci type 5, v ol =1.95 v 30 type 5, v ol = 0.4v 38 i oz output leakage current three-state 10 ma i dd3 3.3v power supply current vdd_core/vdd3.3 = 3.465v, f cpu = 133 mhz 360 ma i ddpd3 3.3v shutdown current vdd_core/vdd3.3 = 3.465v 20 ma note: 9. multiple supplies : the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required.
w320-03 ............... .........document #: 38-07248 rev. *c page 8 of 16 switching characteristics [10] over the operating range parameter output description test conditions min. max. unit t 1 all output duty cycle [11] measured at 1.5v 45 55 % t 3 usb, ref, dot falling edge rate between 2.4v and 0.4v 0.5 2.0 ps t 3 pci,3v66 falling edge rate between 2.4v and 0.4v 1.0 4.0 v/ns t 5 3v66[0:1] 3v66-3v66 skew measured at 1.5v 500 ps t 5 66buff[0:2] 66buff-66buff skew measured at 1.5v 175 ps t 6 pci pci-pci skew measured at 1.5v 500 ps t 7 3v66,pci 3v66-pci clock jitter 3v66 leads. measured at 1.5v 1.5 3.5 ns t 9 3v66 cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 250 ps t 9 usb, dot cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 350 ps t 9 pci cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 500 ps t 9 ref cycle-cycle clock jitter measured at 1.5v t 9 = t 9a ? t 9b 1000 ps cpu 1.0v switching characteristics t 2 cpu risetime measured differential waveform from ?0.35v to +0.35v 175 467 ps t 3 cpu fall time measured differential waveform from ?0.35v to +0.35v 175 467 ps t 4 cpu cpu-cpu skew measured at crossover 150 ps t 8 cpu cycle-cycle clock jitter measured at crossover t 8 = t 8a ? t 8b 150 ps cpu rise/fall matching measured with test loads [12] 325 mv v oh cpu high-level output voltage including overshoot measured with test loads [12] 0.92 1.45 v v ol cpu low-level output voltage including undershoot measured with test loads [12] ?0.2 0.35 v v crossover cpu crossover voltage measured with test loads [12] 0.51 0.76 v cpu 0.7v switching characteristics t 2 cpu risetime measured single ended waveform from 0.175v to 0.525v 175 700 ps t 3 cpu fall time measured single ended waveform from 0.175v to 0.525v 175 700 ps t 4 cpu cpu-cpu skew measured at crossover 150 ps t 8 cpu cycle-cycle clock jitter measured at crossover t 8 = t 8a ? t 8b with all outputs running 150 ps cpu rise/fall matching measured with test loads [13, 14] 20 % v oh cpu high-level output voltage including overshoot measured with test loads [14] 0.85 v v ol cpu low-level output voltage including undershoot measured with test loads [14] ?0.15 v v crossover cpu crossover voltage measured with test loads [14] 0.28 0.43 v notes: 10. all parameters specified with loaded outputs. 11. duty cycle is measured at 1.5v when v dd = 3.3v. when v dd = 2.5v, duty cycle is measured at 1.25v. 12. the 1.0v test load is shown on test circuit page. 13. determined as a fraction of 2*(trp ? trn)/(trp +trn) wher e trp is a rising edge and trp is an intersecting falling edge. 14. the 0.7v test load is r s = 33.2 ? , r p = 49.9 ? in test circuit.
w320-03 ............... .........document #: 38-07248 rev. *c page 9 of 16 definition and application of pwrgd# signal vrm8.5 cpu 3.3v pwrgd# npn clock generator 10k 10k 10k 10k gmch s1 s0 3.3v 3.3v pwrgd# bsel0 bsel1 vtt
w320-03 ............... .......document #: 38-07248 rev. *c page 10 of 16 switching waveforms duty cycle timing t 1b (single ended output) t 1a duty cycle timing (cpu differential output) t 1b t 1a all outputs rise/fall time output t 2 v dd 0v t 3 cpu-cpu clock skew host_b host t 4 host_b host 3v66-3v66 clock skew 3v66 3v66 t 5 pci-pci clock skew pci pci t 6
w320-03 ............... ....... document #: 38-07248 rev. *c page 11 of 16 switching waveforms (continued) 3v66 pci t 7 3v66-pci clock skew t 8a t 8b cpu clock cycle-cycle jitter host_b host t 9a t 9b cycle-cycle clock jitter clk pwrdwn# assertion [15] note: 15. pci_stop# asserted low. power down rest of generator undef 66buff pci_f (apic) cpu cpu# 3v66 66in usb ref pci pwr_dwn#
w320-03 ............... .......document #: 38-07248 rev. *c page 12 of 16 pwrgd# timing diagrams pwrdwn# deassertion [15] 10-30 ? s min. 100-200 ? s max. <3ms 66buff1/gmch 66buff0,2 pci pwr_dwn# cpu cpu# 3v66 66in usb ref pci_f (apic) gnd vrm 5/12v pwrgd# vid [3:0] bsel [1:0] pwrgd# from vrm pwrgd# from npn possible glitch while clock vcc is coming up. will be gone in 0.2?0.3 ms delay. vcc cpu core pwrgd# vcc w320 clock 0.2 ? 0.3 ms delay wait for pwrgd# sample bsels clock state state 0 state 1 state 2 state 3 on off off clock vco clock outputs figure 2. cpu power before clock power on gen
w320-03 ............... .......document #: 38-07248 rev. *c page 13 of 16 figure 3. cpu powe r after clock power gnd vrm 5/12v pwrgd# vid [3:0] bsel [1:0] pwrgd# from vrm pwrgd# from vcc cpu core pwrgd# vcc w320 clock 0.2 ? 0.3 ms delay wait for pwrgd# sample bsels clock state state 0 state 1 state 2 state 3 off off clock vco clock outputs on on gen
w320-03 ............... .......document #: 38-07248 rev. *c page 14 of 16 layout example 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 6 7 13 19 20 24 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 25 26 27 28 40 39 18 41 10 31 30 29 36 35 34 33 32 37 38 fb +3.3v supply ceramic caps c1 = 10?22 f 10 ? f fb = dale ilb1206 - 300 or 2tdkacb2012l-120 or 2 murata blm21b601s 0.005 ?? f g g vddq3 c1 c5 = 0.1 ? f c6 = 10 ? f g v g v g v g v g v g v g v g g vddq3 c5 c6 ?? w320-03 g v g g g g g g g g g g g g g g g g g g g g c2 = 0.005 ? f
w320-03 ............... .......document #: 38-07248 rev. *c page 15 of 16 test circuit [16, 17] 9, 15, 20, 27, 31, 36, 41, 47 vdd_ref, vdd_pci, outputs w320-03 vdd_3v66, vdd_core vdd_48 mhz, vdd_cpu te s t nodes r s r s r p r p cpu ref,usb outputs pci,3v66 outputs 30 pf 20 pf te s t n o d e te s t n o d e 1, 8, 14, 26, 32, 37, 46, 50 0.7v test load 2 pf 2 pf ordering information ordering code package type operating range w320-03h 56-pin ssop commercial w320-03ht 56-pin ssop - tape and reel commercial w320-03x 56-pin tssop commercial w320-03xt 56-pin tssop - tape and reel commercial lead-free CYW320OXC-3 56-pin ssop commercial CYW320OXC-3t 56-pin ssop - tape and reel commercial notes: 16. each supply pin must have an individual decoupling capacitor. 17. all capacitors must be placed as close to the pins as is physically possible. 0.7v amplitude: r s = 33 ? r p = 50 ? . 9, 15, 20, 27, 31, 36, 41, 47 vdd_ref, vdd_pci, outputs w320-03 vdd_3v66, vdd_core vdd_48 mhz, vdd_cpu te s t nodes cpu ref,usb outputs pci,3v66 outputs 30 pf 20 pf te s t n o d e te s t n o d e 1, 8, 14, 26, 32, 37, 46, 50 1.0v test load 2 pf 2 pf 33 33 63.4 63.4 475 1.0v amplitude
w320-03 ............... .......document #: 38-07248 rev. *c page 16 of 16 the information in this document is believed to be accurate in all respects at the time of p ublication but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibil ity for any consequences resulti ng from the use of information included herein. additi onally, silicon laboratories assumes no res ponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon labor atories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other a pplication in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. package diagrams 56-lead shrunk small outline package o56 seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-l t s sm o pg t ii 6 mm 12 mm z56

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