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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt8020 650 mhz clock & crystal multiplier with lvds outputs november 2003 rev. 1.0.2 description the xrt8020 is a monolithic analog phase locked loop that provides a high frequency lvds clock out- put, using a low frequency crystal or reference clock. it is designed for sonet/sdh and other low jitter ap- plications.the high performance of the ic provides a very low jitter lvds clock output up to 650 mhz, while operating at 3.3 volts. the xrt8020 has a selectable 8x, 16x or 32x internal multiplier for an external crys- tal or signal source. the output enable pin provides a true disconnect for the lvds output. the very com- pact (4 x 4 mm) low inductance package is ideal for high frequency operation. applications ? gigabit ethernet ? sonet/sdh ? spi - 4 phase 2 ? 8x, 16x or 32x clock multiplier for computer and telecommunication systems features ? 575 mhz to 675 mhz operating range ? low output jitter: 9ps rms typical at 622 mhz ? on chip crystal oscillator circuit ? optimized for 15 to 40 mhz crystals ? uses parallel fundamental mode crystal ? selectable 8x, 16x or 32x multiplier ? selectable ? 1or ? 2 lvds output ? lvds output meets tia/eia 644a specification (2001) ? 3.3v 10% low power cmos: 80 mw typical ? -40c to +85c operating temperature ? extremely small 16-lead qfn package f igure 1. b lock d iagram of the xrt8020 o gnd fs1 oe agnd pd agnd (crystal) fs0 agnd 15-40 mhz crystal xtal1 xtal2 oscillator circuit & input buffer vco calibration logic phase detector charge pump loop filter vco selectable ? ? ? ? 1or ? ? ? ? 2 divider lvds output feedback divider ? ? ? ? 8, 16 or 32 voltage reference & bias generator r ext 10k w av dd av dd ov dd +3.3v 12 - 20 pf 12 - 20 pf xrt8020 outp outn
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 2 ordering information f igure 2. xrt8020 p in l ocation -(t op v iew ) p art n umber p ackage o perating t emperature r ange xrt8020il 16 - pin qfn -40 cto+85 c 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 xrt8020
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 i description .................................................................................................................... 1 applications ................................................................................................................... ...................... 1 features ....................................................................................................................... ......................... 1 figure 1. block diagram of the xrt8020 ........................................................................................ 1 ordering information ............................................................................................................ ... 2 figure 2. xrt8020 pin location - (top view) ................................................................................. 2 absolute maximum ratings ....................................................................................................................... 3 electrical characteristics ..................................................................................................................... 3 figure 3. lvds output waveforms and test circuits .................................................................... 5 1.0 calibration ................................................................................................................. ................................ 5 t able 1: f requency s election t able .............................................................................................. 5 t able 2: p ower - down and o utput tri - state selection table ....................................................... 5 2.0 crystal selection ............................................................................................................ ........................... 6 3.0 data and plots ................................................................................................................ ........................... 6 figure 4. input referenced jitter connection diagram ................................................................. 6 figure 5. simplified block diagram of the xrt8020 and pecl receiver .................................... 7 figure 6. lvds differential output ................................................................................................. .7 figure 7. pecl differential output ................................................................................................. .8 figure 8. pecl single-ended outputs (positive and negative output referenced to ground) 9 ordering information ............................................................................................. 10 r evisions ............................................................................................................................... .................. 11
xrt8020 rev. 1.0.2 650 mhz clock & crystal multiplier with lvds outputs 3 pin description absolute maximum ratings electrical characteristics p in n ame t ype d escription 1 avdd 3.3v 10% analog supply for crystal oscillator 2 agnd analog ground for crystal oscillator 3 xtal1 i crystal pin 1 or external clock input 4 xtal2 o crystal pin 2 (output drive for crystal) 5 agnd analog ground 6 rext i external bias resistor (10k w to ground) 7oe i output enable, active low ( internal 50k w pull-down to ground ) 8 pd i power down, active high (internal 50k w pull-down to ground) 9 fs1 i frequency select "1" (internal 50k w pull-down to ground) 10 fs0 i frequency select "0" (internal 50k w pull-up to vdd) 11 agnd analog ground 12 ognd output ground for lvds outputs 13 outn o lvds negative output for 50 w line 14 outp o lvds positive output for 50 w line 15 ovdd 3.3v 10% digital supply for lvds output buffer 16 avdd 3.3v 10% analog supply supply voltage -0.5 to 6.0 v v in -0.5 to 6.0 v storage temperature -65c to + 150c operating temperature -40c to + 85c esd >2,000 volts rext (1%) 10k w p arameter s ymbol m in t yp m ax u nit c onditions supply voltage v dd 3.0 3.3 3.6 v supply current i dd 25 30 ma vdd = 3.3v power save current i dd 6 ma vdd=3.3v,pd=1,oeb=0 input digital high v inh 2.0 v pins 7, 8, 9, 10 input digital low v inl 0.8 v pins 7, 8, 9, 10 crystal frequency 15 27 mhz see section 2.0 for crystal selection
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 4 crystal frequency 27 40 mhz see section 2.0 for crystal selection clock input frequency 72 85 mhz ac coupled (fs0=1, fs1=1) power on calibration time 5 ms after vdd reaches 2.8v n ote : calibration time = 16,000 clock cycles max frequency out f out 575 675 mhz 624 mhz nominal f out (see table 1) max frequency out f out 285 340 mhz 312 mhz nominal f out (see table 1) rise time t r 350 ps cl = 5pf, rl = 100 w , (20% - 80%) fall time t f 350 ps cl = 5pf, rl = 100 w , (20% - 80%) duty cycle 45 55 % lvds output differential output skew 10 ps see figure 3 output loading 100 w output voltage swing v out 250 450 mv magnitude of (outp-outn) common mode voltage v cm 1.0 1.2 1.4 v output short circuit current -5.7 -10 ma current limit to ground, v dd or vp to vn cycle-to-cycle jitter 3 ps rms, at 624 mhz cycle-to-cycle jitter 3 ps rms, at 312 mhz accumulated jitter 12 ps rms, at 624 mhz accumulated jitter 12 ps rms, 312 mhz input referenced jitter 9 ps rms at 622 mhz, see figure 4 input referenced jitter 9 ps rms at 312 mhz, see figure 4 p arameter s ymbol m in t yp m ax u nit c onditions
xrt8020 rev. 1.0.2 650 mhz clock & crystal multiplier with lvds outputs 5 f igure 3. lvds o utput w aveforms and t est c ircuits 1.0 calibration t able 1: f requency s election t able fs0 p in 10 fs1 p in 9 c rystal or c lock f requency i nternal c apacitor m ultiply r atio o utput d ivide o utput f requency 1 1 78.0 mhz clock na 8x 1 624 mhz 0 1 39.0 mhz 12 pf 16x 1 624 mhz 1 0 19.5 mhz 20 pf 32x 1 624 mhz 0 0 19.5 mhz 20 pf 32x 2 312 mhz n otes : 1. use parallel fundamental mode crystal 2. fs0 has an internal 50k w pull-up resistor to vdd 3. fs1 has an internal 50k w pull-down resistor to gnd t able 2: p ower - down and o utput tri - state selection table pd p in 8 oe p in 7 s tatus n otes : 1 x outputs tri-stated and chip powered-down 1. x" = don't care 2. pd and oe have an internal 50k w pull-down resis- tor to ground. 0 1 output tri-stated v out c l =5pf c l =5pf r l = 100 w outp outn v out v cm outp outn 50 w 50 w ldvs levels test circuit ldvs switching test circuit outp outn t r t f 80% 20% 80% 20% 0v vcm (differential) ldvs transition time waveform 0v (differential) vout 50% 50% t skew
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 6 the xrt8020 synthesizer jitter performance is optimized by calibration of its voltage controlled oscillator (vco) upon initial power application. this power on calibration procedure is automatic and completely trans- parent to the user. it is initiated automatically upon first application of vdd. in order to bring the center fre- quency of the vco close to the desired output frequency, the vco bias current is adjusted via a current dac at initial power application. the center frequency of vco is checked against input reference frequency and cal- ibrated internally to the desired output frequency value. these bias voltage trim bits are then held in latches for as long as the vdd is held above 2.7v (minimum specified operational value of vdd). the user should note following important facts about this calibration procedure for proper operation of the xrt8020: ? for proper operation of the chip and to achieve lowest jitter, the user should follow layout guidelines as described in the user guide. ? an input crystal of appropriate frequency should be connected at xtal1 and xtal2 pins before power is applied to the chip. ? all vdd pins should be tied to 3.3v 10% simultaneously. ? the power supply should turn on without bouncing below 2.0v smoothly to its specified value in no more than 50msec. ? the calibration takes place during vdd ramp up between 2.6v to 3v values. once the vdd reaches and maintains 3.0v, the chip retains the calibrated vco bias voltages in internal latches for proper operation. ? to change a widely different value of crystal or input reference frequency, it is recommended to power down the chip by bringing vdd to 0v and restarting after the change in frequency has occurred. 2.0 crystal selection it is recommended that a fundamental mode crystal be used as the timing reference of the xrt8020. the fol- lowing part has been qualified by exar: citizen quartz crystals 20 mhz : hcm49-20.000mabjt 40 mhz : hcm49-40.000mabjt 3.0 data and plots all plots were recorded using the following parameters and test setup: ? vdd = 3.3 v ? 2 100 w differential transmission lines (from lvds outputs to receiver inputs) ? fundamental mode crystal of 20 mhz ? vref = 1.5 v (pecl receiver) f igure 4. i nput r eferenced j itter c onnection d iagram xrt8020 channel 1 channel 2 max9111esa tektronix tds7404 tektronix p6330 differential probe tektronix p6245 tds 500/600 outp outn 20.0mhz crystal
xrt8020 rev. 1.0.2 650 mhz clock & crystal multiplier with lvds outputs 7 f igure 5. s implified b lock d iagram of the xrt8020 and pecl r eceiver f igure 6. lvds d ifferential o utput xrt8010/20 clock synthesizer lvds-to-pecl receiver 100ohm transmission lines freq 640.1 mhz ampl 824.0 mv ch1 200 mv m 500 ps lvds differential outputs
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 8 f igure 7. pecl d ifferential o utput freq 640.0 mhz ampl 1.42 v ch1 500 mv m 500 ps pecl differential outputs
xrt8020 rev. 1.0.2 650 mhz clock & crystal multiplier with lvds outputs 9 f igure 8. pecl s ingle -e nded o utputs (p ositive and n egative o utput r eferenced to g round ) freq(1) 640.3 mhz ampl(1) 520.0 mv ch1 200 mv m 500 ps pecl single-ended outputs ch2 200mv freq(2) 639.9 mhz ampl(2) 528.0 mv pos output neg output
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 10 ordering information package dimensions p art n umber p ackage o perating t emperature r ange xrt8020il 16-lead qfn -40 cto+85 c 16 lead quad flat no lead (4 mm x 4 mm, 0.65 pitch qfn) note: the control dimension is in millimeter. min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a2 0.000 0.039 0.00 1.00 d 0.154 0.161 3.90 4.10 d1 0.144 0.152 3.65 3.85 d2 0.088 0.100 2.24 2.54 b 0.009 0.015 0.23 0.38 e 0.0256 bsc 0.65 bsc l 0.014 0.030 0.35 0.75 q 0 12 0 12 symbol inches millimeters q rev. 1.01 note: the actual center pad ismetallicandthesize(d2) is device-dependent w/ a typical tolerance of 0.3mm
xrt8020 650 mhz clock & crystal multiplier with lvds outputs rev. 1.0.2 11 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2003 exar corporation datasheet november 2003. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revisions p1.0.1 accumulated output jitter in electrical specs changed from 25 ps @ 624mhz to 20 @ 622mhz and tbd to 20 ps @312mhz. pin 9 has internal a pull-down resistor instead of pull-up. table 1 fs0 and fs1 bit pattern changed. p1.0.2 changed typical jitter to 6ps and changed package to qfn p1.0.3 corrected package dimension dimension "e" to 0.65 mm bsc. updated electrical tables. added de- scriptive sections on calibration, crystal selection and data and plots. 1.0.0 final release. added intrinsic jitter measurements to the electrical characteristics. 1.0.1 changed the page numbering. changed the qlp to qfn in the features on page 1. 1.0.2 changed the package drawing and dimensions.
xrt8020 -650 mhz high-speed clock synthesizer home news careers investor relations contact us partnernet login search communications interface power management support info request how to order samples how to buy design technical documentation technical faqs product finder product tree technical support packaging evaluation boards cross references product change notifications obsolescence communications brochure storage brochure ibis models bsdl xrt8020 print this page 650 mhz high-speed clock synthesizer features l 575 mhz to 675 mhz operating range l low output jitter: m 9ps rms typical at 622 mhz l on chip crystal oscillator circuit m optimized for 15 to 40 mhz crystals m uses parallel fundamental mode crystal l selectable 8x, 16x or 32x multiplier l selectable 1 or 2 lvds output l lvds output meets tia/eia 644a specification (2001) l 3.3v 10% low power cmos: 80 mw typical l -40c to +85c operating temperature l extremely small 16-lead qfn package l pb-free, rohs compliant versions offered applications l sonet/sdh l gigabit ethernet l spi - 4 phase 2 bus interfaces l voltage controlled crystal oscillator (vcxo) description the xrt8020 is a high-speed clock synthesizer that provides a high frequency low voltage differential swing (lvds) clock output, using a low frequency crystal or reference clock. the device produces clock signals up to 650 mhz by multiplying the output of a standard crystal (ranging from 20 to 40 mhz), and can generate from a clock signal input up to 80mhz. the device utilizes an analog phase locked loop that provides the clock multiplication function (8x, 16x or 32x), and when combined with the crystal frequency augments the output frequency. also, the output can be divided by a factor of two allowing the xrt8020 to cover a wider frequency range. jitter jitter is an important consideration with any clock. different systems will have different requirements for jitter. the xrt8020 is specifications mult ratio 8, 16, 32 pwr sup 3.3v pkgs qfn-16 documents datasheets datasheet version 1.0.2 november 2003 461.57 kb schematics evaluation board schematic version 1.0.0 january 2004 16.14 kb http://www.exar.com/common/content/productdetails.aspx?id=66&parentid=3 (1 of 2) [31-jul-09 1:47:19 pm]
xrt8020 -650 mhz high-speed clock synthesizer quality and reliability quality & reliability homepage material declaration sheets quality manual quarterly quality & reliability report rohs-green solutions capable of attaining 10 ps of jitter at 624 mhz. jitter levels this low allow the device to be designed into many high-speed clock circuits where tolerance for high jitter levels eliminates other solutions. power the ic operates from 3.3v and comes in a low inductance package that is available over the industrial temperature range. also, the part has auto vco (voltage controlled crystal oscillator) calibration logic on power-up that provides stability over wide frequency ranges. reduced package size at 16-pin qlp, the xrt8020 is one of the smallest clock synthesizers in the market. this capability makes it ideal for both oems, and hybrid manufacturers that combine timing components onto a single pc-board module offering pre-tested off-the-shelf timing solutions. part number pkg code rohs min temp. (c) max temp. (c) status buy now order samples xrt8020il-f qfn16 -40 85 active ? 2000-2009 exar corporation, fremont california, u.s.a. terms of use | site map http://www.exar.com/common/content/productdetails.aspx?id=66&parentid=3 (2 of 2) [31-jul-09 1:47:19 pm]

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