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agilent hmpp-389x series minipak surface mount rf pin switch diodes data sheet description/applications these ultra-miniature products represent the blending of agilent technologies proven semiconduc- tor and the latest in leadless packaging technology. the hmpp-389x series is optimized for switching applications where low resistance at low current and low capacitance are required. the minipak package offers reduced parasitics when compared to conventional leaded diodes, and lower thermal resistance. features surface mount minipak package C low height, 0.7 mm (0.028") max. C small footprint, 1.75 mm 2 (0.0028 inch 2 ) better thermal conductivity for higher power dissipation single and dual versions matched diodes for consistent performance low capacitance low resistance at low current low fit (failure in time) rate* six-sigma quality level * for more information, see the surface mount schottky reliability data sheet. pin connections and package marking 3 2 product code date code 4 aa 1 package lead code identification (top view) single 3 2 4 1 #0 anti-parallel 3 2 4 1 #2 parallel 3 2 4 1 #5 shunt switch 3 2 4 1 t anode cathode cathode anode low junction capacitance of the pin diode chip, combined with ultra low package parasitics, mean that these products may be used at frequencies which are higher than the upper limit for conven- tional pin diodes. note that agilent s manufacturing techniques assure that dice packaged in pairs are taken from adjacent sites on the wafer, assuring the highest degree of match. the hmpp-389t low inductance wide band shunt switch is well suited for applications up to 6 ghz. notes: 1. package marking provides orientation and identification. 2. see electrical specifications for appropriate package marking.
2 hmpp-389x series absolute maximum ratings [1] , t c = 25 c symbol parameter units value i f forward current (1 s pulse) amp 1 p iv peak inverse voltage v 100 t j junction temperature c 150 t stg storage temperature c -65 to +150 jc thermal resistance [2] c/w 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25 c, where t c is defined to be the temperature at the package pins where contact is made to the circuit board. electrical specifications, t c = +25 c, each diode part number package minimum breakdown maximum series maximum total hmpp- marking code lead code configuration voltage (v) resistance ( ? ) capacitance (pf) 3890 d 0 single 100 2.5 0.30 3892 c 2 anti-parallel 3895 b 5 parallel 389t t t shunt switch test conditions v r = v br i f = 5 ma v r = 5v measure i r 10 a f = 100 mhz f = 1 mhz esd warning: handling precautions should be taken to avoid static discharge. typical parameters, t c = +25 c part number series resistance carrier lifetime total capacitance hmpp- r s ( ? ) (ns) c t (pf) 389x 3.8 200 0.20 @ 5 v test conditions i f = 1 ma i f = 10 ma f = 100 mhz i r = 6 ma
3 hmpp-389x series typical performance, t c = 25 c, each diode typical applications rf common rf 1 1 2 3 4 bias 1 rf 2 bias 2 rf common rf 2 bias rf 1 2 34 1 2 3 4 1 figure 6. simple spdt switch using only positive bias. figure 7. high isolation spdt switch using dual bias. 120 115 110 105 100 95 90 85 11030 i f ?forward bias current (ma) figure 3. 2nd harmonic input intercept point vs. forward bias current. input intercept point (dbm) diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 04 8121620 v r ?reverse voltage (v) total capacitance (pf) 1 mhz 1 ghz figure 2. capacitance vs. reverse voltage. 200 160 120 80 40 0 10 20 15 25 30 t rr ?reverse recovery time (ns) forward current (ma) figure 4. typical reverse recovery time vs. reverse voltage. v r = 2v v r = 5v v r = ?0v 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f ?forward current (ma) v f ?forward voltage (v) figure 5. forward current vs. forward voltage. 125 c 25 c ?0 c intercept point will be higher at higher frequencies figure 1. total rf resistance at 25 c vs. forward bias current. 10 1 rf resistance (ohms) i f ?forward bias current (ma) 0.1 1 10 100
4 applications information pin diodes in rf and microwave networks, mechanical switches and attenua- tors are bulky, often unreliable, and difficult to manufacture. switch ics, while convenient to use and low in cost in small quantities, suffer from poor distortion performance and are not as cost effective as pin diode switches and attenuators in very large quantities. for over 30 years, designers have looked to the pin diode for high performance/low cost solutions to their switching and level control needs. in the rf and microwave ranges, the switch serves the simple purpose which is implied by its name; it operates between one of two modes, on or off. in the on state, the switch is designed to have the least possible loss. in the off state, the switch must exhibit a very high loss (isolation) to the input signal, typically from 20 to 60 db. the attenuator, however, serves a more complex function. it provides for the soft or controlled variation in the power level of a rf or microwave signal. at the same time as it attenuates the input signal to some predeter- mined value, it must also present a matched input impedance (low vswr) to the source. every microwave network which uses pin diodes (phase shifter, modula- tor, etc.) is a variation on one of these two basic circuits. one can see that the switch and the attenuator are quite different in their function, and will there- fore often require different characteristics in their pin diodes. these properties are easily controlled through the way in which a pin diode is fabricated. see figure 9. bulk attenuator diode epi switching diode p+ diffusion bulk i-layer n+ diffusion metal contact contact over p+ diffusion n+ substrate epi i-layer figure 9. pin diode construction. rf common rf 2 rf 1 bias 2 3 4 1 2 3 4 1 3 4 1 2 figure 8. very high isolation spdt switch, dual bias. diode construction at agilent technologies, two basic methods of diode fabrication are used. in the case of bulk diodes, a wafer of very pure (intrinsic) silicon is heavily doped on the top and bottom faces to form p and n regions. the result is a diode with a very thick, very pure i region. the epitaxial layer (or epi) diode starts as a wafer of heavily doped silicon (the p or n layer), onto which a thin i layer is grown. after the epitaxial growth, diffu- sion is used to add a heavily doped (n or p) layer on the top of the epi, creating a diode with a very thin i layer populated by a relatively large number of imperfections. these two different methods of design result in two classes of diode with distinctly different characteristics, as shown in table 1. as we shall see in the following paragraphs, the bulk diode is almost always used for attenuator applications and sometimes as a switch, while the epi diode (such as the hmpp-3890) is generally used as a switching element. diode lifetime and its implications the resistance of a pin diode is controlled by the conductivity (or resistivity) of the i layer. this conductivity is controlled by the density of the cloud of carriers (charges) in the i layer (which is, in turn, controlled by the dc bias). minority carrier lifetime, indicated by the greek symbol , is a table 1. bulk and epi diode characteristics. characteristic epi diode bulk diode lifetime short long distortion high low current required low high i region thickness very thin thick
5 measure of the time it takes for the charge stored in the i layer to decay, when forward bias is replaced with reverse bias, to some predetermined value. this lifetime can be short (35 to 200 nsec. for epitaxial diodes) or it can be relatively long (400 to 3000 nsec. for bulk diodes). lifetime has a strong influence over a number of pin diode parameters, among which are distortion and basic diode behavior. to study the effect of lifetime on diode behavior, we first define a cutoff frequency f c = 1/ . for short lifetime diodes, this cutoff fre- quency can be as high as 30 mhz while for our longer lifetime diodes f c ? 400 khz. at frequen- cies which are ten times f c (or more), a pin diode does indeed act like a current controlled variable resistor. at frequencies which are one tenth (or less) of f c , a pin diode acts like an ordinary pn junction diode. finally, at 0.1f c f 10f c , the behavior of the diode is very complex. suffice it to mention that in this frequency range, the diode can exhibit very strong capacitive or inductive reactance it will not behave at all like a resistor. however, at zero bias or under heavy forward bias, all pin diodes demonstrate very high or very low impedance (respectively) no matter what their lifetime is. diode resistance vs. forward bias if we look at the typical curves for resistance vs. forward current for bulk and epi diodes (see figure 10), we see that they are very different. of course, these curves apply only at frequencies > 10 f c . one can see that the curve of resistance vs. bias current for the bulk diode is much higher than that for the epi (switching) diode. figure 11. linear equivalent circuit of the minipak pin diode. thus, for a given current and junction capacitance, the epi diode will always have a lower resistance than the bulk diode. the thin epi diode, with its physically small i region, can easily be saturated (taken to the point of minimum resistance) with very little current compared to the much larger bulk diode. while an epi diode is well saturated at currents around 10 ma, the bulk diode may require upwards of 100 ma or more. moreover, epi diodes can achieve reasonable values of resistance at currents of 1 ma or less, making them ideal for battery operated applications. having compared the two basic types of pin diode, we will now focus on the hmpp-3890 epi diode. given a thin epitaxial i region, the diode designer can trade off the device s total resistance (r s + r j ) and junction capacitance (c j ) by varying the diameter of the contact and i region. the hmpp-3890 was designed with the 930 mhz cellular and rfid, the 1.8 ghz pcs and 2.45 ghz rfid markets in mind. combining the low resistance shown in figure 10 with a typical total capacitance of 0.27 pf, it forms the basis for high performance, low cost switching networks. 1000 100 10 1 resistance ( ? ) bias current (ma) 0.01 0.1 1 10 100 hmpp-389x epi pin diode hsmp-3880 bulk pin diode figure 10. resistance vs, forward bias. linear equivalent circuit in order to predict the perfor- mance of the hmpp-3890 as a switch, it is necessary to construct a model which can then be used in one of the several linear analysis programs presently on the market. such a model is given in figure 11, where r s + r j is given in figure 1 and c j is provided in figure 2. careful examination of figure 11 will reveal the fact that the package parasitics (inductance and capacitance) are much lower for the minipak than they are for leaded plastic packages such as the sot-23, sot-323 or others. this will permit the hmpp-389x family to be used at higher fre- quencies than its conventional leaded counterparts. 30 ff 30 ff 20 ff 20 ff 1.1 nh single diode package (hmpp-3890) 2 3 1 4 30 ff 30 ff 20 ff 20 ff 12 ff 12 ff 0.5 nh anti-parallel diode package (hmpp-3892) 2 3 1 4 0.5 nh 0.05 nh 0.5 nh 0.05 nh 0.05 nh 0.5 nh 0.05 nh 30 ff 30 ff 20 ff 20 ff 0.5 nh 0.05 nh parallel diode package (hmpp-3895) 2 3 1 4 0.5 nh 0.05 nh 0.5 nh 0.05 nh 0.5 nh 0.05 nh
6 testing the hmpp-389t on the demo-board introduction the hmpp-389t pin diode is a high frequency shunt switch. it has been designed as a smaller and higher performance version of the hsmp-389t (sc-70 package). the demo-hmpp-389t demo- board allows customers to evalu- ate the performance of the hmpp-389t without having to fabricate their own pcb. since a shunt switch s isolation is limited primarily by its parasitic induc- tance, the product s true potential cannot be shown if a conventional microstrip pcb is used. in order to overcome this problem, a coplanar waveguide over ground-plane structure is used for the demo- board. the bottom ground-plane is connected to the upper ground traces using multiple via-holes. a 50 ? reference line is provided at the top to calibrate the board loss. the bottom line allows the hmpp-389t diode to be tested as a shunt switch. demo-board preparation since the performance of the shunt switch is ultimately limited by the demo-board, a short discussion of the constructional aspects will be beneficial. edge- mounted sma connectors (johnson #142-0701-881) were mounted on both the reference and test lines. a special mounting technique has been used to minimize reflection at the pcb to connector interface. prior to mounting, the connector pins were cut down to two pin diam- eters in length. subsequently, the connector fingers were soldered to the upper ground plane (figure 13). solder was filled between the connector body and fingers on the lower ground plane until the small crescent of exposed teflon was completely covered (figure 14). figure 13. soldering details of connector fingers to upper ground plane. figure 14. soldering details of connector fingers to lower ground plane. test results measurements of the reference line s return and insertion losses were used to gauge the effective- ness of the vswr mitigating steps. in our prototype, the worst case return loss of the reference line was 20 db at 5 ghz (figure 15). frequency (ghz) return loss (db) 16 245 3 -18 -22 -26 -30 -34 -38 figure 15. swept return loss of reference line. insertion loss of the reference was very low and generally, increased with frequency (figure 16). if the demo-board has been constructed carefully, there should not be any evidence of resonance. the reference line s insertion loss trace can be stored in the vna s display memory and used to correct for the insertion loss of the test line in the subsequent measurements. figure 12. demo-board demo-hmpp-389t. test line reference line agilent sk063a hmpp-389t
7 frequency (ghz) insertion loss (db) 0 -0.2 -0.4 -0.6 -0.8 -1.0 16 245 3 figure 16. insertion loss of reference line. to evaluate the hmpp-389t as shunt switch, it was mounted on the test line and then the appropri- ate biasing voltage was applied. in our prototype, the worst case return loss was 10 db at 5 ghz (figure 17). the return loss varied very little when the bias was changed from zero to -20v. frequency (ghz) return loss (db) -5 -15 -25 -35 -45 -55 16 245 3 figure 17. return loss of hmpp-389t mounted on test line at 0v and -20v bias. normalization was used to remove the pcb s and connectors losses from the measurement of the shunt switch s loss. the active trace was divided by the memo- rized trace (data/memory) to produce the normalized data. at zero bias, the insertion loss was under 0.6 db up to 6 ghz (figure 18). applying a reverse bias to the pin diode has the effect of reducing its parasitic capacitance. with a reverse bias of -20v, the insertion loss improved to better than 0.5 db (figure 19). frequency (ghz) insertion loss (db) 0 -0.2 -0.4 -0.6 -0.8 -1.0 16 245 3 figure 18. insertion loss of hmpp-389t at 0v. frequency (ghz) insertion loss (db) 16 245 3 0 -0.2 -0.4 -0.6 -0.8 -1.0 figure 19. insertion loss of hmpp-389t at -20v. the pin diode s resistance is a function of the bias current. so, at higher forward current, the isolation improved. the combina- tion of the hmpp-389t and the sk063a demoboard exhibited more than 17 db of isolation from 1 to 6 ghz at if 1ma (figure 20). frequency (ghz) isolation (db) -10 -14 -18 -22 -26 -30 16 2 0.15 ma 0.25 ma 0.5 ma 1 ma 1.5 ma 20 ma 45 3 figure 20. isolation at different frequencies with forward current as a parameter. the combination of the hmpp-389t and the demo-board allows a high performance shunt switch to be constructed swiftly and economically. the extremely low parasitic inductance of the package allows the switch to operate over a very wide fre- quency range.
8 assembly information the minipak diode is mounted to the pcb or microstrip board using the pad pattern shown in figure 21. 0.4 0.4 0.3 0.5 0.3 0.5 figure 21. pcb pad layout, minipak (dimensions in mm). this mounting pad pattern is satisfactory for most applications. however, there are applications where a high degree of isolation is required between one diode and the other is required. for such applications, the mounting pad pattern of figure 22 is recommended. 2.60 0.40 0.20 0.40 mm via hole (4 places) 0.8 2.40 figure 22. pcb pad layout, high isolation minipak (dimensions in mm). this pattern uses four via holes, connecting the crossed ground strip pattern to the ground plane of the board. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the minipak package, will reach solder reflow temperatures faster than those with a greater mass. agilent s diodes have been quali- fied to the time-temperature profile shown in figure 23. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporat- ing solvents from the solder paste. the reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool- down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. the maximum temperature in the reflow zone (t max ) should not exceed 255 c. these parameters are typical for a surface mount assembly process for agilent diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. time (seconds) temperature ( c) 0 0 50 100 150 200 221 300 250 350 60 90 30 preheat 130 170 c min. 60 s max. 150 s reflow time min. 60 s max. 90 s peak temperature min. 240 c max. 255 c 150 180 210 240 270 300 360 120 330 figure 23. surface mount assembly temperature profile.
9 minipak outline drawing for hmpp-3890, -3892, and -3895 1.44 (0.057) 1.40 (0.055) top view side view bottom view 1.20 (0.047) 1.16 (0.046) 0.70 (0.028) 0.58 (0.023) 1.12 (0.044) 1.08 (0.043) 0.82 (0.032) 0.78 (0.031) 0.32 (0.013) 0.28 (0.011) -0.07 (-0.003) -0.03 (-0.001) 0.00 -0.07 (-0.003) -0.03 (-0.001) 0.42 (0.017) 0.38 (0.015) 0.92 (0.036) 0.88 (0.035) 1.32 (0.052) 1.28 (0.050) 0.00 ordering information part number no. of devices container hmpp-389x-tr2 10000 13?reel hmpp-389x-tr1 3000 7?eel hmpp-389x-blk 100 antistatic bag minipak outline drawing for hmpp-389t dimensions are in millimeters (inches) bottom view 1.12 (0.044) 1.08 (0.043) 0.82 (0.032) 0.78 (0.031) 0.32 (0.013) 0.28 (0.011) -0.07 (-0.003) -0.03 (-0.001) 0.00 -0.07 (-0.003) -0.03 (-0.001) 0.42 (0.017) 0.38 (0.015) 0.92 (0.036) 0.88 (0.035) 1.32 (0.052) 1.28 (0.050) 0.00
10 device orientation tape dimensions and product orientation for outline 4t (minipak 1412) user feed direction cover tape carrier tape reel end view 8 mm 4 mm top view aa aa aa aa note: aa represents package marking code. package marking is right side up with carrier tape perforations at top. conforms to electronic industries rs-481, taping of surface mounted components for automated placement. standard quantity is 3,000 devices per reel. p p 0 p 2 f w c d 1 d e a 0 5 max. t 1 (carrier tape thickness) t t (cover tape thickness) 5 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 1.40 0.05 1.63 0.05 0.80 0.05 4.00 0.10 0.80 0.05 0.055 0.002 0.064 0.002 0.031 0.002 0.157 0.004 0.031 0.002 cavity diameter pitch position d p 0 e 1.50 0.10 4.00 0.10 1.75 0.10 0.060 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 - 0.004 0.010 0.001 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.40 0.10 0.062 0.001 0.213 0.004 0.002 0.00004 cover tape
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/international), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2002-2005 agilent technologies, inc. obsoletes 5989-3178en august 7, 2005 5989-3630en

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