View TC55VBM316ASTN55_6651867.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tc55vbm316aftn/astn40,55 2003-12-25 1/15 toshiba mos digital integrat ed circuit silicon gate cmos 524,288-word by 16-bit/1,048,576-word by 8-bit full cmos static ram description the tc55vbm316aftn/astn is a 8,388,608-bit static random access memory (sram) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. fabricated usin g toshiba's cmos silicon gate process technology, this device operates from a single 2.3 to 3.6 v power supply. advanced circuit technology provides both high speed and low power at an operating current of 3 ma/mhz and a minimum cycle time of 40 ns. it is automatically placed in low-power mode at 0.7 a standby current (at v dd = 3 v, ta = 25c, typical) when chip enable ( ce1 ) is asserted high or (ce2) is asserted low. there are three control inputs. ce1 and ce2 are used to select the device and for data retention control, and output enable ( oe ) provides fast memory access. data byte control pin ( lb , ub ) provides lower and upper byte access. this device is well suited to various microprocessor system applications where high speed, low power and battery backup are requ ired. and, with a guaran teed operating extreme temperature range of ? 40 to 85c, the tc55vbm316aftn/astn can be used in environments exhibiting extreme temperature conditions. the tc55vbm316aftn/astn is available in a plastic 48-pin thin-small-outline package (tsop). features ? low-power dissipation operating: 9 mw/mhz (typical) ? single power supply voltage of 2.3 to 3.6 v ? power down features using ce1 and ce2 ? data retention supply voltage of 1.5 to 3.6 v ? direct ttl compatibility for all inputs and outputs ? wide operating temperature range of ? 40 to 85c ? standby current (maximum): 3.6 v 10 a 3.0 v 5 a pin assignment (top view) pin names 48 pin tsop a0~a18 address inputs (word mode) a-1~a18 address inputs (byte mode) 1 ce , ce2 chip enable r/w read/write control oe output enable lb , ub data byte control i/o1~i/o16 data inputs/outputs byte word/byte mode select v dd power gnd ground nc no connection op* option *: op pin must be open or connected to gnd. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin name a15 a14 a13 a12 a11 a10 a9 a8 nc nc r/w ce2 op ub lb a18 pin no. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pin name a17 a7 a6 a5 a4 a3 a2 a1 a0 1 ce gnd oe i/o1 i/o9 i/o2 i/o10 pin no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pin name i/o3 i/o11 i/o4 i/o12 v dd i/o5 i/o13 i/o6 i/o14 i/o7 i/o15 i/o8 i/o16 /a - 1 gnd byte a16 ? access times (maximum): tc55vbm316aftn/astn 40 55 access time 40 ns 55 ns 1 ce access time 40 ns 55 ns ce2 access time 40 ns 55 ns oe access time 25 ns 30 ns ? package: tsop ? 48-p-1220-0.50 (aftn) (weight:0.51 g typ) tsop ? 48-p-1214-0.50 (astn) (weight:0.36 g typ) (normal) 25 48 24 1
tc55vbm316aftn/astn40,55 2003-12-25 2/15 block diagram ce v dd gnd i/o1 i/o8 r/w ce i/o9 i/o16 oe ub a-1 a0 a1 a2 a3 a4 clock generator a5 byte a16 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a17 a18 lb 1 ce ce2 ce i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 column address register column address decoder column address buffer memory cell array 4,096 128 16 (8,388,608) sense amp row address decoder row address buffer row address register data input buffer data input buffer data output buffer data output buffer
tc55vbm316aftn/astn40,55 2003-12-25 3/15 operating mode mode 1 ce ce2 oe r/w byte lb ub i/o1~i/o8 i/o9~i/o15 i/o16 power l h l h l * * output high-z a-1 i ddo l h l h h l l output output output i ddo l h l h h h l high-z output output i ddo read l h l h h l h output high-z high-z i ddo l h * l l * * input high-z a-1 i ddo l h * l h l l input input input i ddo l h * l h h l high-z input input i ddo write l h * l h l h input high-z high-z i ddo l h h h l * * high-z high-z a-1 i ddo l h h h h l l high-z high-z high-z i ddo l h h h h h l high-z high-z high-z i ddo output deselect l h h h h l h high-z high-z high-z i ddo h * * * h or l * * high-z high-z high-z i dds * l * * h or l * * high-z high-z high-z i dds standby * * * * h h h high-z high-z high-z i dds * = don't care h = logic high l = logic low maximum ratings symbol rating value unit v dd power supply voltage ? 0.3~4.2 v v in input voltage ? 0.3 * ~4.2 v v i/o input/output voltage ? 0.5~v dd + 0.5 v p d power dissipation 0.6 w t solder soldering temperature (10s) 260 c t stg storage temperature ? 55~150 c t opr operating temperature ? 40~85 c * : ? 2.0 v when measured at a pulse width of 20ns dc recommended operating conditions ( ta = ? 40 to 85c ) symbol parameter min typ max unit v dd power supply voltage 2.3 ? 3.6 v v dd = 2.3 v~2.7 v 2.0 v ih input high voltage v dd = 2.7 v~3.6 v 2.2 ? v dd + 0.3 v v il input low voltage ? 0.3 * ? v dd 0.24 v v dh data retention supply voltage 1.5 ? 3.6 v * : ? 2.0 v when measured at a pulse width of 20ns
tc55vbm316aftn/astn40,55 2003-12-25 4/15 dc characteristics (ta = ? 40 to 85c, v dd = 2.3 to 3.6 v) symbol parameter test condition min typ max unit i il input leakage current v in = 0 v~v dd ? ? 1.0 a i oh output high current v oh = v dd ? 0.5 v ? 0.5 ? ? ma i ol output low current v ol = 0.4 v 2.1 ? ? ma i lo output leakage current 1 ce = v ih or ce2 = v il or lb = ub = v ih or r/w = v il or oe = v ih , v out = 0 v~v dd ? ? 1.0 a min ? ? 35 l ddo1 1 ce = v il and ce2 = v ih and r/w = v ih , lb = ub = v il , i out = 0 ma, other input = v ih /v il t cycle 1 s ? ? 8 ma min ? ? 30 l ddo2 operating current 1 ce = 0.2 v and ce2 = v dd ? 0.2 v and r/w = v dd ? 0.2 v, lb = ub = 0.2 v, i out = 0 ma, other input = v dd ? 0.2 v/0.2 v t cycle 1 s ? ? 3 ma i dds1 1) 1 ce = v ih or ce2 = v il (at byte v dd ? 0.2 v or 0.2 v) 2) lb = ub = v ih (at byte v dd ? 0.2 v) ? ? 1 ma v dd = 3.3 v 0.3 v ta = ? 40~85c ? ? 10 ta = 25c ? 0.7 ? ta = ? 40~40c ? ? 2 i dds2 standby current 1) 1 ce = v dd ? 0.2 v, ce2 = v dd ? 0.2 v (at byte v dd ? 0.2 v or 0.2 v) 2) ce2 = 0.2 v (at byte v dd ? 0.2 v or 0.2 v) 3) lb = ub = v dd ? 0.2 v, 1 ce = 0.2 v, ce2 = v dd ? 0.2 v (at byte v dd ? 0.2 v) v dd = 3.0 v ta = ? 40~85c ? ? 5 a capacitance (ta = 25c, f = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf note: this parameter is periodically sampled and is not 100% tested.
tc55vbm316aftn/astn40,55 2003-12-25 5/15 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 2.7 to 3.6 v) read cycle tc55vbm316aftn/astn 40 55 symbol parameter min max min max unit t rc read cycle time 40 ? 55 ? t acc address access time ? 40 ? 55 t co1 chip enable( 1 ce ) access time ? 40 ? 55 t co2 chip enable(ce2) access time ? 40 ? 55 t oe output enable access time ? 25 ? 30 t ba data byte control access time ? 40 ? 55 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t be data byte control low to output active 5 ? 5 ? t od chip enable high to output high-z ? 20 ? 25 t odo output enable high to output high-z ? 20 ? 25 t bd data byte control high to output high-z ? 20 ? 25 t oh output data hold time 10 ? 10 ? ns write cycle tc55vbm316aftn/astn 40 55 symbol parameter min max min max unit t wc write cycle time 40 ? 55 ? t wp write pulse width 30 ? 40 ? t cw chip enable to end of write 35 ? 45 ? t bw data byte control to end of write 35 ? 45 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 20 ? 25 t oew r/w high to output active 0 ? 0 ? t ds data setup time 20 ? 25 ? t dh data hold time 0 ? 0 ? ns note: t od , t odo , t bd and t odw are specified in time when an output becom es high impedance, and are not judged depending on an output voltage level.
tc55vbm316aftn/astn40,55 2003-12-25 6/15 ac characteristics and operating conditions (ta = ? 40 to 85c, v dd = 2.3 to 3.6 v) read cycle tc55vbm316aftn/astn 40 55 symbol parameter min max min max unit t rc read cycle time 55 ? 70 ? t acc address access time ? 55 ? 70 t co1 chip enable( 1 ce ) access time ? 55 ? 70 t co2 chip enable(ce2) access time ? 55 ? 70 t oe output enable access time ? 30 ? 35 t ba data byte control access time ? 55 ? 70 t coe chip enable low to output active 5 ? 5 ? t oee output enable low to output active 0 ? 0 ? t be data byte control low to output active 5 ? 5 ? t od chip enable high to output high-z ? 25 ? 30 t odo output enable high to output high-z ? 25 ? 30 t bd data byte control high to output high-z ? 25 ? 30 t oh output data hold time 10 ? 10 ? ns write cycle tc55vbm316aftn/astn 40 55 symbol parameter min max min max unit t wc write cycle time 55 ? 70 ? t wp write pulse width 40 ? 50 ? t cw chip enable to end of write 45 ? 55 ? t bw data byte control to end of write 45 ? 55 ? t as address setup time 0 ? 0 ? t wr write recovery time 0 ? 0 ? t odw r/w low to output high-z ? 25 ? 30 t oew r/w high to output active 0 ? 0 ? t ds data setup time 25 ? 30 ? t dh data hold time 0 ? 0 ? ns note: t od , t odo , t bd and t odw are specified in time when an output becom es high impedance, and are not judged depending on an output voltage level.
tc55vbm316aftn/astn40,55 2003-12-25 7/15 ac test conditions parameter test condition input pulse level 0.2 v, v dd 0.7 v + 0.2 v t r , t f 1v / ns(fig.1) timing measurements v dd 0.5 reference level v dd 0.5 output load 30 pf + 1 ttl gate(fig.2) fig.1 : input rise and fall time fig.2 : output load function symbol parameter min max unit t bs byte setup time 5 ? ms t br byte recovery time 5 ? ms timing diagrams byte dout 30 pf r2 v tm r1 r1 = 810 ? r2 = 1610 ? v tm = 2.3 v gnd 90% 1 v/ns t r 10% 90% 10% t f v dd typ 1 v/ns byte ce2 t bs 1 ce t br byte
tc55vbm316aftn/astn40,55 2003-12-25 8/15 read cycle (see note 1) write cycle 1 (r/w controlled) (see note 4) ce2 t rc t acc t od valid data out t oe t be t bd hi-z hi-z t co1 1 ce oe t ba t coe t oh t odo t oee t co2 ub , lb address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) r/w ce2 t as t cw t wr valid data in t odw t wp t ds t dh t oew hi-z t cw 1 ce t wc t bw ub , lb (see note 3) (see note 2) (see note 5) (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode)
tc55vbm316aftn/astn40,55 2003-12-25 9/15 write cycle 2 ( controlled) (see note 4) write cycle 3 (ce2 controlled) (see note 4) ce1 r/w t wc t as t wr t wp 1 ce t cw valid data in t ds t dh t be hi-z hi-z ce2 t cw t odw t bw t coe ub , lb (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode) r/w t wc t as t wr t wp 1 ce t cw valid data in t ds t dh hi-z hi-z t cw ce2 t bw t be t coe t odw ub , lb (see note 5) address a0~a18 (word mode) a-1~a18 (byte mode) d out i/o1~16 (word mode) i/o1~8 (byte mode) d in i/o1~16 (word mode) i/o1~8 (byte mode)
tc55vbm316aftn/astn40,55 2003-12-25 10/15 write cycle 4 ( , controlled) (see note 4) note: (1) r/w remains high for the read cycle. (2) if ce1 (or ub or lb ) goes low(or ce2 goes high) coincide nt with or after r/w goes low, the outputs will remain at high impedance. (3) if ce1 (or ub or lb ) goes high(or ce2 goes low) coincident with or before r/w goes high, the outputs will remain at high impedance. (4) if oe is high during the write cycle, the outputs will remain at high impedance. (5) because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. ub lb r/w t wc t as t wr t wp 1 ce valid data in t ds t dh hi-z hi-z t cw ce2 t bw t be t coe t odw ub , lb t cw (see note 5) address a0~a18 (word mode) d out i/o1~16 (word mode) d in i/o1~16 (word mode)
tc55vbm316aftn/astn40,55 2003-12-25 11/15 data retention characteristics ( ta = ? 40 to 85c ) symbol parameter min typ max unit v dh data retention supply voltage 1.5 ? 3.6 v v dh = 3.6 v ta = ? 40~85c ? ? 10 ta = ? 40~40c ? ? 2 i dds2 standby current v dh = 3.0 v ta = ? 40~85c ? ? 5 a t cdr chip deselect to data retention mode time 0 ? ? ns t r recovery time 5 ? ? ms controlled data retention mode (see note 1) ce2 controlled data retention mode (see note 3) , controlled data retention mode (see note 4) v dd 2.3 v gnd v il data retention mode t r t cdr v dd 0.2 v v ih ce2 ce1 v dd 2.3 v gnd v ih data retention mode t r (see note 2) (see note 2) t cdr v dd v dd ? 0.2 v 1 ce ub lb v dd 2.3 v gnd v ih data retention mode t r (see note 5) (see note 5) t cdr v dd v dd ? 0.2 v ub , lb
tc55vbm316aftn/astn40,55 2003-12-25 12/15 note: (1) in ce1 controlled data retention mode, minimum standby current mode is entered when ce2 0.2 v or ce2 v dd ? 0.2 v. (2) when ce1 is operating at the v ih (min.) level, the operating current is given by i dds1 during the transition of v dd from 2.3(2.7) to 2.2v(2.4 v). (3) in ce2 controlled data retention mode, minimum standby current mode is entered when ce2 0.2 v. (4) in ub (or lb ) controlled data retention mode, minimum standby current mode is entered when ce1 0.2 v or ce1 v dd ? 0.2 v, ce2 0.2 v or ce2 v dd ? 0.2 v. (5) when ub (or lb ) is operating at the v ih (min.) level, the operating current is given by i dds1 during the transition of v dd from 2.3(2.7) to 2.2v(2.4 v).
tc55vbm316aftn/astn40,55 2003-12-25 13/15 package dimensions tsop ? 48-p-1220-0.50 unit:mm 18.4 0.1 12.0 0.1 1.0 0.1 0.1 0.05 0.5 0.1 0.145 0.055 20.0 0.2 0.5 0.25 typ m 0.08 0.22 0.08 12.4 max 1.2 max 25 24 1 48 0.1 0~10 weight:0.51 g (typ)
tc55vbm316aftn/astn40,55 2003-12-25 14/15 package dimensions tsop ? 48-p-1214-0.50 unit:mm 12.4 0.1 12.0 0.1 1.0 0.1 0.1 0.05 0.5 0.1 0.145 0.055 14.0 0.2 0.5 0.25 typ m 0.08 0.22 0.08 12.4 max 1.2 max 25 24 1 48 0.1 0~10 weight:0.36 g (typ)
tc55vbm316aftn/astn40,55 2003-12-25 15/15 ? the information contained herein is subject to change without notice. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba produc ts, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specific ations. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semicon ductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, etc .. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the down stream products which ar e prohibited to be produced and sold, under any law and regulations. 030619eb a restrictions on product use

▲Up To Search▲

Price & Availability of TC55VBM316ASTN55

	To Download TC55VBM316ASTN55 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .