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? data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7234 features ? complete integrated remote terminal including: dual low-power 5v only transceiver complete rt protocol logic supports mil-std-1553a/b notice 2, stanag-3838 rt, and mil-std-1760 stores management 1.0 x 1.0 inch, 72-pin package choice of 5v or 3.3v logic power meets 1553a/mcair response time requirements internal fifo for burst mode capability on receive data 16-bit dma interface auto configuration capability comprehensive built-in self-test direct interface to simple (processorless) systems selectable input clock: 10, 12, 16, or 20 mhz description the bu-61703/5 simple system rt (ssrt) mil-std-1553 terminals provide a complete interface between a simple system and a mil- std-1553 bus. these terminals integrate dual transceiver, protocol logic, and a fifo memory for received messages in a 1.0 inch square ceramic package. the ssrt provides multi-protocol support of mil- std-1553a/b, mil-std-1760, mcair, and stanag-3838. the ssrt's transceivers are completely monolithic, require only a +5v supply, and consume low power. there are versions of the sim- ple system rt available with transceivers trimmed for mil-std-1760 compliance, or compatible to mcair standards. as a means of further reducing power consumption, the ssrt is available in versions with its logic powered by +3.3v, or +5v. the ssrt can operate with a choice of clock frequencies of 10, 12, 16, or 20 mhz. the ssrt incorporates a built-in self-test (bit). this bit, which is processed following power turn-on or after receipt of an initiate self- test mode command, provides a comprehensive test of the ssrt's encoders, decoders, protocol, transmitter watchdog timer, and proto- col. the ssrt also includes an auto-configuration feature. the ssrt is ideal for stores and other simple systems that do not require a microprocessor. to streamline the interface to simple sys- tems, the ssrt includes an internal 32-word fifo for received data words. this serves to ensure that only complete, consistent blocks of validated data words are transferred to a system. ? 2000 data device corporation bu-61703/61705 simple system rt (ssrt) make sure the next card you purchase has...
2 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 1. bu-61703/5 block diagram command address bus rt message status rt word inputs data transfer control dma handsake control dma handsake and trandfer control logic system data data buffers dtreq d15-d0 dtgrt dtack hs fail memoe memwr l_bro, t/r, sa4-sa0 wc/mc/cwc4-0 illegal srv_rqst ssflag busy rtactive incmd rtad4-rtad0 rt_ad_lat rt_ad_err gbr clk_in clk_sel1 clk_sel0 msg_err rtfail dual encoder decoder and rt s tat e logic bro_ena auto_cfg mstclr control inputs rt address clock fequencey selection 55 ? ? ? ?
3 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 v v v v v v vcc 10 -50 10 -33 -50 -33 0.4 0.4 -3.4 50 50 2.1 0.8 vcc 0.4 1.0 -10 -350 -10 -350 -350 -350 2.4 2.4 3.4 logic v ih all signals except clk_in clk_in v il all signals except clk_in clk_in schmidt hysteresis all signals except clk_in clk_in i ih (vcc=5.25v, v in =vcc) i ih (vcc=5.25v, v in =2.7v) i ih (vcc=3.6v, v in =vcc) i ih (vcc=3.6v, v ih =2.7v) i il (vcc=5.25v, v ih =0.4v) i il (vcc=3.6v, v ih =0.4v) v oh (vcc=4.5v, v ih =2.7v, v il =0.2v, i oh =max) v oh (vcc=3.0v, v ih =2.7v, v il =0.2v, i oh =max) v ol (vcc=4.5v, v ih =2.7v, v il =0.2v, i ol =max) v ol (vcc=3.0v, v ih =2.7v, v il =0.2v, i ol =max) i ol i oh c i (input capacitance) c io (bi-directional signal input capacitance) vp-p vp-p vp-p mv p - p mv peak nsec nsec 9 27 27 10 250 300 300 7 20 22 150 150 250 6 18 20 -250 100 200 transmitter differential output voltage direct coupled across 35 ? transformer coupled across 70 ? ? receiver differential input resistance (notes 1-6) differential input capacitance (notes 1-6) threshold voltage, transformer coupled, common mode voltage (note 7) v v v v v 6.0 6.0 7.0 6.0 6.0 -0.3 -0.3 -0.3 -0.3 -0.3 absolute maximum rating supply voltage logic +5v or +3.3v ram +5v transceiver +5v voltage input range for +5v powered logic (bu-61705) voltage input range for +3.3v powered logic (bu-61703) units max typ min parameter table 1. simple system rt specifications w w w w w w w w w w w w w w w w w w w w w w w w v v v ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma units max typ min parameter 0.88 1.11 1.33 1.79 0.88 1.17 1.46 2.05 0.69 0.92 1.15 1.60 0.69 0.98 1.28 1.86 0.28 0.51 0.75 1.22 0.28 0.58 0.88 1.48 5.5 3.6 5.25 160 265 370 580 160 276 392 625 100 205 310 520 40 100 216 332 565 40 5.0 3.3 5.0 4.5 3.0 4.75 power dissipation total hybrid (note 11) bu-61705xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-61705xx-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-61703xx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-61703xx-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle hottest die (note 11) bu-6170xxx-xx0 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-6170xxx-xx2 idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle power supply requirements voltages/tolerances +5v logic (bu-61705) (note 10) +3.3v logic (bu-61703) (note 10) +5v ch. a, +5, ch. b (note 10) current drain bu-61705xx-xx0 +5v (logic, ch a, ch b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-61705xx-xx2 +5v (logic, ch a, ch b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle bu-61703xx-xx0 +5v (ch a, ch b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v (logic) bu-61703xx-xx2 +5v (ch a, ch b) idle 25% transmitter duty cycle 50% transmitter duty cycle 100% transmitter duty cycle 3.3v (logic) table 1. simple system rt specs. (cont?d)
4 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 oz (g) in. (mm) c c c c/w c c c c +125 +85 +70 11 125 160 150 +300 9 -55 -40 0 -55 -65 weight flatpack/gull lead package physical characteristics size ceramic flatpack / gull lead thermal -1xx, -4xx -2xx, -5xx -3xx, -8xx ceramic flatpack / gull lead thermal resistance, junction-to- case, hottest die ( max case temperature operating junction temperature storage temperature lead temperature (soldering, 10 sec.) 1553 message timing rt-to-rt response timeout (note 12) rt response time (mid-parity to mid-sync) (note 12) transmitter watchdog timeout mhz mhz mhz mhz % % % % % 0.01 0.10 0.001 0.01 60 16.0 12.0 10.0 20.0 -0.01 -0.10 -0.001 -0.01 40 clock input frequency nominal value default option option option long term tolerance 1553a compliance 1553b compliance short term tolerance, 1 second 1553a compliance 1553b compliance duty cycle units max typ min parameter table 1. simple system rt specs. (cont?d) 0.6 (17) 1.0 x 1.0 x 0.155 (25.4 x 25.4 x 3.94) no tes : notes 1 through 6 are applicable to the receiver differential resistance and differential capacitance specifications: (1) specifications include both transmitter and receiver (tied together internally). (2) impedance parameters are specified directly between pins tx/rx a(b) and tx/rx a(b) of the ssrt hybrid. (3) it is assumed that all power and ground inputs to the hybrid are con- nected. (4) the specifications are applicable for both unpowered and powered conditions. (5) the specifications assume a 2 volt rms balanced, differential, sinu- soidal input. the applicable frequency range is 75 khz to 1 mhz. (6) minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. (7) assumes a common mode voltage within the frequency range of dc to 2 mhz, applied to the pins of the isolation transformer on the stub side (either direct or transformer coupled), and referenced to hybrid ground. transformer must be a ddc recommended transformer or other transformer that provides an equivalent minimum cmrr. (8) an "x" in one or more of the product type fields indicates that the ref- erence is applicable to all available product options. (9) mil-std-1760 requires an output of 20 vp-p minimum on the stub connection. (10) external 10 f tantalum and 0.1 f capacitors to ground should be located as close as possible to pins 20 and 72, and a 0.1 f capac- itor at pin 37. (11) power dissipation specifications assume a transformer coupled con- figuration, with external dissipation (while transmitting) of 0.14 watts for the active isolation transformer, 0.08 watts for the active bus cou- pling transformer, 0.45 watts for each of the two bus isolation resis- tors, and 0.15 watts for each of the two bus termination resistors. (12) measured from mid-parity crossing of command word to mid-sync crossing of rt's status word. (13) m il-std-1760 compliant output voltage not available for bu-61703/5x4 versions.
5 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 an internal built-in-test (bit) word register is updated at the end of each message. the contents of the bit word register are transmitted in response to a transmit bit word mode command. the bu-61703/5 provides a number of real-time output signals. these various signals provide indications of message in progress, valid received message, message error, handshake fail, loop-test fail or transmitter timeout. the bu-61703/5 includes standard dma handshake signals (request, grant, and acknowledge) as well as transfer control out- puts (memoe and memwr ). the dma interface operates in a 16- bit mode, supporting word-wide transfers. the ssrt's system interface allows the bu-61703/5 to be inter- faced directly to a simple system that doesn't include a micro- processor. this provides a low-cost 1553 interface for a/d and d/a converters, switch closures, actuators, and other discrete i/o sig- nals. the bu-61703/5 has an internal fifo for received data words. this 32-word deep fifo may be used to allow the bu-61703/5 to transfer its data words to the local system in burst mode. burst mode utilizes the fifo by transferring data to the local bus at a rate of one data word every three clock cycles. burst mode nego- tiates only once for use of the subsystem bus. negotiation is per- formed only after all 1553 data words have been received and val- idated. in non-burst mode, the bu-61703/5 will negotiate for the local bus after every received data word. the data word transfer period is three clock cycles for each received 1553 data word. the bu-61703/5 may also be used in a shared ram interface con- figuration. by means of tri-state buffers and a small amount of "glue" logic, the bu-61703/5 will store command words and access data words to/from dedicated "mailbox" areas in a shared ram for each broadcast / t/r bit / subaddress / mode code. address mapping a typical addressing scheme for the bu-61703/5 12-bit address bus could be as follows: a11: broadcast/o wnaddress a10: transmit/receive a9-a5: subaddress 4-0 a4-a0: word count/mode code 4-0 this method of address mapping provides for a "mailbox" alloca- tion scheme for the storage of data words. the 12 address outputs may be used to map into 4k words of processor address space. the bu-61703/5's addressing scheme maps messages in terms of broadcast/o wnaddress , transmit/receiv e , subaddress, and word/count mode code. a 32-word message block is allocated for each t/r-subaddress. for non-mode code messages, the data words to be transmitted or received are accessed from (to) relative locations 0 through 31 within the respective message block. for the mil-std-1553b synchronize with data, selected transmitter shut- introduction general the bu-61703/5 simple system rt (ssrt) is a complete mil- std-1553 remote terminal (rt) bus interface unit. contained in this hybrid are a dual transceiver and manchester ii encoder/decoder, and mil-std-1553 remote terminal (rt) pro- tocol logic. also included are built-in self-test capability and a par- allel subsystem interface. the subsystem interface includes a 12- bit address bus and a 16-bit data bus that operates in a 16-bit dma handshake transfer configuration. the local bus and associ- ated control signals may be operated from either +5 volt or +3.3 volt power. the transceiver front end of the bu-61703/5 is implemented by means of low-power monolithic technology. the transceiver requires only a single +5 v voltage source. the voltage source transmitters provide superior line driving capability for long cables and heavy amounts of bus loading. in addition, the monolithic transceivers provide a minimum stub voltage level of 20 volts peak-to-peak transformer coupled, making the bu-61703/5 suit- able for mil-std-1760 applications. the receiver sections of the bu-61703/5 are fully compliant with mil-std-1553b in terms of front-end overvoltage protection, threshold, and bit-error rate. the bu-61703/5 implements all mil-std-1553 message formats, including all 13 mil-std 1553 dual redundant mode codes. any subset of the possible 1553 commands (broadcast, t/r bit, sub- address, word count/mode code) may be optionally illegalized by means of an external prom, pld, or ram. an extensive amount of message validation is performed for each message received. each word received is validated for correct sync type and sync encoding, manchester ii encoding, parity, and bit count. all mes- sages are verified to contain a legal, defined command word and correct word count. if the bu-61703/5 is the receiving rt in an rt- to-rt transfer, it verifies that the t/r bit of the transmit command word is logic "1" and that the transmitting rt responds in time and contains the correct rt address in its status word. the bu-61703/5 may be operated from a 10, 12, 16, or 20 mhz clock input. for any clock frequency, the decoder samples incom- ing data on both edges of the clock input. this oversampling, in effect, provides for a sampling rate of twice the input clocks' fre- quency. benefits of the higher sampling rate include a wider toler- ance for zero-crossing distortion and improved bit error rate per- formance. the bu-61703/5 includes a hardwired rt address input. this includes 5 address lines, an address parity input, and an address parity error output. the rt address can also be latched by means of a latching input signal. the bu-61703/5 supports command illegalization. commands may be illegalized by asserting the input signal illegal active low within approximately 2 s after the mid-parity bit zero-crossing of the received command word. command words may be illegal- ized as a function of broadcast, t/r bit, subaddress, word count, and/or mode code.
6 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 down, override selected transmitter shutdown, and transmit vec- tor word mode commands which involve a single data word trans- fer, the address for the data word is offset from location 0 of the message block for subaddresses 0 and 31 by the value of the mode code field of the received command word. the data words transmitted in response to the transmit last com- mand or transmit bit word mode commands are accessed from a pair of internal registers. dma interface a 16-bit data bus, a 12-bit address bus, and six control signals are provided to facilitate communication with the parallel subsystem. the data bus d15-d0 consists of bi-directional tri-state signals. the address bus l_bro, t/r , sa4-sa0, and wc/mc/cwc4-0; along with the data transfer control signals memoe and memwr are two-state output signals. the control signals include the standard dma handshake signals dtreq , dtgr t , dt a ck , as well as the transfer control outputs memoe and memwr . hs_f ail provides an indication to the subsystem of a handshake failure condition. data transfers between the subsystem and the bu-61703/5 are performed by means of a dma handshake, initiated by the bu-61703/5. a data read operation is defined to be the trans- fer of data from the subsystem to the bu-61703/5. conversely, a data write operation transfers data from the bu-61703/5 to the subsystem. data is transferred as a single 16-bit word. dma read operation in response to a transmit command, the bu-61703/5 needs to read data words from the external subsystem. to initiate a data word read transfer, the ssrt asserts the signal dtreq low. assuming that the subsystem asserts dtgr t in time, the ssrt will then assert the appropriate values of l_bro (logic "0"), t/r (high), sa4-0, and mc/cwc4-0; memwr high, along with dt a ck low and memoe low to enable data to be read from the subsys- tem. after the transfer of each data word has been completed, the value of the address bus outputs cwc4 through cwc0 is incre- mented. dma write operation in response to a receive command, the bu-61703/5 will need to transfer data to the subsystem. there are two options for doing this, the burst mode and the non-burst mode. in burst mode, all received data words are transferred from the ssrt to the subsys- tem in a contiguous burst, only following the reception of the cor- rect number of valid data words. in the non-burst mode, single data words are written to the external subsystem immedi- ately following the reception of each individual data word. to initiate a dma write cycle, the ssrt asserts dtreq low. the subsystem must then respond with dtgr t low. assuming that dtgr t was asserted in time, the bu-61703/5 will then assert dt a ck low. the bu-61703/5 will then assert the appropriate value of l_bro, t/r , sa4-0, and mc/cwc4-0, memoe high, and memwr low. memwr will be asserted low for one clock cycle. the subsystem may then use either the falling or rising edge of memwr to latch the data. similar to the dma read operation, the address outputs cwc4 through cwc0 are incremented after the completion of a dma write operation. handshake fail following the assertion of dtreq low by the ssrt, the external subsystem has 10 s to respond by asserting dt a ck to logic "0". if the bu-61703/5 (ssrt) asserts dtreq and the subsystem does not respond with dtgr t in time for the bu-61703/5 to com- plete a data word transfer, the hsf ail output will be asserted low to inform the subsystem of the handshake failure, and bit 12 in the internal built-in-test (bit) word will be set to logic "1". if the hand- shake failure occurs on a data word read transfer (for a transmit command), the ssrt will abort the current message transmis- sion. in the case of a handshake failure on a write transfer (received command) the ssrt will set the handshake failure out- put and bit word bit, and abort processing the current message. message processing operation following the receipt and transfer of a valid command word, the bu-61703/5 will attempt to perform one of the following opera- tions: (1) transfer received 1553 data to the subsystem, (2) read data from the subsystem for transmission on the 1553 bus, (3) transmit status (and possibly the last command word or rt bit word) on the 1553 bus, and/or (4) set status word conditions. the bu-61703/5 responds to all non-broadcast messages to its rt address with a 1553 status word. rt address rt address 4-0 (rt_ad_4 = msb) and rt address parity (rt_ad_p) should be programmed for a unique rt address and reflect an odd parity sum. the bu-61703/5 will not respond to any mil-std-1553 commands or transfer received data from any non- broadcast messages if an odd parity sum is not presented by rt_ad_4-0 and rt_ad_p. an address parity error will be indicat- ed by a low output on the r t_ad_err pin. the input signal rt_ad_lat operates a transparent latch for rtad4-rtad0 and rtadp. if rt_ad_lat is low, the output of the latch tracks the value presented on the input pins. if rt_ad_lat is high, the out- put of the internal latch becomes latched to the values presented at the time of a low-to-high transition of rt_ad_lat. rt address and rt address parity must be presented valid before the mid-parity crossing of the 1553 command and held, at least, until following the first received data word. command illegalization the bu-61703/5 includes a provision for command illegalization. if a command is illegalized, the bu-61703/5 will set the message error bit and transmit its status word to the bus controller. no data
7 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 l-bro t/r a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 prom / ram / pld (4kx1) sa1 wc/mc/cwc3 wc/mc/cwc2 sa0 wc/mc/cwc4 wc/mc/cwc1 sa4 sa3 sa2 wc/mc/cwc0 illegal a0 d0 bu - 61703 / 5 "ssrt" (400ns max) figure 2. bu-61703/5 illegalization words will be transmitted in response to an illegalized transmit command. however, data words associated with an illegalized receive command will be written to the external subsystem (although these transfers may be blocked using external logic). illegal is sampled approximately 2 s following the mid-parity bit zero crossing of the received command word. a low on ille - gal will illegalize a particular command word and cause the ssrt to respond with its message error bit set in its status word. command illegalization based on broadcast, t/r bit, subaddress, and/or word count/mode code may be implemented by means of an external prom, pld, or ram device, as shown in figure 2. the external device may be used to define the legality of specific commands. any subset of the possible 1553 commands may be illegalized as a function of broadcast, t/r bit, subaddress, word count, and/or mode code. the output of the illegalization device should be tied directly to the bu-61703/5's illegal signal input. the maximum access time of the external illegalizing device is 400 ns. if illegalization is not used, illegal should be hardwired to logic "1". busy the external subsystem may control the ssrt's busy rt status word bit by means of the b usy input signal. the ssrt samples b usy approximately 2 s following the mid-parity bit zero cross- ing of the received command word. if b usy is sampled low for a particular message, the value of the busy bit transmitted in the ssrt's status word will be logic "1". if b usy is sampled high for a particular message, the value of the busy bit transmitted in the ssrt's status word will be logic "0". if the rt responds to a transmit command with a busy bit of logic "1", the status word will be transmitted, but no data words will be transmitted by the ssrt. if the ssrt responds to a receive com- mand with a busy bit of logic "1", data words will be transferred to the external subsystem (although these may be blocked by means of external logic). similar to illegal , it is possible to cause the ssrt to respond with busy for specific command words (only), by means of an external prom, ram, or pld device. transmit command (rt-to-bc transfer) if the bu-61703/5 receives a valid transmit command word that the subsystem determines is legal (input signal illegal is high) and the subsystem is not busy (input signal b usy is high), the bu-61703/5 will initiate a transmit data response following trans- mission of its status word. this entails a handshake/read cycle for each data word transmitted, with the number of data words to be transmitted specified by the word count field of the transmit com- mand word. if illegal is sampled low, the message error bit will be set in the ssrt's status word. no data words will be transmitted following transmission of the status word to an illegalized transmit com- mand. a low on the b usy input will set the busy bit in the status word; in this instance, only the status word will be transmitted, with no data words. receive command (bc-to-rt transfer) in non-burst mode, a dma handshake will be initiated for each data word received from the 1553 data bus. if successful, the respective handshake will be followed by a corresponding write cycle. a handshake timeout will not terminate transfer attempts for the remaining data words, error flagging or status word transmis- sion. after the reception of a valid non-mode code receive command word followed by the correct number of valid data words and assuming that all words are successfully transferred to the subsystem, a negative pulse will be asserted on the good block received (gbr ) output. the width of this pulse is two clock cycles. in burst mode, a dma handshake will not be initiated until after all data words have been received over the 1553 data bus and stored into the ssrt's internal fifo. after the handshake has been negotiated, the ssrt will burst the contents of the fifo to the local bus (d0-d15). after the reception of a valid non-mode code
8 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 loopback test the bu-61703/5 performs a loopback self-test at the end of each non-broadcast message processed. the loopback test consists of the following verifications: (1) the received version of every trans- mitted word is verified for validity (encoding, bit count, parity) and correct sync type; and (2) the received version of the last trans- mitted word is verified by means of a bit-by-bit comparison to the transmitted version of this word. if there is a transmitter timeout (660.5 s) and/or if the loopback test fails for one or more trans- mitted words, the terminal flag status word bit will be set in response to the next non-broadcast message. note that the setting of the terminal flag status bit following a loop test failure may be disabled by means of the auto-config feature; i.e., by setting auto-config bit 4 to logic "0". status word the broadcast command received bit is formulated internally by the ssrt. the message error status bit will be set if the current command is a transmit status word or transmit last command mode command if there was an error in the data portion of the pre- vious receive message. message error will also be set if illegal has been sampled low by the ssrt for the current message. ille - gal , sr v_rqst , b usy , and ssfla g (subsystem flag) will be sampled from their respective status input pins approximately 2 s following the mid-parity bit zero crossing of the received command word. this time is 400 ns maximum following after the l_bro, t/r , sa4-0, and wc/mc/cwc4-0 outputs have been presented valid. protocol self-test the ssrt includes a comprehensive, autonomous off-line self- test of its internal protocol logic. the test includes a comprehen- sive test of all registers, manchester encoder and decoders, trans- mitter failsafe timer, protocol logic, and the internal fifo. this test is completed in approximately 32,000 clock cycles. that is, about 1.6 ms with a 20 mhz clock, 2.0 ms at 16 mhz, 2.7 ms at 12 mhz, and 3.2 ms at 10 mhz. while the ssrt is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from the 1553 bus. unless disabled by means of the ssrt's auto-config feature, the protocol self-test will be performed following the ssrt's power turn-on (i.e., when mstclr is released high). if the auto-config feature is used and auto-config bit 5 is set to logic "0", then a fail- ure of the protocol self-test following power turn-on will result in the ssrt not going online. if bit 5 is set to logic "0" and the protocol self-test passes following power turn-on, the ssrt will go online. the protocol self-test will also be performed following receipt of an initiate self-test mode command from the 1553 bus. if an initiate self-test mode command is received by the ssrt, and auto- config bit 5 is set to logic "0", then a failure of the protocol self-test following will result in the ssrt going offline. receive command word followed by the correct number of valid data words and assuming that all words are successfully trans- ferred to the subsystem, a negative pulse will be asserted on the output good block received (gbr ). the width of this pulse is two clock cycles. rt-to-rt transfer errors for the case where the ssrt is the receiving rt of an rt-to-rt transfer, if the transmitting rt does not respond within the speci- fied time period, the ssrt will determine that a timeout condition has occurred. the value of the ssrt's rt-to-rt timeout timer is in the range from 17.5 to 18.5 s, and is specified from the mid-par- ity bit crossing of the transmit command word to the mid-sync crossing of the transmitting rt's status word. in the case of an rt- to-rt timeout, the ssrt will not respond and the rt-to-rt no transfer timeout bit (bit 2) of the ssrt's bit word will be set to logic "1". also, if the ssrt is the receiving rt for an rt-to-rt transfer, and the t/r bit of the second command word is logic "0", or the rt address field for the transmit command is the same as for the receive command, or the subaddress for the transmit command is 00000 or 11111, the bu-61703/5 will not respond, and will set the rt-to-rt second command error bit (bit 1) of the rt bit word to logic "1". rt status, error handling, and message tim- ing signals message transfers and transfer errors are indicated by means of the incmd , hs_f ail , msg_err , and r tf ail error indication outputs. additional error detection and indication mechanisms include updating of the internal command, rt status and bit word registers. the bu-61703/5 provides a number of timing signals during the processing of 1553 messages. incmd is asserted low when a new command is received. at the end of a message (either valid or invalid), incmd transitions from low to high. as discussed above, hs_f ail will be asserted low if the subsys- tem fails to respond to dtreq within the maximum amount of time (10 s). following the last data word transfer for a valid non-mode code receive message (for either non-burst mode or burst mode), gbr will be asserted low for two clock cycles. msg_err is asserted as a low output level following any detect- ed error in a received message, except for an error in the com- mand word. if an error is detected in a received command word, the rest of the message will be ignored. if msg_err and/or hs_f ail have been asserted (low), they will be cleared to logic "1" following receipt of a subsequent valid com- mand word.
9 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 if the protocol self-test fails: (1) the terminal flag bit will be set to logic "1" in the ssrt status word; (2) bit 8 in the ssrt's bit word, bit test fail, will be set to logic "1"; (3) the ssrt's r tf ail output will be asserted to logic "0". auto-configuration the ssrt includes an auto-configuration feature, which allows various optional features to be enabled or disabled. auto-configu- ration may be enabled or disabled by means of the input signal a ut o_cfg . if a ut o_cfg is connected to logic "1", then the auto-configure option is disabled, and the six configuration para- meters revert to their default values. note that the default condition for each configuration para- meter is enab led (for the mil-std-1553a/b protocol selection, - 1553 b is the default). if a ut o_cfg is connected to logic "0", then the configuration parameters are transferred over d5-d0 by means of a dma read data transfer. the transfer occurs during the time that the rtactive and dt a ck outputs are logic "0", following mstclr transitioning from logic "0" to logic "1" and a successful dt_req -to-dtgr t handshake. note that if dtgr t is hardwired to logic "0", the handshake process is not necessary (i.e., dt a ck and rtactive will both be asserted to logic "0" one clock cycle following dt_req ). each of the configuration parameters is enabled if the ssrt reads a value of logic "1" for the respective data bit. the auto-configuration parameters are defined by table 2. the timing signals pertaining to auto-configuration mode are illustrated in figure 12. 0 1 1 0 clk_sel_0 12 mhz 16 mhz 1 20 mhz 0 10 mhz 0 clock frequency clk_sel_1 1 table 3. clock frequency selection clock input the ssrt may be operated from one of four clock frequencies: 10, 12, 16, or 20 mhz. the selected clock frequency must be des- ignated by means of the input signals clk_sel_1 and clk_sel_0, as shown in table 3. mil-std-1553a /b (-b is logic "1", or the default). power-up self- test enable burst mode subaddress 30 wraparound rtfail-to-terminal flag auto-wrap rt goes online if self-test fails function in mil-std-1553b mode, subaddress 31 is a mode code subaddress, and mode codes are implemented in full accordance with mil-std-1553b. in mil-std-1553a mode, subaddress 31 is a non-mode code subaddress, and no data words are transmitted or anticipat- ed to be received for mode code mes- sages. if enabled, the ssrt will perform self- test following the rising edge of mst - clr . 0 enables burst mode (using the internal fifo) for received data words. in burst mode, for a receive message, all data words are transferred to the external system in a contiguous burst following reception of the last data word. 1 subaddress 30 wraparound is enabled. that is, the data words for a receive message to subaddress 30 are stored in the internal fifo, and not transferred to the external system. for a subsequent transmit message to subaddress 30, the transmitted data words are read from the internal fifo, rather than from the external system. 2 if the loop test fails for a particular mes- sage, the terminal flag bit will be set in the ssrt's status response for the sub- sequent non-broadcast message. 4 if logic "0", the rt will become enabled only if the self-test passes. if auto-config is not used, or if this bit is logic "1", or if the power-up self-test passes, then the rt will go online following self-test. 5 description bit 3 table 2. auto-configuration parameters
10 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 3. rt receive command (burst mode) timing 1553 bus rx command data #2 data #1 status l-bro, t/r, sa4-sa0 wc/mc/cwc incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail mid-parity mid-parity mid-parity mid-parity mid-sync burst data write transfer t1 t11 t12 t6 t2 t15 t9 previous msg cwc illegal, srv_rqst ssflag, busy valid t3 t5 t4 t8 wc / mc wc / mc cwc = 0 cwc = 1 rt receive command (burst mode) 1f t7 t14 t13 t10 note 1 note 1 : if the rx message is a broadcast message then the rising edge of incmd is referenced from the rising edge of gbr. (refer to figure 9)
11 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 mid-parity crossing of received command word delay to sa4-sa0, l-bro, t/r bit, and wc/mc valid all s t2 mid-parity crossing of received command word delay to falling edge of incmd all s t3 mid-parity crossing of received command word delay to msg_err and hs_f ail rising all s t4 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r , and cwc/mc valid all ns t5 l_bro, t/r , sa4-0, and wc/mc4-0 valid prior to incmd low. all 500 ns t6 illegal , sr v_rqst , ssfla g , b usy hold time following falling edge of incmd all 300 ns t7 mid-parity crossing of first data word to wc/cwc valid data of 1fh all s t8 duration of wc/cwc data value of 1fh all ns t9 rt response time. all 4 s t10 cwc transition to next word following mid-parity of subsequent received data words. all s t11 mid-parity crossing of last data word to dtreq falling edge (requesting data word burst write transfer) all 4 s t12 mid-sync crossing of status response to r t_f ail rising all s t13 cwc valid following falling edge of dtreq all ns t14 gbr pulse width (see note 1) 20 mhz ns ref description clock frequency response time units table for figure 3. rt receive command timing (burst mode) t15 mid-parity crossing of status word to incmd rising all s min typ max 1.5 2 1.5 400 1 200 6.5 7 1 4.5 5.25 1.5 30 100 3 16 mhz ns 125 12 mhz ns 167 10 mhz ns 200 no te : (1) if the rx message is a broadcast message then the rising edge of incmd is referenced from the rising edge of gbr .
12 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 4. rt receive command (non-burst mode) timing 1553 bus rx command data #2 data #1 status l-bro, t/r, sa4-sa0 wc/mc/cwc incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail mid-parity mid-parity mid-parity mid-parity mid-sync t1 t13 t16 t6 t2 t12 t17 t11 previous msg cwc = 1 wc / mc illegal, srv_rqst ssflag, busy valid t3 t5 t4 t9 t10 wc / mc cwc = 0 rt receive command (non-burst mode) 1f t7 t14 t8 t15 single word write data word #1 single word write data word #2 (refer to figure 10)
13 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 mid-parity crossing of received command word delay to sa4-sa0, l-bro, t/r bit, and wc/mc valid all s t2 mid-parity crossing of received command word delay to falling edge of incmd all s t3 mid-parity crossing of received command word delay to msg_err and hs_fail rising all s t4 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r , and cwc/mc valid all ns t5 rt sub-address, l-bro, and t/r bit setup time prior to incmd low all 500 ns t6 illegal , sr v_rqst , ssfla g , b usy valid time following falling edge of incmd all 300 ns t7 mid-parity crossing to wc/cwc value of 1fh all s t8 mid-parity crossing of first data word to dtreq falling edge t9 wc/cwc data value of 1fh held t10 cwc valid following falling edge of dtreq all ns t11 rt response time. all 4 s t12 delay from following mid-parity of last received data word to gbr low. (see notes 1, 2) all 4 s t13 mid-parity crossing of all data words, except first data word, to dtreq falling edge all s t14 gbr pulse width 20 mhz ns ref description clock frequency response time units table for figure 4. rt receive command timing (non-burst mode) t15 cwc transition to wc prior to mid-sync crossing of status response. min typ max 1.5 2 1.5 400 1 30 6.5 7 1 100 16 mhz ns 125 12 mhz ns 167 10 mhz ns 200 t16 mid-sync crossing of status response to r t_f ail rising all s 1.5 t17 mid-parity crossing of status word to incmd rising all s 3.0 20 mhz s 1.2 16 mhz s 1.25 12 mhz s 1.33 10 mhz s 1.4 20 mhz ns 75 16 mhz ns 94 12 mhz ns 125 10 mhz ns 150 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 no tes : (1) assumes that dtgr t is tied to logic ? 0 ? . if dtgr t is not connected to logic ? 0 ? , the minimum time to drive gbr active low will increase by the amount of the dtgr t (low) - to - dtgr t (low) delay. (2) the transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
14 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 5. rt transmit command timing 1553 bus tx command data #2 data #1 status incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail mid-parity mid-sync mid-parity mid-sync mid-sync single word read data word #1 single word read data word #2 t15 t9 t10 t4 t1 illegal, srv_rqst ssflag, busy valid t7 t5 t13 t14 rt transmit command l-bro, t/r, sa4-sa0 wc/mc/cwc t2 t3 previous msg cwc = 1 t6 t11 t12 wc wc cwc = 0 1f t8 (refer to figure 11)
15 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 rt response time. all 4 s t2 mid-parity crossing of received command word delay to l-bro, t/r bit, sa4-sa0, and wc/mc valid all s t3 mid-parity crossing of received command word delay to falling edge of incmd all s t4 mid-parity crossing of receive command word delay to msg_err and hs_f ail rising all s t5 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r bit, and cwc/mc valid all ns t6 l-bro, t/r , sa4-0, and wc/mc4-0 setup time prior to incmd low all 500 ns t7 illegal , sr v_rqst , ssfla g , b usy hold time following falling edge of incmd all 300 ns t8 mid-sync crossing of status word to wc/cwc valid data of 1fh t9 mid-sync crossing of status word to dtreq falling edge t10 mid-sync crossing of status response to r t_f ail rising (see note 1) all s t11 duration of wc/cwc value of 1fh t12 cwc valid following falling edge of dtreq all ns t13 mid-sync crossing of received data word to dtreq falling edge 20 mhz s ref description clock frequency value units table for figure 5. rt transmit command timing t14 mid-sync crossing of last received data word for cwc to transition to wc min typ max 6.5 7 1.5 2 1.5 400 1.5 30 1.75 16 mhz s 1.81 12 mhz s 1.92 10 mhz s 2 t15 mid-parity crossing of status word to incmd rising all s 3 20 mhz s 1.55 16 mhz s 1.56 12 mhz s 1.59 10 mhz s 1.6 20 mhz s 6.75 16 mhz s 6.81 12 mhz s 6.92 10 mhz s 7 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 all s 6.5 no te : (1) assuming that r tf ail was previously low.
16 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 6. rt - rt transmit timing incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail single word read data word #1 single word read data word #2 t15 t9 t10 t4 t1 illegal, srv_rqst ssflag, busy valid t7 t5 t13 t14 rt - rt transmit command l-bro, t/r, sa4-sa0 wc/mc/cwc t2 t3 previous msg cwc = 1 t6 t11 t12 wc wc cwc = 0 1f t8 1553 bus rx command status tx command data #1 mid-parity mid-parity mid-sync mid-sync mid-sync data #2 status (refer to figure 11)
17 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 rt - rt response timeout for transmitting rt. all 17.5 s t2 mid-parity crossing of received command word delay to l-bro, t/r bit, sa4-sa0, and wc/mc valid all s t3 mid-parity crossing of received command word delay to falling edge of incmd all s t4 mid-parity crossing of received command word delay to msg_err and hs_f ail rising all s t5 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r , and cwc/mc valid all ns t6 l-bro, t/r , sa4-0, and wc/mc4-0 setup time prior to incmd low all 500 ns t7 illegal , sr v_rqst , ssfla g , b usy hold time following falling edge of incmd all 300 ns t8 mid-sync crossing of status word to wc/cwc valid data of 1fh t9 mid-sync crossing of status word to dtreq falling edge t10 mid-sync crossing of status response to r t_f ail rising all s t11 duration of wc/cwc value of 1fh t12 cwc valid following falling edge of dtreq all ns t13 mid-sync crossing of received data word to dtreq falling edge 20 mhz s ref description clock frequency value units table for figure 6. rt-rt transmit command timing t14 mid-sync crossing of last received data word for cwc to transition to wc min typ max 18.5 19.5 1.5 2 1.5 400 1.5 30 1.75 16 mhz s 1.81 12 mhz s 1.92 10 mhz s 2 t15 mid-parity crossing of status word to incmd rising all s 3 20 mhz s 1.55 16 mhz s 1.56 12 mhz s 1.59 10 mhz s 1.6 20 mhz s 6.75 16 mhz s 6.81 12 mhz s 6.92 10 mhz s 7 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 all s 6.5
18 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 7. rt - rt receive (burst-mode) timing l-bro, t/r, sa4-sa0 wc/mc/cwc incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail mid-parity mid-parity mid-parity mid-parity mid-sync burst data write transfer t1 t12 t13 t6 t2 t16 t10 previous msg cwc illegal, srv_rqst ssflag, busy valid t3 t5 t4 t9 wc / mc wc / mc cwc = 0 cwc = 1 rt - rt receive command (burst mode) 1f t8 t15 t14 t11 note 1 note 1 : if the rx message is a broadcast message then the rising edge of incmd is referenced from the rising edge of gbr. 1553 bus rx command status tx command data #1 mid-parity mid-sync t7 data #2 status (refer to figure 9)
19 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 mid-parity crossing of received command word delay to sa4-sa0, l-bro, t/r bit, and wc/mc valid all s t2 mid-parity crossing of received command word delay to falling edge of incmd all s t3 mid-parity crossing of received command word delay to msg_err and hs_f ail rising all s t4 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r , and cwc/mc valid all ns t5 l_bro, t/r , sa4-0, and wc/mc4-0 valid prior to incmd low. all 500 ns t6 illegal , sr v_rqst , ssfla g , b usy hold time following falling edge of incmd all 300 ns t7 rt - rt response timeout for transmitting rt. all 17.5 s t8 mid-parity crossing of first data word to wc/cwc valid data of 1fh all s t9 duration of wc/cwc data value of 1fh all ns t10 rt response time. all 4 s t11 cwc transition to next word following mid-parity of subsequent received data words. all s t12 mid-parity crossing of last data word to dtreq falling edge (requesting data word burst write transfer) all 4 s t13 mid-sync crossing of status response to r t_f ail rising all s t15 gbr pulse width (see note 1) 20 mhz ns ref description clock frequency response time units table for figure 7. rt-rt receive command timing (burst mode) t16 mid-parity crossing of status word to incmd rising all s min typ max 1.5 2 1.5 400 18.5 19.5 1 200 6.5 7 1 4.5 5.25 1.5 100 3 16 mhz ns 125 12 mhz ns 167 10 mhz ns 200 t14 cwc valid following falling edge of dtreq all ns 30 no te : (1) if the rx message is a broadcast message then the rising edge of incmd is referenced from the rising edge of gbr .
20 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 8. rt - rt receive (non-burst-mode) timing l-bro, t/r, sa4-sa0 wc/mc/cwc incmd dtreq dtgrt dtack gbr memwr memoe d15-d0 rt_fail msg_err hs_fail t1 t14 t17 t6 t2 t13 t18 previous msg cwc = 1 wc / mc illegal, srv_rqst ssflag, busy valid t3 t5 t4 t10 t11 wc / mc cwc = 0 rt - rt receive command (non-burst mode) 1f t8 t15 t9 t16 single word write data word #1 single word write data word #2 mid-parity mid-parity mid-parity mid-parity mid-sync t12 1553 bus rx command status tx command data #1 mid-parity mid-sync t7 data #2 status (refer to figure 10)
21 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 mid-parity crossing of received command word delay to sa4-sa0, l-bro, t/r bit, and wc/mc valid all s t2 mid-parity crossing of received command word delay to falling edge of incmd all s t3 mid-parity crossing of receive command word delay to msg_err and hs_f ail rising all s t4 illegal , sr v_rqst , ssfla g , b usy input access time from sa4-sa0, l-bro, t/r , and cwc/mc valid all ns t5 rt sub-address, l-bro, and t/r bit setup time prior to incmd low all 500 ns t6 illegal , sr v_rqst , ssfla g , b usy valid time following falling edge of incmd all 300 ns t7 rt - rt response timeout for transmitting rt. all 17.5 s t9 mid-parity crossing of first data word to dtreq falling edge t10 wc/cwc data value of 1fh held t11 cwc valid following falling edge of dtreq all ns t12 rt response time. all 4 s t13 delay from following mid-parity of last received data word to gbr low. (see notes 1, 2) all 4 s t14 mid-parity crossing of all data words, except first data word, to dtreq falling edge all s t15 gbr pulse width 20 mhz ns ref description clock frequency response time units table for figure 8. rt-rt receive command timing (non-burst mode) t16 cwc transition to wc prior to mid-sync crossing of status response. min typ max 1.5 2 1.5 400 18.5 19.5 30 6.5 7 1 100 16 mhz ns 125 12 mhz ns 167 10 mhz ns 200 t17 mid-sync crossing of status response to r t_f ail rising all s 1.5 t18 mid-parity crossing of status word to incmd rising all s 3.0 20 mhz s 1.2 16 mhz s 1.25 12 mhz s 1.33 10 mhz s 1.4 20 mhz ns 75 16 mhz ns 94 12 mhz ns 125 10 mhz ns 150 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 t8 mid-parity crossing to wc/cwc value of 1fh all s 1 no tes : (1) assumes that dtgr t is tied to logic ? 0 ? . if dtgr t is not connected to logic ? 0 ? , the minimum time to drive gbr active low will increase by the amount of the dtgr t (low) - to - dtgr t (low) delay. (2) the transceiver delays are measured at a range of 150ns to 450ns for the receiver and 100ns to 250ns for the transmitter.
22 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 9. dma write transfer (burst-mode) timing clock in dtreq dtgrt dtack memwr memoe wc/mc/cwc d15-d0 data valid data valid t1 t2 t6 t5 t4 t8 t11 t12 t13 t7 t7 t11 t12 t13 t15 t3 t10 t14 t16 t10 t14 t19 t20 t17 l-bro, t/r, sa4-sa0 valid gbr incmd cwc = 0 cwc = 1 wc t18 t21 t9 dma write - burst mode (shown for two data words) 1 incmd rising edge is shown for the case of a rx broadcast command message. for the non-broadcast case, incmd rising edge is after the mid-parity crossing of the rt status response. 1
23 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 clock in rising to dtreq low all ns t2 dtreq falling to dtgr t low all s t4 dtgr t low setup prior to clock in rising edge all 10 ns t6 clock in rising to dt a ck low all ns t7 data output valid following clock in all ns t8 dtgr t hold time following dt a ck falling all ns t10 data output setup time prior to memwr low t12 memwr low pulse width t13 clock in rising to memwr high all ns t15 data output hold time following clock in rising all 10 ns t16 cwc (all but first data word) setup time prior to memwr low 20 mhz 10 ns ref description clock frequency value @5 volts units table for figure 9. ssrt dma write (burst mode) timing t20 gbr low pulse width min typ max 40 10 40 40 30 30 16 mhz 23 ns 12 mhz 43 ns 10 mhz 60 ns t21 incmd rising following clock in rising (see note 3) all ns 30 20 mhz 10 ns 16 mhz 22 ns 12 mhz 43 ns 10 mhz 60 ns 20 mhz 90 ns 100 16 mhz 115 ns 125 12 mhz 157 ns 167 10 mhz 190 ns 200 20 mhz 40 ns 50 16 mhz 52.5 ns 62.5 12 mhz 73.3 ns 83.3 10 mhz 90 ns 100 t3 cwc setup time prior to memwr falling for first word of burst transfer (see note 1) 20 mhz 60 ns 16 mhz 85 ns 12 mhz 127 ns 10 mhz 160 ns t5 dtgr t falling to dt a ck low 20 mhz ns 100 16 mhz ns 113 12 mhz ns 133 10 mhz ns 150 t9 dt a ck low pulse width (based on a two data word transfer) (see note 2) 20 mhz 290 ns 300 16 mhz 365 ns 375 12 mhz 490 ns 500 10 mhz 590 ns 600 t11 clock in rising to memwr low all ns 40 t14 data output and cwc hold time following memwr high 20 mhz 20 ns 16 mhz 33 ns 12 mhz 53 ns 10 mhz 70 ns t17 clock in rising to dtreq and dt a ck high all ns 30 t18 data output signal tri-state following clock in rising all ns t19 clock in rising to gbr falling edge all ns 40 40 15 15 10 value @3.3 volts min typ max 40 10 40 40 30 40 23 43 60 40 10 22 43 60 90 100 115 125 157 167 190 200 40 50 52.5 62.5 73.3 83.3 90 100 60 85 127 160 105 118 138 155 290 300 365 375 490 500 590 600 40 10 23 43 60 40 40 40 no tes : (1) assume dtgr t is low at the time that dtreq is asserted low. if not, then this time will increase by the amount of the dtreq (low) - to - dtgr t (low) delay. (2) dt a ck pulse width is 3 clock cycles per data word transfer. (3) rising edge of incmd will immediately follow the rising edge of gbr only for a broadcast message. for a non-broadcast message, the rising edge of incmd will occur after the mid-parity crossing of the rt status response. this additional delay time is approximately 96 clock cycles: 9.6 s at 10 mhz, 8 s at 12 mhz, 6.0 s at 16 mhz, or 4.8 s at 20 mhz.
24 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 10. dma write transfer (non-burst-mode) timing clock in dtreq dtgrt dtack memwr memoe wc/mc/cwc d15-d0 data valid t1 t2 t6 t5 t4 t8 t11 t12 t13 t17 t16 t7 t14 t10 t3 t15 l-bro, t/r, sa4-sa0 valid cwc = 0 t9 non-burst dma write note: with the dtgrt pin tied to gnd, the time from dtreq to dtack is 1 clock cycle.
25 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 clock in rising to dtreq low all ns t2 dtreq (low) - to - dtgr t (low) delay time all s t4 dtgr t low setup prior to clock in rising all 10 ns t6 clock in rising to dt a ck low all ns t7 data output valid following clock in rising all ns t8 dtgr t hold time following dt a ck falling all ns t10 data output setup time prior to memwr low t12 memwr low pulse width t13 clock in rising to memwr high all ns t15 clock in rising to dtreq and dt a ck high all ns ref description clock frequency value @5 volts units table for figure 10. ssrt dma write timing (non-burst) min typ max 40 10 40 40 30 40 30 20 mhz 60 ns 16 mhz 85 ns 12 mhz 127 ns 10 mhz 160 ns 20 mhz 40 ns 50 16 mhz 52.5 ns 62.5 12 mhz 73.3 ns 83.3 10 mhz 90 ns 100 t3 cwc setup time prior to memwr falling (see note) 20 mhz 110 ns 16 mhz 148 ns 12 mhz 210 ns 10 mhz 260 ns t5 dtgr t falling to dt a ck low 20 mhz ns 100 16 mhz ns 113 12 mhz ns 133 10 mhz ns 150 t9 dt a ck low pulse width 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 t11 clock in rising to memwr low all ns 40 t14 data output hold time following memwr high 20 mhz 20 ns 16 mhz 33 ns 12 mhz 53 ns 10 mhz 70 ns t17 data output signal tri-state following clock in rising all ns 40 15 value @3.3 volts min typ max 40 10 40 40 30 40 40 60 85 127 160 40 50 52.5 62.5 73.3 83.3 90 100 110 148 210 260 105 118 138 155 200 250 333 400 40 10 23 43 60 40 t16 data output hold time following clock in rising all 10 ns 15 no tes : (1) assume that dtgr t is low at the time dtreq is asserted low. if not, these values can increase by the delay time from dtreq (low) - to - dtgr t (low).
26 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 11. dma read transfer timing clock in dtreq dtgrt dtack memwr memoe wc/cwc d15-d0 data valid t1 t2 t6 t9 t5 t4 t7 t10 t11 t13 t12 l-bro, t/r, sa4-sa0 valid cwc = 0 t8 t3 dma single word read
27 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 t1 clock in rising to dtreq low all ns t2 dtreq (low) - to - dtgr t delay time all s t4 dtgr t low setup prior to clock in rising all ns t6 clock in rising to dt a ck low all ns t7 dtgr t hold time following dt a ck falling all ns t10 memoe low pulse width t11 time for input data to become valid following falling edge of memoe t12 data input hold time following clock in rising (see note) all 30 ns t13 clock in rising to dtreq , dt a ck , and memoe high all ns ref description clock frequency value @5 volts units table for figure 11. ssrt dma read timing min typ max 40 10 10 40 30 30 20 mhz ns 150 16 mhz ns 188 12 mhz ns 250 10 mhz ns 300 20 mhz ns 80 16 mhz ns 105 12 mhz ns 146 10 mhz ns 180 t3 cwc setup time prior to memoe falling 20 mhz 60 ns 16 mhz 85 ns 12 mhz 127 ns 10 mhz 160 ns t5 dtgr t falling to dt a ck low 20 mhz ns 100 16 mhz ns 113 12 mhz ns 133 10 mhz ns 150 t8 dt a ck low pulse width 20 mhz ns 200 16 mhz ns 250 12 mhz ns 333 10 mhz ns 400 30 value @3.3 volts min typ max 40 10 10 40 30 40 150 188 250 300 70 95 136 170 60 85 127 160 105 118 138 155 200 250 333 400 t9 clock in rising to memoe low all ns 40 40 no te : (1) the ssrt ? s data sampling time occurs one clock cycle prior to the rising edge of memoe .
28 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 12. auto-configuration - dma read transfer timing clock in dtreq dtgrt dtack memwr memoe d15-d0 mstclr rtactive data valid t2 t3 t6 t5 t4 t7 t9 t11 t13 note1 t10 t8 t12 auto-configuration - dma single word read note1: rtactive asserted high 1 clock following dtack high assuming self-test is not enabled. when self-test is enabled rtactive is delayed in the amount of 't12'. see the table reference for details. t1
29 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 no tes : (1) during auto-configuration the ssrt samples data three clock cycles following the falling edge of dt a ck . (2) if self-test mode is not enabled, then rtactive will go active high 1 clock cycle following the rising edge of dt a ck . if self-test is enabled then rtactive will be delayed from going active high in accordance with ? t12 ? . t2 clock in rising to dtreq low all ns t3 dtreq (low) - to - dtgr t delay time all s t4 dtgr t low setup prior to clock in rising all ns t6 clock in rising to dt a ck low all ns t7 dtgr t hold time following dt a ck falling all ns t9 time for input data to become valid following falling edge of dt a ck t12 rtactive high delayed from dt a ck high (see note 2) t13 clock in rising to rtactive high all ns ref description clock frequency value @5 volts units table for figure 12. auto-configuration - dma read timing min typ max 40 10 10 40 30 30 20 mhz ns 120 16 mhz ns 157 12 mhz ns 220 10 mhz ns 270 20 mhz ms 1.6 16 mhz ms 2.0 12 mhz ms 2.7 10 mhz ms 3.2 t5 dtgr t falling to dt a ck low 20 mhz ns 100 16 mhz ns 113 12 mhz ns 133 10 mhz ns 150 t8 dt a ck low pulse width 20 mhz 185 ns 200 215 16 mhz 235 ns 250 265 12 mhz 318 ns 333 348 10 mhz 385 ns 400 415 value @3.3 volts min typ max 40 10 10 40 30 40 120 157 220 270 1.6 2.0 2.7 3.2 105 118 138 155 185 200 215 235 250 265 318 333 348 385 400 415 t10 data input hold time following sampling time (see note 1) all 30 ns 30 t11 clock in rising to dtreq , dt a ck , and memoe high all ns 30 40 t1 mstclr high delay to dtreq low 20 mhz 35 ns 50 65 16 mhz 47.5 ns 62.5 77.5 12 mhz 68.3 ns 83.3 98.3 10 mhz 85 ns 100 115 35 50 65 47.5 62.5 77.5 68.3 83.3 98.3 85 100 115
30 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 13. clock edge signal timing clock in signal in signal out high to low signal out low to high t1 t2 t3 clock edge to signal in / out timing t1 signal input setup time prior to clock in rising edge 10 ns t2 clock in rising edge to signal output driven low (see note) ns t3 clock in rising edge to signal output driven high (see note) ns ref description value @5 volts units table for figure 13. ssrt clock edge to signal in / out valid timing min typ max 40 30 15 value @3.3 volts min typ max 40 40 no te : (1) assumes a 50 pf external load. for loading above 50pf, the validity of output signals is delayed by an additional 0.14 ns/pf typ, 0.28ns/pf max.
31 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 interface to mil-std-1553 bus figure 14 illustrates the interface between the bu-61703/5 ssrt and a mil-std-1553 bus. connections for both direct (short stub) coupling and transformer (long stub) coupling, as well as the peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. bu-61703/5 ssrt data bus z 0 55 ? ?
32 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 pulse transformers in selecting isolation transformers to be used with the simple system rt, there is a limitation on the maximum amount of leak- age inductance. if this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by mil-std-1553. in addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. the maximum allowable leakage inductance is 6.0 h, and is measured as follows: the side of the transformer that connects to the simple system rt is defined as the ? primary ? winding. if one side of the primary is shorted to the primary center-tap, the inductance should be measured across the ? secondary ? (stub side) winding. this inductance must be less than 6.0 h. similarly, if the other side of the primary is shorted to the prima- ry center-tap, the inductance measured across the ? secondary ? (stub side) winding must also be less than 6.0 h. the difference between these two measurements is the ? differential ? leakage inductance. this value must be less than 1.0 h. beta transformer technology corporation (bttc), a subsidiary of ddc, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct cou- pled, and 1:1.79 transformer coupled. table 4 provides a listing of many of these transformers. for further information, contact bttc at 631-244-7393 or at www.bttc-beta.com. table 4. recommended beta transformers for use with ssrt b-3819 single epoxy transformer, surface mount, hi-temp solder, 0.625" x 0.625", 0.220" max height. (may be used with bu-6170xx4 version of ssrt) b-3310 dual epoxy transformer, side by side, surface mount, 0.930" x 0.630", 0.155" max height b-3261 dual epoxy transformer, side by side, flat pack, 0.930" x 0.630", 0.155" max height b-3300 lpb-5015 dual epoxy transformer, side by side, through-hole, 0.930" x 0.630", 0.155" max height b-3818 hlp-6015 single metal transformer, hermetically sealed, surface mount, 0.630" x 0.630", 0.175" max height hlp-6014 single metal transformer, hermetically sealed, flat pack, 0.630" x 0.630", 0.175" max height tst-9027 dual epoxy transformer, twin stacked, flat pack, 0.625" x 0.625", 0.280" max height tst-9017 dual epoxy transformer, twin stacked, surface mount, 0.625" x 0.625", 0.280" max height tst-9007 dual epoxy transformer, twin stacked, 0.625" x 0.625", 0.280" max height lpb-5014 single epoxy transformer, flat pack, 0.625" x 0.625", 0.150" max height b-3227 single epoxy transformer, surface mount, 0.625" x 0.625", 0.275" max height b-3231 single epoxy transformer, flat pack, 0.625" x 0.625", 0.275" max height b-3226 single epoxy transformer, through-hole, 0.625" x 0.625", 0.250" max height bttc part no. transformer configuration single epoxy transformer, surface mount, 0.625" x 0.625", 0.150" max height single epoxy transformer, through-hole, 0.625" x 0.625", 0.220" max height. (may be used with bu-6170xx4 version of ssrt) b-3229 single epoxy transformer, through hole, transformer coupled only, 0.500" x 0.350", 0.250" max height dual epoxy transformer, side by side, surface mount, 1.410" x 0.750", 0.130" max height dlp-7115 (see note 3) notes: 1. for mcair version of the simple system rt (bu-6170xx4) , only the b-3818 or b-3819 transformers (shown in bold in the table) may be used. 2. for all other applications, any of the other transformers listed may be used. 3. dlp-7115 operates to +105 c max. all other transformers listed operate to +130 c max..
33 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 p.c. board layout guidelines ground planes as is the rule in all high-speed digital circuits, it is good practice to use ground and power supply planes under the ssrt hybrid as well as the associated digital components. the reason for not using supply or ground planes under the ana- log signal traces is that the effect of the distributed capacitance will be to lower the input impedance of the terminal, as seen from the 1553 bus. mil-std-1553 requires a minimum input imped- ance of 2000 ohms for direct coupled terminals and 1000 ohms for transformer (stub) coupled terminals. if there are ground planes under the analog bus signal traces, it is likely that the ter- minal will not meet this requirement. power and ground distribution another important consideration is power and ground distribu- tion. refer to figure 15. for the ssrt hybrid/transformer com- bination, the high current path when the ssrt is transmitting will be from the +5 volt power supply, through the transmitter output stage, through one leg of the isolation transformer to the trans- former center tap. it is important to realize that the high current return path is through the transformer center tap and not through the ssrt ground pins. another important layout consideration is to minimize the power supply distribution impedance along this path. any resistance will result in voltage drops for the power supply input voltage, and can ultimately lower the transmitter output voltage, possibly below the minimum level required by mil-std-1553 or mil-std-1760. however, it is very important that there be no ground and/or power supply planes underneath the analog bus signal traces. this applies to the tx/rx signals running between the ssrt and the isolation transformers as well as the traces between the transformers to any connectors or cables leaving the board. figure 15. power - ground distribution logic rx transceiver tx high level currents low level currents low / medium level currents logic gnd gnd a/b logic +5 v a/b +5 v or +3.3 v ssrt
34 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 1553 bus connections the isolation transformers should be placed as physically close as possible to the respective tx/rx pins on the ssrt. in addi- tion, the distance from the isolation transformers to any connec- tors or cables leaving the board should be as short as possible. in addition to limiting the voltage drops in the analog signal traces when transmitting, reducing the hybrid-to-transformer and transformer-to-connector spacing serves to minimize crosstalk from other signals on the board. the general practice in connecting the stub side of a transformer (or direct) coupled terminal to an external system connector is to make use of 78 ohm twisted-pair shielded cable. this minimizes impedance discontinuities. the decision of whether to isolate or make connections between the center tap of the isolation trans- former's secondary, the stub shield, the bus shield, and/or chas- sis ground must be made on a system basis, as determined by an analysis of emi/rfi and lightning considerations. in most systems, it is specified that the 1553 terminal's input impedance must be measured at the system connector. this is despite the fact that the mil-std-1553b requirement is for it to be measured looking directly in from the bus side of the isolation transformer. the effect of a relatively long stub cable will be to reduce the measured impedance (looking in from the bus). in order to keep the impedance above the required level of 1000 ohms (for trans- former-coupled stubs), the length of any cable between the 1553 rt and the system connector should be minimized. "simulated bus" (lab bench) interconnec- tions for purposes of software development and system integration, it is generally not necessary to integrate the required couplers, ter- minators, etc., that comprise a complete mil-std-1553b bus. in most instances, a simplified electrical configuration will suffice. the three connection methods illustrated in figure 16 allow the ssrt to be interfaced over a "simulated bus" to simulation and test equipment. it is important to note that the termination resistors indicated are necessary in order to ensure reliable com- munications between the ssrt and the simulation/test equipment. figure 16. "simulated bus" (lab bench) interconnections ssrt hybrid test/ simulation equipment stub coupling stub coupling isolation transformer 78 ? ? ? ? ? ? ? ? ? ? ?
35 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 simple system interface figure 17 illustrates the capability of the ssrt to interface to a system with no host processor in burst mode. in this example, only one set of external latches is needed to buffer the data words written by the ssrt to the external system. in burst mode, all received data words are stored in the internal fifo until the last word is received. at this point, the ssrt will transfer the entire contents of the fifo to the system if the message is vali- dated. in this case, gbr will be driven low for two clock cycles following the burst transfer cycle. if the received message is not valid, the fifo data will not be transferred to the external system and gbr will remain high. figure 17. ssrt-to-simple system interface (shown for burst mode) d15-d0 write address decoder read address decoder latch latch tri-state buffer tri-state buffer en tri-state buffer en en en l-bro, t/r, sa4-0, wc/cwc4-0 memwr discrete digital inputs discrete digital outputs auto- configuration (optional) rtactive dtack auto_cfg memoe bu-61703/5 ssrt en clock oscillator clk-in rtad4-0, rtadp mstclr +5v rt address bus a bus b dtgrt +5v
36 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 bit word the bu-61703/5 provides an internally formulated built-in-test word (bit word). this word is transmitted to the bc in response to a transmit bit word mode code command. the bit word bit functions and descriptions are provided in table 5. if set, indicates that, for the previous message, the ssrt was the receiving rt for an rt-to-rt trans- fer and that the transmitting rt either did not respond or responded later than the ssrt rt-to-rt timeout time. the ssrt's rt-to-rt response timeout time is defined as the time from the mid-bit crossing of the parity bit of the transmit command word to the mid-sync crossing of the transmitting rt status word. the value of the ssrt's rt-to-rt response timeout time is in the range from 17.5 to 19.5 s. indicates that a received command word is not defined in accordance with mil-std-1553b. this includes the following undefined command words: (1) the command word is a non-mode code, broadcast, transmit command; (2) a message with a t/r bit of "0", a subaddress/mode field of 00000 or 11111, and a mode code field with a value between 00000 and 01111; (3) a mode code command that is not permitted to be broadcast (e.g., transmit status) is sent to the broadcast address 11111. indicates that the ssrt received one or more words containing one or more of the following error types: sync field error, manchester encoding error, parity error, and/or bit count error. this bit is set if the ssrt is the receiving rt for an rt-to-rt transfer and one or more of the follow- ing errors occurs: (1) if the transmitting rt responds with a response time of less than 4 s, per mil- std-1553b (mid-parity bit to mid-sync); i.e., less than 2 s dead time; and/or (2) there is an incorrect sync type or format error (encoding, bit count, and/or parity error) in the transmitting rt status word; and/or (3) the rt address field of the transmitting rt status word does not match the rt address in the transmit command word. if the ssrt is the receiving rt for an rt-to-rt transfer, if this bit is set, it indicates one or more of the following error conditions in the transmit command word: (1) t/r bit = logic "0"; (2) subaddress = 00000 or 11111; (3) same rt address field as the receive command word. if set, indicates that the ssrt detected a command sync in a received data word. set to logic "1" if the previous message had a low word count error. rt-rt transfer no response timeout command word contents error invalid word manchester/parity error received rt-rt transfer response error (no gap, data, sync, address mismatch) rt-rt transfer - t/r error on second command or invalid address incorrect sync type received low word count 2 0 (lsb) 4 3 1 5 6 set to logic "1" if the previous message had a high word count error. high word count 7 set to logic "1" to denote that the ssrt has failed its off-line protocol self-test. this bit will be logic "0" if the self-test passed or had not been performed. bit test fail 8 set to logic "1" if the ssrt's terminal flag rt status bit has been disabled by an inhibit terminal flag mode code command. will revert to logic "0" if an override inhibit terminal flag mode code command is received. terminal flag inhibited 9 if this bit is set, it indicates that the subsystem had failed to respond with the dma handshake input dtgr t asserted within 10 s after the ssrt has asserted dtreq . handshake failure 12 a loopback test is performed on the transmitted portion of every non-broadcast message. a validity check is performed on the received version of every word transmitted by the ssrt. in addition, a bit- by-bit comparison is performed on the last word transmitted by the rt for each message. if either the received version of the last word does not match the transmitted version and/or the received version of any transmitted word is determined to be invalid (sync, encoding, bit count, parity), or a failsafe timeout occurs on the respective channel, the loop test failure bit for the respective bus chan- nel will be set. ch. b loop test failure ch. a loop test failure 14 13 set if the ssrt's failsafe timer detected a fault condition. the transmitter timeout circuit will automati- cally shut down the ch. a or ch. b transmitter if it transmits for longer than 660.5 s. transmitter timeout 15 (msb) table 5. internal built-in-test (bit) word definition description function bit if either of these bits are logic "1", this indicates that the respective 1553 transmitter has been shut down by means of a transmitter shutdown mode command. transmitter shutdown b transmitter shutdown a 11 10 note : bits 15 through 9 are cleared only following a reset input or receipt of a reset remote terminal mode command. bits 8 through 0 are updated as a result of every message processed.
37 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 mode codes the bu-61703/5 fully implements all 13 of the dual redundant mil-std-1553b mode codes. four mode codes, transmit vector word, synchronize (with data), selected transmitter shutdown, and override transmitter shutdown, involve data transfers with the subsystem. for the transmit last command mode command, the data word transmitted is from the ssrt's last command internal register. for the transmit bit word mode command, the ssrt's internally formulated bit word is transmitted. table 6 provides a summary of the 1553b mode codes supported by the bu-61703/5. summary of responses to mode code mes- sages the ssrt's responses to mode codes, including responses to various error conditions, are summarized in table 6. no ye s transmit bit word inhibit terminal flag from internal register no 10011 00110 1 1 no ye s transmit last command override transmitter shutdown from internal register no 10010 00101 1 1 tbd no ye s reserved transmit vector word initiate self test from subsystem from subsystem no 10110-11111 10000 00011 1 1 1 ye s tbd no override selected transmitter shutdown (see note) reserved transmit status word to subsystem no no 10101 01001-01111 00010 0 1 1 ye s ye s ye s selected transmitter shutdown (see note) reset remote terminal synchronize to subsystem no no 10100 01000 00001 0 1 1 ye s no override inhibit terminal flag dynamic bus control no no 00111 00000 1 1 no undefined no 00000-01111 0 table 6. mode code summary broadcast allowed function data word mode code t/r bit tbd ye s ye s reserved synchronize with data transmitter shutdown to subsystem to subsystem no 10110-11111 10001 00100 0 0 1 note : for the selected transmitter shutdown and override transmitter shutdown mode commands, the ssrt responds with clear status but no action is taken.
38 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 detailed mode codes functional description the applicable mode codes for the ssrt are described below: dynamic bus control ( t/r = 1; 00000) message sequence = dbc + status the ssrt responds with status showing non-acceptance of the mode code command. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast received bits (status word), command word contents error (bit word). 5. broadcast address. no status response. set message error and broadcast received bits (status word), command word contents error (bit word). synchronize without data word ( t/r = 1; 00001) message sequence = sync + status the ssrt responds with status. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast received bits (status word), command word contents error (bit word). transmit status word ( t/r = 1; 00010) message sequence = transmit status + status the status register is not updated before it is transmitted and contains the resulting status from the previous command (assuming that it was not a transmit status or transmit last command mode command). error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word) 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast received bits (status word), command word contents error (bit word). 5. broadcast address. no status response. set message error and broadcast command received bits (status word), command contents error (bit word). initiate self-test ( t/r = 1; 00011) message sequence = self test + status if the command was non-broadcast, the ssrt responds with status. if the command was either non-broadcast or broadcast, the ssrt will go offline and perform its internal off-line protocol self-test. the self-test exercises the ssrt's encoder and decoders, registers , transmitter watchdog timer, and protocol logic. this test is completed in approximately 32,000 clock cycles. that is, about 1.6 ms with a 20 mhz clock , 2.0 ms at 16 mhz, 2.7 ms at 12 mhz, and 3.2 ms at 10 mhz. while the ssrt is performing its off-line self-test, it will ignore (and therefore not respond to) all messages received from t he 1553 bus. the bus controller may determine the result of the self-test by means of a transmit bit word mode command. if the self-test passes, bit 8 of the ssrt's bit word (bit test fail) will be logic "0"; if the self-test fails, this bit will be logic "1". in addition, if self-test fails, the terminal flag status word bit will be set to logic ? 1 ? in response to the next non-broadcast message. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). 5. loopback test failure. set terminal flag bit in internal status register (status word for next non-broadcast command), current channel (a or b) loop test failure and ch a/b loop test failure (bit word), assert r tf ail output.
39 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 override inhibit terminal flag bit ( t/r = 1; 00111) message sequence = override inhibit terminal flag + status the ssrt responds with status and re-enables the terminal flag bit in its internal status register. if the command was a broadca st, the broadcast command received bit is set and status transmission is suppressed. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). inhibit terminal flag bit ( t/r = 1; 00110) message sequence = inhibit terminal flag + status the ssrt responds with status and inhibits further setting of the terminal flag bit in its internal status word register. once t he terminal flag has been inhibited, it can only be reactivated by an override inhibit terminal flag or reset rt mode code commands, or by reset . if the com- mand was broadcast, the broadcast received bit is set, the state of the terminal flag bit in the internal status word register remains unchanged and status transmission is suppressed. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). override transmitter shutdown ( t/r = 1; 00101) message sequence = override shutdown + status this command is only used with dual redundant bus systems. the ssrt responds with status. at the end of the status transmission, the ssrt reactivates the transmitter of the alternate redundant bus. if the command was broadcast, the broadcast command received st atus word bit is set and status transmission is suppressed. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). transmitter shutdown ( t/r = 1; 00100) message sequence =shutdown + status this command is only used with dual redundant bus systems. the ssrt responds with status. following the status transmission, the ssrt inhibits any further transmission from the alternate redundant channel. once shutdown, the transmitter can only be reactivated b y an override transmitter shutdown or reset rt mode command, or hardware reset (mstrclr input). note that the receivers on both channels are a lways active, even when the transmitters are inhibited. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word).
40 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 transmit vector word ( t/r = 1; 10000) message sequence = transmit vector word + status vector word the ssrt transmits a status word followed by a vector word. the vector word is read from the external subsystem. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), and low word count (bit word). 4. t/r bit set to zero plus one data word . the ssrt will respond with status 5. zero t/r bit and broadcast address, no data word. no status response. set message error and broadcast command received bits (status word), and low word count (bit word). 6. zero t/r bit and broadcast address, plus one data word. no status response. set broadcast command received bits (status word) 7. broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). synchronize with data word ( t/r = 0; 10001) message sequence = synchronize command/data word + status the ssrt will write the received 16 bit data word to the external subsystem. error conditions 1. invalid command. no response, command ignored. 2. correct command not followed by data word. no status response. set message error bit (status word), low word count (bit word) 3. command followed by too many data words. no status response. set message error bit (status word), high word count (bit word). 4. command t/r bit set to one followed by data word. no status response. set message error bit (status word), and high word count (bit word). 5. command t/r bit set to one not followed by data word. the ssrt replies with status plus one data word. the data word is read from the subsystem (or single-word data block for subaddress 0000 or 1111). 6. command t/r bit set to one and broadcast address. no status response. set message error and broadcast command received bits (status word); set command word contents error (bit word). reserved mode codes ( t/r = 1; 01001 - 01111) message sequence = reserved mode command + status the ssrt responds with status. if the command has been illegalized by means of the illegalization table, the message error statu s word bit will be set. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). reset remote terminal ( t/r = 1; 01000) message sequence = reset remote terminal + status the ssrt responds with status and internally resets. the message error and broadcast command received bits of the internal statu s register are reset to 0. the internal bit word register is reset to 0. if either of the 1553 transmitters has been shut down, the shutdown condition is over- ridden. if the terminal flag bit has been inhibited, the inhibit is overridden. if the command is received as a broadcast, the broadcast command received bit is set and the status word is suppressed. also, if the com- mand is received as a broadcast and the terminal flag bit had been set as a result of the loopback test of the previous message , the terminal flag bit is not reset to zero. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. t/r bit set to zero. no status response. set message error bit (status word), command word contents error (bit word). 4. zero t/r bit and broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word).
41 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 selected transmitter shutdown ( t/r = 0; 10100) message sequence = transmitter shutdown/data + status the data word received is transferred to the subsystem and status is transmitted. no other action is taken by the ssrt. no transm itters are shut down as a result of this mode command. this command is intended for use with rts with more than one dual redundant channel. if the command was a broadcast, the broadcast command received bit is set and status transmission is suppressed. error conditions 1. invalid command. no response, command ignored. 2. command not followed by data word. no status response. set message error bit (status word), and low word count bit (bit word). no status response. bits set: message error (sw), high word count, illegal mode code (bit word) 3. command followed by too many data words. no status response. set message error bit (status word), and high word count bit (bit word). 4. command t/r bit set to one followed by one data word. no status response. set message error bit (status word), and high word count (bit word). 5. command t/r bit set to one not followed by data word. the ssrt replies with status plus one data word. the data word is read from the subsystem. 6. command t/r bit set to one and broadcast address. no status response. set message error and broadcast command received bits (status word), and command contents error (bit word). transmit bit word ( t/r = 1; 10011) message sequence = transmit bit word + status/bit word the ssrt responds with status followed by the built-in test (bit) word. error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count error (bit word). 3. t/r bit set to zero, no data word. no status response. set message error bit (status word), low word count (bit word). 4. t/r bit set to zero, plus one data word. the ssrt will respond with status. the data word is transferred to internal registers. 5. zero t/r bit and broadcast address, no data word. no status response. set message error and broadcast received bits (status word), low word count error (bit word). 6. zero t/r bit and broadcast address, one data word. no status response. set broadcast received bit (status word). the data word is transferred to internal registers. 7. broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word). transmit last command ( t/r = 1; 10010) message sequence = transmit last command + status/last command the status register is not updated before transmission. it contains the status from the previous command. the data word transmitt ed contains the previous valid command (providing it was not another transmit last command or transmit status word mode command). error conditions 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count error (bit word). 3. t/r bit set to zero, no data word. no status response. set message error bit (status word), low word count (bit word). 4. t/r bit set to zero, plus one data word. the ssrt will respond with status. the data word is transferred to the internal register. 5. zero t/r bit and broadcast address, no data word. no status response. set message error and broadcast received bits (status word), low word count error(bit word). 6. zero t/r bit and broadcast address, one data word. no status response. set broadcast received bit (status word). the data word is transferred to the internal register. 7. broadcast address. no status response. set message error and broadcast command received bits (status word), command word contents error (bit word).
42 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 reserved mode codes ( t/r = 1; 11111) message sequence (when t/r = 1) = reserved mode code status/data (when t/r = 0) = reserved mode code data + status for a reserved receive command, the ssrt stores the data word to the subsystem. if the command was a broadcast, the broadcast command received bit is set and status transmission is suppressed. for a reserved transmit command word, the ssrt responds with status plus a single data word. the data word is read from the subsystem. error conditions (t/r = 1) 1. invalid command. no response, command ignored. 2. command followed by data word. no status response. set message error bit (status word), high word count (bit word). 3. broadcast command. no status response. set message error bit (status word), and command word contents error (bit word). error conditions (t/r = 0) 1. invalid command. no response, command ignored. 2. command not followed by contiguous data word. no status response. set message error bit (status word), and low word count (bit word). 3. command followed by too many data words. no status response. set message error bit (status word), and high word count (bit word). override selected transmitter shutdown ( t/r = 0; 10101) message sequence = transmitter shutdown/data + status the data word received is transferred to the subsystem. no transmitters that have been previously shut down are reactivated as a result of this command. no other action is taken by the ssrt. this command is intended for use with rts with more than one dual redundant channe l. if the command was a broadcast, the broadcast command received bit is set and status transmission is suppressed. error conditions 1. invalid command. no response, command ignored. 2. command not followed by data word. no status response. set message error bit (status word), and low word count (bit word). 3. command followed by too many data words. no status response. set message error bit (status word), and high word count bit (bit word). 4. command t/r bit set to one followed by data word. no status response. set message error bit (status word), and high word count (bit word). 5. command t/r bit set to one not followed by data word. the ssrt replies with status plus one data word. the data word is read from the subsystem. 6. command t/r bit set to one and broadcast address. no status response. set message error and broadcast command received bits (status word), and command contents error (bit word).
43 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 table 8. mil-std-1553 isolation transformer interface analog transmit/receive signals. connect directly to 1553 isolation transformers. 16 tx/rx-b (i/o) 13 tx/rx-b (i/o) 7 tx/rx-a (i/o) 5 tx/rx-a (i/o) description pin signal name +5v vcc ch a pin signal name 72 channel a transceiver power. +5v vcc ch b 20 channel b transceiver power. +5v / +3.3v logic 37 logic power. for bu-61703 this pin must be connected to +3.3v . for bu-61705 this pin must be connected to +5v . ground 17 ground. 18 19 26 table 7. power and ground 71 67 65 description signal descriptions by functional groups
44 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 3 l_bro (o) latched broadcast. this two-state output signal is latched following receipt of a new command word. for a broadcast command, this signal outputs a value of logic "1". for a non-broadcast message, this signal will output logic "0". 4 t / r transmit/receive. this two-state output signal is latched following receipt of a new command word. for a transmit mes- sage, this signal will output a value of logic "1". for a receive message, this signal will output logic "0". 69 sa2 (o) subaddress. these five two-state output signals are latched following receipt of a new command word. they provide the subaddress field of the received command word. pin 9 wc / mc / cwc2 (o) word count/mode code/current word count. following receipt of a new command word, these five two-state output sig- nals provide the contents of the command word's word count/mode code field. for a non-mode code receive message, the contents of wc/cwc are updated and incremented to reflect the value of the current data word being transferred to the system (in non-burst mode), or to the internal fifo (in burst mode). cwc increments from 0 to the value of the word count field - 1 during the message. at the end of a non-mode code receive message in burst mode, the contents of cwc will then increment from 0 to the value of the word count field -1, as each word is transferred from the internal fifo to the external system over d15-d0. in burst mode, it takes three clock cycles to transfer each word to the external system. for a non-mode code transmit command, the value of cwc starts from 0 and increments to the value of word count - 1, as each word is read from the external system and transferred to the ssrt. for a mode code command, the wc/cwc outputs the command word mode code field, which remains latched through the end of the message (until receipt of a subsequent command word). table 10. command / address bus signal sa4 (o) sa3 (o) sa1 (o) 22 11 6 sa0 (o) 68 wc / mc / cwc4 (o) (msb) wc / mc / cwc3 (o) wc / mc / cwc1 (o) 27 12 description 10 wc / mc / cwc0 (o) (lsb) 15 bi-directional data bus. when the ssrt is writing data to the external system, these signals are active outputs. at all other times, these signals are high impedance inputs. 42 d10 (i/o) d0 (i/o) (lsb) 38 d1 (i/o) 43 d2 (i/o) 44 d3 (i/o) d4 (i/o) 39 45 d5 (i/o) 36 d6 (i/o) 47 d7 (i/o) 46 d8 (i/o) 51 54 d9 (i/o) 52 d11 (i/o) 49 d12 (i/o) table 9. data bus (16) 48 d13 (i/o) 50 d14 (i/o) 53 d15 (i/o) (msb) description pin signal name
45 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 description remote terminal address error. output signal that reflects the parity combination of the rtad[4:0] inputs and rtadp input. a high level indicates odd (correct) parity. a low level indicates even (incorrect) parity. note , if r t_ad_err is low, then the ssrt will not recognize any valid command word received to its own rt address. r t_ad_err (o) 1 rt address inputs. rtad0 (i) (lsb) rtad1 (i) rtad2 (i) rtad3 (i) rtad4 (i) (msb) 33 41 21 34 35 signal table 12. rt address remote terminal address parity. this input signal must provide an odd parity sum with rtad4-rtad0 in order for the rt to respond to non-broadcast commands. that is, there must be an odd number of logic "1"s from among rtad-4- rtad0 and rtadp. rtadp (i) 40 pin rt address latch. if rt_ad_lat is connected to logic "0", then the ssrt is configured to accept a hardwired rt address from rtad4-rtad and rtadp. if rt_ad_lat is initially logic "0", and then transitions to logic "1", the values presented on rtad4-rtad0 and rtadp will be latched internally by the ssrt on the rising edge of rt_ad_lat. rt_ad_lat (i) 31 signal table 11. dma handshake and transfer control signals pin dt a ck (o) memwr (o) memoe (o) hs_f ail (o) dtgr t (i) 29 23 14 57 64 description data transfer acknowledge. active low output signal used to indicate the ssrt's acceptance of the system data bus (d15-d0), in response to a data transfer grant (dtgr t ). the ssrt's data transfers over d15-d0 will be framed by the time that dt a ck is asserted low. if a ut o_cfg is strapped to logic "0", there will be a dtreq /dtgr t handshake cycle after the rising edge of mstclr , following power turn-on. after dtgr t is sampled low, dt a ck and rtactive will then be asserted low to enable configu- ration data to be read from an external tri-state buffer. for transmit messages, or receive messages in non-burst mode, or for receive messages to subaddress 30 assuming that subaddress 30 autowrap is disabled, dt a ck will be asserted low to indicate the transfer of individual words between the external system and the ssrt. for receive messages in burst mode assuming a valid received message, dt a ck will be asserted low after the dtreq - to-dtgr t handshake following the receipt of the last received data word. it will remain low for the duration of the dma burst write transfer from the ssrt to the external system. the total time for a burst write transfer is three clock cycles times the number of data words. memory write. active low two-state output signal (one clock cycle wide) asserted low during ssrt write cycles. used to transfer data from the ssrt to the external system. the external system may latch data on either the falling or rising edge of memwr . memory output enable. memoe two-state output signal is used to enable data inputs from the external system to be enabled on to d15-d0. memoe pulses low for three clock cycles for each data word read from the external system. the ssrt latches the data one clock cycle prior to the rising edge of memoe . handshake fail. if this signal is asserted low, this indicates a handshake timeout condition. that is, the system did not respond with a dtgr t in time, following the ssrt's assertion of dtreq . data transfer grant. input from the external subsystem that must be asserted low in response to the ssrt asserting dtreq low in order to enable the ssrt to read data from or write data to the external subsystem. the maximum allowable time from dtreq to dtgr t is 10 s. if the ssrt's dma handshake isn't required, dtgr t may be hardwired to logic "0". data transfer request. active low level output signal used to request use of the external system data bus (d15-d0). dtreq (o) 24
46 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 description remote terminal fail. this two-state output signal will be asserted low following a failure of the built-in self-test performed following power turn-on or as the result of the receipt of an initiate self-test mode command. the built-in off-line self-test includes tests of the manchester encoder and decoders, transmitter failsafe timer, and rt protocol logic. in addition, r tf ail will be asserted low following a failure of the on-line loop test for any non-broadcast message. the on- line loop test verifies the validity of the received version of all transmitted words (sync, manchester encoding, bit count, parity), and includes a bit-by-bit comparison and verification of the last transmitted word. if asserted to logic "0", r tf ail will clear to logic "1" when the ssrt begins transmission of its status word in response to a subsequent valid non-broadcast message. message error. active low level two-state output signal used to flag to the external system that there was a message error on the 1553 bus communication (word, gap, or word count error) for a particular message. this output goes low upon detecting the error and is reset following the receipt of the next valid command word (to the rt) from the 1553 bus, or if mstclr is asserted low. if this output goes low, all further servicing of the current message is aborted. good block received. low level two-state output pulse (2 clock cycles wide) that is used to indicate to the external sys- tem that a valid, legal, non-mode receive command with the correct number of valid data words has been received and transferred to the external system. for non-burst mode, this pulse will occur after the last data word is transferred. assuming a dtreq -to-dtgr t time of 0, this will be approximately 4 s following the mid-parity bit crossing of the last received data word. for burst mode, the gbr pulse will begin synchronous with the rising edge of dt a ck at the end of the burst write transfer. r tf ail (o) msg_err (o) gbr (o) 58 28 60 signal table 14. rt activity and message status indicators rt active. this signal will be low (logic "0") following power turn-on, and when the ssrt is reading its auto-configure word or is performing its internal self-test. after the self-test passes, or if the auto-configure option is not used, or if aut o- configure is used but bit 5 of the auto-configure word is logic "1" (meaning for the rt to always go online), rtactive will then transition to logic "1". when this occurs, the ssrt will begin processing messages over the 1553 bus. if auto-configure is enabled, and bit 5 of the auto-configure word is logic "0" and the self-test fails, then rtactive will remain at logic "0". in this case, the ssrt will remain offline and not process any 1553 messages. a failed self test will cause rtfail_l to be asserted low (logic ? 0"). if the auto-configure option is used, the external system should enable the configuration bits on d5-d0 when rtactive and dt a ck are both outputting logic "0". rtactive 56 pin in-command. this two-state output is asserted low whenever a message is being processed by the ssrt. incmd 25 description busy. if this input is asserted low, the busy bit will be set to logic "1" in the ssrt's status word. if the busy bit in the sta- tus word is logic "1", the ssrt will not transmit any data words, except for a transmit last command or transmit bit word mode command. for a receive command, if the ssrt is busy, it will still transfer data words to the external system (although these transfers may be blocked by means of external logic). subsystem flag. if this input is asserted low, the subsystem flag bit will be set in the ssrt's status word. b usy (i) ssfla g (i) 55 32 signal table 13. rt status word inputs illegal. input to the ssrt that is sampled after the command word transfer. a logic "0" will cause the message error bit in the status response to be set (logic "1"), while a logic "1" on this input will have no effect on the message error bit. illegal (i) 62 pin service request. when this input is logic "0", the service request bit in the ssrt's status word will be logic "1". when this input is logic "1", the service request bit in the ssrt's status word will be logic "0". sr v_rqst (i) 61
47 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 description signal table 16. clock input clock input. the clock frequency must be designated by means of the clk_sel_1 and clk_sel_0 inputs. clk_in (i) 30 pin these two inputs are used to designate the ssrt's clock frequency, as follows: clk_sel_1 clk_sel_0 cloc k frequenc y 0 0 10 mhz 0 1 20 mhz 1 0 12 mhz 1 1 16 mhz clk_sel_1 (i) clk_sel_0 (i) 66 8 description xcvr_tp (reset*) xcvr_tp (readouta) p5(*) p3(*) signal table 17. factory test xcvr_tp (zap volta) p1(*) pin xcvr_tp (readoutb) p2(*) for factory test only. do not connect for normal operation. xcvr_tp (zap voltb) xcvr_tp (clock) p6(*) p4(*) (*) note that the test output pins are pads located on the bottom of the package. description transmitter inhibit input for the mil-std-1553 transmitters. for normal operation, this input should be connected to logic "0". to force a shutdown of the channel a and channel b transmitters, a value of logic "1" should be applied to this input. tx_inh (i) 59 broadcast enable. if this input is logic "1", the ssrt will recognize rt address 31 as the broadcast address. if this input is logic "0", the ssrt will not recognize rt address 31 as the broadcast address; however, in this configuration, rt address 31 may be used as a standard rt address. bro_ena (i) 63 auto-configure input. if connected to logic "1", then the auto-configure option is disabled, and the six configuration para- meters revert to their default values as listed in table 2. note that the default condition for each configuration parameter is enabled (for the mil-std-1553a/b protocol selection, -1553b is the default). if a ut o_cfg is connected to logic "0", then the configuration parameters are transferred over d5-d0 during a dma read data transfer, when rtactive and dt a ck are logic "0", following mstclr transitioning from logic "0" to logic "1". each of the configuration parameters is enabled if the ssrt reads a value of logic "1" for the respective data bit. a ut o_cfg (i) 70 master clear. negative true reset input, asserted low following power turn-on. when coming out of a ? reset ? condition, note that the risetime of mstclr must be less than 10 s. mstclr (i) 2 signal table 15. control inputs pin
48 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 72 71 +5v vcc-ch. a ground 70 a ut o_cfg 69 sa4 68 67 sa0 ground 66 clk_sel_1 65 ground 64 63 dtgr t br o_ena 62 illegal 61 sr v_rqst 60 59 58 gbr tx_inh r t_f ail 57 hs_f ail 56 rtactive 55 b usy 54 53 52 d10 d15 d11 51 d9 50 d14 49 d12 48 d13 pin 47 d7 46 45 44 d8 d5 d3 43 d2 42 d0 41 rtad1 40 39 bu-61703 (3.3v) bu-61705 (5v) 38 rtadp d4 d1 37 +5v/3.3v-logic xcvr tp (zap voltb) p6 ** xcvr tp (reset_l) p5 ** xcvr tp (clock) p4 ** xcvr tp (readouta) p3 ** xcvr tp (readoutb) p2 ** xcvr tp (zap volta) p1 ** pin bu-61703 (3.3v) bu-61705 (5v) ** note that the test output pins on the flat pack are pads which are located on the bottom of the package. table 18. ? gull wing ? and flat package pin functions r t_ad_err 1 mstclr l_bro pin t/r 2 bu-61703 (3.3v) bu-61705 (5v) 3 4 tx/rx_a 5 sa3 6 tx/rx_a 7 clk_sel_0 wc4 wc3 8 9 10 sa2 11 wc2 12 tx/rx_b 13 memoe 14 wc0 15 tx/rx-b ground ground 16 17 18 ground 19 +5v vcc-ch. b 20 rtad2 21 sa1 memwr dtreq 22 23 24 incmd 25 ground 26 wc1 msg_err 27 28 dt a ck 29 clock_in 30 rt_ad_lat ssfla g 31 32 rtad0 33 rtad3 34 rtad4 d6 35 36 pin functions
49 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 18. flat package mechanical outline drawing 1.000 sq
50 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 figure 19. ? gull wing ? package mechanical outline drawing 1.00 sq
51 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 ordering information bu-61705f3-120x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above test criteria: 0 = standard testing 2 = mil-std-1760 amplitude compliant (not available with voltage/transceiver option 4) process requirements: 0 = standard ddc practices, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in temperature range**/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c with variables test data 5 = -40 c to +85 c with variables test data 6 = custom part (reserved) 7 = custom part (reserved) 8 = 0 c to +70 c with variables test data voltage/transceiver option: 3 = +5 volts rise/fall times = 100 to 300 ns (-1553b) 4 = +5 volts rise/fall times = 200 to 300 ns (-1553b and mcair compatible) (not available with test criteria option ? 2 ? mil-std-1760 amplitude compliant) package type: f = flat pack g = ? gull wing ? (formed lead) logic voltage 3 = 3.3 volt 5 = 5 volt product type: bu-6170 = rt only with simple (non-processor) interface *standard ddc processing with burn-in and full temperature test ? see table below. ** temperature range refers to ? case temperature ? . ? 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing
52 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 notes:
53 data device corporation www.ddc-web.com bu-61703/61705 d1 web-09/02-0 notes:
54 d1 web-09/02-0 printed in the u.s.a. data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7234 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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