1 features over voltage shutdown reset comparator error amplifier + - to v out + + - v ref enable comparator bandgap supply output current limit bandgap reference thermal shutdown - v in enable reset v out gnd 5v 4% output voltage 300ma low dropout voltage (1v @ 150ma) low quiescent current (2.5ma @ i out = 150ma) p compatible control functions low current sleep mode i q =250a fault protection thermal shutdown short circuit 60v load dump enable reset package options 5 lead to-220 tab (gnd) 14 lead soic narrow 8 lead pdip cs8120 5v, 300ma linear regulator with and enable reset 1 cs8120 description the cs8120 is a 5v, 300ma precision linear regulator with two microproces- sor compatible control functions and protection circuitry included on chip. the composite npn-pnp output pass transistor assures a lower dropout volt- age (1v @ 200ma) without requiring excessive supply current (2.5ma). the cs8120?s two logic control func- tions make this regulator well suited to applications requiring microprocessor- based control at the board or module level. controls the output stage. a high voltage (>2.9v) on the lead turns off the regula- tor?s pass transistor and sends the ic into sleep mode where it draws only 250a. the function sends a signal when the ic is power- ing up or whenever the output voltage moves out of regulation. the signal is valid down to v out = 1v. the cs8120 design optimizes supply rejection by switching the internal bandgap reference from the supply input to the regulator output as soon as the nominal output voltage is achieved. additional on chip filtering enhances rejection of high frequency transients on all external leads. the cs8120 is fault protected against short circuit, over voltage and thermal runaway conditions. reset reset reset enable enable block diagram * 1 v in sense nc v out gnd nc nc nc nc nc nc nc reset enable 1 v in enable gnd reset v out sense nc nc 1v in 2 3 gnd 4 5v out reset enable * to-220 block diagram 1 5 lead d 2 pak rev. 6/22/99 cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com a company ?
2 electrical characteristics: v in = 14v, i out =5 ma, -40c t j 150c, -40c t c 125c unless otherwise specified parameter test conditions min typ max unit cs8120 absolute maximum ratings dc input voltage ............................................................................................................... ............................................-0.7 to 26v load dump ...................................................................................................................... ...........................................................60v output current ................................................................................................................. ................................internally limited electrostatic discharge (human body model) ..................................................................................... .................................2kv operating temperature .......................................................................................................... .............................-40c to +125c junction temperature........................................................................................................... ................................-40c to +150c storage temperature ............................................................................................................ ................................-55c to +150c lead temperature soldering wave solder (through hole styles only) .....................................................................................10 s ec. max, 260c peak reflow (smd styles only) ......................................................................................60 sec. max above 183c, 230c peak * to have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable. output stage output voltage, v out 7v v in 26v, 1ma i out 300ma 4.8 5.0 5.2 v line regulation 7v v in 26v, i out = 200ma 50 mv load regulation 1ma i out 300ma 50 mv supply voltage rejection v in = 14vdc + 1 vrms 40 70 db @120hz, i load = 25 ? dropout voltage i out = 200ma 1.0 1.5 v quiescent current = high, v in = 12v 0.25 0.65 ma = low, i out = 200ma 2.5 15.0 ma protection circuits short circuit current 300 600 ma thermal shutdown 150 190 c overvoltage shutdown 26 40 v saturation voltage 1v < v out < v rt(off) , 3.1k ? pull-up 0.1 0.4 v to v out output leakage = low 0 25 a current v out > v rt(on) , v = v out power on/off 3.1k ? pull-up to v out 0.7 1.0 v peak output voltage threshold on v out - 0.10 v out - 0.04 v (v out increasing) threshold off 4.75 v out - 0.14 v (v out decreasing) threshold hysteresis 10 40 mv input high voltage 7v < v in < 26v 2.9 3.9 v input low voltage 7v < v in < 26v 1.1 2.1 v input hysteresis 7v < v in < 26v 0.4 0.8 2.8 v input current gnd < v in(hi) < v out -10 0 +10 a enable reset reset reset reset reset enable reset reset reset enable enable
-35 -40 -45 -50 0 100 200 300 400 500 -30 -25 -20 -15 -10 -5 0 -40 c 25 c 125 c i out (ma) load reg. (mv) v in =14v load regulation vs. output current over temperature 5.02 5.01 5 4.99 4.98 4.97 4.96 4.95 -40 -20 0 20 40 60 80 100 120 140 150 junction temperature ( c) v out (v) 5.00v @25 c i out = 100ma output voltage vs. temperature 0 -10 0 50 100 150 200 250 300 350 400 450 500 10 20 30 40 50 -40 c 125 c i out (ma) line reg. (mv) 25 c v in = 7 to 25v line regulation vs. output current over temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 output current (ma) dropout voltage (v) -40 c 25 c 125 c 50 100 350 150 200 250 300 dropout voltage vs. output current over temperature 3 cs8120 typical performance characteristics package lead description package lead # lead symbol function 5 lead 8 lead 14 lead so 5 lead d 2 to-220 pdip narrow pak 12 1 1 v in supply voltage to ic, usually direct from the battery. 2 4 5 2 cmos compatible logical input. v out is disabled i.e. placed in a high impedance state when is high. 3 8 13 3 gnd ground connection. 4 6 10 4 cmos compatible output lead. goes low when- ever v out falls out of regulation. the delay is externally programmed. 51 14 5 v out regulated output voltage, 5v (typ). n/a 7 12 sense kelvin connection which allows remote sensing of out- put voltage for improved regulation. if remote sensing is not desired, connect to v out . 3, 5 2,3,4, nc no connection 6,7,8,9,11 reset reset reset enable enable
precision voltage reference the regulated output voltage depends on the precision band gap voltage reference in the ic. by adding an error amplifier into the feedback loop , the output voltage is maintained within 4% over temperature and supply variation. output stage the composite pnp- npn output structure (figure 1) provides 300ma (typ) of output current while maintain- ing a low drop out volt- age (1.00v, typ) and drawing little quiescent current (2.5ma). the npn pass device prevents deep saturation of the out- put stage which in turn improves the ic?s efficiency by preventing excess current from being used and dissipated by the ic. output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (figure 2). 4 cs8120 circuit description typical performance characteristics: continued voltage reference and output circuitry v out v in i out v out v in load dump short circuit thermal shutdown > 30v figure 1: composite output stage of the cs8120 5.5 10.0 0.0 supply voltage (v) supply current (ma) v out (v) v out i q 5.0 4.0 3.0 2.0 1.0 0.0 22.0 20.0 16.0 12.0 8.0 4.0 0.0 2.0 4.0 6.0 8.0 output voltage and supply current vs. input voltage 2000 1800 1600 1400 1200 1000 800 600 400 200 0 1 5 10 15 20 25 30 35 40 v in = 5v reset output current (ma) reset output voltage (mv) reset output voltage vs. output current 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 050 -40 c 25 c 125 c output current (ma) quiescent current (ma) v in = 14v 100 150 200 250 300 350 quiescent current vs. output current over temperature figure 2: typical circuit waveforms for output stage protection.
if the input voltage rises above 26v (e.g. load dump), the output shuts down. this response protects the internal cir- cuitry and enables the ic to survive unexpected voltage transients. using an emitter sense scheme, the amount of current through the npn pass transistor is monitored. feedback circuitry insures that the output current never exceeds a preset limit. should the junction temperature of the power device exceed 180c (typ) the power transistor is turned off. thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the ic. the cs8120 contains two microprocessor compatible con- trol functions: and (figure 3). function switches the output transistor. when the voltage on the lead exceeds 2.9v typ, the output pass transistor turns off, leaving a high impedance facing the load. the ic will remain in sleep mode, drawing only 250a, until the voltage on the lead drops below 2.1v typ. hysteresis (800mv) is built into the function to figure 3: circuit waveforms for cs8120 provide good noise immunity. function a signal (low voltage) is generated as the ic pow- ers up (v out > v out - 100mv) or when v out drops out of regulation (v out < v out - 140mv, typ). 40mv of hysteresis is included in the function to minimize oscillations. the output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic, thereby figure 4: rc network for delay circuitry guaranteeing that the signal is valid for v out as low as 1v. an external rc network on the lead (figure 4) pro- vides a sufficiently long delay for most microprocessor based applications. rc values can be chosen using the fol- lowing formula: r tot c rst where: r tot = r rst in parallel with r in, r in = p port impedance, c rst = delay capacitor, t delay = desired delay time, v rst = v sat of lead (0.7v @ turn - on), and v t = p logic threshold voltage. reset reset ] [ reset reset reset c rst r rst c 2 22 f 5v to p and system power to p reset port reset cs8120 v out reset reset reset (1) = no reset delay capacitor (2) = with reset delay capacitor for 7v < v in < 26v v out v rt(on) enable v rt(off) (1) (2) v in v in(hi) h hi lo vr peak vr sat vr peak reset enable enable enable enable reset enable regulator control functions 5 ?t delay ln ) v t ? v out v rst ? v out ( applications notes cs8120 the circuit depicted in figure 5 lets the microprocessor control its power source, the cs8120 regulator. an i/o port on the p and the switch port are used to drive the base of q1. when q1 is driven into saturation, the voltage on the lead falls below its lower threshold. the regulator?s output is switched out. when the drive cur- rent is removed, the voltage on the lead rises, the output is switched off and the ic moves into sleep mode where it draws 250a. by coupling these two controls with , the system has added flexibility. once the system is running, the state of the switch is irrelevant as long as the i/o port continues to drive q1. the p can turn off its own power by withdrawing drive current, once the switch is open. this software control at the i/o port allows the p to fin- ish key housekeeping functions before power is removed. the logic options are summarized in table 1 below enable enable enable circuit description: continued table 1: logic control of cs8120 output p i/o drive switch output on closed low on open low on off closed low on open high off enable
6 application notes the i/o port of the microprocessor typically provides 50a to q1. in automotive applications the switch is connected to the ignition switch. the output or compensation capacitor, c 2 , helps deter- mine three main characteristics of a linear regulator: start- up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instabil- ity. the aluminum electrolytic capacitor is the least expen- sive solution, but, if the circuit operates at low tempera- tures (-25c to -40c), both the value and esr of the capacitor will vary considerably. the capacitor manufac- turers data sheet usually provides this information. the value for the output capacitor c 2 shown in figure 6 should work for most applications, however it is not nec- essarily the optimized solution. to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4 : maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input volt- age conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capaci- tor will usually cost less and occupy less board space. if the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: remove the unit from the environmental chamber and heat the ic with a heat gun. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. stability considerations cs8120 c 1 0.1 f v in gnd reset cs8120 v out enable 500k ? q 1 500k ? 100k ? 100k ? c rst r rst c 2 22 f v cc i/o port p switch v bat reset figure 5: microprocessor control of cs8120 using an external switching transistor (q 1) .
7 the maximum power dissipation for a single output regu- lator (figure 7) is: p d(max) = { v in(max) ? v out(min) } i out(max) + v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the applica- tion, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permis- sible value of r ja can be calculated: r ja = (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja 's less than the calculated value in equation 2 will keep the die temperature below 150c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja = r jc + r cs + r sa (3) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heatsink thermal resistance, and r sa = the heatsink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the inter- face between them. these values appear in heat sink data sheets of heat sink manufacturers. 150c - t a p d calculating power dissipation in a single output linear regulator application notes: continued heat sinks v in smart regulator v out i out i in i q control features } figure 7. single output regulator with key performance parameters labeled. cs8120 reset v out r rst c 2 ** 10 f c rst enable v in c 1 * 0.1 f to p reset port 5v to p and system power cs8120 figure 6. circuit showing output compensation capacitor. *c 1 is required if regulator is far from power source filter. **c 2 is required for stability.
part number description CS8120YT5 5 lead to-220 straight cs8120ytva5 5 lead to-220 vertical cs8120ytha5 5 lead to-220 horizontal cs8120yn8 8 lead pdip cs8120ydp5 5 lead d 2 pak cs8120ydpr5 5 lead d 2 pak (tape & reel) cs8120yd14 14 lead soic narrow cs8120ydr14 14 lead soic narrow (tape & reel) d lead count metric english 8 ordering information rev. 6/22/99 cs8120 package specification package thermal data package dimensions in mm (inches) max min max min 14 lead soic narrow 8.75 8.55 .344 .337 8 lead pdip 10.16 9.02 .400 .355 ? 1999 cherry semiconductor corporation cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information. thermal data 5 lead 5 lead 8 lead 14 lead soic to-220 d 2 pak pdip narrow r jc typ 3.1 3.1 52 30 c/w r ja typ 50 10-50* 100 125 c/w *depending on thermal properties of substrate. r ja = r jc + r ca plastic dip (n); 300 mil wide 0.39 (.015) min. 2.54 (.100) bsc 1.77 (.070) 1.14 (.045) d some 8 and 16 lead packages may have 1/2 lead at the end of the package. all specs are the same. .203 (.008) .356 (.014) ref: jedec ms-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) 5 lead to-220 (t) straight 2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 13.72 (.540) 1.02 (.040) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560) 5 lead d 2 pak (dp) 1.70 (.067) ref 0.10 (.004) 0.00 (.000) 10.31 (.406) 10.05 (.396) 0.91 (.036) 0.66 (.026) 1.40 (.055) 1.14 (.045) 4.57 (.180) 4.31 (.170) 1.68 (.066) 1.40 (.055) 2.74(.108) 2.49(.098) .254 (.010) ref 2.79 (.110) 2.29 (.090) 15.75 (.620) 14.73 (.580) 8.53 (.336) 8.28 (.326) surface mount narrow body (d); 150 mil wide 1.27 (.050) bsc 0.51 (.020) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) d 0.25 (0.10) 0.10 (.004) 1.75 (.069) max 1.27 (.050) 0.40 (.016) ref: jedec ms-012 0.25 (.010) 0.19 (.008)
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