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hm628128b series 1 m sram (128-kword 8-bit) ade-203-243e (z) rev. 5.0 nov. 1997 description the hitachi hm628128b is a cmos static ram organized 131,072-word 8-bit. it realizes higher density, higher performance and low power consumption by employing 0.8 m m hi-cmos shrink process technology. it offers low power standby power dissipation, therefore, it is suitable for battery backup systems. the device, packaged in a 525 mil sop or a 8 mm 20 mm tsop or a 600 mil plastic dip is available. features single 5 v supply: 5.0 v 10% access time: 70/75/85 ns (max) power dissipation ? active: 50 mw/mhz (typ) ? standby: 10 m w (typ) (l/l-sl version) completely static memory ? no clock or timing strobe required equal access and cycle times common data input and output ? three state output directly ttl compatible all inputs and outputs capability of battery backup operation (l/l-sl version) ? 2 chip selection for battery backup
hm628128b series 2 ordering information type no. access time data retention current package hm628128blp-7 hm628128blp-8 70 ns 85 ns 50 m a 50 m a 600-mil 32-pin plastic dip (dp-32) hm628128blp-7sl hm628128blp-8sl 70 ns 85 ns 15 m a 15 m a hm628128blfp-7 hm628128blfp-75 hm628128blfp-8 70 ns 75 ns 85 ns 50 m a 50 m a 50 m a 525-mil 32-pin plastic sop (fp-32d) hm628128blfp-7sl hm628128blfp-75sl hm628128blfp-8sl 70 ns 75 ns 85 ns 15 m a 15 m a 15 m a hm628128blt-7 hm628128blt-75 hm628128blt-8 70 ns 75 ns 85 ns 50 m a 50 m a 50 m a normal-bend type 32-pin plastic 8 mm 20 mm tsop (tfp-32d) HM628128BLT-7SL hm628128blt-75sl hm628128blt-8sl 70 ns 75 ns 85 ns 15 m a 15 m a 15 m a hm628128blr-7 hm628128blr-8 70 ns 85 ns 50 m a 50 m a reverse-bend type 32-pin plastic 8 mm 20 mm tsop (tfp-32dr) hm628128blr-7sl hm628128blr-8sl 70 ns 85 ns 15 m a 15 m a
hm628128b series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc a15 cs2 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 (top view) hm628128bp/bfp series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we cs2 a15 v cc nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 v ss i/o2 i/o1 i/o0 a0 a1 a2 a3 (top view) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a4 a5 a6 a7 a12 a14 a16 nc v cc a15 cs2 we a13 a8 a9 a11 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 cs1 a10 oe hm628128br series (reverse type tsop) hm628128bt series (normal type tsop) (top view) pin description pin name function a0 to a16 address input i/o0 to i/o7 data input/output cs1 chip select 1 cs2 chip select 2 we write enable oe output enable nc no connection v cc power supply v ss ground
hm628128b series 4 block diagram ? ? ? ? ? ? ? ? ? ? ? i/o0 i/o7 cs2 we oe a0 a1 a2 a10 a9 v cc v ss row decoder memory matrix 512 x 2,048 column i/o column decoder input data control timing pulse generator read/write control a11 a16 a8 a13 a4 a5 a6 a7 a12 a14 a15 cs1 a3 msb lsb msb lsb
hm628128b series 5 function table we cs1 cs2 oe mode v cc current i/o pin ref. cycle h standby i sb , i sb1 high-z l standby i sb , i sb1 high-z h l h h output disable i cc high-z h l h l read i cc dout read cycle l l h h write i cc din write cycle (1) l l h l write i cc din write cycle (2) note: : h or l absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc C0.5 to + 7.0 v voltage on any pin relative to v ss v t C0.5* 1 to v cc + 0.3* 2 v power dissipation p t 1.0 w operating temperature range topr 0 to +70 c storage temperature range tstg C55 to +125 c storage temperature under bias tbias C10 to 85 c notes: 1. v t min: C3.0 v for pulse half-width 30 ns 2. maximum voltage is 7.0 v recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il C0.3 * 1 0.8 v note: 1. v il min: C3.0 v for pulse half-width 30 ns
hm628128b series 6 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs1 = v ih or cs2 = v il or oe = v ih or we = v il , v i/o = v ss to v cc operating current i cc 1525ma cs1 = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma average operating current i cc1 35 70 ma min cycle, duty = 100%, cs1 = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma i cc2 10 20 ma cycle time = 1 m s, duty = 100%, i i/o = 0 ma, cs1 0.2 v, cs2 3 v cc C 0.2 v, others = v ih /v il v ih 3 v cc C 0.2 v, v il 0.2 v standby current i sb 1 2 ma cs2 = v il or cs1 = v ih , cs2 = v ih i sb1 2* 2 100* 2 m a 0 v vin v cc (1) 0 v cs2 0.2 v or (2) cs1 3 v cc C 0.2 v, cs2 3 v cc C 0.2 v i sb1 2* 3 50* 3 m a output high voltage v ol 0.4 v i ol = 2.1 ma output low voltage v oh 2.4 v i oh = C1.0 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. 2. this characteristic is guaranteed only for l version. 3. this characteristic is guaranteed only for l-sl version. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 8 pf vin = 0 v input/output capacitance* 1 c i/o 10 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm628128b series 7 ac characteristics (ta = 0 to +70 c, v cc = 5.0 v 10%) test conditions input pulse levels: 0.8 v to 2.4 v input rise and fall time: 5 ns input and output timing reference levels: 1.5 v output load: 1 ttl gate and c l (100 pf) (including scope and jig) read cycle hm628128b -7 -75 -8 parameter symbol min max min max min max unit notes read cycle time t rc 70 75 85 ns address access time t aa 70 75 85 ns chip selection to output valid t co1 70 75 85 ns t co2 70 75 85 ns output enable to output valid t oe 35 35 45 ns chip selection to output in low-z t lz1 10 10 10 ns 2, 3 t lz2 10 10 10 ns output enable to output in low-z t olz 5 5 5 ns 2, 3 chip deselection to output in high-z t hz1 0 25 0 25 0 30 ns 1, 2, 3 t hz2 0 25 0 25 0 30 ns output disable to output in high-z t ohz 0 25 0 25 0 30 ns 1, 2, 3 output hold from address change t oh 10 10 10 ns
hm628128b series 8 write cycle hm628128b -7 -75 -8 parameter symbol min max min max min max unit notes write cycle time t wc 70 75 85 ns chip selection to end of write t cw 60 60 75 ns 5 address setup time t as 000 ns6 address valid to end of write t aw 60 60 75 ns write pulse width t wp 50 50 55 ns 4, 13 write recovery time t wr 000 ns7 write to output in high-z t whz 0 25 0 25 0 30 ns 1, 2, 8 data to write time overlap t dw 30 30 35 ns data hold from write time t dh 000 ns output active from end of write t ow 555 ns2 output disable to output in high-z t ohz 0 25 0 25 0 30 ns 1, 2, 8 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temperature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the overlap of a low cs1 , a high cs2, and a low we . a write begins at the latest transition among cs1 going low, cs2 going high, and we going low. a write ends at the earliest transition among cs1 going high, cs2 going low, and we going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1 going low or cs2 going high to the end of write. 6. t as is measured from the address valid to the beginning of write. 7. t wr is measured from the earliest of cs1 or we going high or cs2 going low to the end of write cycle. 8. during this period, i/o pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. if cs1 goes low simultaneously with we going low or after we going low, the outputs remain in a high impedance state. 10. dout is the same phase of the latest written data in this write cycle. 11. dout is the read data of next address. 12. if cs1 is low and cs2 high during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp 3 t dw min + t whz max
hm628128b series 9 timing waveform read timing waveform ( we = v ih ) t aa t co1 t rc t lz1 t oe t olz t hz2 t ohz valid data address cs1 oe dout t oh cs2 valid address t co2 t lz2 high impedance t hz1
hm628128b series 10 write timing waveform (1) ( oe clock) address cs1 we dout din t wc t cw t wr t wp t ohz t dw t dh *9 valid address t aw cs2 t as high impedance valid data oe
hm628128b series 11 write timing waveform (2) ( oe low fixed) address cs1 we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *12 *10 *11 *9 valid address valid data cs2 high impedance
hm628128b series 12 low v cc data retention characteristics (ta = 0 to +70 c) parameter symbol min typ * 4 max unit test conditions *3 v cc for data retention v dr 2.0 v 0v vin v cc (1) 0 v cs2 0.2 v or (2) cs2 3 v cc C 0.2 v cs1 3 v cc C 0.2 v data retention current i ccdr 1 50 *1 m av cc = 3.0 v, 0v vin v cc (1) 0 v cs2 0.2 v or (2) cs2 3 v cc C 0.2 v, cs1 3 v cc C 0.2 v i ccdr 1 15 *2 m a chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5ms notes: 1. this characteristic is guaranteed only for l version, 20 m a max. at ta = 0 to 40 c. 2. this characteristic is guaranteed only for l-sl version, 3 m a max. at ta = 0 to 40 c. 3. cs2 controls address buffer, we buffer, cs1 buffer, oe buffer, and din buffer. if cs2 controls data retention mode, vin levels (address, we , oe , cs1 , i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be cs2 3 v cc C 0.2 v or 0 v cs2 0.2 v. the other input levels (address, we , oe , i/o) can be in the high impedance state. 4. typical values are at v cc = 3.0 v, ta = +25 c and not guaranteed.
hm628128b series 13 low v cc data retention timing waveform (1) ( cs1 controlled) v cc 4.5 v 2.2 v 0 v cs1 t cdr t r cs1 3 v cc ?0.2 v v dr1 data retention mode low v cc data retention timing waveform (2) (cs2 controlled) v cc 4.5 v 0 v cs2 t r v dr2 data retention mode 0.4 v t cdr 0 v cs2 0.2 v
hm628128b series 14 package dimensions hm628128blp series (dp-32) 0.51 min 2.54 min 5.08 max 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 41.90 42.50 max 13.4 13.7 max 15.24 32 17 1 16 2.30 max 1.20 hitachi code jedec eiaj weight (reference value) dp-32 conforms 5.1 g unit: mm
hm628128b series 15 package dimensions (cont.) hm628128blfp series (fp-32d) 0.15 m 0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max 0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 hitachi code jedec eiaj weight (reference value) fp-32d conforms ? 1.3 g 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04 unit: mm dimension including the plating thickness base material dimension
hm628128b series 16 package dimensions (cont.) hm628128blt series (tfp-32d) 0.10 0.08 m 0.50 8.00 0.22 0.08 20.00 0.20 1.20 max 18.40 0.17 0.05 0 ?5 32 116 17 0.13 0.05 8.20 max 0.45 max 0.50 0.10 0.80 0.20 0.06 0.125 0.04 dimension including the plating thickness base material dimension hitachi code jedec eiaj weight (reference value) tfp-32d conforms conforms 0.39 g unit: mm
hm628128b series 17 package dimensions (cont.) hm628128blr series (tfp-32dr) 0.10 0.08 m 0.50 8.00 0.22 0.08 20.00 0.20 1.20 max 18.40 0.17 0.05 17 16 1 32 0.13 0.05 8.20 max 0 ?5 0.50 0.10 0.45 max 0.80 0.20 0.06 0.125 0.04 dimension including the plating thickness base material dimension hitachi code jedec eiaj weight (reference value) tfp-32dr conforms conforms 0.39 g unit: mm
hm628128b series 18 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm628128b series 19 revision record rev. date contents of modification drawn by approved by 0.0 oct. 5, 1994 initial issue m. higuchi k. yoshizaki 1.0 dec. 20, 1994 dc characteristics i cc max: 15 ma to 25 ma i cc2 typ: 5 ma to 10 ma i cc2 max: 10 ma to 20 ma m. higuchi k. yoshizaki 2.0 mar. 20, 1995 low vcc data retention characteristics addition of note 3: typical values at v cc = 3.0 v, ta = +25 c and not guaranteed m. higuchi k. yoshizaki 3.0 aug. 10, 1996 change of format addition of hm628128b-10/10sl series ac characteristics change order of note. m. higuchi k. yoshizaki 4.0 jul. 1, 1997 addition of hm628128b-75 series dc characteristics v oh test condition: C0.1 ma to C1.0 ma m. higuchi k. imato 5.0 nov. 1997 change of subtitle

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