View W223-02G_6657060.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary sdram buffer -2 dimm w223-02 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07243 rev. ** revised september 17, 2001 2 features ? ten skew controlled cmos outputs (sdram0:9) supports two sdram dimms ideal for high performance systems designed around intel?s latest mobile chip set i 2 c serial configuration interface skew between any two outputs is less than 250 ps 4 to 8 ns propagation delay dc to 133 mhz operation single 3.3v supply voltage low power cmos design packaged in a 28-pin, 0.209 inch ssop (shrink small outline package) key specifications supply voltages:........................................... v dd = 3.3v5% operating temperature: ................................... 0 c to +70 c input threshold: .................................................. 1.5v typical maximum input voltage:.......................................v dd + 0.5v input frequency: ............................................... 0 to 133mhz buf_in to sdram0:9 propagation delay: ..............4 to 8 ns output edge rate:................................................. > 1.5 v/ns output skew:............................................................ 250 ps output duty cycle: .................................. 45/55% worst case output impedance:...............................................15 ? typical output type:................................................ cmos rail-to-rail i 2 c is a trademark of philips corporation. intel is a registered trademark of intel corporation. simplified block diagram pin configuration ssop sdram1 sdram2 sdram3 sdram4 sdram5 sdram6 sdram7 sdram8 sdram9 sdram0 serial port sclock sdata device control buf_in oe vdd sdram0 sdram1 gnd vdd sdram2 sdram3 gnd buf_in vdd sdram8 gnd vdd sdata vdd sdram7 sdram6 gnd vdd sdram5 sdram4 gnd oe vdd sdram9 gnd gnd sclk 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 note: 1. internal pull-up resistor of 250k on sdata, sclk and oe inputs (should not be relied upon for pulling up to v dd ). [1]
w223-02 preliminary document #: 38-07243 rev. ** page 2 of 11 pin definitions pin name pin no. pin type pin description sdram0:9 2, 3, 6, 7, 22, 23, 26, 27, 11, 18 o sdram outputs: provides buffered copy of buf_in. the propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. all outputs are skew controlled to within 250 ps of each other. buf_in 9 i clock input: this clock input has an input threshold voltage of 1.5v (typ). sdata 14 i/o i 2 c data input: data should be presented to this input as described in the i 2 c section of this data sheet. internal 250-k ? pull-up resistor. sclock 15 i i 2 c clock input: the i 2 c data clock should be presented to this input as described in the i 2 c section of this data sheet. internal 250-k ? pull-up resistor. vdd 1, 5, 10, 13, 19, 24, 28 p power connection: power supply for core logic and output buffers, connected to 3.3v supply. gnd 4, 8, 12,16, 17, 21, 25 g ground connection: connect all ground pins to the common system ground plane.
w223-02 preliminary document #: 38-07243 rev. ** page 3 of 11 overview the cypress w223-02 is a low-voltage, ten-output clock buff- er. output buffer impedance is approximately 15 ? which is ideal for driving sdram dimms. functional description output control pins outputs three-stated when oe = 0, and toggle when oe = 1. outputs are in phase with buf_in but are phase delayed by 3 to 7ns. outputs can also be controlled via the i 2 c interface. output drivers the w223-02 output buffers are cmos type which deliver a rail-to-rail (gnd to v dd ) output voltage swing into a nominal capacitive load. thus, output signaling is both ttl and cmos level compatible. nominal output buffer impedance is 15 ? . operation data is written to the w223-02 in eleven bytes of eight bits each. bytes are written in the order shown in table 1 . table 1. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the w223-02 to accept the bits in data bytes 0 ? 7 for inter- nal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the w223-02 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code ? don ? t care ? unused by the w223-02, therefore bit values are ignored ( ? don ? t care). this byte must be included in the data write sequence to maintain prop- er byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writing to anoth- er addressed slave receiver on the serial data bus. 3 byte count ? don ? t care ? unused by the w223-02, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to main- tain proper byte allocation. the byte count byte is part of the standard serial communication protocol and may be used when writing to anoth- er addressed slave receiver on the serial data bus. 4 data byte 0 ? don ? t care ? refer to cypress clock drivers. 5 data byte 1 6 data byte 2 7 data byte 3 8 data byte 4 9 data byte 5 refer to table 2 the data bits in these bytes set internal w223-02 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 2 , data byte serial configuration map. 10 data byte 6 11 data byte 7
w223-02 preliminary document #: 38-07243 rev. ** page 4 of 11 writing data bytes each bit in the data bytes control a particular device function. bits are written msb (most significant bit) first, which is bit 7. table 2 gives the bit formats for registers located in data bytes 5 ? 7. note: 2. at power up all sdram outputs are enabled and active. it is recommended to program bits 4 ? 7 of byte 5 and bits 0 ? 3 of byte 6 to a ? 0 ? to save power and reduce noise. table 2. data bytes 5 ? 7 serial configuration map [2] bit(s) affected pin control function bit control pin no. pin name 0 1 data byte 5 sdram active/inactive register (1 = enable, 0 = disable) 7 n/a reserved (reserved) -- -- 6 n/a reserved (reserved) -- -- 5 n/a reserved (reserved) -- -- 4 n/a reserved (reserved) -- -- 3 7 sdram3 clock output disable low active 2 6 sdram2 clock output disable low active 1 3 sdram1 clock output disable low active 0 2 sdram0 clock output disable low active data byte 6 sdram active/inactive register (1 = enable, 0 = disable) 7 27 sdram7 clock output disable low active 6 26 sdram6 clock output disable low active 5 23 sdram5 clock output disable low active 4 22 sdram4 clock output disable low active 3 n/a reserved (reserved) -- -- 2 n/a reserved (reserved) -- -- 1 n/a reserved (reserved) -- -- 0 n/a reserved (reserved) -- -- data byte 7 sdram active/inactive register (1 = enable, 0 = disable) 7 18 sdram9 clock output disable low active 6 11 sdram8 clock output disable low active 5 n/a reserved (reserved) -- -- 4 n/a reserved (reserved) -- -- 3 n/a reserved (reserved) -- -- 2 n/a reserved (reserved) -- -- 1 n/a reserved (reserved) -- -- 0 n/a reserved (reserved) -- --
w223-02 preliminary document #: 38-07243 rev. ** page 5 of 11 how to use the serial data interface electrical requirements figure 1 illustrates electrical characteristics for the serial inter- face bus used with the w223-02. devices send data over the bus with an open drain logic output that can (a) pull the bus line low, or (b) let the bus default to logic 1. the pull-up resistor on the bus (both clock and data lines) establish a default logic 1. all bus devices generally have logic inputs to receive data. although the w223-02 is a receive-only device (no data write-back capability), it does transmit an ? acknowledge ? data pulse after each byte is received. thus, the sdata line can both transmit and receive data. the pull-up resistor should be sized to meet the rise and fall times specified in ac parameters, taking into consideration total bus line capacitance. data in data out n clock in clock out chip set (serial bus master transmitter) sdclk sdata serial bus clock line serial bus data line n data in data out clock in clock device (serial bus slave receiver) sclock sdata n ~ 2k ? ~ 2k ? vdd vdd figure 1. serial interface bus electrical characteristics
w223-02 preliminary document #: 38-07243 rev. ** page 6 of 11 signaling requirements as shown in figure 2 valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock high (logic 1) pulse. a transitioning data line during a clock high pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). a write sequence is initiated by a ? start bit ? as shown in figure 3 . a ? stop bit ? signifies that a transmission has ended. as stated previously, the w223-02 sends an ? acknowledge ? pulse after receiving eight data bits in each byte as shown in figure 4 . sending data to the w223-02 the device accepts data once it has detected a valid start bit and address byte sequence. device functionality is changed upon the receipt of each data bit (registers are not double buff- ered). partial transmission is allowed meaning that a transmis- sion can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). trans- mission is truncated with either a stop bit or new start bit (re- start condition). t sdata sclock valid data bit change of data allowed figure 2. serial data bus valid data bit sdata sclock start bit stop bit figure 3. serial data bus start and stop bit
preliminary w223-02 document #: 38-07243 rev. ** page 7 of 11 t sthd t low t r t high t f t dsu t dhd t sp t spsu t sthd t spsu t spf sdata sclock figure 4.4 serial data bus write sequence msb 12345678a12345678a 1234 sclock 12345678a 11 01 001 0 lsb msb msb lsb sdata sdata signaling from system core logic start condition msb lsb slave address (first byte) command code (second byte) last data byte (last byte) byte count (third byte) stop condition signaling by clock device acknowledgment bit from clock device figure 5.5 serial data bus timing diagram
w223-02 preliminary document #: 38-07243 rev. ** page 8 of 11 absolute maximum ratings stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. note: 1. oe, sdata, and sclock logic pins have a 250-k ? internal pull-up resistor (v dd ? 0.8v). parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c dc electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v5% parameter description test condition/ notes min. typ. max. unit i dd 3.3v supply current 66 mhz [1] 120 160 ma i dd 3.3v supply current 100 mhz [1] 185 220 ma i dd tristate 3.3v supply current in three-state 5 10 ma logic inputs v il input low voltage v ss ? 0.3 0.8 v v ih input high voltage 2.0 v dd +0.5 v i ileak input leakage current, buf_in ? 5+5a i ileak input leakage current ? 20 +5 a logic outputs (sdram0:9) v ol output low voltage i ol = 1ma 50 mv v oh output high voltage i oh = ? 1ma 3.1 v i ol output low current v ol = 1.5v 70 110 185 ma i oh output high current v oh = 1.5v 65 100 160 ma pin capacitance/inductance c in input pin capacitance (except buf_in) 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh
w223-02 preliminary document #: 38-07243 rev. ** page 9 of 11 ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v5% (lump capacitance test load = 30 pf) parameter description test condition min. typ. max. unit f in input frequency 0 133 mhz t r output rise edge rate measured from 0.4v to 2.4v 1.5 4.0 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1.5 4.0 v/ns t sr output skew, rising edges 250 ps t sf output skew, falling edges 250 ps t en output enable time 1.0 8.0 ns t dis output disable time 1.0 8.0 ns t pr rising edge propagation delay 6 ns t pf falling edge propagation delay 6 ns t d duty cycle measured at 1.5v 45 55 % z o ac output impedance 15 ? ordering information ordering code package name package type w223-02 g 28-pin plastic ssop (209-mil)
w223-02 preliminary document #: 38-07243 rev. ** page 10 of 11 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 28-pin shrink small outline package (ssop, 209-mil)
w223-02 preliminary document #: 38-07243 rev. ** page 11 of 11 document title: w223-03 sdram buffer-2 dimm document number: 38-07243 rev. ecn no. issue date orig. of change description of change ** 110508 10/31/01 szv change from spec number: 38-00980 to 38-07243

▲Up To Search▲

Price & Availability of W223-02G

	To Download W223-02G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .