28 cal crystal lab, inc. / comclok, inc. 800-333-9825 1156 north gilbert street ? anaheim, ca 92801 tri-state enable/disable oscillators / hcmos / ttl (full & half size) model ct 5.0vdc test circuit full size test circuit half size note: 1. c l capacitance includes probe and test jig 20pf typical (10khz ~ 69.999mhz) c l capacitance includes probe and test jig 15pf typical (70mhz ~ 160.000mhz) 2. r l = 400 w - 10ttl 2k w - 10lsttl 3. all diodes are 1n941, 1n43064 or equivalent full size tri-state pins connections 1 enable / disable 7 gnd 8 output 14 +5 vdc 10% half size tri-state pins connections 1 enable / disable 4 gnd 5 output 8 +5 vdc 10% model model model model model frequency range storage temperature range operating temperature range supply voltage symmetry 10khz ~ 69.999mhz 0 o c ~+70 o c extended temperature ranges available -55 o c ~+125 o c +5 vdc 10% 60/40 @ 50% vcc, optional tolerances available ct ct ct ct ct frequency stability rise & fall time (tr & tf) 6 nsec max 100ppm standard, optional tolerances available current consumption 10.0khz ~ 23.999mhz: 15ma max 24.000mhz ~ 69.999mhz: 30ma max logic 1 logic 0 output load (max) 10ttl / 20pf 0.5 vdc max 4.5 vdc min 70mhz ~ 160.0mhz 100ppm standard, optional tolerances available 0 o c ~+70 o c extended temperature ranges available -55 o c ~+125 o c 70.0mhz ~ 99.9mhz: 30ma max 100.00mhz ~ 129.9mhz: 35ma max 130.00mhz ~ 160.00mhz: 40ma max +5 vdc 10% 60/40 @ 50% vcc, optional tolerances available 3 nsec max 4.5 vdc min 0.5 vdc max 2ttl / 15pf aging < 5ppm per year < 5ppm per year ct ct ct ct ct enable - logic 1 2.0 vdc min disable - logic 0 0.5 vdc max enable input enable - logic 1 2.0 vdc min disable - logic 0 0.5 vdc max
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