1 tm caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. pspice?is a registered trademark of microsim corporation. ultrafet?is a registered trademark of intersil corporation. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 HUFA75229P3 44a, 50v, 0.022 ohm, n-channel ultrafet power mosfet this n-channel power mosfet is manufactured using the innovative ultrafet process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?iency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. features 44a, 50v low on-resistance, r ds(on) = 0.022 ? temperature compensating pspice?model thermal impedance spice model peak current vs pulse width curve uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-220ab this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a copy of the requirements, see aec q101 at: http://www.aecouncil.com/ reliability data can be found at: http://www.mtp.intersil.com/automotive.html. all intersil semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certificati on. ordering information part number package brand HUFA75229P3 to-220ab 75229p note: when ordering use the entire part number. d g s drain source gate drain (flange) data sheet november 2000 file number 4937
2 absolute maximum ratings t c = 25 o c, unless otherwise specified units drain to source voltage (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 50 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 50 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 44 figure 5 a pulsed avalanche rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e as figure 6, 14, 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 0.6 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 50 - - v gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 2 - 4 v zero gate voltage drain current i dss v ds = 45v, v gs = 0v - - 1 a v ds = 40v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance r ds(on) i d = 44a, v gs = 10v (figure 9) 0.017 0.020 0.022 ? turn-on time t on v dd = 30v, i d ? 44a, r l = 0.68 ? , v gs = 10v, r gs = 9.1 ? (figures 18, 19) - - 105 ns turn-on delay time t d(on) -12-ns rise time t r -58-ns turn-off delay time t d(off) -33-ns fall time t f -33-ns turn-off time t off - - 100 ns total gate charge q g(tot) v gs = 0v to 20v v dd = 30v, i d ? 44a, r l = 0.68 ? i g(ref) = 1.0ma (figures 13, 16, 17) -6075nc gate charge at 10v q g(10) v gs = 0v to 10v - 35 43 nc threshold gate charge q g(th) v gs = 0v to 2v - 2.0 2.5 nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 1060 - pf output capacitance c oss - 405 - pf reverse transfer capacitance c rss -95-pf thermal resistance junction to case r jc (figure 3) - - 1.66 o c/w thermal resistance junction to ambient r ja to-220 - - 62 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 44a - - 1.25 v reverse recovery time t rr i sd = 44a, di sd /dt = 100a/ s--72ns reverse recovered charge q rr i sd = 44a, di sd /dt = 100a/ s - - 120 nc HUFA75229P3
3 typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 i d , drain current (a) t c , case temperature ( o c) 0 10 20 30 40 50 25 50 75 100 125 150 175 0.01 0.1 1 2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 z jc , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t, rectangular pulse duration (s) 1 10 100 200 1 10 100 200 v ds , drain to source voltage (v) i d , drain current (a) 100 s 10ms 1ms limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c bv dss max = 50v 40 100 400 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t, pulse width (s) i dm , peak current (a) v gs = 10v transconductance may limit current in this region i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: t c = 25 o c HUFA75229P3
4 note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature typical performance curves (continued) 10 100 300 0.001 0.01 0.1 1 10 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 0 20 40 60 0 12345 80 i d , drain current (a) v ds , drain to source voltage (v) v gs = 6v v gs = 10v v gs = 20v pulse duration = 250 s t c = 25 o c v gs = 5v v gs = 8v 100 v gs = 7v 0 3.0 4.5 6.0 7.5 1.5 i d , drain current (a) v gs , gate to source voltage (v) 175 o c -55 o c 25 o c pulse test pulse duration = 250 s duty cycle = 0.5% max v dd = 15v 0 20 40 60 80 100 0.5 1.0 1.5 2.0 2.5 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 250 s, v gs = 10v, i d = 44a 200 -80 -40 0 40 80 120 160 0.4 0.6 0.8 1.0 1.2 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 200 1.2 1.1 1.0 0.9 0.8 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 200 HUFA75229P3
5 figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current typical performance curves (continued) 1500 600 0 01020304050 c, capacitance (pf) 900 v ds , drain to source voltage (v) 300 c iss c oss c rss v gs = 0v, f = 1mhz 1200 10 8 6 4 0 v gs , gate to source voltage (v) v dd = 30v 2 15 20 35 0 q g , gate charge (nc) 510 i d = 44a i d = 27a i d = 11a waveforms in descending order: 25 30 HUFA75229P3
6 test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform figure 18. switching time test circuit figure 19. resistive switching waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 HUFA75229P3
7 pspice electrical model subckt HUFA75229P3 2 1 3 ; rev 6/19/97 ca 12 8 1.72e-9 cb 15 14 1.52e-9 cin 6 8 9.61e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 58.13 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 2.86e-9 lsource 3 7 2.69e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 1e-3 rgate 9 20 1.52 rldrain 2 5 10 rlgate 1 9 26.9 rlsource 3 7 28.6 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 13.85e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*135),3.5))} .model dbodymod d (is = 7.50e-13 rs = 5.05e-3 trs1 = 2.21e-3 trs2 = 1.02e-6 cjo = 1.51e-9 tt = 4.05e-8 m = 0.5) .model dbreakmod d (rs = 2.14e-1 trs1 = 9.62e-4 trs2 = 1.23e-6) .model dplcapmod d (cjo = 13.5e-10 is = 1e-30 n = 10 m = 0.85) .model mmedmod nmos (vto = 3.25 kp = 2.50 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.52) .model mstromod nmos (vto = 3.80 kp = 70.0 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.91 kp = 0.06 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 15.2 rs = 0.1) .model rbreakmod res (tc1 = 1.05e-3 tc2 = 1.94e-7) .model rdrainmod res (tc1 = 8.04e-2 tc2 = 1.37e-4) .model rslcmod res (tc1 = 4.83e-3 tc2 = 1.16e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc = -3.43e-3 tc2 = -1.63e-5) .model rvtempmod res (tc1 = -1.35e-3 tc2 = 1.16e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -7.90 voff= -4.90) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -4.90 voff= -7.90) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.50 voff= 2.50) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 2.50 voff= -0.50) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 HUFA75229P3
8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com spice thermal model rev 16 june 97 HUFA75229P3 ctherm1 7 6 4.90e-7 ctherm2 6 5 4.90e-4 ctherm3 5 4 1.96e-3 ctherm4 4 3 7.90e-3 ctherm5 3 2 1.85e-1 ctherm6 2 1 2.70 rtherm1 7 6 1.10e-2 rtherm2 6 5 3.30e-2 rtherm3 5 4 1.64e-1 rtherm4 4 3 7.90e-1 rtherm5 3 2 3.60e-1 rtherm6 2 1 1.60e-1 rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 1 2 3 4 5 6 7 junction case HUFA75229P3
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