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differential-to-0.7v differential pci express? jitter attenuator ics871002i-02 idt ? / ics ? 0.7v differential jitter attunuator 1 ics871002agi-02 rev. a september 14, 2007 preliminary g eneral d escription the ics871002i-02 is a high performance jitter attenuator designed for use in pci express? systems. in some pci express systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the pll synthesizer and from the system board. the ics871002i-02 has two pll bandwidth modes: 350khz and 2000khz. the 350khz mode will provide maximum jitter attenuation, but with higher pll tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. the 2000khz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. the ics871002i-02 can be set for different modes using the f_selx pins as shown in table 3c. the ics871002i-02 uses idt 3 rd generation femtoclock tm pll technology to achieve the lowest possible phase noise. the device is packaged in a small 20 lead tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. features ? two 0.7v differential output pairs ? one differential clock input ? clk and nclk supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency range: 98mhz - 640mhz ? input frequency range: 98mhz - 128mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter: 20ps (typical) ? 3.3v operating supply ? two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram bw_sel 0 = pll bandwidth: ~350khz (default) 1 = pll bandwidth: ~2000khz pll b andwidth 5 (fixed) vco 98 - 640 mhz phase detector output divider 00 5 01 4 10 2 (default) 11 1 q0 nq0 q1 nq1 fb_out nfb_out bw_sel clk nclk fb_in nfb_in f_sel[1:0] mr oe pulldown pullup:pulldown pulldown pullup pullup pulldown pullup pulldown 2 - + iref 0 = 350khz 1 = 2000khz p in a ssignment ics871002i-02 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view nq0 iref fb_out nfb_out mr bw_sel f_sel1 v dda f_sel0 v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q0 v dd q1 nq1 nfb_in fb_in gnd nclk clk oe the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? 0.7v differential jitter attunuator 2 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 3a. o utput e nable f unction t able t able 3b. pll b andwidth c ontrol t able t u p n i h t d i w d n a b l l p l e s _ w b 0) t l u a f e d ( z h k 0 5 3 1z h k 0 0 0 2 t able 3c. f_sel x f unction t able y c n e u q e r f t u p n i ) z h m ( s t u p n i y c n e u q e r f t u p t u o ) z h m ( 1 l e s _ f0 l e s _ fr e d i v i d 0 0 1005 0 0 1 0 0 1014 5 2 1 0 0 1102 ) t l u a f e d ( 0 5 2 0 0 1111 0 0 5 t u p n is t u p t u o e o] 0 : 1 [ q n / ] 0 : 1 [ qt u o _ b f n / t u o _ b f 0z i hd e l b a n e 1d e l b a n ed e l b a n e r e b m u ne m a ne p y tn o i t p i r c s e d 0 2 , 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d 2f e r it u p n i 5 7 4 ( r o t s i s e r n o i s i c e r p d e x i f a a s e d i v o r p d n u o r g o t n i p s i h t m o r f ) . s t u p t u o k c o l c x q n / x q e d o m - t n e r r u c l a i t n e r e f f i d r o f d e s u t n e r r u c e c n e r e f e r , 3 4 , t u o _ b f t u o _ b f n t u p t u o . s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o k c a b d e e f l a i t n e r e f f i d 5r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a d e t r e v n i e h t d n a w o l o g o t ) t u o _ b f , x q ( s t u p t u o e u r t e h t g n i s u a c t e s e r s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t ) t u o _ b f n , x q n ( s t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o e h t d n a 6l e s _ w bt u p n in w o d l l u p . z h k 0 0 0 2 = 1 , z h k 0 5 3 = 0 . t u p n i t c e l e s h t d i w d n a b l l p . b 3 e l b a t e e s , 7 9 , 1 l e s _ f 0 l e s _ f t u p n i , p u l l u p n w o d l l u p . c 3 e l b a t e e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f 8v a d d r e w o p. n i p y l p p u s g o l a n a 9 1 , 0 1v d d r e w o p. n i p y l p p u s e r o c 1 1e ot u p n ip u l l u p e h t , w o l n e h w . e v i t c a e r a s t u p t u o e h t , h g i h n e h w . n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s e c n a d e p m i h g i h a n i e r a s t u p t u o . a 3 e l b a t e e s 2 1k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 3 1k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 4 1d n gr e w o p. d n u o r g y l p p u s r e w o p 5 1n i _ b ft u p n in w o d l l u p. t u p n i k c a b d e e f l a i t n e r e f f i d g n i t r e v n i - n o n 6 1n i _ b f nt u p n ip u l l u p. t u p n i k c a b d e e f l a i t n e r e f f i d g n i t r e v n i 8 1 , 7 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l s c h . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? 0.7v differential jitter attunuator 3 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 86.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 7 9 . 23 . 33 6 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 3 1 . 0 ?3 . 3v d d v i d d t n e r r u c y l p p u s r e w o p 5 7a m i a d d t n e r r u c y l p p u s g o l a n a 3 1a m t able 4b. lvcmos/lvttl dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n iv d d v 3 6 . 3 =2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n iv d d v 3 6 . 3 =3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h e o , 1 l e s _ fv d d v = n i v 3 6 . 3 =5a l e s _ w b , r m , 0 l e s _ fv d d v = n i 3 6 . 3 =0 5 1a i l i t u p n i t n e r r u c w o l e o , 1 l e s _ fv d d v , v 3 6 . 3 = n i v 0 =0 5 1 -a l e s _ w b , r m , 0 l e s _ fv d d v , v 3 6 . 3 = n i v 0 =5 -a t able 4c. d ifferential dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i , k l c n i _ b f v d d v = n i v 3 6 . 3 =0 5 1a , k l c n n i _ b f n v d d v = n i v 3 6 . 3 =5 a i l i t n e r r u c w o l t u p n i , k l c n i _ b f v d d v = n i v 3 6 =0 5 1a , k l c n n i _ b f n v d d v = n i v 3 6 . 3 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 +
idt ? / ics ? 0.7v differential jitter attunuator 4 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary t able 5. ac c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 8 90 4 6z h m t ) c c ( t i j1 e t o n ; r e t t i j e l c y c - o t - e l c y ce d o m l l p0 2s p v h g i h h g i h e g a t l o v 0 6 60 5 8v m v w o l w o l e g a t l o v 0 5 1 -v m v s v o t o o h s r e v o , e g a t l o v . x a m v h g i h 3 . 0 +v v s d u t o o h s r e d n u , e g a t l o v . n i m 3 . 0 -v v b r e g a t l o v k c a b g n i r 2 . 0v v s s o r c e g a t l o v g n i s s o r c e t u l o s b a 0 5 20 5 5v m v s s o r c v f o n o i t a i r a v l a t o t s s o r c s e g d e l l a r e v o 0 4 1v m t r t / f e m i t l l a f / e s i r t u p t u o n e e w t e b d e r u s a e m v 5 2 5 . 0 o t v 5 7 1 . 0 5 7 10 0 7s p t r / t f n o i t a i r a v e m i t l l a f / e s i r 5 2 1s p t m f r g n i h c t a m l l a f / e s i r 5 2 1s p c d oe l c y c y t u d t u p t u o 5 45 5% . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 1 e t o n
idt ? / ics ? 0.7v differential jitter attunuator 5 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod d ifferential i nput l evel 3.3v hcsl o utput l oad ac t est c ircuit c ycle - to -c ycle j itter v cmr cross points v pp gnd clk, fb_in nclk, nfb_in v dd clock outputs 0.175v 0.525v 0.525v 0.175v t r t f v swing nq0, nq1, nfb_out ? ? ? ? t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles o utput r ise /f all t ime q0, q1, fb_out nq0, nq1, nfb_out 475 measurement point 33 100 100 33 measurement point 49.9 49.9 hcsl gnd 2pf 2pf t pw t period t pw t period odc = x 100% q0, q1, fb_out v dd v dda
idt ? / ics ? 0.7v differential jitter attunuator 6 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics871002i-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a 0.01 f bypass capacitor should be connected to each v dda pin. f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd i nputs : lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : d ifferential o utputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? 0.7v differential jitter attunuator 7 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. f igure 3c. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/nclk i nput d riven by a 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v f igure 3a. h i p er c lock s clk/nclk i nput d riven by an idt o pen e mitter h i p er c lock s lvhstl d river 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/nclk i nput d riven by a 3.3v hcsl d river zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 zo = 50 hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 f igure 3f. h i p er c lock s clk/nclk i nput d riven by a 2.5v sstl d river clk nclk hiperclocks sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
idt ? / ics ? 0.7v differential jitter attunuator 8 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary r ecommended t ermination figure 4a is the recommended termination for applications which require the receiver and driver to be on a separate pcb. all traces should be 50 impedance. f igure 4a. r ecommended t ermination figure 4b is the recommended termination for applications which require a point to point connection and contain the driver f igure 4b. r ecommended t ermination and receiver on the same pcb. all traces should all be 50 impedance.
idt ? / ics ? 0.7v differential jitter attunuator 9 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics871002i-02. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics871002i-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.63v * (75ma + 15ma) = 326.7mw ? power (outputs) max = 47.75mw/loaded output pair if all outputs are loaded, the total power is 2 * 47.75mw = 95.5mw total power _max (3.63v, with all outputs switching) = 326.7mw + 95.5mw = 422.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 86.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.422w * 86.7c/w = 121c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 20-p in tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 86.7c/w 82.4c/w 80.2c/w
idt ? / ics ? 0.7v differential jitter attunuator 10 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v dd ? 2v. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_max /r l ) * (v dd_max ? v oh_max ) pd_l = (v ol_min /r l ) * v ol_min pd_h = (0.85v /50 ) * (3.63v ? 0.85v) = 47.3mw pd_l = (0.15v/50 ) * 0.15v = 0.45mw total power dissipation per output pair = pd_h + pd_l = 47.75mw f igure 5. hcsl d river c ircuit and t ermination ic vout rl 50 vddo
idt ? / ics ? 0.7v differential jitter attunuator 11 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary r eliability i nformation t ransistor c ount the transistor count for ics871002i-02 is: 1704 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 86.7c/w 82.4c/w 80.2c/w
idt ? / ics ? 0.7v differential jitter attunuator 12 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions l o b m y s s r e t e m i l l i m n i mx a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 reference document: jedec publication 95, mo-153
idt ? / ics ? 0.7v differential jitter attunuator 13 ics871002agi-02 rev. a september 14, 2007 ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 2 0 - i g a 2 0 0 1 7 8 s c i2 0 - i 1 0 0 1 7 s c ip o s s t d a e l 0 2e b u tc 5 8 o t c 0 4 - t 2 0 - i g a 2 0 0 1 7 8 s c i2 0 - i 1 0 0 1 7 s c ip o s s t d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 2 0 - i g a 2 0 0 1 7 8 s c id b tp o s s t " e e r f - d a e l " d a e l 0 2y a r tc 5 8 o t c 0 4 - t f l 2 0 - i g a 2 0 0 1 7 8 s c id b tp o s s t " e e r f - d a e l " d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics871002i-02 differential-to-0.7v differential pci express? jitter attenuato r preliminary

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