k6r1008c1d cmos sram preliminary - 1 - preliminary preliminary rev. 3.0 july 2004 document title 128kx8 bit high-speed cmos static ram(5v operating). operated at commercial and industrial temperature ranges. revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. rev. no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 1.0 rev. 2.0 rev. 3.0 remark preliminary preliminary preliminary final final final history initial release with preliminary. current modify 1. delete 15ns speed bin. 2. change icc for industrial mode. 1. final datasheet release. 2. delete ub ,lb releated ac characteristics and timing diagram. 1. delete 12ns speed bin. 1. add the lead free package type. item previous current i cc(industrial) 10ns 85ma 75ma 12ns 75ma 65ma draft data june. 8. 2001 september. 9. 2001 december.18 june. 19. 2002 july. 8. 2002 july. 26, 2004
k6r1008c1d cmos sram preliminary - 2 - preliminary preliminary rev. 3.0 july 2004 1mb async. fast sram ordering information org. part number vdd(v) speed ( ns ) pkg temp. & power 256k x4 k6r1004c1d-j(k)c(i) 10 5 10 j : 32-soj k: 32-soj(lf) c : commercial temperature ,normal power range i : industrial temperature ,normal power range k6r1004v1d-j(k)c(i) 08/10 3.3 8/10 128k x8 k6r1008c1d-j(k,t,u)c(i) 10 5 10 j : 32-soj k : 32-soj(lf) t : 32-tsop2 u : 32-tsop2(lf) k6r1008v1d-j(k,t,u)c(i) 08/10 3.3 8/10 64k x16 k6r1016c1d-j(k,t,u,e)c(i) 10 5 10 j : 44-soj k : 44-soj(lf) t : 44-tsop2 u : 44-tsop2(lf) e : 48-tbga k6r1016v1d-j(k,t,u,e)c(i) 08/10 3.3 8/10
k6r1008c1d cmos sram preliminary - 3 - preliminary preliminary rev. 3.0 july 2004 128k x 8 bit high-speed cmos static ram(5.0v operating) general description features fast access time 10(max.) power dissipation standby (ttl) : 20ma(max.) (cmos) : 5ma(max.) operating k6r1008c1d-10: 65ma(max.) single 5.0v10% power supply ttl compatible inputs and outputs i/o compatible with 3.3v device fully static operation - no clock or refresh required three state outputs center power/ground pin configuration standard pin configuration k6r1008c1d-j : 32-soj-400 k6r1008c1d-k : 32-soj-400 (lead-free) k6r1008c1d-t : 32-tsop2-400cf k6r1008c1d-u : 32-tsop2-400cf (lead-free) operating in commercial and industrial temperature range. clk gen. i/o 1 ~i/o 8 cs we oe functional block diagram row select data cont. column select clk gen. pre-charge circuit memory array 512 rows 256x8 columns i/o circuit pin function pin name pin function a 0 - a 16 address inputs we write enable cs chip select oe output enable i/o 1 ~ i/o 8 data inputs/outputs v cc power(+5.0v) v ss ground n.c no connection the k6r1008c1d is a 1,048,576-bit high-speed static random access memory organized as 131,072 words by 8 bits. the k6r1008c1d uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. the device is fabricated using sam- sung s advanced cmos process and designed for high- speed circuit technology. it is particularly well suited for use in high-density high-speed system applications. the k6r1008c1d is packaged in a 400mil 32-pin plastic soj or tsop2 forward. pin configuration (top view) soj/ tsop2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 16 a 15 a 14 a 13 oe i/o 8 i/o 7 vss vcc i/o 6 i/o 5 a 12 a 11 a 10 a 9 a 8 a 0 a 1 a 2 a 3 cs i/o 1 i/o 2 vcc vss i/o 3 i/o 4 we a 4 a 5 a 6 a 7 a 10 a 11 a 12 a 13 a 14 a 15 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 9 a 16 a 8
k6r1008c1d cmos sram preliminary - 4 - preliminary preliminary rev. 3.0 july 2004 absolute maximum ratings* * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to vcc+0.5v v voltage on v cc supply relative to v ss v cc -0.5 to 7.0 v power dissipation p d 1w storage temperature t stg -65 to 150 c operating temperature commercial t a 0 to 70 c industrial t a -40 to 85 c recommended dc operating conditions* (t a =0 to 70 c) * the above parameters are also guaranteed at industrial temperature range. ** v il (min) = -2.0v a.c(pulse width 8ns) for i 20ma. *** v ih (max) = v cc + 2.0v a.c (pulse width 8ns) for i 20ma. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 000v input high voltage v ih 2.2 - v cc + 0.5*** v input low voltage v il -0.5** - 0.8 v capacitance * (t a =25 c, f=1.0mhz) * capacitance is sampled and not 100% tested. item symbol test conditions typ max unit input/output capacitance c i/o v i/o =0v - 8 pf input capacitance c in v in =0v -6pf dc and operating characteristics* (t a =0 to 70 c, vcc=5.0v 10%, unless otherwise specified) * the above parameters are also guaranteed at industrial temperature range. parameter symbol test conditions min max unit input leakage current i li v in =v ss to v cc -2 2 a output leakage current i lo cs =v ih or oe =v ih or we =v il v out =v ss to v cc -2 2 a operating current i cc min. cycle, 100% duty cs =v il, v in =v ih or v il, i out =0ma com. 10ns - 65 ma ind. 10ns - 75 standby current i sb min. cycle, cs =v ih -20 ma i sb1 f=0mhz, cs v cc -0.2v, v in v cc -0.2v or v in 0.2v -5 output low voltage level v ol i ol =8ma - 0.4 v output high voltage level v oh i oh =-4ma 2.4 - v
k6r1008c1d cmos sram preliminary - 5 - preliminary preliminary rev. 3.0 july 2004 test conditions* * the a bove test conditions are also applied at industrial temperature range. parameter value input pulse levels 0v to 3v input rise and fall times 3ns input and output timing reference levels 1.5v output loads see below ac characteristics (t a =0 to 70 c, v cc =5.0v 10%, unless otherwise noted.) output loads(b) d out 5pf* 480 ? 255 ? for t hz , t lz , t whz , t ow , t olz & t ohz +5.0v * including scope and jig capacitance output loads(a) d out r l = 50 ? z o = 50 ? v l = 1.5v 30pf* * capacitive load consists of all components of the test environment. read cycle* * the above parameters are also guaranteed at industrial temperature range. parameter symbol k6r1008c1d-10 unit min max read cycle time t rc 10 - ns address access time t aa -10ns chip select to output t co -10ns output enable to valid output t oe -5ns chip enable to low-z output t lz 3-ns output enable to low-z output t olz 0-ns chip disable to high-z output t hz 05 ns output disable to high-z output t ohz 05 ns output hold from address change t oh 3- ns chip selection to power up time t pu 0-ns chip selection to power downtime t pd -10ns
k6r1008c1d cmos sram preliminary - 6 - preliminary preliminary rev. 3.0 july 2004 address data out previous valid data valid data timing diagrams timing waveform of read cycle(1) (address controlled , cs =oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) (we =v ih ) write cycle* * the above parameters are also guaranteed at industrial temperature range. parameter symbol k6r1008c1d-10 unit min max write cycle time t wc 10 - ns chip select to end of write t cw 7-ns address set-up time t as 0- ns address valid to end of write t aw 7- ns write pulse width(oe high) t wp 7- ns write pulse width(oe low) t wp1 10 - ns write recovery time t wr 0- ns write to output high-z t whz 05 ns data to write time overlap t dw 5- ns data hold from write time t dh 0- ns end of write to output low-z t ow 3-ns valid data high-z t rc cs address oe data out t hz(3,4,5) t aa t co t oe t olz t lz(4,5) t ohz t pu t pd 50% 50% v cc current i cc i sb t dh
k6r1008c1d cmos sram preliminary - 7 - preliminary preliminary rev. 3.0 july 2004 notes (read cycle) 1. we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs =v il. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. timing waveform of write cycle(1) (oe = clock) address cs t wp(2) t dw t dh valid data we data in data out t wc t wr(5) t aw t cw(3) high-z(8) high-z oe t ohz(6) t as(4) timing waveform of write cycle(2) (oe =low fixed) address cs t wp1(2) t dw t dh t ow t whz(6) valid data we data in data out t wc t as(4) t wr(5) t aw t cw(3) (10) (9) high-z(8) high-z
k6r1008c1d cmos sram preliminary - 8 - preliminary preliminary rev. 3.0 july 2004 notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low cs and we . a write begins at the latest transition cs going low and we going low ; a write ends at the earliest transition cs going high or we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cyc le. 8. if cs goes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when cs is low : i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied. timing waveform of write cycle(3) (cs = controlled) address cs t aw t dw t dh data valid we data in data out high-z high-z(8) t cw(3) t wp(2) t as(4) t wc t wr(5) high-z high-z t lz t whz(6) functional description * x means don t care. cs we oe mode i/o pin supply current h x x* not select high-z i sb , i sb1 l h h output disable high-z i cc l h l read d out i cc llx write d in i cc
k6r1008c1d cmos sram preliminary - 9 - preliminary preliminary rev. 3.0 july 2004 #1 32-soj-400 #32 20.95 0.12 0.825 0.005 10.16 0.400 +0.10 max 21.36 0.841 0.20 -0.05 +0.004 0.008 -0.002 9.40 0.25 0.370 0.010 max 0.148 3.76 min 0.69 0.027 1.30 ( ) 0.051 1.30 ( ) 0.051 0.95 ( ) 0.0375 +0.10 0.43 -0.05 +0.004 0.017 -0.002 +0.10 0.71 -0.05 +0.004 0.028 -0.002 1.27 0.050 #16 #17 0.004 0.10 max 11.18 0.12 0.440 0.005 package dimensions units:millimeters/inches 32-tsop2-400cf #32 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max #1 0.95 ( ) 0.037 10.16 0.400 +0.10 0.15 -0.05 +0.004 0.006 -0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 1.27 0.050 0.40 0.10 0.016 0.004 0~8
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