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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev. 10/02 1 ?2002, micron technology inc. 512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance ? 9mb qdr ? sram 4-word burst mt54v512h18e features ? 9mb density (512k x 18) separate independent read and write data ports with concurrent transactions 100 percent bus utilization ddr read and write operation high-frequency operation with future migration to higher clock frequencies fast clock to valid data times full data coherency, providing most current data four-tick burst counter for reduced address frequency double data rate operation on read and write ports two input clocks (k and k#) for precise ddr timing at clock rising edges only two output clocks (c and c#) for precise flight time and clock skew matching?clock and data delivered together to receiving device single address bus simple control logic for easy depth expansion internally self-timed, registered writes +2.5v core and hstl i/o clock-stop capability 13mm x 15mm, 1mm pitch, 11 x 15 grid fbga package user-programmable impedance outputs jtag boundary scan general description the micron ? qdr ? (quad data rate?) synchro - nous pipelined burst sram employs high-speed, low- power cmos designs using an advanced 6t cmos process. the qdr architecture consists of two separate ddr (double data rate) ports to access the memory array. the read port has dedicated data outputs to support read operations. the write port has dedicated data inputs to support write operations. this architecture eliminates the need for high-speed bus turnaround. access to each port is accomplished using a common address bus. addresses for reads and writes are latched on alternate rising edges of the k input clock. each address location is associated with four 18-bit words that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both clocks (k, k#, c and c#) memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. options marking 1 note: 1. a part marking guide for fbga devices can be found on micron?s web site http://www.micron.com/numberguide clock cycle timing 6ns (167 mhz) -6 7.5ns (133 mhz) -7.5 10nx (100 mhz) -10 configurations 512k x 18 mt54v512h18e package 165-ball, 13mm x 15mm fbga f table 1: valid part numbers part number description mt54v512h18ef-xx 512k x 18, qdrb4 fbga figure 1: 165-ball fbga
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 2 ?2002, micron technology inc. depth expansion is accomplished with port selects for each port (read r#, write w#) which are received at k rising edge. port selects permit independent port operation. all synchronous inputs pass through regis - ters controlled by the k or k# input clock rising edges. active low byte writes (bw0#, bw1#) permit byte write selection. write data and byte writes are regis - tered on the rising edges of both k and k#. the addressing within each burst of four is fixed and sequential. all synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (c and c# if provided, otherwise k and k#). four balls are used to implement jtag test capabili - ties: test mode select (tms), test data-in (tdi), test clock (tck), and test data-out (tdo). jtag circuitry is used to serially shift data to and from the sram. jtag inputs use jedec-standard 2.5v i/o levels to shift data during this testing mode of operation. the sram operates from a +2.5v power supply, and all inputs and outputs are hstl-compatible. the device is ideally suited for applications that benefit from a high-speed fully-utilized ddr data bus. please refer to micron?s web site ( www.micron.com / sramds ) for the latest data sheet. read/write operations all bus transactions operate on an uninterruptable burst of four data, requiring two full clock cycles of bus utilization. any request that attempts to interrupt a burst in progress is ignored. the resulting benefit is that the address rate is kept down to the clock fre - quency even when both buses are 100 percent utilized. read cycles are pipelined. the request is initiated by asserting r# low at k rising edge. data is delivered after the next rising edge of k using c and c# as the output timing references, or using k and k#, if c and c# are tied high. if c and c# are tied high, they may not be toggled during device operation. output tri- stating is automatically controlled such that the bus is released if no data is being delivered. this permits banked sram systems with no complex oe timing generation. back-to-back read cycles are initiated every second k rising edge. any command in between is ignored, since the burst sequence may not be inter - rupted and requires two full clock cycles. write cycles are initiated by w# low at k rising edge. data is expected at both rising edges of k andk# beginning one clock period later. write registers are incorporated to facilitate pipelined self-timed write cycles and provide fully coherent data for all combina - tions of reads and writes. a read can immediately follow a write even if they are to the same address. although the write data has not been written to the memory array, the sram will deliver the data from the write register instead of using the older data from the memory array. the latest data is always utilized for all bus transactions. write cycles are initiated every sec - ond k rising edge. any command in between is ignored, since the burst sequence may not be inter - rupted. figure 2: functional block diagram: 512k x 18 note: 1. the functional block diagram illustrates simplified device operation. see truth tables, ball descriptions, and timing diagrams for detailed information. 2. n = 17 address d (data in) n n r# w# k 18 36 36 36 36 72 k# k r# w# bw0# bw1# k n 2 x 72 memory array c address registry & logic data registry & logic c,c# 18 q (data out) r e g w r i t e mux mux d r i v e r w r i t e o u t p u t o u t p u t r e g b u f f e r a m p s s e n s e o u t p u t s e l e c t
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 3 ?2002, micron technology inc. byte write operations byte write operations are supported. the active low byte write controls, bw0# and bw1#, are regis - tered coincident with their corresponding data. this feature can eliminate the need for some read/mod - ify/write cycles, collapsing it to a single byte write operation in some instances. programmable impedance output buffer the qdr sram is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision resistor (rq) is con - nected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for example, a 350 resistor is required for an output impedance of 70 . to ensure that output impedance is one fifth the value of rq (within 15 percent), the range of rq is 175 to 350 . alternately, the zq ball can be connected directly to v dd q, which will place the device in a minimum impedance mode. output impedance updates may be required because variations may occur in supply voltage and temperature over time. the device samples the value of rq. impedance updates are transparent to the sys - tem; they do not affect device operation, and all data sheet timing and current specifications are met during an update. the device will power up with an output impedance set at 50 . to guarantee optimum output driver impedance after power-up, the sram needs 1,024 cycles to update the impedance. the user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. clock considerations the device does not utilize internal phase-locked loops and can therefore be placed into a stopped-clock state to minimize power without lengthy restart times. it is strongly recommended that the clocks operate for a number of cycles prior to initiating commands to the sram. this delay permits transmission line charging effects to be overcome and allows the clock timing to be nearer to its steady-state value. single clock mode the sram can be used with the single k, k# clock pair by tying c and c# high. in this mode, the sram will use k and k# in place of c and c#. this mode pro - vides the most rapid data output but does not com - pensate for system clock skew and flight times. depth expansion port select inputs are provided for the read and write ports. this allows for easy depth expansion. both port selects are sampled on the rising edge of k only. each port can be independently selected and dese - lected and do not affect the operation of the opposite port. all pending transactions are completed prior to a port deselecting. figure 3: application example vt vt = v ref vt cc# zq q k# d sa k cc# zq q k# d sa k bus master (cpu or asic) sram #1 sram #4 data in data out addresses read# write# bwn# return clk source clk return clk# source clk# r = 50 ? r = 250 ? r = 250 ? r # w # b w n # r # w # b w n # vt vt vt r r
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 4 ?2002, micron technology inc. table 2: ball assignment (top view) 165-ball fbga 1 2 3 4 5 6 7 8 9 10 11 a dnu v ss / sa 1 nc/ sa 2 w# bw1# k# nc r# nc/ sa 3 v ss / s a 4 dnu b nc q9 d9 sa nc k bw0# sa nc nc q8 c nc nc d10 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v dd q v ss v ss v ss v dd q nc d6 q6 f nc q12 d12 v dd q v dd v ss v dd v dd q nc nc q5 g nc d13 q13 v dd q v dd v ss v dd v dd q nc nc d5 h nc v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc d14 v dd q v dd v ss v dd v dd q nc q4 d4 k nc nc q14 v dd q v dd v ss v dd v dd q nc d3 q3 l nc q15 d15 v dd q v ss v ss v ss v dd q nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi note: 1. expansion address: 2a for 144mb 2. expansion address: 3a for 36mb 3. expansion address: 9a for 18mb 4. expansion address: 10a for 72mb
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 5 ?2002, micron technology inc. table 3: ball descriptions symbol type description sa input synchronous address inputs: these inputs are re gistered and must meet the setup and hold times around the rising edge of k. see ball assignment figures for address expansion inputs. all transactions operate on a burst of four 18-bit data (two clock periods of bus activity). these inputs are ignored when both ports are deselected. r# input synchronous read: when low, this input causes the address inputs to be registered and a read cycle to be initiated. this input must me et setup and hold times around the rising edge of k and is ignored on the s ubsequent rising edge of k. w# input synchronous write: when low, this input causes the address inputs to be registered and a write cycle to be initiated. this input must me et setup and hold times around the rising edge of k and is ignored on the subsequent rising edge of k. this input is also ignored if a read cycle is being initiated. bw0# bw1# input synchronous byte writes: when low, these inputs cause their respective bytes to be registered and written if w# had initiated a write cycle. these signals must meet setup and hold times around the rising edges of k and k# for each of the four rising edges comprising the write cycle. bw0# controls d0:d8, and bw1# controls d9:d17. see ball assignment figures for signal to data relationships. k k# input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. c c# input output clock: this clock pair provides a user -controlled means of tuning device output data. the rising edge of c is used as the output timi ng reference for second and fourth output data. the rising edge of c# is used as the output reference for first and third output data. ideally, c# is 180 degrees out of phase with c. c and c# may be tied high to force the use of k and k# as the output reference clocks instead of having to provide c and c# clocks. if tied high, these inputs may not be allowed to toggle during device operation. tms tdi input ieee 1149.1 test inputs: 2.5v i/o levels. these balls may be left as no connects if the jtag function is not used in the circuit. tck input ieee 1149.1 clock input: 2.5v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. v ref input hstl input reference voltage: nominally v dd q/2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffer trip point. zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq output impedanc e is set to 0.2 x rq, where rq is a resistor from this ball to ground. alternately, this ball can be connected directly to v dd q, which enables the minimum impedance mode. this ball cannot be connected directly to gnd or left unconnected. d_ input synchronous data inputs: input data must meet setup and hold times around the rising edges of k and k# during write operat ions. see ball assignment figures for ball site location of individual signals. dnu output do not use: these balls should not be used. tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level. q_ output synchronous data outputs: output data is sync hronized to the respective c and c# or to k and k# rising edges if c and c# are tied high. this bus operates in response to r# commands. see ball assignment figures for ball site location of individual signals. v dd supply power supply: 2.5v nominal. see dc electrical characteristics and operating conditions for range. v dd q supply power supply: isolated output buffer supply. nominally 1.5v. see dc electrical characteristics and operating conditions for range. v ss supply power supply: gnd.
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 6 ?2002, micron technology inc. nc ? no connect: these signals are not internally connected and may be connected to ground to improve package heat dissipation. nc/ sa these balls are reserved for higher-order address bits, respectively. table 3: ball descriptions (continued) symbol type description
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 7 ?2002, micron technology inc. figure 4: bus cycle state diagram note: 1. the address is concatenated with 2 additional internal lsbs to facilitate burst operation. the address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. bus cycle is terminated at the end of this sequence (burst count = 4). 2. state transitions: rd = (r# = low); wt = (w# = low). 3. read and write state machines can be active simultaneous ly. read and write cannot be simultaneously initiated. read takes precedence. 4. state machine control timing sequence is controlled by k load new read address; r_count=0; r_init=1 read double; r_count=r_count+2 increment read address by two 1 r_init=0 power-up supply voltage provided read port nop r_init=0 rd & r_count=4 rd r_count=2 always always /rd & r_count=4 /rd load new write address; w_count=0 write double; w_count=w_count+2 increment write address by two 1 supply voltage provided write port nop wt & w_count=4 wt & r_init=0 w_count=2 always always /wt /wt & w_count=4
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 8 ?2002, micron technology inc. note: 1. x means ?don?t care.? h means logic high. l means logic low. means rising edge; means falling edge. 2. data inputs are registered at k and k# rising edges. data outputs are delivered at c and c# rising edges, except if c and c# are high, then data outputs are delivered at k and k# rising edges. 3. r# and w# must meet setup and hold times around the rising edge (low to high) of k and are registered at the ris - ing edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. it is recommended that k = /k# = c =/c# when clock is sto pped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. if this signal was low to initiate the previous cycle, this signal becomes a ?don?t care? for this operation; however, it is strongly recommended that this signal is brought high as shown in the truth table. 8. this signal was high on previous k clock rising edge. in itiating consecutive read or write operations on consecu - tive k clock rising edges is not permitte d. the device will ignore the second request. 9. assumes a write cycle was initiated. bw0# and bw1# can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. table 4: truth table notes 1 - 8 operation k r# w# d or q d or q d or q d or q write cycle: load address, input write data on two consecutive k and k# rising edges l h h 7 l 8 d a (a + 0) at k(t + 1) d a (a + 1) at k # (t + 1 ) d a (a + 2) at k(t + 2) d a (a + 3) at k#(t + 2) read cycle: load address, output data on two consecutive c and c# rising edges l h l 8 x q a (a+0) at c(t + 1) q a (a+1) at c#(t + 1) q a (a+2) at c(t + 2) q a (a+3) at c#(t + 2) nop: no operation l h h h d = x q = high-z d = x q = high-z d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state previous state previous state table 5: byte write operation note 9 operation k k# bw0# bw1# write d0-17 at k rising edge l h 0 0 write d0-17 at k# rising edge l h 0 0 write d0-8 at k rising edge l h 0 1 write d0-8 at k# rising edge l h 0 1 write d9-17 at k rising edge l h 1 0 write d9-17 at k# rising edge l h 1 0 write nothing at k rising edge l h 1 1 write nothing at k# rising edge l h 1 1
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 9 ?2002, micron technology inc. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi - tions above those indicated in the operational sections of this specification is not implied. exposure to abso - lute maximum rating conditions for extended periods may affect reliability. maximum junction temperature depends upon package type, cycle time, loading, ambient tempera - ture, and airflow. see micron technical note tn-05-14 for more information. absolute maximum ratings voltage on v dd supply relative to v ss ............................................. 0.5v to +3.6v voltage on v dd q supply relative to v ss ....................................... -0.5v to + v dd v in ..................................................... -0.5v to v dd + 0.5v storage temperature ............................. -55oc to +125oc junction temperature .......................................... +125oc short circuit output current .............................. 70ma table 6: dc electrical characteristics and operating conditions notes appear following parameter tables; 0c t a +70c; +2.4v v dd +2.6v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih ( dc ) v ref + 0.1 v dd q + 0.3 v 3 , 4 input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.1 v 3 , 4 clock input signal voltage v in -0.3 v dd q + 0.3 v 3 , 4 input leakage current 0v v in v dd q il i -5 5 a output leakage current output(s) disabled, 0v v in v dd q (q) il o -5 5 a output high voltage | i oh | 0.1ma v oh ( low ) v dd q - 0.2 v dd q v 3 , 5 , 7 note 1 v oh v dd q/2 - 0.08 v dd q/2 + 0.08 v 3 , 5 , 7 output low voltage i ol 0.1ma v ol ( low ) v ss 0.2 v 3 , 5 , 7 note 2 v ol v dd q/2 - 0.08 v dd q/2 + 0.08 v 3 , 5 , 7 supply voltage v dd 2.4 2.6 v 3 isolated output buffer supply v dd q 1.4 1.6 v 3 , 6 reference voltage v ref 0.68 0.9 v 3 table 7: ac electrical characteristics and operating conditions notes appear following parameter tables; 0c t a +70c; +2.4v v dd +2.6v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih ( ac ) v ref + 0.2 ? v 3 , 4 , 8 input low (logic 0) voltage v il ( ac ) ? v ref - 0.2 v 3 , 4 , 8
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 10 ?2002, micron technology inc. table 9: capacitance note 14 ; notes appear following parameter tables table 10: thermal resistance note 14 ; notes appear following parameter tables ta bl e 8 : i dd operating conditions and maximum limits notes appear following parameter tables; 0c t a +70c; v dd = max unless otherwise noted max description conditions sym typ -6 -7.5 -10 units notes operating supply current: ddr all inputs v il or v ih ; cycle time t khkh (min ); outputs open i dd 400 550 500 375 ma 9 , 10 , 11 standby supply current: nop t khkh = t khkh (min); device in nop state; all addresses/data static i sb 1 150 250 225 175 ma 10 , 12 stop clock current cycle time = 0; input static i sb tbd 75 75 75 ma 10 output supply current: ddr (information only) c l = 15pf i dd q 34 27 20 ma 13 description conditions symbol typ max units address/control input capacitance t a = 25oc; f = 1 mhz c i 4 5 pf output capacitance (d, q) c o 6 7 pf clock capacitance c ck 5 6 pf description conditions symbol typ units notes junction to ambient (airflow of 1m/s) soldered on a 4.25 x 1.125 inch, 4-layer, printed circuit board ja 25 oc/w 15 junction to case (top) jc 10 oc/w junction to balls (bottom) jb 12 oc/w 16
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 11 ?2002, micron technology inc. table 11: ac electrical characteristics and recommended operating conditions notes 14 , 17 - 19 ; notes appear following parameter tables; 0c t a +70c; +2.4v v dd +2.6v description sym -6 -7.5 -10 units notes min max min max min max clock clock cycle time (k, k#, c, c#) t khkh 6.0 7.5 10 ns clock high time (k, k#, c, c#) t khkl 2.4 3.0 3.5 ns clock low time (k, k#, c, c#) t klkh 2.4 3.0 3.5 ns clock to clock# ( k k # , c c # ) at t khkh minimum t khk#h 2.7 3.4 4.6 ns clock# to clock ( k k # , c c # ) at t khkh minimum t k#hkh 2.7 3.4 4.6 ns clock to data clock (k c , k# c# ) t khch 0.0 2.0 0.00 2.5 0.0 3.0 ns output times c, c# high to output valid t chqv 2.5 3.0 3.0 ns c, c# high to output hold t chqx 1.2 1.2 1.2 ns c high to output high-z t chqz 2.5 3.0 3.0 ns 20 , 21 c high to output low-z t chqx1 1.2 1.2 1.2 ns 20 , 21 setup times address valid to k rising edge t avkh 0.7 0.8 1.0 ns control inputs valid to k rising edge t ivkh 0.7 0.8 1.0 ns data-in valid to k, k# rising edge t dvkh 0.7 0.8 1.0 ns 20 , 21 hold times 20 , 21 k rising edge to address hold t khax 0.7 0.8 1.0 ns k rising edge to control inputs hold t khix 0.7 0.8 1.0 ns 22 k, k# rising edge to data-in hold t khdx 0.7 0.8 1.0 ns 22
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 12 ?2002, micron technology inc. notes 1. outputs are impedance-controlled. |i oh | = (v dd q/2)/(rq/5) for values of 175 rq 350 . 2. outputs are impedance-controlled. i ol = (v dd q/ 2)/(rq/5) for values of 175 rq 350 . 3. all voltages referenced to v ss (gnd). 4. overshoot: v ih ( ac ) v dd + 0.7v for t t khkh/2 undershoot: v il ( ac ) -0.5v for t t khkh/2 power-up: v ih v dd q + 0.3v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . r# and w# signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 5. ac load current is higher than the shown dc val - ues. ac i/o curves are available upon request. 6. for higher v dd q voltages, contact factory for product information. 7. hstl outputs meet jedec hstl class i and class ii standards. 8. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il ( ac ) or v ih ( ac ) b. reach at least the target ac level c. after the ac target level is reached, continue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ) 9. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. typical value is measured at 7.5ns cycle time. 10. typical values are measured at v dd =2.5v, v dd q = 1.5v, and temperature = 25c. 11. operating supply currents and burst mode cur - rents are calculated with 50 percent read cycles and 50 percent write cycles. 12. nop currents are valid when entering nop after all pending read and write cycles are com - pleted. 13. average i/o current and power is provided for informational purposes only and is not tested. calculation assumes that all outputs are loaded with c l (in farads), f = input clock frequency, half of outputs toggle at each transition (for example, n = 18 for x36), c o = 6pf, v dd q = 1.5v and uses the equations: average i/o power as dissipated by the sram is: p = 0.5 n x f x v dd q 2 x (c l + 2c o ). average i dd q = n x f x v dd q x (c l + c o ). 14. this parameter is sampled. 15. average thermal resistance between the die and the case top surface per mil spec 883 method 1012.1. 16. junction temperature is a function of total device power dissipation and device mounting environ - ment. measured per semi g38-87. 17. control input signals may not be operated with pulse widths less than t khkl (min). 18. test conditions as specified with the output load - ing as shown in figure 5 , unless otherwise noted. 19. if c, c# are tied high, then k, k# become the ref - erences for c, c# timing parameters. 20. transition is measured 100mv from steady state voltage. 21. t chqxi is greater than t chqz at any given voltage and temperature. 22. this is a synchronous device. all addresses, data, and control lines must meet the specified setup and hold times for all latching clock edges.
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 13 ?2002, micron technology inc. ac test conditions input pulse levels . . . . . . . . . . . . . . . . . . 0.25v to 1.25v input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns input timing reference levels . . . . . . . . . . . . . . . . 0.75v output reference levels . . . . . . . . . . . . . . . . . . .v dd q/2 zq for 50 impedance . . . . . . . . . . . . . . . . . . . . . 250 output load . . . . . . . . . . . . . . . . . . . . . . . . . see figure 5 figure 5: output load equivalent 50 ? v dd q/2 250 ? z = 50 ? o zq sram 0.75v v ref
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 14 ?2002, micron technology inc. figure 6: read/write timing note: 1. q00 refers to output from address a0 + 0. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1, etc. 2. outputs are disabled (high-z) one clock cycle after a nop. 3. in this example, if address a0 = a1, data q20 = d10, q21 = d11. write data is forwarded immediately as read results. k 1 23456 7 k# r# w# a q d c c# a0 read read write write q00 q03 d10 d11 d12 d13 d30 d31 d32 d33 a1 t khkl t khk#h t khch t chqv t chqx t klkh t khkh t t khix t avkh t khax t dvkh t khdx t khch q01 q02 q23 q22 q20 q21 nop nop qx3 a2 t dvkh t khdx don?t care undefined t chqx1 t chqv t chqx t chqz ivkh tt khix ivkh t khkl t khk#h t klkh t khkh a3
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 15 ?2002, micron technology inc. ieee 1149.1 serial boundary scan (jtag) the qdr sram incorporates a serial boundary scan test access port (tap). this port operates in accor - dance with ieee standard 1149.1-2001 but does not have the set of functions required for full 1149.1 com - pliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully-compliant taps. the tap operates using jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the opera - tion of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. figure 7: tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between the tdi and tdo balls is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 7 . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most-significant bit (msb) of any register, as shown in figure 8 . test data-out (tdo) the tdo output ball is used to serially clock data- out from the registers. the output is active depending upon the current state of the tap state machine, as depicted in figure 7 .) the output changes on the fall - ing edge of tck. tdo is connected to the least signifi - cant bit (lsb) of any register, illustrated in figure 8 .) test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 16 ?2002, micron technology inc. figure 8: tap controller block diagram note: x = 69 for all configurations. performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is seri - ally loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in figure 2. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through reg - isters, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with mini - mal delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. several no connect (nc) balls are also included in the scan regis - ter to reserve balls. the sram has a 69-bit-long regis - ter. the boundary scan register is loaded with the con - tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the balls on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction regis - ter. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift- dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple - mented. the tap controller cannot be used to load bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 17 ?2002, micron technology inc. overview (continued) address, data, or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller dur - ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction regis - ter and through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, hence this device is not ieee 1149.1 compliant. the tap controller does recognize an all-0 instruc - tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sam - ple/preload instruction has been loaded. extest does not place the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins/balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc - tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bi-directional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap con - troller?s capture setup plus hold time (tcs plus tch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruc - tion will have the same effect as the pause-dr com - mand. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 18 ?2002, micron technology inc. figure 9: tap timing note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 10 . t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined table 12: tap dc electrical characteristics notes 1 , 2 ; 0oc t a +70oc; +2.4v v dd +2.6v description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 19 ?2002, micron technology inc. tap ac test conditions input pulse levels . . . . . . . . . . . . . . . . . . . . . v ss to 2.5v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . 1ns input timing reference levels . . . . . . . . . . . . . . . . 1.25v output reference levels . . . . . . . . . . . . . . . . . . . . . 1.25v test load termination supply voltage . . . . . . . . . 1.25v figure 10: tap ac output load equivalent note: 1. all voltages referenced to v ss (gnd) . 2. overshoot: v ih ( ac ) v dd + 0.7v for t t khkh/2 undershoot: v il ( ac ) -0.5v for t t khkh/2 power-up: v ih +2.6 and v dd +2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max). tdo 1.25v 20pf z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions 0oc t a +70oc; +1.7v v dd +1.9v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1 , 2 input low (logic 0) voltage v il -0.3 0.7 v 1 , 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, 0v v in v dd q (dqx) il o -5.0 5.0 a output low voltage i olc = 100a v ol 1 0.2 v output low voltage i olt = 2ma v ol 2 0.7 v 1 output high voltage i ohc = -100a v oh 1 2.1 v 1 output high voltage i oht = -2ma v oh 1 1.7 v 1
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 20 ?2002, micron technology inc. table 13: identification register definitions instruction field 512k x 18 description revision number (31:28) 000 version number. device id (28:12) 00011000011000000 512k x 18 qdr 4-word burst. micron jedec id code (11:1) 00000101100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. table 14: scan register sizes register name bit size (x18) instruction 3 bypass 1 id 32 boundary scan 69 table 15: instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. this operation does not affect sram operations. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operations. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 21 ?2002, micron technology inc. table 16: boundary scan (exit) order bit# signal name ball id bit# signal name ball id 1 c# 6r 36 bw0# 7b 2 c 6p 37 k 6b 3 sa 6n 38 k# 6a 4 sa 7p 39 bw1# 5a 5 sa 7n 40 w# 4a 6 sa 7r 41 sa 5c 7 sa 8r 42 sa 4b 8 sa 8p 43 nc/ sa19 3a; reads as 1 9 sa 9r 44 gnd/ sa21 2a; reads as 0 10 d0 10p 45 reserved 1a; reads as x 11 q0 11p 46 d9 3b 12 d1 11n 47 q9 2b 13 q1 10m 48 d10 3c 14 d2 11m 49 q10 3d 15 q2 11l 50 d11 2d 16 d3 10k 51 q11 3e 17 q3 11k 52 d12 3f 18 d4 11j 53 q12 2f 19 zq 11h 54 d13 2g 20 q4 10j 55 q13 3g 21 d5 11g 56 d14 3j 22 q5 11f 57 q14 3k 23 d6 10e 58 d15 3l 24 q6 11e 59 q15 2l 25 d7 11d 60 d16 3m 26 q7 10c 61 q16 3n 27 d8 11c 62 d17 2n 28 q8 11b 63 q17 3p 29 reserved 11a; reads as x 64 sa 3r 30 gnd/ sa20 10a; reads as 0 65 sa 4r 31 nc/ sa18 9a; reads as 1 66 sa 4p 32 sa 8b 67 sa 5p 33 sa 7c 68 sa 5n 34 nc 6c; reads as 0 69 sa 5r 35 r# 8a
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron and the m logo are registered trademarks and the micron logo is a trademark of micron technology, inc. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, micron technology, inc., nec, and samsung. 512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram ?2002, micron technology inc. mt54v512h18e_16_a.fm - rev 10/02 22 figure 11: 165-ball fbga note: 1. all dimensions are in millimeters. data sheet designation advance: this data sheet contains initial descriptions of products still under development. 10.00 14.00 15.00 0.10 1.00 typ 1.00 typ 5.00 0.05 13.00 0.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 63% sn, 37% pb solder ball pad: ? .33mm solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40 seating plane 0.85 0.075 0.12 c c 165x ? 0.45 ball a11
512k x 18 2.5v v dd , hstl, qdrb4 sram 0.16m process advance 512k x 18, 2.5v v dd , hstl, qdrb4 sram micron technology, inc., reserves the right to change products or specifications without notice. mt54v512h18e_16_a.fm - rev 10/02 23 ?2002, micron technology inc. revision history new advance data sheet for 0.16m process, rev. a, pub. 10 /02 .....................................................................10/02

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