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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product wedpnf8m722v-xbx september 2000 rev. 0 8mx72 synchronous dram + 16mb flash mixed module multi-chip package advanced* features n package: ? 275 plastic ball grid array (pbga), 32mm x 25mm n commercial, industrial and military temperature ranges n weight: ? wedpnf8m722v-xbx - 2.5 grams typical sdram performance features n organized as 8m x 72 n high frequency = 100, 125mhz n single 3.3v 0.3v power supply n fully synchronous; all signals registered on positive edge of system clock cycle n internal pipelined operation; column address can be changed every clock cycle n internal banks for hiding row access/precharge n programmable burst length 1,2,4,8 or full page n 4096 refresh cycles flash performance features n user configurable as 2mx8, 1m x16 or 512k x 32 n access times of 100, 120, 150ns 32 25 discrete approach s a v i n g s area 5 x 265mm + 2 x 54mm = 1433mm 2 2 2 800mm 2 44% 5 x 54 pins + 2 x 48 balls = 366 connections 275 balls 25% actual size 22.3 11.9 11.9 i/o count 11.9 11.9 11.9 48 pbga 6.0 9.0 note: dimensions in millimeters 48 pbga 6.0 9.0 n 3.3 volt for read and write operations n 1,000,000 erase/program cycles n sector architecture ? one 16kbyte, two 8kbytes, one 32kbyte, and fifteen 64kbytes in byte mode ? one 8k word, two 4k words, one 16k word, and fifteen 32k word sectors in word mode. ? any combination of sectors can be concurrently erased. also supports full chip erase n boot code sector architecture (bottom) n embedded erase and program algorithms n erase suspend/resume ? supports reading data from or programing data to a sector not being erased benefits n 44% space savings n reduced part count n reduced i/o count ? 25% i/o reduction n suitable for hi-reliability applications n sdram upgradeable to 16m x 72 density (contact factory for information) * this data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 1 pin configuration notes: 1. dnu = do not use top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t u v dq 12 dq 14 dq 15 dq 0 dq 1 dq 3 dq 5 dq 6 dq 63 dq 62 dq 59 dq 61 dq 60 dq 48 dq 50 dq 53 dnu dq 29 dq 30 dq 31 v ss dq 16 dq 17 dq 18 dq 19 v cc v ss v cc dq 43 dq 40 dq 41 dq 37 dq 36 dq 34 dq 35 dq 9 dq 10 dq 11 dq 13 dq 2 dq4 dq7 dqml 0 v ss v cc dq 58 dq56 dq 57 dq 49 dq 51 dq 55 dqml 3 dq 54 fd 18 fd 25 fd 17 v cc v cc v cc v ss v ss v cc v ss v cc v cc v ss v ss v ss v cc v cc v cc dq 8 cke 0 clk 0 dqmh 0 we 0 cas0 ras 0 cs0 v ss v cc cke 3 clk 3 dqmh 3 dq 52 cas 3 ras 3 cs 3 we 3 fd 31 fd 26 fa 17 foe fcs 2 fa 1 v ss fcs 1 v cc v ss v cc v cc v cc v cc dnu a 4 dnu a 3 fa 16 fa 13 fa 10 v ss v ss v ss v cc v cc v ss v cc v ss v ss v cc v cc v cc v ss v ss v ss byte 2 fd 21 fd 24 byte 1 fd 15 v ss v ss v cc a 5 a 6 a 1 a 2 fa 15 fa1 2 fa 9 fa 7 fa 5 fa 2 dnu ryby 1 v ss v cc v ss v cc v cc v cc dq 77 dq 79 dq 69 dq 71 rst fwe fa 19 fa 18 fa 3 v ss v cc v cc dq 76 dq 78 dq 68 dq 70 fd 22 fd 27 fd 4 fd 11 fd 12 v cc v ss v ss cke 4 cs 4 ras 4 cas 4 fd 29 fd 19 fd 3 fd 10 fd 2 v ss v ss v ss clk 4 dqmh 4 we 4 dqml 4 fa 14 fa 11 fa 8 fa 6 fa 4 dnu v ss v cc dq 73 dq 75 dq 65 dq 67 fd 30 fd 20 fd 6 fd 5 fd 13 v ss v ss v cc a 9 a 11 ba 1 ba 0 17 18 cke 1 clk 1 dqmh 1 dq 24 dqml 1 cas 1 ras 1 cs 1 we 1 cke 2 clk 2 dqmh 2 dq 46 dq 39 we 2 cs 2 ras 2 cas 2 dq 25 dq 26 dq 27 dq 28 dq 20 dq 21 dq 22 dq 23 v cc v ss dq 47 dq 44 dq 45 dq 42 dq 32 dq 33 dq 38 dqml 2 ry/by2 fd 9 fd 1 fd 8 fd 0 v cc v cc v ss dq 72 dq 74 dq 64 dq 66 fd 23 fd 28 fd 16 fd 7 fd 14 v ss v ss v cc a 7 a 8 a 10 a 0
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 2 functional block diagrams a 0-11 a 0-11 ba 0-1 ba 0-1 clk 0 clk cas dq 0 dq 15 cke 0 cke cs 0 cs dqml 0 dqml dqmh 0 dqmh ras 1 we 1 cas 1 dq 0 dq 15 we u1 ras a 0-11 ba 0-1 clk 1 clk cas dq 16 dq 31 ras 0 we 0 cas 0 dq 0 dq 15 we u0 ras cke 1 cke cs 1 cs dqml 1 dqml dqmh 1 dqmh ras 2 we 2 cas 2 dq 0 dq 15 we u2 ras a 0-11 ba 0-1 clk 2 clk cas dq 32 dq 47 cke 2 cke cs 2 cs dqml 2 dqml dqmh 2 dqmh ras 3 we 3 cas 3 dq 0 dq 15 we u3 ras a 0-11 ba 0-1 clk 3 clk cas dq 48 dq 63 cke 3 cke cs 3 cs dqml 3 dqml dqmh 3 dqmh ras 4 we 4 cas 4 dq 0 dq 15 we u4 ras a 0-11 ba 0-1 clk 4 clk cas dq 64 dq 79 cke 4 cke cs 4 cs dqml 4 dqml dqmh 4 dqmh 4mx16 4mx16 4mx16 4mx16 4mx16 sdram flash 16 fd 0-15 byte1 rst fwe foe fa 1-19 fcs1 ry/by1 u5 1mx8/ 512kx16 16 fd 16-31 byte2 rst fwe foe fa 1-19 fcs2 ry/by2 u6 1mx8/ 512kx16
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx signal name pin number v cc d15, e15, f8, f10, f15, g4, h4, j14, j15, j16, j17, k2, k3, k4, k5, l14, l15, l16, m5, m14, m15, n4, n5, n7, n8, n14, p4, p5, p6, p7, p11, p12, p13, p14, r4, t15, u15, v15 gnd d4, d16, e4, f4, f7, f9, f11, f12, f13, g14, g15, h15, j2, j3, j4, j5, k14, k15, k16, k17, l4, l5, m4, n6, n9, n10, n11, n12 , n13, n15, p8, p9, p10, p15, r15, t4, u4, v4 fd0 - 15 e8, c8, e9, c9, c10, d11, c11, d12, d8, b8, d9, d10, e10, e11, e12, e13 ryby1 h5 rst a7 byte1 d13 fd16 - 31 c12, c15, a15, b9, b11, b13, a10, a12, c13, b15, b14, b10, b12, a9, a11, a14 ryby2 a8 byte2 a13 fa1-19 f14, f5, e7, e6, e5, d6, d5, c6, c5, c4, b6, b5, b4, a6, a5, a4, c14, d7, c7 fcs1 h14 fcs2 e14 fwe b7 foe d14 a0 - a11 v12, u13, v13, v14, t14, r13, t13, r12, t12, r11, u12, t11 ba0 - 1 u11, v11 cs0 h3 we0 e3 clk0 c3 cke0 b3 ras0 g3 cas0 f3 dqml0 h2 dqmh0 d3 cs1 h18 we1 j18 clk1 b18 cke1 a18 ras1 g18 cas1 f18 dqml1 e18 dqmh1 c18 cs2 t18 we2 r18 clk2 l18 cke2 k18 ras2 u18 cas2 v18 dqml2 v17 dqmh2 m18 cs3 u3 we3 v3 clk3 m3 cke3 l3 ras3 t3 package pinout listing
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx signal name pin number package pinout listing (continued) cas3 r3 dqml3 u2 dqmh3 n3 cs4 t10 we4 u9 clk4 r9 cke4 r10 ras4 u10 cas4 v10 dqml4 v9 dqmh4 t9 dq0 - 15 e1, f1, e2, g1, f2, h1, j1, g2, a3, a2, b2, c2, b1, d2, c1, d1, dq16 - 31 e16, f16, g16, h16, e17, f17, g17, h17, d18, a17, b17, c17, d17, a16, b16, c16 dq32 - 47 r17, t17, u16, v16, t16, r16, u17, p18, n16, p16, p17, m16, m17, n17, n18, l17 dq48 - 63 r1, p2, t1, r2, p3, u1, v2, t2, m2, n2, l2, m1, p1, n1, l1, k1 dq64 - 79 u8, u6, v5, v6, u7, u5, v7, v8, r8, r6, t8, t6, r7, r5, t7, t5 dnu f6, g5, r14, u14, v1
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx dc electrical characteristics and operating conditions (notes 1, 3) (v cc = +3.3v 0.3v; t a = -55 c to +125 c) parameter/condition symbol units min max supply voltage v cc 3 3.6 v input high voltage: logic 1; all inputs (4) v ih 0.7 x vcc v cc + 0.3 v input low voltage: logic 0; all inputs (4) v il -0.3 0.8 v sdram input leakage current: any input 0v v in v cc i i -5 5 m a (all other pins not under test = 0v) sdram input leakage address current (all other pins not under test = 0v) i i -25 25 m a sdram output leakage current: i/os are disabled; 0v v out v cc i oz -5 5 m a sdram output high voltage (i out = -4ma) v oh 2.4 C v sdram output low voltage (i out = 4ma) v ol C 0.4 v flash flash input leakage current (v cc = 3.6, v in = gnd or v cc) i li 10 m a flash output leakage current (v cc = 3.6, v in = gnd or v cc) i lox8 10 m a flash output high voltage (i oh = -2.0 ma, v cc = 3.0) v oh1 0.85 x v cc v flash output low voltage (i ol = 5.8 ma, v cc = 3.0) v o l 0.45 v flash low v cc lock-out voltage (5) v lko 2.3 2.5 v notes: 1. all voltages referenced to v ss . 2. this parameter is not tested but guaranteed by design. f = 1 mhz, t a = 25 c. 3. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation i s ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 4. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 5. guaranteed by design, but not tested. absolute maximum ratings parameter unit supply voltage range (v cc ) -0.5 to +4.0 v signal voltage range -0.5 to vcc +0.5 v operating temperature t a (mil) -55 to +125 c operating temperature t a (ind) -40 to +85 c storage temperature, plastic -65 to +150 c power dissipation 5 w flash endurance (write/erase cycles) 1,000,000 min. cycles note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. sdram capacitance (note 2) parameter symbol max unit input capacitance: clk c i1 10 pf addresses, ba 0-1 input capacitance c a 35 pf input capacitance: all other input-only pins c i2 10 pf input/output capacitance: i/os c io 12 pf flash data retention parameter test conditions min unit minimum pattern data 150 c 10 years retention time 125 c 20 years
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx sdram description the 64mbyte (512mb) sdram is a high-speed cmos, dynamic random-access ,memory using 5 chips containing 134, 217, 728 bits. each chip is internally configured as a quad-bank dram with a synchronous interface. each of the chips 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst oriented; ac- cesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba 0 , ba 1 select the bank; a 0-11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 64mb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 64mb sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl compatible. sdrams offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. sdram functional description read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro- i cc specifications and conditions (notes 1,2,3,4) (v cc = +3.3v 0.3v; t a = -55 c to +125 c) parameter/condition symbol max units sdram operating current: active mode; i cc1 750 ma burst = 2; read or write; t rc = t rc (min); cas latency = 3 (5, 6, 7); fcs = high sdram operating current: burst mode; continuous burst; fcs = high i cc4 750 ma read or write; all banks active; cas latency = 3 (5, 6, 7) sdram self refresh current; fcs = high (14) i cc7 10 ma flash v cc active current for read : fcs = v il , foe = v ih , f = 5mhz (9, 13); cs = cke = high i fcc1 310 ma flash v cc active current for program or erase: fcs = v il , foe = v ih (10, 13); cs = cke = high i fcc2 320 ma standby current: active mode; cke = high; cs = high; fcs = high; i cc3 250 ma all banks active after t rcd met; no accesses in progress (5, 7, 8) notes: 1. all voltages referenced to v ss . 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 4. i cc specifications are tested after the device is properly initialized. 5. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 7. address transitions average one transition every two clocks. 8. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 9. the i cc current listed includes both the dc operating current and the frequency dependent component (at 5 mhz). the frequency component typically is less than 8 ma/mhz, with oe at v ih . 10. i cc active while embedded algorithm (program or erase) is in progress. 11. maximum i cc specifications are tested with v cc = v cc max. 12. automatic sleep mode enables the low power mode when addressed remain stable for tacc + 30 ns. 13. sdram in self refresh mode 14. self refresh available in commercial and industrial temperatures only.
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx grammed number of locations in a programmed sequence. ac- cesses begin with the registration of an active command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba 0 and ba 1 select the bank, a 0-11 select the row). the address bits (a 0-8 ) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and de- vice operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v ddq (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100 m s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100 m s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100 m s delay has been satisfied with at least one com- mand inhibit or nop command having been applied, a precharge command should be applied. all banks must be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be per- formed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of opera- tion of the sdram. this definition includes the selec-tion of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 3. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 speci- fies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 3. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a 1-8 when the burst length is set to two; by a 2-8 when the burst length is set to four; and by a 3-8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 1.
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 3 mode register definition m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a 10 a 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices. table 1 - burst definition burst starting column order of accesses within a burst length address a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-9/8/7 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (y) (location 0-y) cn - 1, cn notes: 1. for full-page accesses: y = 512. 2. for a burst length of two, a 1-8 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a 2-8 select the block-of-four burst; a 0-1 select the starting column within the block. 4. for a burst length of eight, a 3-8 select the block-of-eight burst; a 0-2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a 0-8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a 0-8 select the unique column to be accessed, and mode register bit m3 is ignored. type = sequential type = interleaved
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n +m. the i/ os will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the i/os will start driving after t1 and the data will be valid by t2. table 2 indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because table 2 - cas latency fig. 4 cas latency allowable operating frequency (mhz) cas cas speed latency = 2 latency = 3 -100 75 100 -125 100 125 clk i/o t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don? care undefined clk i/o t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single- location (nonburst) accesses. commands the truth table provides a quick reference of available com- mands. this is followed by a written description of each com- mand. three additional truth tables appear following the opera- tion section; these tables provide current state/next state infor- mation.
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx table 3 truth table - commands and dqm operation (note 1) name (function) cs ras cas we dqm addr i/os command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) ( 3) l l h h x bank/row x read (select bank and column, and start read burst) (4) l h l h l/h 8 bank/col x write (select bank and column, and start write burst) (4) l h l l l/h 8 bank/col valid burst terminate l h h l x x active precharge (deactivate row in bank or banks) ( 5) l l h l x code x auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x x x load mode register (2) l l l l x op-code x write enable/output enable (8) C C C C l C active write inhibit/output high-z (8) C C C C h C high-z notes: 1. cke is high for all commands shown except self refresh. 2. a 0-11 define the op-code written to the mode register. 3. a 0-11 provide row address, and ba 0 , ba 1 determine which bank is made active. 4. a 0-8 provide column address; a 10 high enables the auto precharge feature (nonpersistent), while a 10 low disables the auto precharge feature; ba 0 , ba 1 determine which bank is being read from or written to. 5. a 10 low: ba 0 , ba 1 determine the bank being precharged. a 10 high: all banks precharged and ba 0 , ba 1 are dont care. 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the i/os during writes (zero-clock delay) and reads (two-clock delay). read the read command is used to initiate a burst read access to an active row. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-8 selects the starting column location. the value on input a 10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the i/os subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding i/os will be high-z two clocks later; if the dqm signal was registered low, the i/os will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-8 selects the starting column location. the value on input a 10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the i/os is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. opera- tions already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. op- erations already in progress are not affected. load mode register the mode register is loaded via inputs a 0-11 . see mode register heading in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba 0 , ba 1 inputs selects the bank, and the address provided on inputs a 0-11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank.
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a 10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba 0 , ba 1 select the bank. otherwise ba 0 , ba 1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same indi- vidual-bank precharge function described above, without re- quiring an explicit command. this is accomplished by using a 10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full- page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge com- mand was issued at the earliest possible time. burst terminate the burst terminate command is used to truncate either fixed- length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated. auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas-before-ras (cbr) refresh in conven- tional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. each 128mb sdram requires 4,096 auto refresh cycles every refresh period (t ref ). providing a distributed auto re- fresh command will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh com- mands can be issued in a burst at the minimum cycle rate (t rc ), once every refresh period (t ref ). self refresh* the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become dont care, with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr , because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued as both self refresh and auto refresh utilize the row refresh counter. * self refresh available in commercial and industrial temperatures only.
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx parameter symbol -100 -125 unit min max min max access time from clk (pos. edge) cl = 3 t ac 66ns cl = 2 t ac 6ns address hold time t ah 11ns address setup time t as 22ns clk high-level width t ch 33ns clk low-level width t cl 33ns clock cycle time (6) cl = 3 t ck 88ns cl = 2 t ck 10 ns cke hold time t ckh 11ns cke setup time t cks 22ns cs, ras, cas, we, dqm hold time t cmh 11ns cs, ras, cas, we, dqm setup time t cms 22ns data-in hold time t dh 11ns data-in setup time t ds 22ns data-out high-impedance time cl = 3 (7) t hz 66ns cl = 2 (7) t hz 7ns data-out low-impedance time t lz 11ns data-out hold time (load) t oh 33ns data-out hold time (no load) (8) t oh n 1.8 1.8 ns active to precharge command t ras 50 120,000 45 120,000 ns active to active command period t rc 70 68 ns active to read or write delay t rcd 20 20 ns refresh period (4,096 rows) C commercial, industrial t ref 64 64 ms refresh period (4,096 rows) C military t ref 16 ms auto refresh period t rfc 70 ns precharge command period t rp 20 20 ns active bank a to active bank b command t rrd 15 16 ns transition time (9) t t 0.3 1.2 0.3 1.2 ns write recovery time (10) t wr 1 clk + 7ns 1 clk + 7ns (11) 15 15 ns exit self refresh to active command t xsr 80 78 ns sdram electrical characteristics and recommended ac operating characteristics (notes 1, 2, 3, 4, 5) notes: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. outputs measured at 1.5v with equivalent load: 5. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 6. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 7. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 8. guaranteed by design, but not tested. 9. ac characteristics assume t t = 1ns. 10. auto precharge mode only. the precharge timing budget (t rp ) begins 7.5ns/7ns after the first clock delay, after the last write is executed. 11. precharge mode only. q 50pf
14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx notes: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100ms is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc must be powered up simultaneously.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 7. timing actually specified by t cks ; clock(s) specified as a reference only at minimum cycle rate. 8. timing actually specified by t wr plus t rp ; clock(s) specified as a reference only at minimum cycle rate. 9. timing actually specified by t wr . 10. required clocks are specified by jedec functionality and are not depen- dent on any timing parameter. 11. jedec and pc100 specify three clocks. q 50pf sdram ac functional characteristics (notes 1,2,3,4,5,6) parameter/condition symbol -100 -125 units read/write command to read/write command (10) t ccd 11t ck cke to clock disable or power-down entry mode (7) t cked 11t ck cke to clock enable or power-down exit setup mode (7) t ped 11t ck dqm to input data delay (10) t dqd 00t ck dqm to data mask during writes t dqm 00t ck dqm to data high-impedance during reads t dqz 22t ck write command to input data delay (10) t dwd 00t ck data-in to active command (8) t dal 45t ck data-in to precharge command (9) t dpl 22t ck last data-in to burst stop command (10) t bdl 11t ck last data-in to new read/write command (10) t cdl 11t ck last data-in to precharge command (9) t rdl 22t ck load mode register command to active or refresh command (11) t mrd 22t ck data-out to high-impedance from precharge command (10) cl = 3 t roh 33t ck cl = 2 t roh 2t ck
15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx flash description the 16mbit (2mb) 3.3 volt-only flash memory is organized as 2,097,152 words of 8 bits each,1,048,576 words of 16 bits each or 524,288 words of 32 bits each. the byte-wide (x8) data appears on fd 0-7 ; the word-wide (x16) data appears on fd 0-15 , double-word- wide (x32) data appears on fd 0-31 . this device requires only a single 3.3 volt vcc supply to perform read, program, and erase operations. a standard eprom programmer can also be used to program and erase the device. this device features unlock bypass programming and in-system sector protection/unprotection. this device offers access times of 100, 120 and 150ns, allowing operation without wait states. to eliminate bus contention the device has separate chip selects (fcs 1-2 ), wite enable (fwe) and output enable (foe) controls. the device requires only a single 3.3 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and program circuitry. write cycles also internally latch addresses and data needed for the programming circuitry. write cycles also internally latch addresses abd data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm C an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. the unlock bypass mode faciclitates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm C an internal algorithm that automaticaally preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether as program or erase operation is complete by observing the ry/by 1-2 pin, or by reading fd 7 (data polling) and fd 6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectords. the device is fully erased when shipped from the factory. hardware data protection measures include a low vcc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables bith program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset (rst) pin terminates any operation in progress and resets the internal state machine to reading array data. the rst pin may be tied to the reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from flash memory. the device offers two power saving features. when addresses have been stable for specified amount of time, the device enters the automatic sleep mode. the system can also place the device into the standby mode. power consumption is greatly reduced in both these modes device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres- sable memory location. the register is composed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 4 lists the device bus operations, the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. word/byte configuration the byte1 pin controls whether the device data i/o pins fd o-15 operate in the byte or word configuration. if the byte1 pin is set at logic 1, the device is in word configuration, fd 0-15 are active and controlled by fcs1 and foe. if the byte1 pin is set at logic 0, the device is in byte configuration, and only data i/o pins fd 0-7 are active and controlled by fcs1 and foe. the data i/o pins fd 8-14 are tri stated, and the fd 15 pin is used as an input for the lsb (fa-1) address function. the byte2 pin controls whether the device data i/o pins fd 16-31 operate in the byte or word configuration. if the byte2 pin is set at logic 1, the device is in word configuration, fd0-15 are active and controlled by fcs2 and foe. if the byte2 pin is set at logic 0, the device is in byte configuration, and only data i/o pins fd 0-7 are active and controlled by fcs2 and foe. the data i/o pins fd 24-30 are tri stated, and the fd 31 pin is used as an input for the lsb (fa-1) address function.
16 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx requirements for reading array data to read array data from the outputs, the system must drive the fcs1-2 and foe pins to v il . fcs1-2 are the power controls and select the devices. foe is the output control and gates array data to the output pins. fwe should remain at v ih . the byte1-2 pins determine whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device data outputs. the device remains en- abled for read access until the command register contents are altered. see reading array data for more information. refer to the flash ac read-only operations table for timing specifications and to figure 11 for the timing diagram. i fcc1 in the i cc specifications and conditions table represents the active current specification for reading array data. write commands/command sequences to writes a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive fwe and fcs1-2 to v il , and foe to v ih . for program operations, the byte1-2 pins determine whether the device accepts program data in bytes or words. refer to word/ byte configuration for more information. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a byte, instead of four. an erase operation can erase one sector, multiple sectors, or the entire device. table 5 indicates the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. the flash command defini- tions section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on fd 7-0 and fd 23-16 respectively . stan- dard read cycle timings apply in this mode. refer to the "autoselect mode" and "autoselect command sequence" sections for more information. i fcc2 in the dc characteristics table represents the active current specifications for the write mode. the flash ac characteristics section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on fd 7-0 and fd 23-16 respectively. standard read cycle timings and i fcc read specifications apply. refer to write operation status for more information, and to flash ac characteristics for timing diagrams. table 4 - device bus operations legend: l = logic low = v il x = dont care fd out = flash data out h = logic high = v ih fa in = flash address in v id = 12.0 0.5v fd in = flash data in notes: 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the "sector protecti on/unprotection" section. 2. addresses are fa18: fa0 in word mode (byte1-2 = v ih ), fa18: fa-1 in byte mode (byte1-2 = v il ) fd 8-15/ fd 24-31 operation fcs 1-2 foe fwe rst addresses (2) fd 0-7 /fd 16-23 byte1-2 byte1-2 = v ih =v il read l l h h fa in fd out fd out fd 8-14, 24-30 = high z write lhlhfa in fd out fd out fd 15, 31 = fa- 1 standby vcc 0.3v x x vcc 0.3v x high z high z high z output disable l h h h x high z high z high z reset x x x l x high z high z high z sector address, sector protect (1) l h l v id fa 6 = l, fa 1 = h, fd in xx fa 0 = l sector address, sector unprotect (1) l h l v id fa 6 = h, fa 1 = h, fd in xx fa 0 = l temporary sector unprotect x x x v id a in fd in fd in high z
17 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx standby mode when the system is not reading or writing to the device, it can place the device in standby mode. in this mode, current consump- tion is greatly reduced, and the outputs are placed in the high impedance state, independent of the foe input. the device enters the cmos standby mode when the fcs1-2 and rst pins are held at vcc 0.3v. (note that this is a more restricted voltage range than v ih .) if fcs1-2 and rst are held at v ih , but not within vcc 0.3v the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. in the flash dc characteristics table, i fcc3 and i fcc4 represent the standby current specifications. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the fcs1-2, fwe, and foe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. if cc 5 in the dc characteristics table represents the automatic sleep mode current specification. rst: hardware reset pin the rst pin provides a hardware method of resetting the device to reading array data. when the rst pin is driven low for at least a period of t rp or greater the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the rst pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the rst pulse. when rst is held at vss 0.3v, the device draws cmos standby current (i fcc4 ). if rst is held at v il but not within vss 0.3v, the standby current will be greater. the rst pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if rst is asserted during a program or erase operation, ry/by1 pin remains 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by1-2 to determine whether the reset operation is complete. if rst is asserted when a program or erase operation is not executing (ry/by1-2 pins are 1), the reset operation is completed within a time of t ready (not during embed- ded algorithms). the system can read data t rh after the rst pin returns to v ih . refer to the flash ac characteristics and hardware reset tables for rst parameters and to figure 19 for the timing diagram. table 5 - bottom boot block sector address table sector size (x8) address range sector a 18 a 17 a 16 a 15 a 14 a 13 a 12 (kbytes) (in hexidecimal) sa 0 0 0 0 0 0 0 x 16 00000h-03fffh sa 1 0 0 0 0 0 1 0 8 04000h-05fffh sa 2 0 0 0 0 0 1 1 8 06000h-07fffh sa 3 0 0 0 0 1 x x 32 08000h-0ffffh sa 4 0 0 0 1 x x x 64 10000h-1ffffh sa 5 0 0 1 0 x x x 64 20000h-2ffffh sa 6 0 0 1 1 x x x 64 30000h-3ffffh sa 7 0 1 0 0 x x x 64 40000h-4ffffh sa 8 0 1 0 1 x x x 64 50000h-5ffffh sa 9 0 1 1 0 x x x 64 60000h-6ffffh sa 10 0 1 1 1 x x x 64 70000h-7ffffh sa 11 1 0 0 0 x x x 64 80000h-8ffffh sa 12 1 0 0 1 x x x 64 90000h-9ffffh sa 13 1 0 1 0 x x x 64 a0000h-affffh sa 14 1 0 1 1 x x x 64 b0000h-bffffh sa 15 1 1 0 0 x x x 64 c0000h-cffffh sa 16 1 1 0 1 x x x 64 d0000h-dffffh sa 17 1 1 1 0 x x x 64 e0000h-effffh sa 18 1 1 1 1 x x x 64 f0000h-fffffh
18 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx autoselect mode the autoselect mode provides sector protection verification, through identifier codes input codes output on fd 7-0 . this mode is prima- rily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode re- quires v id (11.5v to 12.5v) on address pin fa 9 . address pins fa 6 , fa 1 , and fa 0 must be as shown in table 6. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 5). table 6 shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equip- ment may then read the corresponding identifier code on fd 7-0 or fd 23-16 . to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 7. this method does not require v id . see com- mand definitions for details on using the autoselect mode. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previ- ously protected sectors. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. this operation requires v id on the rst pin only, and can be implemented either in-system or via programming equipment. the timing diagram is shown in figure 18. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unpro- tected sectors must first be protected prior to the first sector unprotect write cycle. table 6 - autoselect codes (high voltage method) description fcs1-2 foe fwe fa 18 - 12 fa 11 - 10 fa 9 fa 8 - 7 fa 6 fa 5 - 2 fa 1 fa 0 fd 7 - 0 fd 23-16 sector protection llhsa xv id xlxh l verificaton l = logic low = v il , h = logic high = v ih , sa = sector address, x = don't care 01h (protected) 00h (unprotected) temporary sector unprotect this feature allows temporary unprotection of previously pro- tected sector groups to change data-in system. the sector unprotect mode is activated by setting the rst pin to v id . during this mode, formerly protected sector can be programmed or erased by select- ing the sector addresses. once v id is removed from the rst pin, all the previously protected sector groups will be protected again. figure 16 shows the algorithm and the timing diagram is shown in figure 17, for this feature. hardware data protection the command sequence requirement of unlock cycles for pro- gramming or erasing provides data protection against inadvertent writes (refer to table 7 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during vcc power-up and power- down transitions, or from system noise. low vcc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse "glitch" protection noise pulses of less than 5ns (typical) on foe, fcs1-2 or fwe do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of foe = v il , fcs1-2 = v ih or fwe = v ih . to initiate a write cycle, fcs1-2 and fwe must be a logical zero while foe is a logical one. power-up write inhibit if fwe = fcs1-2 = v il and foe = v ih during power up, the device does not accept commands on the rising edge of fwe. the internal state machine is automatically reset to reading array data on power-up. 01h (protected) 00h (unprotected)
19 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx flash command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 7 defines the valid register command sequences. writing incorrect ad- dress and data values or writing them in improper se- quence will reset the device to the read array data . all addresses are latched on falling edge of fwe or fcs1-2, whichever occurs later. all data is latched on the rising edge of fwe or fcs1-2, whichever occurs first. refer to the appropriate timing diagrams in the flash ac characteristics section. read array data upon initial device power-up the device defaults to read array data. no commands are required to retrieve data. the device is also ready to read array data after it has completed an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspend sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume com- mands for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if fd 5 goes high, or while in the autoselect mode. see the reset command section, next. see also requirements for reading array data on the bus operations section for more information. the data sheet read operations table provides the read parameters, and the read operations timing diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this com- mand. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is com- plete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend mode). if fd 5 or fd 21 , respectively goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in fast total programming time. table 7 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don't care for both cycles. the device then returns to reading array data. figure 5 illustrates the algorithm for the program operation. see the erase/program operations table in the flash ac characteristics for parameters, and to figure 12 for timing diagrams. autoselect command sequence the autoselect command sequence allows the host system to determine whether or not a sector is protected. table 7 shows the address and data requirements. this method is an alternative to that shown in table 6, which is intended for prom programmers and requires v id on address bit fa 9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 02h in that sector is protected, or 00h if it is unprotected. refer to table 5 for valid sector addresses. the system must write the reset command to exit autoselect mode and return to reading array data.
20 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx word/byte program command sequence the system may program the devices by word or byte, depending on the state of the byte1-2 pins. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timing. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 7 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using fd 7 , fd 6 , or ry/by1and fd 23 , 22 or ry/by2 respectively. see write operation status for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the program command sequences should be reinitiated once the device has reset to reading array data, to ensure date integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set fd 5 and fd 21 respectively to 1, or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. chip erase command sequence chip erase is six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a setup command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 7 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be re-initiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using fd 7 , fd 6 , or fd 2 , or ry/by1 and fd 23 , fd 22 , fd 18 or ry/by2, respectively. see write operation status for information on fig. 5 program operation start write program command sequence data poll from system programming completed no increment address last address ? no verify data? yes yes embedded program algorithm in progress note: see table 7 for program command sequence.
21 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 6 illustrates the algorithm for the erase operation. see the erase/program operations tables in flash ac characteristics for parameters, and to figure 12 for timings diagram. sector erase command sequence sector erase is six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a setup command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command, which in turn invokes the embedded erase algorithm. table 7 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 m s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 m s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts can be re- enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 m s, the system need not monitor fd 3 and fd 19 , respectively. any command other than the sector erase or erase suspend during the time-out period resets the device to reading array data . the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor fd 3 and fd 19 , respectively to determine if the sector erase timer has timed out. see the fd 3 /fd 19 : sector erase timer section. the time-out begins from the rising edge of the final fwe pulse in command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using fd 7 , fd 6 , or fd 2 , or ry/by1 and fd 23 , fd 22 , fd 18 , or ry/by2. see write operation status for information on these status bits. fig. 6 erase operation start write erase command sequence data poll from system erasure completed no data = ffh ? yes embedded erase algorithm in progress 1. see table 5 for erase command sequence. 2. see "fd 3 : sector erase timer" for more information.
22 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx figure 6 illustrates the algorithm for the erase operation. see the erase/program operations tables in the flash ac characteristics for parameters, and to figure 12 for timings diagram. erase suspend/erase resume command sequence the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 m s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are don't cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 m s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on fd 7-0 and fd 23-16 respectively. the system can use fd 7 , or fd 6 , and fd 2 and fd 23 or fd 22 and fd 18 together respectively, to determine if a sector is actively erasing or is erase suspended. see "write operation status" for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the fd 7 or fd 6 status bits and fd 23 or fd 22 status bits respectively, just as in the standard program operation. see the write operation status for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. the system must write the erase resume command (address bits are don't care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing.
23 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the fwe or fcs1-2 pulses, wh ichever occurs first. pd = data to be programmed at location pa. data is latched on the rising edge of fwe or fcs1-2 pulses, whichever occurs first. sa = address of the sector to be erased. the combination of fa 18 - 12 will uniquely select any sector. notes: 1. bus operations are defined in table 3. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits fa 18 - 11 = dont care for unlock and command cycles, unless pa or sa is required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if fd 5 and fd 21 , respectively goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. 9. the unlock bypass command is required prior to the unlock bypass program command. 10.the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11.the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation. 12.the erase resume command is valid only during the erase suspend mode. 13.data bits fd 8-15 and fd 24-31, respectively are dont cares for unlock and command cycles. 14.the command definitions refer to each flash device individually. table 7 - command definitions (14) bus cycles (notes 2, 3, 4, 13) first bus second bus third bus fourth bus fifth bus sixth bus cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 byte 4 aaa aa 555 55 aaa 90 x02 5b word 555 2aa 555 x01 225b byte 4 aaa aa 555 55 aaa 90 (sa) xx00 x04 01 word 555 2aa 555 (sa) xx00 x02 xx01 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 word 555 2aa 555 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note10)2 xxx 90 pa 00 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa 555 sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 word 555 2aa 555 555 2aa erase suspended (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 bus write cycles req'd command sequence (note 1) device id, bottom boot block sector protect verify (note 7,8) autoselect
24 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx write operation status the device provides several bits to determine the status of a write operation: fd 2 , fd 3 , fd 5 , fd 6 , and fd 7; fd 18 , fd 19 , fd 21 , fd 22 and fd 23 respectively. table 8 and the following subsections describe the functions of these bits. fd 7, ry/by1, and fd 6 ; fd23, ry/by2, and fd22 respectively each offer a method for determining whether a program or erase operation is complete or in progress. these bits are discussed first. fd 7/ fd 23 : data polling the data polling bit, fd 7 /fd 23 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend data polling valid after the rising edge of the final fwe pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on fd 7/ fd 23 the complement of the datum programmed to fd 7/ fd 23 . this fd 7/ fd 23 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to fd 7/ fd 23 . the system must provide the program address to read valid status information on fd 7/ fd 23 . if a program address falls within a protected sector, data polling on fd / fd 237 is active for approximately 1 m s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a 0 on fd 7/ fd 23 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a 1 on fd 7/ fd 23 . this analogous to the complement/ true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status information on fd 7/ fd 23 . after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on fd 7/ fd 23 is active for approximately 100 m s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects fd 7/ fd 23 has changed from the complement to true data, it can read valid data at fd 7-0 and fd 23-16 respectively on the following read cycles. this because fd 7/ fd 23 may change asynchronously with fd 0-6 and fd 16-22 respectively while flash output enable (foe) is asserted low. figure 14, data polling timings (during embedded algorithms), in the flash ac characteristics section illustrates this. table 8 shows the outputs for data polling on fd 7 /fd 23 . figure 7 shows the data polling algorithm. fig.7 data polling algorithm 1. fd 7 /fd 23 should be rechecked even if fd 5 /fd 21 = 1 because fd 7 /fd 23 may change simultaneously with fd 5 /fd 21 respectively. start read byte (fd0-7/fd16-23) addr = va read byte (fd0-7-fd16-23) addr = va fail fd7/fd23 = data ? fd5/fd21 = 1 ? fd7/fd23 = data ? no yes yes yes no pass no va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any non-protected sector group address during chip erase
25 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx ry/by1-2: ready/busy the ry/by1-2 is a dedicated, open drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by1-2 status is valid after the rising edge of the final fwe pulse in the command sequence. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode.), or is in the standby mode. table 8 shows the outputs for ry/by1-2. figures 11, 12, 13, 19 show ry/by1-2 for read, program, erase and reset operations, respectively. fd6/fd22: toggle bit i toggle bit i on fd 6 /fd 22 indicates whether an embedded program or erase algorithm is in progress or has been completed, or whether the device has entered the erase suspend mode. toggle bit i may read at any address, and is valid after the rising edge of the final fwe pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address will result in fd 6 /fd 22 toggling. (the system may use either foe or fcs1-2 to control the read cycles.) when operation is complete, fd 6 /fd 22 stop toggling. after the erase command sequence is written, if all sectors selected for erasing are protected, fd 6 /fd 22 toggles for approximately 100 m s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use fd 6 /fd 22 and fd 2/ fd 18 respectively , together to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress) fd 6 /fd 22 toggles. when the device enters the erase suspend mode, fd 6 /fd 22 stops toggling. however, the system must also use fd 2 /fd 18 to determine which sectors are erasing or erase-suspended. alternatively, the system can use fd 7 /fd 23 (see the subsection on fd 7 /fd 23 : data polling). if a program address falls within a protected sector, fd 6 /fd 22 also toggles for approximately 1 m s after the program command sequence is written, then returns to reading array data. fd 6 /fd 22 also toggles during erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 8 shows the outputs for toggle bit i on fd 6 /fd 22 . figure 9 shows the toggle bit algorithm. figure 20 shows the toggle bit timing diagrams. figure 19 shows the difference between fd 2 / fd 18 and fd 6 /fd 22 in graphical form. see also the subsection on fd 2 /fd 18 : toggle bit ii. fd 2 : toggle bit ii the toggle bit ii on fd 2 /fd 18 , when used with fd 6 /fd 22 , indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress) or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final fwe pulse in the command sequence. fd 2 /fd 18 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either foe or fcs 1-2 to control the read cycles.) fd 2 /fd 18 cannot distinguish whether the sector is actively erasing or is erase-suspended. fd 6 /fd 22 , by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 8 to compare outputs for fd 2 /fd 18 and fd 6 /fd 22 . figure 8 shows the toggle bit algorithm in flowchart form, and the section fd 2 /fd 18 : toggle bit ii explains the algorithm. see also the subsection on fd 6 /fd 22 : toggle bit i. figure 20 shows the toggle bit timing diagrams. figure 19 shows the difference between fd 2 /fd 18 and fd 6 /fd 22 in graphical form. reading toggle bits fd 6,22 /fd 2,18 refer to figure 8 for the following discussion. whenever the system initially begins reading toggle bit status, it must read fd 7- fd 0, and fd 23 -fd 16 respectively, at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on fd 7-0, and fd 23 -fd 16 respectively, on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of fd 5 /fd 21 is high (see the section on fd 5 / fd 21 ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and fd 5 /fd 21 has not gone high. the system may continue to monitor the toggle bit and fd 5 /fd 21 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 8).
26 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fd 5 /fd 21 : exceeded timing limits fd 5 /fd 21 will indicate whether the program or erase time has exceeded the specified limits (internal pulse count). under these conditions fd 5 /fd 21 will produce a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. the fd 5 /fd 21 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded timing limits, the fd 5 /fd 21 bit will produce a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. fd 3 /fd 19 : sector erase timer after writing a sector erase command sequence, the system may read fd 3 /fd 19 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is completed, fd 3 /fd 19 switches from 0 to 1. the system may ignore fd 3 /fd 19 if the system can guarantee that the time between additional sector erase commands will always be less than 50 m s. see also the sector command sequence section. after the sector erase command sequence is written, the system should read the status on fd 7 /fd 23 (data polling) or fd 6 /fd 22 (toggle bit i) to ensure the device has accepted the command sequence, and then read fd 3 /fd 19 . if fd 3 /fd 19 is high (1) the internally controlled erase cycle has begun; all further commands (other than erase suspend) will be ignored until the erase operation is completed. if fd 3 /fd 19 is low (0), the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of fd 3 /fd 19 prior to and following each subsequent sector erase command. if fd 3 /fd 19 is high on the second status check, the last command may not have been accepted. table 8 shows the outputs for fd 3 /fd 19 . fig. 8 toggle bit algorithm 1. read toggle bit twice to detemine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as fd 5 /fd 21 changes to 1. see text. start read byte (fd0-fd7, fd16-fd23) read byte (fd0-fd7, fd16-fd23) (1) read byte (fd0-fd7, fd16-fd23) (1,2) twice program/erase operaton not complete, write reset command toggle bit = toggle? fd5/fd21= 1 ? toggle bit = toggle? no yes yes yes no program/erase operaton complete no
27 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx notes: 1. fd 5 /fd 21 switches to "1" when an embedded program or embedded erase operation has exceeded the maximum timing limits. see "fd 5 /fd 21 : exceed timing limits" for more information. 2. fd 7 /fd 23 and fd 2 /fd 18 require valid address when reading status information. refer to the appropriate subsection for further details. table 8 - write operation status status fd 7 /fd 23 (2) fd 6 /fd 22 fd 5 /fd 21 (1) fd 3 /fd 19 fd 2 /fd 18 (2) ry/by1-2 embedded program algorithm fd 7 toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspended program fd 7 toggle 0 n/a n/a 0 standard mode erase suspend mode flash ac characteristics C write/erase/program operations,cs controlled (v cc = 3.3v, v ss = 0v, t a = -55 c to +125 c) parameter symbol -100 -120 -150 unit min max min max min max write cycle time t avav t wc 100 120 150 ns write enable setup time t wlel t ws 000 ns chip select pulse width t eleh t cp 45 50 50 ns address setup time t avel t as 000 ns data setup time t dveh t ds 45 50 50 ns data hold time t ehdx t dh 000 ns address hold time t elax t ah 45 50 50 ns chip select pulse width high t ehel t cph 20 20 20 ns duration of byte programming operation (1) t whwh1 300 300 300 m s sector erase time t whwh2 15 15 15 sec read recovery time (2) t ghel 000 m s chip programming time 50 50 50 sec 1. typical value for t whwh1 is 9 m s. 2. guaranteed by design, but not tested.
28 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx flash ac characteristics C write/erase/program operations - we controlled (v cc = 3.3v, t a = -55 c to +125 c) parameter symbol -100 -120 -150 unit min max min max min max write cycle time t avav t wc 100 120 150 ns chip select setup time t elwl t cs 000ns write enable pulse width t wlwh t wp 50 50 65 ns address setup time t avwl t as 000ns data setup time t dvwh t ds 50 50 65 ns data hold time t whdx t dh 000ns address hold time t wlax t ah 50 50 65 ns write enable pulse width high t whwl t wph 30 30 35 ns duration of byte programming operation (1) t whwh1 300 300 300 m s sector erase t whwh2 15 15 15 sec read recovery time before write (3) t gh w l 000 m s v cc setup time t vcs 50 50 50 m s chip programming time 50 50 50 sec output enable setup time t oes 000ns output enable hold time (2) t oeh 10 10 10 ns 1. typical value for t whwh1 is 9 m s. 2. for toggle and data polling. 3. guaranteed by design, but not tested. flash ac characteristics C read-only operations (v cc = 3.3v, t a = -55 c to +125 c) parameter symbol -100 -120 -150 unit min max min max min max read cycle time t avav t rc 100 120 150 ns address access time t avqv t acc 100 120 150 ns chip select access time t elqv t ce 100 120 150 ns output enable to output valid t glqv t oe 40 50 55 ns chip select high to output high z (1) t ehqz t df 30 30 40 ns output enable high to output high z (1) t ghqz t df 30 30 40 ns output hold from addresses, fcs or foe change, t axqx t oh 000ns whichever is first 1. guaranteed by design, not tested. fig. 9 ac test circuit ac test conditions notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. parameter typ unit input pulse levels v il = 0, v ih = 2.5 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh
29 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 10 flash ac waveforms for read operations addresses fcs1/fcs2 fdx fdx foe fwe outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df
30 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. fd 7 /fd 23 is the output of the complement of the data written to each chip. 4. fd out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. fig. 11 flash write/erase/program operation, fwe controlled addresses fcs1/fcs2 fax fdx foe fwe data aaah pa pa t wc t cs pd fd 7/ fd 23 fd out t ah t wph t dh t ds data polling t as t rc t wp a0h t oe t df t oh t ghwl ry/by1-2 t busy t ghwl t whwh1
31 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 12 flash ac waveforms chip/sector erase operations note: 1. sa is the sector address for sector erase. addresses fcs1/fcs2 fax fax foe fwe data v cc aaah 555h 555h sa aaah aaah t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t ghwl t wph t dh t ds t as
32 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 13 flash ac waveforms for data polling during embedded algorithm operations addresses fcs1/fcs2 fax fdx foe fwe data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t ghwl t wph t dh t ds t as
33 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx notes: 1. fpa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. fd 7 /fd 23 is the output of the complement of the data written to each chip. 4. fd out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. addresses fwe fax fdx foe fcs1/fcs2 data aaah pa pa t wc t ws pd fd 7 / fd 23 d out t ah t cph t cp t dh t ds data polling t as t ghel a0h t whwh1 fig. 14 flash alternate fcs1/fcs2 controlled programming operation timings
34 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 15 temporary sector unprotect operation start rst = v id (note 1) perform erase or program operations temporary sector unprotect complete (note 2) rst = v ih 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. parameter description all speed options unit t vidr vid rise and fall time (see note) min 500 ns t rsp rst setup time for temporary sector min 4 m s unprotect fig. 16 temporary sector unprotect timing diagram fcs1/fcs2 t rsp fwe t vidr program or erase command sequence t vidr rst 0or3v 12v
35 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 17 ac characteristics sector protect/unprotect timing diagram rst sa, fa6 fa1, fa0 data fcs1/fcs2 fwe foe 1s sector protect: 150 s sector unprotect: 15 ms valid* valid* valid* valid* sector protect/unprotect 60h 60h 40h status verify v id v ih *for sector protect, fa6 = 0, fa1 = 1, fa0 = 0. for sector unptotect, fa6 = 1, fa1 - 1, fa0 = 0
36 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx ry/by1-2 fcs1/fcs2, foe rst ry/by1-2 fcs1/fcs2, foe rst reset timings not during embedded algorithms reset timings during embedded algorithms t rp t ready t rh t ready t rb t rp fig. 18 hardware reset (rst) parameter description test setup all speed options unit t ready rst pin low (during embedded algorithms) to read or write (see note) max 20 m s t ready rst pin low ( not during embedded algorithms) to read or write (see note) max 500 ns t rp rst pulse width min 500 ns t rh rst high time before read (see note) min 50 ns t rpd rst low to standby mode min 20 m s t rb ry/by1-2 recovery time min 0 ns note: not 100% tested.
37 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 19 ac characteristics fd2/fd18 vs. fd6/fd22 enter embedded erasing erase suspend erase enter erase suspend program erase suspend read erase suspend program erase suspend read erase resume erase erase complete fwe fd6/fd22 fd2/fd18 note: the system may use fcs1/fcs2 or foe to toggle fd2/fd18 and fd6/fd22. fd2/fd18 toggles only when read at an address within an erase-suspended sector.
38 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx fig. 20 toggle bit timings (during embedded algorithms) addresses fce foe fwe fd6/fd2 ry/by1-2 t rc t rcc t ce t ch t oe t oeh t df t oh t busy high z va va va valid status valid status valid status valid data (first read) (second read) (stops toggling) va note: va = valid address; not required for fd6. illustration shows first two status cycle after command sequence, last status r ead cycle, and array data read cycle.
39 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx package 743: 275 plastic ball grid array (pbga) all linear dimensions are millimeters and parenthetically in inches 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t r p n m l k j h g f e d c b a 1.27 (0.050) bsc 1.27/2 32.32 (1.272) max 25.25 (0.994) max 2.54 (1.00) max 0.60 (0.024) 0.10 (0.004) 255 x ? 0.835 1.27/2 21.59 (0.850) nom 21.59 (0.850) nom u v bottom view
40 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx
41 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wedpnf8m722v-xbx wed p n f 8m 72 2 v - xxxx b x ordering information device grade: m = military -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c package: b = 275 plastic ball grid array (pbga) frequency (mhz) 1010 = 100mhz sdram / 100ns flash 1012 = 100mhz sdram / 120ns flash 1015 = 100mhz sdram / 150ns flash 1210 = 125mhz sdram / 100ns flash 1212 = 125mhz sdram / 120ns flash 1215 = 125mhz sdram / 150ns flash 3.3v power supply flash configuration, 2m x 8, 1m x 16 or 512k x 32 (2mb) sdram configuration, 8m x 72 (64mb) flash sdram plastic mcp (multichip package) white electronic designs corp.

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