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? 2010-2013 microchip technology inc. ds20002266e-page 1 mcp79410/MCP79411/mcp79412 device selection table timekeeping features: ? real-time clock/calendar (rtcc): - hours, minutes, seconds, day of week, day, month, year - leap year compensated to 2099 - 12/24 hour modes ? oscillator for 32,768 khz crystals: - optimized for 6-9 pf crystals ? on-chip digital trimming/calibration: - 1 ppm resolution - +/- 129 ppm ? dual programmable alarms ? multifunction output pin: - clock out with selectable frequency - alarm output - programmable operation ? power-fail time-stamp: - time logged on power-up/down low-power features: ? wide operating voltage: -v cc : 1.8v to 5.5v -v bat : 1.3v to 5.5v ? low typical operating current: -v cc standby: 5 a -v bat standby: 700 na ? automatic battery switchover user memory: ? 64-byte battery-backed sram ? 1 kbit eeprom memory: - software write-protect - page write up to 8 bytes - endurance: 1m erase/write cycles ? 64-bit protected eeprom memory area: - robust write unlock sequence -eui-48 ? mac address -eui-64 ? mac address -custom specified operating ranges: ? 2-wire serial interface, i 2 c? compatible -i 2 c clock rate up to 400 khz ? temperature range: - industrial (i): -40c to +85c packages: ? 8-lead soic, msop, tssop and 2x3 tdfn general description: the mcp7941x real-time clock/calendar (rtcc) tracks time using internal counters for hours, minutes, seconds, days, months, years and day of week. alarms can be configured on all counters up to and including months. for usage and configuration, the mcp7941x supports i 2 c communications up to 400 khz. the open collector, multifunctional output can be configured to assert on an alarm match, on modification of an internal register or to output a selectable frequency square wave. the mcp7941x is designed to operate using a 32,768 khz tuning fork crystal with external crystal load capacitors. on-chip digital trimming can be used to adjust for frequency variance caused by crystal tolerance and temperature. sram and timekeeping circuitry are powered from the back-up supply allowing the device to maintain accurate time and the sram contents when the main supply is unavailable. the time when the device switches over to the back-up supply and returns to main power is logged by the power-fail time-stamp. the mcp7941x features 1 kbit of internal nonvolatile eeprom with software write-protectable regions. there is an additional 64 bits of nonvolatile memory, referred to as the unique id space, which is only writable after an unlock sequence. the mcp7941x device is available with the unique id space pre- programmed with eui-48 or eui-64 unique mac id?s or unprogrammed. package types part number unique id mcp79410 unprogrammed MCP79411 eui-48 ? mcp79412 eui-64 ? soic, tssop, msop x1 x2 v bat v ss 1 2 3 4 8 7 6 5 v cc mfp scl sda tdfn x1 x2 v bat v ss mfp scl sda v cc 8 7 6 5 1 2 3 4 battery-backed i 2 c? real-time clock/calendar with eeprom and unique id
mcp79410/MCP79411/mcp79412 ds20002266e-page 2 ? 2010-2013 microchip technology inc. figure 1-1: schematic figure 1-2: block diagram v cc v cc v cc .1f scl sda mfp x1 x2 v bat mcp7941x mcu 2k 2k 10k 1 2 3 4 8 6 5 7 32.768 khz c x1 c x2 100pf 1k diode oscillator x1 x2 v bat control and switchover vcc v bat i 2 c? interface and addressing scl sda rtcc divider frequency out alarms sram mfp eeprom+id seconds minutes hours day date rtcc control logic month year control registers calibration mfp logic
? 2010-2013 microchip technology inc. ds20002266e-page 3 mcp79410/MCP79411/mcp79412 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v maximum voltage on sda and scl................................................................................................. ..........................6.5v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied......................................................................................... .......-40c to +125c esd protection on all pins ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ????????????????????????? 4 kv ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp79410/MCP79411/mcp79412 ds20002266e-page 4 ? 2010-2013 microchip technology inc. table 1-1: dc characteristics dc characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c param. no. sym. characteristic min. typ. max. units conditions ? scl, sda pins ???? d1 v ih high-level input voltage 0.7 v cc ?v? d2 v il low-level input voltage ? 0.3 v cc 0.2 v cc vv cc = 2.5v to 5.5v d3 v hys hysteresis of schmitt trigger inputs (sda, scl pins) 0.05 v cc ?v ( note 1 ) d4 v ol low-level output voltage (mfp, sda) ?0.40vi ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v d5 i li input leakage current ? 1 ? av in = v ss or v cc d6 i lo output leakage current ? 1 ? av out = v ss or v cc d7 c in , c out pin capacitance (sda, scl and mfp) ?10pfv cc = 5.0v ( note 1 ) t a = 25c, f = 400 khz d8 i cc read operating current eeprom ? 400 ? av cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v d9 i cc read operating current sram ? 300 ? av cc = 5.5v, scl = 400 khz i cc write ? 400 ? av cc = 5.5v, scl = 400 khz d10 i ccs standby current ? 1 ? av cc = 5.5v, scl = sda = v cc ( note 3 ) iv cc ?5? ? av cc = 3.6v @ 25c, figure 2-2 ( note 2 ) d11 v trip v bat change over 1.3 1.5 1.7 v typical at t amb = 25c d12 v bat v bat voltage range 1.3 5.5 v ( note 1 ) d13 i bat operating current, figure 2-1 ? ? ? 700 1150 1800 5300 na v bat = 1.8v @ 25c, ( note 2 ) v bat = 3.0v @ 25c, ( note 2 ) v bat = 5.0v @ 25c, ( note 2 ) d14 c osc oscillator pin capacitance ?3?pf ( note 1 ) note 1: this parameter is periodically sampled and not 100% tested. 2: standby with oscillator running. 3: standby with oscillator not running.
? 2010-2013 microchip technology inc. ds20002266e-page 5 mcp79410/MCP79411/mcp79412 table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c param. no. symbol characteristic min. max. units conditions 1f clk clock frequency ? ? 100 400 khz 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 2t high clock high time 4000 600 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 3t low clock low time 4700 1300 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 4t r sda and scl rise time ( note 1 ) ? ? 1000 300 ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 5t f sda and scl fall time ( note 1 ) ? ? 1000 300 ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 6t hd : sta start condition hold time 4000 600 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 7t su : sta start condition setup time 4700 600 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 8t hd : dat data input hold time 0 ? ns ( note 4 ) 9t su : dat data input setup time 250 100 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 10 t su : sto stop condition setup time 4000 600 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 11 t aa output valid from clock ? ? 3500 900 ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 12 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 ? ? ns 1.8v ? v cc < 2.5v 2.5v ? v cc ? 5.5v 13 t sp input filter spike suppression (sda and scl pins) ?50ns ( note 1 and note 2 ) 14 t wc write cycle time (byte or page) ?5ms? 15 ? endurance 1m ? cycles 25c, v cc = 5.5v page mode ( note 3 ) 16 t osf oscon time out 1 ms ( note 5 ) 17 t fvcc v cc fall time 300 ? sfrom v trip (max) to v trip (min) ( note 1 ) 18 t rvcc v cc rise time 0 ? sfrom v trip (min) to v trip (max) ( note 1 ) 19 f xtal crystal frequency 32.768 khz note 1: not 100% tested. 2: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. 3: this parameter is not tested but ensured by characterization. 4: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of the scl to avoid unintended generation of start or stop conditions. 5: parameter is not tested, ensured by characterization.
mcp79410/MCP79411/mcp79412 ds20002266e-page 6 ? 2010-2013 microchip technology inc. figure 1-3: i 2 c bus timing data scl sda in sda out 5 7 6 13 3 2 89 11 d4 4 10 12
? 2010-2013 microchip technology inc. ds20002266e-page 7 mcp79410/MCP79411/mcp79412 2.0 dc and ac characteristics graphs and charts figure 2-1: typical i bat v s . v bat across temperature figure 2-2: typical iv cc v s . v cc @ 25c 500 1000 1500 2000 2500 3000 3500 4000 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 -40c 0c 25c 65c 85c vbat (v) ibat (na) 0 2 4 6 8 10 12 14 16 1.522.533.544.555.5 i d d ( a ) vcc (v) idd (a)
mcp79410/MCP79411/mcp79412 ds20002266e-page 8 ? 2010-2013 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin descriptions figure 3-1: device pinouts 3.1 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open-drain terminal, therefore, the sda bus requires a pull-up resistor to v cc (typically 10 k ? for 100 khz, 2 k ?? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 3.2 serial clock (scl) this input is used to synchronize the data transfer from and to the device. 3.3 x1, x2 external crystal pins for 32.768 khz crystal and load capacitors. x1 = oscillator input, also external oscillator input x2 = oscillator output 3.4 mfp (multifunction pin) open drain pin used for alarm and clock-out, addition- ally the state of this pin may be changed using the out bit. this pin is also controlled by the oscillator bit. see section 8.5 ?multifunction pin (mfp)? for more details. this pin may be left floating if not used. 3.5 v bat input for backup supply to maintain rtcc and sram during the time when v cc is below v trip . see section 8.6 ?battery backed operation? for more details. pin name pin function pin number x1 xtal input, external oscillator input 1 x2 xtal output 2 v bat battery backup input 3 vss ground 4 sda bidirectional serial data (i 2 c?) 5 scl serial clock (i 2 c) 6 mfp multifunction pin 7 vcc power supply 8 note: exposed pad on tfdn can be connected to vss or left floating. x1 x2 v bat vss vcc mfp scl sda 1 2 3 4 8 7 6 5 soic/tdfn/msop/tssop
? 2010-2013 microchip technology inc. ds20002266e-page 9 mcp79410/MCP79411/mcp79412 4.0 rtcc functionality the mcp7941x family is a highly integrated rtcc. on- board time and date counters are driven from a low-power oscillator to maintain the time and date. an integrated v cc switch enables the device to maintain the time and date, and also the contents of the sram during a v cc power failure if an external supply is connected to the v bat pin and configured. 4.1 crystal oscillator the crystal oscillator built into the mcp7941x has been designed to operate with a standard 32.768 khz tuning fork crystal. the mcp7941x family of devices require both an external crystal and matching external load capacitors. capacitors are not included on-chip. suitable crystals have a load capacitance (c l ) of 6-9 pf. we do not recommend using crystals with a load capacitance (c l ) of 12.5 pf. figure 9.1 shows the required external oscillator com- ponents. c x1 and c x2 pin capacitance and stray capac- itance form the crystal load. this is calculated using the equation below: equation 4-1: cl calculation figure 4-1: oscillator schematic for a list of tested and recommended crystals, please refer to an1519, ?recommended crystals for micro- chip stand-alone real-time clock calendar devices? . this document provides a reference for suitable crystals and recommended load capacitors. for information on suggested board layout, please refer to an1365, ?recommended usage of microchip serial rtcc devices? . it is recommended that the final application should be tested with the chosen crystal and capacitor combina- tions across all operating and environmental condi- tions. please also consult the crystal specification to observe correct handling and reflow conditions during assembly. 4.2 rtcc memory map the rtcc registers are contained in addresses 0x00- 0x1f. 64 bytes of user-accessible sram are located in the address range 0x20-0x5f. the sram memory is a separate block from the rtcc control and configu- ration registers. all sram locations are battery- backed-up during a v cc power fail. unused locations are not accessible, mcp7941x will noack after the address byte if the address is out of range, as shown in the shaded region of the memory map in figure 4-2 . ? addresses 0x00-0x06 are the rtcc time and date registers. ? addresses 0x07-0x09 are the device configura- tion, calibration and id unlock registers. ? addresses 0x0a-0x10 are the alarm 0 registers. these are used to set up the alarm 0, the inter- rupt polarity and the alarm 0 compare. ? addresses 0x11-0x17 are the same as 0x0bh- 0x11h but are used for alarm 1. ? addresses 0x18-0x1f are used for the time- stamp feature. the detailed memory map is shown in table 4-1 . no error checking is provided when loading time and date registers. c l c x2 c x1 ? c x2 c x1 + ------------------------ -c stray + = x1 x2 rtcc c x1 c x2 note: these are read/write registers. care must be taken when writing to these regis- ters with the oscillator running. incorrect data can appear in the time and date reg- isters if a write is attempted during the time frame where these internal registers are being incremented. the user can min- imize the likelihood of data corruption by ensuring that any writes to the time and date registers occur before the contents of the second register reach a value of 0x59.
mcp79410/MCP79411/mcp79412 ds20002266e-page 10 ? 2010-2013 microchip technology inc. figure 4-2: memory map 0x00 0x06 time and date configuration and calibration alarm 0 alarm 1 time-stamp sram (64 bytes) 0x07 0x09 0x0a 0x10 0x11 0x17 0x18 0x1f 0x20 0x5f 0x00 eeprom memory 0xf0 0xf7 0xff rtcc register/sram eeprom unique id location eui-48/64 0x7f status register unimplemented ? device does not ack i 2 c? address: 1101111x i 2 c? address: 1010111x
? 2010-2013 microchip technology inc. ds20002266e-page 11 mcp79410/MCP79411/mcp79412 table 4-1: detailed rtcc memory map addressbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 function section 5.0 ?time and date registers? 00h st 10 seconds seconds seconds 01h 10 minutes minutes minutes 02h 12/24 10 hour am/pm 10 hour hour hours 03h oscon vbat vbaten day day 04h 10 date date date 05h lp 10 month month month 06h 10 year year year 07h out sqwe alm1 alm0 extosc rs2 rs1 rs0 control reg. 08h calibration calibration 09h unique id unlock unlock id section 7.0 ?alarm registers? 0ah 10 seconds seconds seconds 0bh 10 minutes minutes minutes 0ch 12/24 10 hour am/pm 10 hours hour hours 0dh alm0pol alm0c2 alm0c1 alm0c0 alm0if day day 0eh 10 date date date 0fh 10 month month month 10h reserved ? do not use reserved section 7.0 ?alarm registers? 11h 10 seconds seconds seconds 12h 10 minutes minutes minutes 13h 12/24 10 hour am/pm 10 hours hour hours 14h alm1pol alm1c2 alm1c1 alm1c0 alm1if day day 15h 10 date date date 16h 10 month month month 17h reserved ? do not use reserved section 8.6.1 ?power-down time-stamp registers? 18h 10 minutes minutes power-down minutes 19h 12/24 10 hour am/pm 10 hours hour power-down hours 1ah 10 date date power-down date 1bh day 10 month month power-down day/month section 8.6.2 ?power-up time-stamp registers? 1ch 10 minutes minutes power-up minutes 1dh 12/24 10 hour am/pm 10 hours hour power-up hours 1eh 10 date date power-up date 1fh day 10 month month power-up day/ month note: grey areas are unimplemented.
mcp79410/MCP79411/mcp79412 ds20002266e-page 12 ? 2010-2013 microchip technology inc. 5.0 time and date registers the mcp7941x serial real-time clock/calendar uses a low-power external 32.768 khz crystal to maintain the time and date in a system. the real-time clock using an external oscillator tracks the time and date with separate registers for hours, minutes, seconds. the mcp7941x also has separate calendar registers for date, month, year and day of the week. the calendar adjusts automatically for months with less than 31 days and also calculates the leap year until 2099. the time and date registers store the current time and date as bcd. using an external backup supply, the time can be maintained during a v cc power-fail. register 5-1: seconds 0 x 00 r/w-0 r/w-0 r/w-0 st 10 seconds seconds bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 st: start oscillator bit 1 = oscillator enabled 0 = oscillator disabled; the oscillator should be disabled before setting the time registers. bit 6-4 10 seconds <6:4>: binary-coded decimal value of second?s tens digit contains a value from 0 to 5 bit 3-0 seconds<3:0>: binary-coded decimal value of second?s ones digit contains a value from 0 to 9 register 5-2: minutes 0 x 01 u-0 r/w-0 r/w-0 ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: binary-coded decimal value of minute?s tens digit contains a value from 0 to 5 bit 3-0 minutes<3:0>: binary-coded decimal value of minute?s ones digit contains a value from 0 to 9
? 2010-2013 microchip technology inc. ds20002266e-page 13 mcp79410/MCP79411/mcp79412 register 5-3: hour 0 x 02 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 12/24 : 12 or 24 hour time format 0 = 24-hour format 1 = 12-hour format bit 5 10 hour, am/pm 24-hour format. this is the ten?s hour. bits 5:4 contain the binary-coded decimal of the ten?s hour. contains a value 0 to 2 12-hour format. this bit contains the am/pm indicator 0 = pm 1 = am bit 4 10 hour bit 3-0 hour<3:0>: binary-coded decimal value of hour?s ones digit contains a value from 0 to 5
mcp79410/MCP79411/mcp79412 ds20002266e-page 14 ? 2010-2013 microchip technology inc. register 5-4: day 0 x 03 u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 ? ? oscon vbat vbaten day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 oscon: oscillator status bit not used in timekeeping (see section 8.1 ?oscillator failure status? ) bit 4 vbat: power-fail cycle status flag bit not used in timekeeping (see section 8.6.1 ?power-down time-stamp registers? ) bit 3 vbaten: external battery enable bit not used in timekeeping (see section 8.6 ?battery backed operation? ) bit 2-0 day<2:0>: undefined, device does not put any limitations on how the day is represented. binary- coded decimal value of day. contains a value from 1 to 7.
? 2010-2013 microchip technology inc. ds20002266e-page 15 mcp79410/MCP79411/mcp79412 register 5-5: date 0 x 04 u-0 u-0 r/w-0 r/w-1 ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0>: binary-coded decimal value of dates?s tens digit contains a value from 0 to 3 bit 3-0 date<3:0>: binary-coded decimal value of dates?s ones digit contains a value from 0 to 9 register 5-6: month 0 x 05 u-0 u-0 r-0 r/w-0 r/w-1 ? ? lp 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 lp: leap year, set during a leap year and is read-only 1 = year is a leap year 0 = year is not a leap year bit 4 10 month: binary-coded decimal value of month?s tens digit contains a value of 0 or 1 bit 3-0 month<3:0>: binary-coded decimal value of month?s ones digit contains a value from 0 to 9 register 5-7: year 0 x 06 r/w-0 r/w-1 10 year year bit 7 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-4 10 year<3:0>: binary-coded decimal value of year?s tens digit contains a value from 0 to 9 bit 3-0 year<3:0>: binary-coded decimal value of year?s ones digit contains a value from 0 to 9
mcp79410/MCP79411/mcp79412 ds20002266e-page 16 ? 2010-2013 microchip technology inc. 6.0 control register the control register is used to enable additional features of the rtcc, such as alarms and mfp square wave divider. this register also contains bits that can be used to toggle the mfp pin and also allow the rtcc to be driven by an external cmos 32.768 khz clock. . register 6-1: control reg 0 x 07 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 out sqwe alm1 alm0 extosc rs2 rs1 rs0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 out: level of mfp pin bit this bit sets the logic level on the mfp pin when not using this as a square wave output. this pin is open-drain. 1 = pin is not asserted 0 = pin is logic low ? asserted bit 6 sqwe: square wave enable bit setting this bit enables the divided output from the crystal oscillator 1 = enable square wave 0 = disable square wave bit 5 alm1: alarm 1 enable bit 1 = alarm 1 enabled 0 = alarm 1 disabled bit 4 alm0: alarm 0 enable bit 1 = alarm 0 enabled 0 = alarm 0 disabled bit 3 extosc: external oscillator input bit 1 = enable rtcc x1 pin to be driven by external 32.768 khz source 0 = disable external 32.768 khz input. bit 2 rs2: digital trimming/digital calibration mode bit this bit is used to switch between digital trimming and digital calibration mode 1 = enable the digital calibration mode. calibration signal appears on clkout if sqwe is set (64 hz nominal, see section 8.4 ?digital calibration mode? ). 0 = disable the calibration output function, digital trimming is enabled, see section 8.3 ?digital trim- ming? . bit 1-0 rs<1:0>: clkout divider bits sets the internal divider for the 32.768 khz oscillator to be driven to the clkout. the following frequencies are available. the output is responsive to the calibration register, see section 3.4 ?mfp (multifunction pin)? . - 00 ? 1 hz - 01 ? 4.096 khz - 10 ? 8.192 khz - 11 ? 32.768 khz note 1: when rs2 is set to enable the calibration output function, the rtcc counters will continue to increment.
? 2010-2013 microchip technology inc. ds20002266e-page 17 mcp79410/MCP79411/mcp79412 7.0 alarm registers the mcp7941x family feature two independent alarms. the registers associated with the alarms are located at 0ah-16h in the rtcc memory map. the alarms feature independent interrupt flags and interrupt polarity. the alarms interrupt is generated on the mfp pin. the alarm function on the mcp7941xx allows the user to load a time into a series of registers that represent a future time. when the current time reaches that set time, the alarm is activated and an interrupt can be generated. using the alarm feature will allow the system to offload the task to checking for a specific time to the rtcc. the alarms on the mcp7941x are not single-shot trigger, that is, the alarm will retrigger immediately if the current alarm still matches the set conditions. clearing the almxif bit while the alarm match is still true will retrigger the alarm. the alarms offer programmable match conditions: for example, if the alarm is configured to match on the minutes, when the match is true the alarm will retrigger until the match is false. this would be similar to trying to exit an interrupt on an mcu without clearing the interrupt flag. it is suggested that the seconds, minutes, hour, day, date and month match condition. both alarm0 and alarm1 offer identical operation. table 7-1: almxc<2:0> match condition time alarm match true duration 000 seconds only 1 second 001 minutes only 1 minute 010 hours only 1 hour 011 day only 1 day 100 date only 1 day 101 unimplemented na 110 unimplemented na 111 seconds, minutes, hour, day, date and month 1 second note: the x variable used in this section is used to designate alarm 0 or alarm 1. register 7-1: alarm x seconds (0 x 0a/0 x 11) u-0 r/w-0 r/w-0 ? 10 seconds seconds bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 10 seconds<2:0>: binary-coded decimal value of second?s tens digit contains a value from 0 to 5 bit 3-0 seconds<3:0>: binary-coded decimal value of second?s ones digit contains a value from 0 to 9
mcp79410/MCP79411/mcp79412 ds20002266e-page 18 ? 2010-2013 microchip technology inc. register 7-2: alarm x minutes (0 x 0b/0 x 12) u-0 r/w-0 r/w-0 ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: binary-coded decimal value of minute?s tens digit contains a value from 0 to 5 bit 3-0 minutes<3:0>: binary-coded decimal value of minute?s ones digit contains a value from 0 to 9 register 7-3: alarm x hours (0 x 0c/0 x 13) u-0 r/w-0 r/w-0 ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 12/24: this is a copy of bit 6 in the hours register (0x03) bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0>: binary-coded decimal value of hour?s ones digit contains a value from 0 to 9
? 2010-2013 microchip technology inc. ds20002266e-page 19 mcp79410/MCP79411/mcp79412 register 7-4: alarm x day (0 x 0d/0 x 14) r/w-0 r/w-0 r/w-0 r/w-1 almxpol almxc2 almxc1 almxc0 almxif day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 almxpol: the asserted level of the alarm ( 1 = high, 0 = low) bit 6-4 almxc<2:0>: alarm x configuration bits sets the condition on what the alarm will trigger. the following options are available: - 000 ? seconds match - 001 ? minutes match - 010 ? hours match (logic takes into account 12/24 operation) - 011 ? day match. generates interrupt at 12:00:00 am - 100 ? date match - 101 ? unimplemented, do not use - 110 ? unimplemented, do not use - 111 ? seconds, minutes, hour, day, date and month bit 3 almxif: alarm x interrupt flag bit this bit is set by hardware when an alarm condition has been generated. the bit must be cleared in software. 1 = alarm has been triggered 0 = no alarm pending bit 2-0 day<2:0>: binary-coded decimal value of day contains a value from 1 to 7 register 7-5: alarm x date (0 x 0e/0 x 15) u-0 u-0 r/w-0 r/w-1 ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0>: binary-coded decimal value of date?s tens digit contains a value from 0 to 3 bit 3-0 date<3:0>: binary-coded decimal value of date?s ones digit contains a value from 0 to 9
mcp79410/MCP79411/mcp79412 ds20002266e-page 20 ? 2010-2013 microchip technology inc. register 7-6: alarm x month (0 x 0f/0 x 16) u-0 u-0 u-0 r/w-0 r/w-1 ? ? ? 10 month month bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 10 month: binary-coded decimal value of month?s tens digit contains a value of 0 or 1 bit 3-0 month<3:0>: binary-coded decimal value of month?s ones digit contains a value from 0 to 9
? 2010-2013 microchip technology inc. ds20002266e-page 21 mcp79410/MCP79411/mcp79412 8.0 special features 8.1 oscillator failure status the mcp7941x family of devices support an on-board oscillator failure flag. in register 0x03 (day register ? shown below), the oscon (bit 5) provides a way to observe the current status of the oscillator. the state of the bit indicates the oscillator status. 1 = the oscillator is running 0 = the oscillator is not running the status does not indicate that the oscillator is run- ning accurately. the oscon bit is set after 32 stable oscillator cycles. if the oscillator is stopped by either clearing the st bit or the oscillator support components fail, the oscon bit is cleared by the hardware after t osf . this is timed internally using an on-chip time-out circuit. figure 8-1 shows the operation. it should be noted that this bit is both set and cleared by the rtcc hardware, and it will not show that the oscillator failed in the past. the user can poll this bit at any time to determine if the oscillator is running. figure 8-1: oscon diagram oscon bit (register 0x03 bit 5) 32 oscillator cycles t osf crystal oscillator : not used in this section.
mcp79410/MCP79411/mcp79412 ds20002266e-page 22 ? 2010-2013 microchip technology inc. 8.2 unique id the mcp7941x features an additional 64-bit unique id area. this is separate and in addition to the 1k of on- board eeprom. the unique id is located at addresses 0xf0 through 0xf7 using the eeprom i 2 c address. reading the unique id requires the user to simply address these bytes.the unique id is factory programmed on devices to provide a unique ieee eui-48 or eui-64 value. in addition, customer-provided codes can also be programmed. please contact your microchip sales channel for more information on custom programming. the unique id locations are always readable. the format of the unique id is shown in figure 8-2 . this is an example and the oui may change. figure 8-2: eui-48/64 node address physical memory map example the unique id area is protected to prevent unintended writes to these locations. the unlock sequence is detailed in 8.2.1 ?unlock sequence? and consists of the following sequence: ? a single write of 0x55 to rtcc addr. 0x09. stop ? a single write of 0xaa to rtcc addr. 0x09. stop a stop condition must be used to terminate a i 2 c sequence, a restart will not complete the sequence. f2h f7h 24-bit organizationally unique identifier 24-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-48? node address: 00-04-a3-12-34-56 description data array address corresponding eui-64? node address: 00-04-a3-12-34-56-78-9a ffh ffh unused f1h f0h f7h 24-bit organizationally unique identifier 40-bit extension identifier a3h 12h 34h 56h 78h 9ah description data array address 04h 00h f0h f3h f4h f5h f6h
? 2010-2013 microchip technology inc. ds20002266e-page 23 mcp79410/MCP79411/mcp79412 figure 8-3: id unlock flowchart 8.2.1 unlock sequence the i 2 c bus sequence to unlock the unique id locations is show in figure 8-4 . this example shows all eight locations being written, any location may be written individually. write 0x55 to sram 0x09 stop write 0xaa to sram 0x09 stop all data written finish id locked start id locked write data to unique id location yes no
mcp79410/MCP79411/mcp79412 ds20002266e-page 24 ? 2010-2013 microchip technology inc. figure 8-4: unique id unlock sequence bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1101 0 1 11 p 0 bus activity master sda line bus activity s t a r t control byte address byte data byte 0 s t o p a c k a c k a c k data byte 7 a c k s 1010 0 p 1 00 01 001 0 1 0101 01 bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1101 0 1 11 p 000 01001 10101010 1110000 111 register 8-2: unlock id 0 x 09 w-0 unique unlock id sequence bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-0 unlock id: this is the unlock sequence address. to unlock write access to the unique id area in the eeprom, a sequence must be written to this address in separate commands. the process is shown in figure 8-4 .
? 2010-2013 microchip technology inc. ds20002266e-page 25 mcp79410/MCP79411/mcp79412 8.3 digital trimming the mcp7941x uses digital trimming to correct for inaccuracies of the input clock source (either externally driven or from a crystal). these inaccuracies are due to crystal, capacitor and temperature variations. this enables the user to compensate for differences in tem- perature over the operating conditions of the device, offering higher time accuracy over an uncalibrated rtcc. digital trimming is always enabled in the mcp794xx device. digital trimming is achieved by dig- itally modifying the number of clock cycles per minute to achieve ppm level adjustments in the internal timing function of the mcp7941x. the amount by which the mcp794xx adjusts the time is determined by the value loaded into the calibration register. a value of 0x00 in the calibration register results in no time adjustment. the calibration value is maintained during a v cc power-fail if the backup supply is enabled. digital trimming is also performed during this time. the same calibration value is used until it is changed by the system firmware. the msb of the calibration register is the sign bit, with a ? 1 ? indicating a negative ppm calibration and a ? 0 ? indicating a positive ppm calibration. the calibration value can range from 0 to 127, combined with the sign bit this gives the mcp7941x the ability to calibrate 129 ppm of combined error. the calibration is performed on the minute rollover. given that each bit provides 2 internal clocks of trimming, the effective ppm of each bit is 1.017 ppm. the calibration value is determined by measuring the error over a period of time. if the time is running fast then a positive calibration is loaded into the calibration register. conversely, if the time is running slow, a negative calibration is loaded. example: time is running fast five seconds per day. five seconds per day can be expressed in ppm using equation 8-1 . equation 8-1: in this example, the calibration value to be loaded is 57. the same method can be used if the mcp7941x is running slow. register 8-3: calibration 0 x 08 r/w-0 calsign calibration bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 calsign: sign of calibration, allows for positive and negative calibration bit 6-0 calibration<6:0>: calibration value bits note 1: this is an 8-bit register that is used to add or subtract clocks from the rtcc counter every minute. the msb is the sign bit and indicates if the count should be added or subtracted. the remaining 7 bits, with each bit adding or subtracting two clocks, give the user the ability to add or subtract up to 254 clocks per minute. each bit represents 1.017 ppm. ppm seconds per day 1x10 6 ? ?? 24 60 60 ? ? --------------------------------------------------------------------- - = giving 58ppm 5x10 6 ?? 86400 ?? ------------------- = 57 58 ppm 1.017 ppm -------------------------- = calibration register value
mcp79410/MCP79411/mcp79412 ds20002266e-page 26 ? 2010-2013 microchip technology inc. 8.4 digital calibration mode the mcp7941x utilizes digital trimming to correct for inaccuracies of the input clock source. however, as this internal trimming is performed on the minute rollover, a digital calibration mode is available. using this mode the oscillator frequency can be directly observable. the internal timing function can be monitored using the mfp open-drain output pin by setting bit<6:0> (sqwe) and bits<2:0> (rs2, rs1, rs0) of the control register (see section 6.0, control register ). note that the mfp output waveform is disabled when the mcp7941x is running in v bat mode. with the sqwe bit set to ? 1 ?, and the rs2 bit set to ? 1 ? the digital calibration mode is enabled. unlike digital trimming previously described, the calibration setting is continuously applied and affects every cycle of the output waveform. this results in the modulation of the frequency of the output waveform based upon the setting of the calibration register. using this setting, the calibration function can be expressed as: since the calibration is done every cycle, the frequency of the output mfp waveform is constant. with a crystal frequency of exactly 32.768 khz the output on the mfp pin will be 64 hz. deviation of the crystal frequency will shift this frequency. 8.5 multifunction pin (mfp) pin 7 is a multifunction pin and supports the following functions: ? the value of the out bit determines the logic level of the i/o. this is only available when operating from v cc . ? alarm outputs ? available when operating from v cc or backup power supply ? fout mode ? driven from a fosc divider ? not available when operating from backup power supply (clkout mode) the internal control logic for the mfp is connected to the switched internal supply bus, this allows operation in v bat mode. the alarm output is the only mode that operates when operating from backup power supply, other modes are suspended, see ta b l e 8 - 2 . the following diagram shows how the internal mfp control logic is implemented. this pin in an open-drain and can be left floating if it is not being used. when the mfp is used for clkout mode of operation the following frequencies are available. t output = (2 * (256 +/- (2 * calreg))) t input where: t output = clock period of mfp output signal t input = clock period of input signal calreg = decimal value of the calibration register setting, and the sign is determined by the msb of the calibration register. table 8-1: clkout divider rs2 rs1 rs0 clkout frequency 000 32.768 khz * 001 8.192 khz 010 4.096 khz 011 1hz note: *not effected by calibration
? 2010-2013 microchip technology inc. ds20002266e-page 27 mcp79410/MCP79411/mcp79412 figure 8-5: mfp funct ional block diagram 8.6 battery backed operation the mcp7941x features an internal power switch that can power the clock and the sram in the event that the v cc supply is not available. the voltage applied to the v bat pin serves as the backup supply. to enable the external battery switchover operation, bit 3 vbaten (day register) must be set. setting this bit enables the path from the v bat pin to the internal power switch. a 1k series resistor is recommended between the external battery and the v bat pin to limit the current to the internal switch circuit. additionally, an 100 pf capacitor is required between the v bat pin and v ss . this is shown in figure 1-1 . the v trip is the voltage at which the internal switch operates the device from the v bat supply. when it falls below v trip , the system will continue to operate the rtcc and sram using the v bat supply. when v cc is above v trip the device is operated using the main supply. the following conditions apply: if the battery backup feature is not being used, the v bat pin should be connected to gnd. for more information on v bat conditions, see an1365, ?rtcc best practices?. 1 0 1 0 1 0 v ss oscillator sqwe x1 x2 alm0if alm1if alm0pol alm1pol out mfp pin postscaler 32.768 khz 8.192 khz 4.096 khz 1hz 64hz (digital cal) rs2:0 011 010 001 000 1xx mux table 8-2: mfp function with supply supply condition read/write access powered by clkout alarms time keeping v cc < v trip no v bat no yes yes v cc > v trip yes v cc yes yes yes
mcp79410/MCP79411/mcp79412 ds20002266e-page 28 ? 2010-2013 microchip technology inc. register 8-4: day 0 x 03 u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 ? ? oscon vbat vbaten day bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 oscon: oscillator status bit not used in this section. bit 4 vbat: external battery switched flag bit not used in this section. bit 3 vbaten: external battery enable bit 1 = the internal battery switch over is connected to the v bat pin 0 = v bat pin is disconnected and the only current drain on the external battery is the v bat pin leakage bit 2-0 day<2:0>: not used in this section
? 2010-2013 microchip technology inc. ds20002266e-page 29 mcp79410/MCP79411/mcp79412 8.6.1 power-down time-stamp registers the mcp7941x family of rtcc devices feature a power-fail time-stamp feature. this feature will store the time at which v cc crosses the v trip voltage and is shown in figure 8-6 . to use this feature, a v bat supply must be present and the oscillator must also be running. the month through minutes are saved. there are two separate sets of registers that are used to record this information: ? the first set, located at 0x18 through 0x1b, is loaded at the time when v cc falls below v trip and the rtcc operates on the v bat . the vbat (day register bit 4) bit is also set at this time. ? the second set of registers, located at 0x1c through 0x1f, is loaded at the time when v cc is restored and the rtcc switches to v cc . the power-fail time-stamp registers are cleared when the vbat (day register bit 4) bit is cleared in software. only the first power-down and power-up time-stamps are saved by the rtcc. figure 8-6: power-fail graph v cc v trip(max) v trip(min) t fvcc t rvc c power-down power-up time stamp time stamp note: it is strongly recommended that the time saver function only be used when the oscillator is running. this will ensure accurate functionality.
mcp79410/MCP79411/mcp79412 ds20002266e-page 30 ? 2010-2013 microchip technology inc. register 8-5: minutes 0 x 18 u-0 r/w-0 r/w-0 ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 10minutes<2:0>: binary-coded decimal value of minute?s tens digit contains a value from 0 to 5 bit 3-0 minutes<3:0>: binary-coded decimal value of minute?s ones digit contains a value from 0 to 9 register 8-6: hours 0 x 19 u-0 r/w-0 r/w-0 ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 12/24 : this is a copy of the status of the bit in register 0x03:6 at the time of the event bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0>: binary-coded decimal value of hour?s ones digit contains a value from 0 to 9
? 2010-2013 microchip technology inc. ds20002266e-page 31 mcp79410/MCP79411/mcp79412 register 8-7: date 0 x 1a u-0 u-0 r/w-0 r/w-0 ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0>: binary-coded decimal value of date?s tens digit contains a value from 0 to 3 bit 3-0 date<3:0>: binary-coded decimal value of date?s ones digit contains a value from 0 to 9 register 8-8: month 0 x 1b r/w-0 r/w-0 r/w-0 day 10 month month bit 7 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-5 day<2:0>: binary-coded decimal value of day. contains a value from 1 to 7. bit 4 10 month: binary-coded decimal value of month?s ones digit contains a value of 0 or 1 bit 3-0 month<3:0>: binary-coded decimal value of month?s ones digit contains a value from 0 to 9
mcp79410/MCP79411/mcp79412 ds20002266e-page 32 ? 2010-2013 microchip technology inc. 8.6.2 power-up time-stamp registers note: it is strongly recommended that the time saver function only be used when the oscillator is running. this will ensure accurate functionality. register 8-9: minutes 0 x 1c u-0 r/w-0 r/w-0 ? 10 minutes minutes bit 7 bit 6 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 10 minutes<2:0>: binary-coded decimal value of minute?s tens digit contains a value from 0 to 5 bit 3-0 minutes<3:0>: binary-coded decimal value of minute?s ones digit contains a value from 0 to 9 register 8-10: hours 0 x 1d u-0 r/w-0 r/w-0 ? 12/24 10 hour am/pm 10 hour hour bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 12/24 : this is a copy of the status of the bit in register 0x03:6 at the time of the event bit 5 10 hour am/pm bit 4 10 hour bit 3-0 hour<3:0>: binary-coded decimal value of hour?s ones digit contains a value from 0 to 9
? 2010-2013 microchip technology inc. ds20002266e-page 33 mcp79410/MCP79411/mcp79412 register 8-11: date 0 x 1e u-0 u-0 r/w-0 r/w-0 ? ? 10 date date bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 10 date<1:0>: binary-coded decimal value of date?s tens digit contains a value from 0 to 3 bit 3-0 date<3:0>: binary-coded decimal value of date?s ones digit contains a value from 0 to 9 register 8-12: month 0 x 1f r/w-0 r/w-0 r/w-0 day 10 month month bit 7 bit 5 bit 4 bit 3 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-5 day<2:0>: binary-coded decimal value of days contains a value from 1 to 7 bit 4 10 month: binary-coded decimal value of month?s ones digit contains a value of 0 or 1 bit 3-0 month<3:0>: binary-coded decimal value of month?s ones digit contains a value from 0 to 9
mcp79410/MCP79411/mcp79412 ds20002266e-page 34 ? 2010-2013 microchip technology inc. 9.0 i 2 c bus characteristics 9.1 i 2 c interface the mcp7941x supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the start and stop conditions, while the mcp7941x works as slave. both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 9.1.1 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 9-1 ). 9.1.1.1 bus not busy (a) both data and clock lines remain high. 9.1.1.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 9.1.1.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. 9.1.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 9.1.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable-low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (mcp7941x) will leave the data line high to enable the master to generate the stop condition. figure 9-1: data transfer sequence on the serial bus note: the mcp7941x does not generate any eeprom acknowledge bits if an internal programming cycle is in progress. the user may still access the sram and rtcc registers during an eeprom write. address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a)
? 2010-2013 microchip technology inc. ds20002266e-page 35 mcp79410/MCP79411/mcp79412 figure 9-2: acknowledge timing 9.1.2 device addressing and operation a control byte is the first byte received following the start condition from the master device ( figure 9-2 ). the control byte consists of a control code; for the mcp7941x this is set as ? 1010111x ? for read (0xaf) and write (0xae) operations for the eeprom. the control byte for accessing the sram and rtcc registers are set to ? 1101111x ? (0xdf for a read, 0xde for a write). the rtcc registers and the sram share the same address space. the last bit of the control byte defines the operation to be performed. when set to a ? 1 ? a read operation is selected, and when set to a ? 0 ? a write operation is selected. the next byte received defines the address of the data byte ( figure 9-3 ). the upper address bits are transferred first, followed by the least significant bits (lsb). following the start condition, the mcp7941x monitors the sda bus, checking the device type identifier being transmitted. upon receiving an ? 1010111x ? or ? 1101111x ? code, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the mcp7941x will select a read or write operation. figure 9-3: control byte and address sequence bit assignments scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit 1010 r/w a7 a 0 ?????? eeprom control byte address byte control code 111 1101 r/w a7 a 0 ?????? sram/rtcc control byte address byte control code 111
mcp79410/MCP79411/mcp79412 ds20002266e-page 36 ? 2010-2013 microchip technology inc. 9.1.3 acknowledge polling since the device will not acknowledge an eeprom command during an eeprom write cycle, this can be used to determine when the cycle is complete. this feature can be used to maximize bus throughput. once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be resent. if the cycle is complete, then the device will return the ack, and the master can then proceed with the next read or write command. see figure 9-4 for the flow diagram. figure 9-4: acknowledge polling flow send ee write command send stop condition to initiate ee write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no* yes note*: for added system robustness, implement time-out checking to avoid a potential infinite loop. note: for added systems robustness, it is recommended that time-out functionality be implemented in the acknowledge poll- ing routine to avoid potentially hanging the system by entering an infinite loop. this can easily be done by designing in a maximum number of loops the routine will execute, or through the use of a hardware timer if a time out occurs, polling should be aborted by sending a stop condition. a user-generated error-handling routine can then be called, allowing the system to recover in a manner appropriate for the application.
? 2010-2013 microchip technology inc. ds20002266e-page 37 mcp79410/MCP79411/mcp79412 10.0 on-board memory the mcp7941x has both on-board eeprom memory and battery-backed sram. the sram is arranged as 64 bytes and is retained when the v cc supply is removed, provided the v bat supply is present and enabled. the eeprom is organized as 128 x 8 bytes. the eeprom is nonvolatile memory and does not require the v bat supply for retention. 10.1 sram/rtcc figure 10-1: sram/rtcc byte write figure 10-2: sram/rtcc multiple byte write the 64 bytes of user sram are at location 0x20h and can be accessed during the time when the rtcc is being internally updated. upon por, the sram will be in an undefined state. writing to the sram and rtcc is accomplished in a similar way to writing to the eeprom (as described later in this document) with the following consider- ations: ? there is no page. the entire 64 bytes of sram or 32 bytes of rtcc register can be written in one command. ? the sram allows an unlimited number of read/ write cycles. ? the rtcc and sram are not accessible when the device is running on the external v bat supply. ? the rtcc and sram are separate blocks. the sram array may be accessed during an rtcc update. ? read and write access is limited to either the rtcc register block or the sram array. the address pointer will rollover to the start of the addressed block. ? data written to the rtcc and sram are on a per byte basis. bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1101 0 1 11 p 0 bus activity master sda line bus activity s t a r t control byte address byte data byte 0 s t o p a c k a c k a c k data byte n a c k s 1101 0 111 p 0 note: entering an address past 0x5f for an sram operation will result in the mcp7941x not acknowledging the address.
mcp79410/MCP79411/mcp79412 ds20002266e-page 38 ? 2010-2013 microchip technology inc. 10.2 eeprom the mcp794xx features 1kbits of internal high endurance eeprom. this eeprom block features an 8-byte page. 10.2.1 block protection the eeprom does not support a hardware write protection pin, however, software block protection is available to the user and is configured using the status register. 10.2.2 status register the status register is in the nonvolatile eeprom array. to access the status register, the address of 0xffh is written to and read from. ack polling may be used to determine if the write is complete. the bits in this register are defined as: ? bit 3:2 (bp<1:0>) are the eeprom array block protection bits. if an attempt is made to perform a write to an area of eeprom that is protected, the mcp794xx will acknowledge but the write will not take place. these bits are in the nonvolatile eeprom array. this allows protection of the following areas: ? the unused bits are reserved at this time and read as ? 0 ?. ? with the current address read operation, the address is not incremented. consequently, the subsequent reads are done from the same location. if multiple bytes are loaded to the status register, only the last byte is written. the write to the status register is initiated by the i 2 c stop condition. table 10-1: block protection bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (60h-7fh) 10 upper 1/2 (40h-7fh) 11 all (00h-7fh) register 10-1: status register 0 x ff uuuur/w-0r/w-0uu ? ? ? ? bp1 bp0 ? ? bit 7 bit 3 bit 2 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is clear ?x? = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3-2 bp<1:0>: eeprom array block protection bits bit 1-0 unimplemented: read as ? 0 ?
? 2010-2013 microchip technology inc. ds20002266e-page 39 mcp79410/MCP79411/mcp79412 10.2.3 eeprom byte write following the start condition from the master, the control code and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the mcp7941x. after receiving another acknowledge signal from the mcp7941x, the master device transmits the data word to be written into the addressed memory location. the mcp7941x acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and, during this time, the mcp7941x does not generate acknowledge signals for eeprom write commands. access to the rtcc/sram registers is possible during an eeprom write cycle. if an attempt is made to write to an address and the protection is set then the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. after a byte write command, the internal address counter will point to the address location following the one that was just written. 10.2.4 eeprom page write the write control byte, word address, and the first data byte are transmitted to the mcp7941x in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to seven additional bytes (mcp7941x has an 8-byte page), which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. after receipt of each word, the three lower address pointer bits are internally incremented by one. if the master should transmit more than eight bytes prior to generating the stop condition, the address counter will roll over and the data received previously will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin ( figure 10-4 ). note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being transmitted. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. note: addressing undefined eeprom locations will result in the mcp7941x not acknowledging the address.
mcp79410/MCP79411/mcp79412 ds20002266e-page 40 ? 2010-2013 microchip technology inc. figure 10-3: ee byte write figure 10-4: ee page write bus activity master sda line bus activity s t a r t control byte address byte data s t o p a c k a c k a c k s 1010 0 1 11 p 0 bus activity master sda line bus activity s t a r t control byte address byte data byte 0 s t o p a c k a c k a c k data byte 7 a c k s 1010 0 111 p 0
? 2010-2013 microchip technology inc. ds20002266e-page 41 mcp79410/MCP79411/mcp79412 10.2.5 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the control byte is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 10.2.5.1 current address read the mcp7941x contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. in the case of a page write, if the last byte written is the last byte of a page, the next address location would be the first byte of the same page written. upon receipt of the control byte with r/w bit set to one, the mcp7941x issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the mcp7941x discontinues transmission ( figure 10-1 ). figure 10-1: current address read (eeprom shown) 10.2.5.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the mcp7941x as part of a write operation (r/w bit set to ? 0 ?). after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the mcp7941x will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but it does generate a stop condition which causes the mcp7941x to discontinue transmission ( figure 10-2 ). after a random read command, the internal address counter will point to the address location following the one that was just read. 10.2.5.3 sequential read sequential reads are initiated in the same way as a random read except that after the mcp7941x transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the mcp7941x to transmit the next sequentially addressed 8-bit word ( figure 10-3 ). following the final byte transmitted to the master, the master will not generate an acknowledge but will generate a stop condition. to provide sequential reads, the mcp7941x contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over to the start of the block. figure 10-2: random read (eeprom shown) figure 10-3: sequential read (eeprom shown) bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00 1 byte 111 bus activity master sda line bus activity a c k n o a c k a c k a c k s t o p s t a r t control byte address byte control byte data byte s t a r t s 1010 0 111 s 1010 1 p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p
mcp79410/MCP79411/mcp79412 ds20002266e-page 42 ? 2010-2013 microchip technology inc. 11.0 packaging information 11.1 package marking information 8-lead soic (3.90 mm) example: xxxxxt xxyyww nnn 8-lead tssop example: 79410i sn 1303 13f 8-lead msop example: xxxx tyww nnn xxxxx ywwnnn 7941 i303 13f 79401i 30313f 3 e 8-lead 2x3 tdfn xxx yww nn ac4 303 13 example: part number 1st line marking codes tssop msop tdfn mcp79410 7941 79410t aap MCP79411 9411 79411t aaq mcp79412 9412 79412t aar t = temperature grade nn = alphanumeric traceability code legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2010-2013 microchip technology inc. ds20002266e-page 43 mcp79410/MCP79411/mcp79412 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp79410/MCP79411/mcp79412 ds20002266e-page 44 ? 2010-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010-2013 microchip technology inc. ds20002266e-page 45 mcp79410/MCP79411/mcp79412
mcp79410/MCP79411/mcp79412 ds20002266e-page 46 ? 2010-2013 microchip technology inc. d n e e1 note 1 12 b e c a a1 a2 l1 l
? 2010-2013 microchip technology inc. ds20002266e-page 47 mcp79410/MCP79411/mcp79412 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp79410/MCP79411/mcp79412 ds20002266e-page 48 ? 2010-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010-2013 microchip technology inc. ds20002266e-page 49 mcp79410/MCP79411/mcp79412 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp79410/MCP79411/mcp79412 ds20002266e-page 50 ? 2010-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010-2013 microchip technology inc. ds20002266e-page 51 mcp79410/MCP79411/mcp79412 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp79410/MCP79411/mcp79412 ds20002266e-page 52 ? 2010-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2010-2013 microchip technology inc. ds20002266e-page 53 mcp79410/MCP79411/mcp79412
mcp79410/MCP79411/mcp79412 ds20002266e-page 54 ? 2010-2013 microchip technology inc. appendix a: revision history revision a (10/2010) original release of this document. revision b (03/2011) minor typographical edits; added appendix b: device errata revision c (07/2011) updated section 4.2.6, crystal specs; revised figure 4-4. revision d (12/2011) added dc/ac char. charts revision e (04/2013) revised features page; revised schematic, block diagram; added detailed descriptions for registers. minor updates to the overall content. appendix b: device errata devices with silicon revision prior to a4 (date code prior to 11/10) have an errata where the am/pm bit (bit 5 in register 02h) may be flipped if the oscillator is stopped. this is coincident with the oscon bit getting cleared. this can occur due to the following conditions: ? the oscillator is stopped on the application. ? the oscillator is stopped by clearing the st bit (bit 7 in register 00h). ? the external cmos source is stopped in extosc mode. the work-around is to determine when the oscon bit is cleared and check in software for am/pm bit corrup- tion. devices with silicon revision a4 or later (date code after 11/09) do not have this issue.
? 2010-2013 microchip technology inc. ds20002266e-page 55 mcp7941x the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
mcp7941x ds20002266e-page 56 ? 2010-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds20002266e mcp7941x 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2010-2013 microchip technology inc. ds20002266e-page 57 mcp7941x product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . not every possible ordering combination is listed below. part no. x /xx package temperature range device device: mcp79410 = 1.8v - 5.5v i 2 c? serial rtcc mcp79410t = 1.8v - 5.5v i 2 c serial rtcc (tape and reel) MCP79411 = 1.8v - 5.5v i 2 c serial rtcc, eui-48 tm MCP79411t = 1.8v - 5.5v i 2 c serial rtcc, eui-48 tm (tape and reel) mcp79412 = 1.8v - 5.5v i 2 c serial rtcc, eui-64 tm mcp79412t = 1.8v - 5.5v i 2 c serial rtcc, eui-64 tm (tape and reel) temperature range: i = -40c to +85c package: sn = 8-lead plastic small outline (3.90 mm body) st = 8-lead plastic thin shrink small outline (4.4 mm) ms = 8-lead plastic micro small outline mny (1) = 8-lead plastic dual flat, no lead examples: a) mcp79410-i/sn: industrial temperature, soic package. b) mcp79410t-i/sn: industrial tempera- ture, soic package, tape and reel. c) mcp79410t-i/mny: industrial tempera- ture, tdfn package, tape and reel. d) MCP79411-i/sn: industrial temperature, soic package, eui-48 tm . e) MCP79411-i/ms: industrial temperature msop package, eui-48 tm . f) mcp79412-i/sn: industrial temperature, soic package, eui-64 tm . g) mcp79412-i/st: industrial temperature, tssop package, eui-64 tm . h) mcp79412t-i/st: industrial temperature, tssop package, tape and reel, eui-64 tm . note 1: "y" indicates a nickel palladium gold (nipdau) finish.
mcp7941x ds20002266e-page 58 ? 2010-2013 microchip technology inc. notes:
? 2010-2013 microchip technology inc. ds20002266e-page 59 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2010-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620771778 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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