? 2001 cali f o r nia micro d e vices co r p . all rights rese r v ed. 12/18/2001 1 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cm8870/70c california micro devices cmos integrated dtmf receiver features ? full dtmf receiver less than 35mw power consumption industrial temperature range uses quartz crystal or ceramic resonators adjustable acquisition and release times 18-pin dip, 18-pin dip eiaj, 18-pin soic, 20-pin plcc ? cm8870c ? power down mode ? inhibit mode ? buffered osc3 output (plcc package only) cm8870c is fully compatible with cm8870 for 18-pin devices by grounding pin 5 and pin 6. product description the camd cm8870/70c provides full dtmf receiver capability by integrating both the band-split filter and digital decoder functions into a single 18-pin dip, soic, or 20-pin plcc package. the cm8870/70c is manufac- tured using state-of-the-art cmos process technology for low power consumption (35mw, max) and precise data handling. the filter section uses a switched capaci- tor technique for both high and low group filters and dial applications pabx central office mobile radio remote control remote data entry call limiting telephone answering systems paging systems c1581000 tone rejection. the cm8870/70c decoder uses digital counting techniques for the detection and decoding of all 16 dtmf tone pairs into a 4-bit code. this dtmf receiver minimizes external component count by provid- ing an on-chip differential input amplifier, clock genera- tor, and a latched three-state interface bus. the on-chip clock generator requires only a low cost tv crystal or ceramic resonator as an external component. block dia g ra m digital detection algorithm zero crossing detectors code converter and latch + ? v dd in+ in ? bias circuit v ss chip ref chp bias chp power v ref std steering logic pd dial tone filter high group filter low group filter + ? inh toe q1 est st gt osc 1 osc 2 osc 3 to all chip clocks st/gt q2 q3 q4 gs obsolete product
?2001 cali f o r nia micro d e vices co r p . all rights rese r v ed. 12/18/2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 2 cm8870/70c california micro devices absolute maximum ratin gs s y mbol p a r a m e t e rv a l ue v dd power supply volta g e (v dd /v ss ) 6 v ma x vdc voltage on any pin v ss ? 0.3v to v dd + 0.3v i dd current on any pin 10ma max t a operating temperature ? 40 ? c to 85 ? c t s storage temperature 65 ? c to 150 ? c absolute maximum ratings: (note 1) this device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. notes: 1. exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied. d c c haracteristic s s y mbol p a r a m e t e r test c onditions min typ max u ni t v dd operatin g supply volta g e 4.7 5 5 .2 5 v i dd operating supply current 3.0 7.0 ma i ddq standby supply current pd = v dd 25 a p o power consumption f = 3.579 mhz; v dd = 5v 15 35 mw v il low level input voltage v dd = 5v 1.5 v v ih high level input voltage v dd = 5v 3.5 v i ih/ l il input leakage current v in = v ss = v dd (note 1) 0.1 a i so pull up (source) current on toe toe = 0v, v dd = 5v 6.5 20 a r in input impedance, (in+, in ) @ 1khz 8 10 m ? v tst steering threshold voltage v dd = 5v 2.2 2.5 v v ol low level output voltage v dd = 5v, no load 0.03 v v oh high level output voltage v dd = 5v, no load 4.97 v i ol output low (sink) current v out = 0.4v 1.0 2.5 ma i oh output high (source) current v out = 4.6v 0.4 0.8 ma v ref output voltage v ref v dd = 5.0v, no load 2.4 2.7 v r or output resistance 10 k ? dc characteristics: all voltages referenced to v ss , v dd = 5v 5%, t a = 40 c to 85 c unless otherwise noted. operatin g characteristic s s y mbol p a r a m e t e r test c onditions min typ max u ni t i in input leaka g e current v ss < v in < v dd 1 00 na r in input resistance 10 m ? v os input offset voltage 25 mv psrr power supply rejection 1 khz (note 12) 50 db cmrr common mode rejection 3v < v in < 3v 40 db a vol dc open loop voltage gain 32 db fc open loop unity gain bandwidth 0.3 mhz v o output voltage swing r l 100 kw to v ss 4 v p-p c l maximum capacitive load (gs) 100 pf r l maximum resistive load (gs) 50 k ? vcm common mode range (no load) no load 2.5 v p-p operating characteristics: all voltages referenced to v ss , v dd = 5v 5%, t a = 40 c to 85 c unless otherwise noted. gain setting amplifier obsolete product
? 200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 1 2 / 18 /2001 3 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cm8870/70c california micro devices a c c haracteristic s symbol p a r a m e t e rn o t es min typ max u ni t valid input si g nal levels 1, 2, 3, 4, 5, 8 2 9 1 d b m (each tone of composite signal) 27.5 869 mv rms positive twist accept 2, 3, 4, 8 10 db negative twist accept 10 db freq. deviation aceept limit 2, 3, 5, 8, 10 1.5%2hz norm. freq. deviation reject limit 2, 3, 5 3.5% norm. third tone tolerance 2, 3, 4, 5, 8, 9, 13, 14 16 db noise tolerance 2, 3, 4, 5, 6, 8, 9 12 db dial tone tolerance 2, 3, 4,5, 7, 8, 9 22 db t dp tone present detection time refer to timing diagram 5 8 14 ms t da tone absent dectection time refer to timing diagram 0.5 3 8.5 ms t rec min tone duration accept 15 40 ms max tone duration reject 15 20 ms t id min interdigit pause accept 15 40 ms t do max interdigit pause reject 15 20 s t pq propagation delay (st to q) toe = v dd 6 11 s t ps t d propagation delay (st to std) toe = v dd 9 16 s t qs t d output data set up (q to std) toe = v dd 3.4 s t pte propagation delay (toe to q) enable r l = 10k ? 50 ns t ptd disable c l = 50pf 300 ns f clk crystal/clock frequency 3.5759 3.5795 3.5831 mhz c lo clock ouput (osc 2) capacitive load 30 pf ac characteristics: all voltages referenced to v ss , v dd = 5.0v 5%, t a = 40 c to +85 c, f clk = 3.579545 mhz using test circuit in figure 1 unless otherwise noted. notes: 1. dbm = decibels above or below a reference power of 1mw into a 600 ? load. 2. digit sequence consists of all 16 dtmf tones. 3. tone duration = 40ms. tone pause = 40ms. 4. nominal dtmf frequencies are used. 5. both tones in the composite signal have an equal amplitude. 6. bandwidth limited (0 to 3khz) gaussian noise. 7. the precise dial tone frequencies are (350hz and 440hz) 2%. 8. for an error rate of better than 1 in 10,000 9. referenced to lowest level frequency component in dtmf signal. 10. minimum signal acceptance level is measured with specified maximum frequency deviation. 11. input pins defined as in+, in , and toe. 12. external voltage source used to bias v ref . 13. this parameter also applies to a third tone injected onto the power supply. 14. referenced to figure 1. input dtmf tone level at 28dbm. 15. times shown are obtained with circuit in figure 1 (user adjustable). obsolete product
?200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 1 2 / 18 /2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 4 cm8870/70c california micro devices events interdigit pause a toe st/gt est v in decoded tone # n+1 tone # n tone # n+1 tone # n+1 decoded tone # n high impedance decoded tone # n+1 vtst tpte std output data outputs q1-q4 tptd tqstd tpstd tgta tgtp tpq tdp trec trec tdo tone dropout tid tda b c e f g d explanation of events a. tone bursts detected, tone duration invalid, outputs not updated. b. tone #n detected, tone duration valid, tone decoded and latched in outputs. c. end of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone. d. outputs switched to high impedance state. e. tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). f. acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched. g. end of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone. explanation of symbols v in dtmf composite input signal. est early steering output. indicates detection of valid tone frequencies. st/gt steering input/guard time output. drives external rc timing circuit. q1-q4 4-bit decoded tone output. std delayed steering output. indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid signal. toe tone output enable (input). a low level shifts q1-q4 to its high impedance state. t rec maximum dtmf signal duration not detected as valid. t rec minimum dtmf signal duration required for valid recognition. t id minimum time between valid dtmf signals. t do maximum allowable drop-out during valid dtmf signal. t dp time to detect the presence of valid dtmf signals. t da time to detect the absence of valid dtmf signals. t gtp guard time, tone present. t gta guard time, tone absent. timing diagram obsolete product
? 200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 1 2 / 18 /2001 5 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cm8870/70c california micro devices functional description the camd cm8870/70c dtmf integrated receiver provides the design engineer with not only low power consumption, but high performance in a small 18-pin dip, soic, or 20-pin plcc package configuration. the cm8870/70c s internal architecture consists of a band-split filter section which separates the high and low tones of the received pair, followed by a digital decode (counting) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus. filter section separation of the low-group and high-group tones is achieved by applying the dual-tone signal to the inputs of two 9 th -order switched capacitor bandpass filters. the bandwidths of these filters correspond to the bands enclosing the low-group and high-group tones (see figure 3). the filter section also incorporates notches at 350hz and 440hz which provides excellent dial tone rejection. each filter output is followed by a single order switched capacitor section which smooths the signals prior to limiting. signal limiting is performed by high-gain comparators. these comparators are provided with a hysteresis to prevent detection of unwanted low-level signals and noise. the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. decoder section the cm8870/70c decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard dtmf frequencies. a complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while providing tolerance to small frequency variations. the averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering signals (third tones) and noise. when the detector recognizes the simultaneous pres- ence of two valid tones (known as signal condition ), it raises the early steering flag (est). any subsequent loss of signal condition will cause est to fall. steering circuit before the registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character-recognition-condition ). this check is per- formed by an external rc time constant driven by e st . a logic high on est causes v c (see figure 4) to rise as the capacitor discharges. providing signal condition is maintained (est remains high) for the validation period (t gtp ), v c reaches the threshold (v tst ) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (see figure 2) into the output latch. at this point, the gt output is activated and drives vc to v dd . gt continues to drive high as long as est remains high, signaling that a received tone pair has been registered. the contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (toe) to a logic high. the steering circuit works in reverse to validate the interdigit pause between signals. thus, as well as rejecting signals too short to be consid- ered valid, the receiver will tolerate signal interruptions (drop outs) too short to be considered a valid pause. this capability together with the capability of selecting the steering time constants externally, allows the de- signer to tailor performance to meet a wide variety of system requirements. guard time adjustment in situations which do not require independent selection of receive and pause, the simple steering circuit of figure 4 is applicable. component values are chosen according to the following formula: t rec = t dp + t gtp t gtp = 0.67 rc the value of t dp is a parameter of the device and t rec is the minimum signal duration to be recognized by the receiver. a value for c of 0.1f is recommended for most applications, leaving r to be selected by the designer. for example, a suitable value of r for a t rec of 40ms would be 300k. a typical circuit using this steering configuration is shown in figure 1. the timing require- ments for most telecommunication applications are satisfied with this circuit. different steering arrange- ments may be used to select independently the guard-times for tone-present (t gtp ) and tone absent (t gta ). this may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. guard time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. increasing t rec improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. on the other hand, a relatively short t rec with a long t do would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. design information for guard time adjustment is shown in figure 5. obsolete product
?200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 1 2 / 18 /2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 6 cm8870/70c california micro devices input configuration the input arrangement of the cm8870/70c provides a differential input operational amplifier as well as a bias source (v ref ) which is used to bias the inputs at mid-rail. provision is made for connection of a feedback resistor to the op-amp output (gs) for adjustment of gain. in a single-ended configuration, the input pins are con- nected as shown in figure 1, with the op-amp connected for unity gain and vref biasing the input at ? v dd . figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor r5. clock circuit the internal clock circuit is completed with the addition of a standard television color burst crystal or ceramic resonator having a resonant frequency of 3.579545mhz. the cm8870c in a plcc package has a buffered oscillator output (osc3) that can be used to drive clock inputs of other devices such as a micropro- cessor or other cm887x s as shown in figure 7. mul- tiple cm8870/70cs can be connected as shown in figure 8 such that only one crystal or resonator is required. pin f u n c ti on n a m e f u n c ti o n discri p tio n in+ non-invertin g input connection to the front-end differential amplifier in inverting input connection to the front-end differential amplifier gs gain select gives access to output of front-end differential amplifier for connection of feedback resistor. v ref reference output voltage may be used to bias the inputs at mid-rail. (nominally v dd /2) inh inhibits detection of tones represents keys a, b, c, and d osc3 digital buffered oscillator output pd power down logic high powers down the device and inhibits the oscillator. osc1 clock input 3.579545mhz crystal connected between these pins completes internal oscillator osc2 clock output 3.579545mhz crystal connected between these pins completes internal oscillator v ss negative power supply normally connected to ov toe three-state output enable (input) logic high enables the outputs q1-q4. internal pull-up. q 1 three-state ouputs when enabled by toe, provides the code corresponding to the last valid q 2 tone pair received. (see figure 2). q 3 q 4 std delayed steering output presents a logic high when a received tone pair has been registered and the output latch is updated. returns to logic low shen the voltage on st/gt falls below v tst . est early steering output presents logic high immediately when the digital algorithm detects a recongnizable tone pair (signal condition). any momentary loss of signal condition will cause est to return to a logic low. st/gt steering input/guard a voltage greater than v tst detected at st causes the device to register time output (bidirectional) the dectected tone pair. the gt output acts to reset the external steering time constrant, and its state is a function of est and the voltage on st. (see figure 2). v dd positve power supply ic internal connection must be tied to v ss (for 8870 configuration only). obsolete product
? 200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 1 2 / 18 /2001 7 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cm8870/70c california micro devices figure 1. single ended input configuration f u n c ti o n a l di ode t ab l e f l ow f hi gh key t o w q 4 q 3 q 2 q 1 69 712 09 1 h 0 0 0 1 697 1336 2 h 0 0 1 0 697 1477 3 h 0 0 1 1 770 1209 4 h 0 1 0 0 770 1336 5 h 0 1 0 1 770 1477 6 h 0 1 1 0 852 1209 7 h 0 1 1 1 852 1336 8 h 1 0 0 0 852 1477 9 h 1 0 0 1 941 1336 0 h 1 0 1 0 941 1209 * h 1 0 1 1 941 1477 # h 1 1 0 0 697 1633 a h 1 1 0 1 770 1633 b h 1 1 1 0 852 1633 c h 1 1 1 1 941 1633 d h 0 0 0 0 - - any l z z z z l logic low, h = logic, z = high impedance figure 2. functional decode table in+ 1 3 4 5 6 7 8 9 2 18 16 15 14 13 12 11 10 17 0.1f 0.1f 5v 3.58 mhz 100k ? 100k ? 300k ? v dd cm8870 in ? st/gt gs est v ref std inh q4 pd q3 osc 1 q2 osc 2 q1 v ss toe in+ 1 3 4 5 6 7 8 9 2 18 16 15 14 13 12 11 10 17 0.1f 0.1f all resistors are 1% tolerance. all capacitors are 5% tolerance. 5v 3.58 mhz 100k ? 100k ? 300k ? v dd cm8870c in ? st/gt gs est v ref std inh q4 pd q3 osc 1 q2 osc 2 q1 v ss toe obsolete product
?200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 12 / 18 /2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 8 cm8870/70c california micro devices v dd v dd v tst v dd c r v c tgta = (rc) in st/gt est std v dd v dd ? v tst tgtp = (rc) in figure 4. basic steering circuit v dd v dd v tst tgta = (r p c) in r p = r 1 r 2 r 1 + r 2 v dd v dd ? v tst tgtp = (r 1 c) in (a.) decreasing tgta (tgtp > tgta) st/gt est c r1 r2 v dd v dd v tst tgta = (r 1 c) in r p = r 1 r 2 r 1 + r 2 v dd v dd ? v tst tgtp = (r p c) in (b.) decreasing tgtp (tgtp < tgta) st/gt est c r1 r2 figure 5. guard time adjustment 50 0 xy abc d frequency hz precise dial tones dtmf tones attenuation db 1k ef g h 2k 40 30 20 10 0 x = 350hz y = 440hz a = 607hz e = 1209hz b = 770hz f = 1336hz c = 852hz g = 1477hz d = 841hz h = 1633hz figure 3. typical filter characteristic c1 + ? r1 r2 r5 r3 in+ in ? c2 r4 cm8870 c1 = c2 = 10nf r1 = r4 = r4 =100 k ? r2 = 60k ? , r3 = 37.5k ? all resistors are ? 1% tolerance. all capacitors are ? 5% tolerance. (xxxx) = 2 r2 + 2 voltage gain (av diff) = imput impedance r3 = r2r5 r2 + r5 differential input amplifier v ref gs r5 r1 1 wc figure 6. differential input configuration obsolete product
? 200 1 cali f o r nia micro d e vices co r p . all rights rese r v ed. 12 / 18 /2001 9 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cm8870/70c california micro devices figure 7. cm8870c crystal connection (plcc package only) osc1 osc2 osc3 clock input of other devices 30pf osc1 of other cm887x's osc1 osc2 3.58mhz 30pf 30pf osc1 osc2 osc1 osc2 figure 8. cm8870/70c crystal connection pin assignments in+ in ? gs v ref ic* ic* osc 1 osc 2 v ss v dd st/gt est std q4 q3 q2 q1 toe 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 cm8870 in+ in ? gs v ref inh ic* osc 1 osc 2 v ss v dd st/gt est std q4 q3 q2 q1 toe 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 cm8870c in- nc in+ gs v ref ic* ic* osc 1 osc 2 v ss v dd st/gt est std nc q4 q3 q2 q1 toe cm8870 4 5 6 7 8 9 10 11 12 13 18 17 16 15 14 3 2 1 20 19 in- gs in+ gs v ref pd osc 3 osc 1 osc 2 v ss v dd st/gt est std nc q4 q3 q2 q1 toe cm8870c 4 5 6 7 8 9 10 11 12 13 18 17 16 15 14 3 2 1 20 19 p plastic dip (18) f plastic sop eiaj (18) s spic (18) p plastic dip (18) f plastic sop eiaj (18) s soic (18) pe plcc (20) * connected to v ss pe plcc (20) ordering information ip cm8870 cm8870c product identification number example: package p plastic dip (18) f plastic sop eiaj (18) pe plcc (20) s soic (18) temperature/processing none 0 ? c to 70 ? c, 5% p.s. tol. i 40 ? c to 85 ? c, 5% p.s. tol. obsolete product
|
