a11 a7 a6 a5 a4 a3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 v dd we oe a0 to a14 we oe cs i/o1 to i/o8 v dd v ss address input write enable output enable chip select data input/output power supply (2.7 to 5.5v) power supply (0v) srm2b256sltmt (tsop) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 a9 a8 a13 a14 a12 a2 a1 a0 v ss a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 a4 a13 a8 a9 a11 oe 7 6 5 4 3 2 1 28 27 26 25 24 23 22 v dd a12 a3 srm2b256slrmt (tsop-r1)(reverse bending) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 a5 a6 a7 we a14 a10 cs v ss a2 a1 a0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v dd we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 srm2b256slmt/ct a14 1 (dip/sop2) a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 cs oe we i/o buffer column gate memory cell array 512 5 64 5 8 64 5 8 8 9 512 6 64 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 a13 a14 y decoder address buffer x decoder cs control logic oe, we control logic n description the srm2b256slmt is a low voltage operating 32,768 words 5 8-bit asynchronous, static, random access memory fabricated using an advanced cmos technology. its very low standby power consumption makes it ideal for applications requiring non-volatile storage with back-up batteries. and C40 to 85 c operating temperature range makes it ideal for industrial use. the asynchronous and static nature of the memory requires no external clock or refresh circuit. output ports are 3-state output allows easy expansion of memory capacity. these features makes the srm2b256slmt usable for wide range of applications from microprocesser systems to terminal devices. n features l wide temperature range ................... C40 to 85 c l extended supply voltage range ......... 2.7 to 5.5v l fast access time ............................... 100ns (3v 10%) 55ns (5v 10%) l extremely low standby current .......... sl version l completely static ............................... no clock required l 3-state output l battery back-up operation l package .............. srm2b256slct dip2-28pin (plastic) srm2b256slmt sop2-28pin (plastic) srm2b256sltmt tsop (i) -28pin (plastic) srm2b256slrmt tsop (i) -28pin-r1 (plastic) 256k-bit static ram pf857-02 n pin configuration n pin description n block diagram l wide temperature range l extremely low standby current l access time 100ns (2.7v) /55ns s (4.5v) l 32,768 words x 8-bit asynchronous wide voltage operation products srm2b256slmt 55/70/10
srm2b256slmt 55/70/10 2 supply voltage input voltage input/output voltage power dissipation operating temperature storage temperature soldering temperature and time v dd v i v i/o p d t opr t stg t sol ?.5 to 7.0 ?.5 ] to 7.0 ?.5 ] to v dd +0.3 1.0 ?0 to 85 ?5 to 150 260 c, 10s(lead only) parameter symbol rating unit (v ss =0v) ] v i , v i/o (min.)= ?3.0v when pulse width is less or equal to 50ns v v v w c c (v ss =0v, ta= ?0 to 85 c) parameter input voltage supply voltage symbol min. v dd v ss v ih v il ] v il (min.)= ?v when pulse width is less or equal to 50ns note : this parameter is made by the inspection data of sample, not for all products. v dd =3v 10% 2.7 0 2.2 ?.3 ] typ. max. 3.3 0 v dd +0.3 0.4 min. 4.5 0 2.2 ?.3 ] typ. max. 5.5 0 v dd +0.3 0.8 v v v v v dd =5v 10% unit parameter symbol conditions unit input leakage high level output voltage low level output voltage operating supply current average operating current i li v oh v ol i dds i ddo ?.0 a a ma v (v ss =0v, ta= ?0 to 85 c) min. typ. ] 1 max. v dd =3v 10% i dda ] 1 typical values are measured at ta=25 c and v dd =3.0v ] 2 typical values are measured at ta=25 c and v dd =5.0v ] 3 v dd =3v 10% v i =0 to v dd cs=v ih 2.4 1.0 v ma standby supply current i dds1 i dda1 i oh =?.0ma, ?.5ma ] 3 i ol =2.1ma, 1.0ma ] 3 cs 3 v dd ?.2v v i =v il , v ih i i/o =0ma, t cyc =min. v i =v il , v ih i i/o =0ma, t cyc =1 s v i =v il , v ih i i/o =0ma ma ma 0.3 10 0.4 2 25 15 5 5 v dd =5v 10% min. typ. ] 2 max. ?.0 1.0 2.4 0.4 ? 0.5 50 30 45 10 ?0 (f=1mhz, ta=25 c) v dd =3v 10% v dd =5v 10% v dd =3v 10% v dd =5v 10% v dd =3v 10% v dd =5v 10% parameter symbol input capacitance i/o capacitance c i c i/o min. typ. max. unit conditions pf pf v i =0v v i/o =0v 8 10 read cycle time address access time cs access time oe access time cs output set time cs output floating oe output set time oe output floating output hold time t rc t acc t acs t oe t clz t chz t olz t ohz t oh min. 100 15 0 15 max. 100 100 60 35 35 min. 55 10 0 10 max. 55 55 30 20 20 min. 120 15 0 15 max. 120 120 70 40 40 min. 70 10 0 10 max. 70 70 35 25 25 min. 180 15 0 15 max. 180 180 90 50 50 min. 100 10 0 10 max. 100 100 45 35 35 srm2b256slmt 55 srm2b256slmt 70 srm2b256slmt 10 unit ns ns ns ns ns ns ns ns ns conditions symbol parameter (v ss =0v, ta=?0 to 85 c) output leakage i lo a cs=v ih or we=v il or oe=v ih , v i/o =0 to v dd ?.0 1.0 ?.0 1.0 ] 1 ] 2 ] 1 n absolute maximum ratings n electrical characteristics l dc electrical characteristics l terminal capacitance l ac electrical characteristics m read cycle n dc recommended operating conditions
srm2b256slmt 55/70/10 3 address cs d out oe address cs we d out address cs we d out din m read cycle ] 1 m write cycle (1)(cs control) ] 2 m write cycle (2)(we control) ] 3, ] 4 t rc t acc t acs t clz t oe t olz t oh t chz t ohz t wc t aw t cw t as t wp t wr t whz t clz t dw t dh din t aw t as t wp t whz t ow t dw t dh t wc t wr note : ] 1 during read cycle time, we is to be "h" level. ] 2 during write cycle time that is controlled by cs, output buffer is in high impedance state, whether oe level is "h" or "l". ] 3 during write cycle time that is controlled by we, output buffer is in high impedance state if oe is "h" level. ] 4 when i/o terminals are output mode, be careful that do not give the opposite signals to the terminals. l write cycle l timing chart ] 2 test conditions 1. input pulse level : 0.6v to 2.4v 2. t r =t f =5ns 3. input timing reference levels : 1.5v 4. output timing reference levels: 200mv (the level displaced from stable output voltage level) 5. output load c l =5pf ] 1 test conditions 1. input pulse level: 0.6v to 2.4v 2. t r =t f =5ns 3. input and output timing reference levels : 1.5v 4. output load c l =100pf (v ss =0v, ta=?0 to 85 c) v dd =3v 10% v dd =5v 10% v dd =3v 10% v dd =5v 10% v dd =3v 10% v dd =5v 10% write cycle time chip select time address valid to end of write address setup time write pulse width address hold time input data set time input data hold time write to output floating output active from end to wirte t wc t cw t aw t as t wp t wr t dw t dh t whz t ow ] 1 ] 2 min. 100 80 80 0 75 0 40 0 5 max. 35 min. 55 50 50 0 40 0 25 0 5 max. 20 min. 120 90 90 0 80 0 45 0 5 max. 40 min. 70 60 60 0 45 0 30 0 5 max. 25 min. 180 110 110 0 100 0 60 0 5 max. 50 min. 100 80 80 0 60 0 40 0 5 max. 35 srm2b256slmt 55 srm2b256slmt 70 srm2b256slmt 10 unit ns ns ns ns ns ns ns ns ns ns conditions symbol parameter c l i/o c l =100pf (includes jig capacitance) c l i/o c l =5pf (includes jig capacitance) 1ttl 1ttl
srm2b256slmt 55/70/10 4 parameter symbol conditions min. typ. ] 1 max. unit data retention supply voltage data retention current chip select data hold time v ddr i ddr t cdr 2.0 5.5 20 v a ns (v ss =0v, ta=?0 to 40 c) 0 5 operation recovery time t r ms v dd =3v, cs 3 v dd ?.2v ] 1 typical values are measured at 25 c 0.25 10 a 0.25 2 a 0.25 ?0 to 85 c 0 to 70 c 0 to 40 c l data retention characteristic with low voltage power supply n functions l truth table l read mode the data appear when the address is set while holding cs="l" oe="l" and we="h" . when oe="h", data i/o terminals are in high impedance state, that makes circuit design and bus control easy. l write mode there are the following 3 ways of writing data into memory. (1) hold cs="l" and we="l", set address (2) hold cs="l" then set address and give "l"pulse to we. (3) after setting addresses, give "l"pulse to both cs and we. in above any case data on the data i/o terminals are latched up into the chip when cs or we is in positive- going. since data i/o terminals are high impedance when cs or oe="h", bus contention between data driver and memory outputs can be avoided. l standby mode when cs is "h" the chip become in the standby mode. in this mode, data i/o terminals are high impedance and all inputs of addresses, we and data can be any "h"or "l". when cs is over than v dd -0.2v, the chip is in the data retention battery backup mode, in this case, there is a small current in the chip which flow through the high resistances of the memory cells. note: during standby mode in which the data is retentive, the supply voltage (v dd ) can be in low voltage until v dd =v ddr . at this mode data reading and writing are impossible. x : "h" or "l", ?"h", "l" or "hi-z" h l l l cs x x l h x l h h oe we data i/o i dd mode i dds , i dds1 i dda , i dda1 i dda , i dda1 i dda , i dda1 hi-z d in d out hi-z standby write read output disable v dd cs t cdr v ih t r v ih v ddr 3 2.0v cs 3 v dd ?.2v data hold mode data retention timing 2.7v 2.7v
srm2b256slmt 55/70/10 5 n package dimensions plastic tsop(i)-28pin unit : mm (inch) plastic tsop(i)-28pin-r1 unit : mm (inch) plastic sop2-28pin unit : mm (inch) plastic dip-28pin unit : mm (inch) 28 15 114 37.4 max ( 1.472 max ) 1.5 ( 0.059 ) 0.46 0.1 ( 0.018 ) 2.54 ( 0.1 ) 0 15 15.24 ( 0.6 ) 36.7 0.1 ( 1.445 ) +0.003 ?.004 13.4 0.1 ( 0.528 ) +0.003 ?.004 4.6 0.1 ( 0.181 ) +0.004 ?.003 3 min ( 0.119 min ) 0.6 0.1 ( 0.024 ) +0.003 ?.004 0.25 0.05 ( 0.01 ) +0.001 ?.002 4 0.1 ( 0.157 ) +0.004 ?.003 22 8 7 index 28 1 21 11.8 0.2 ( 0.465 ) +0.007 ?.008 0 10 8 0.2 ( 0.315 0.007 ) 13.4 0.3 ( 0.528 ) +0.011 ?.012 0.8 ( 0.031 ) 0.5 0.1 ( 0.02 ) +0.003 ?.004 0.15 0.1 ( 0.006 ) +0.003 ?.004 0.55 ( 0.022 ) 1.27 max ( 0.05 max ) 0.2 0.1 ( 0.008 ) +0.003 ?.004 0 ( 0 ) 7 21 22 index 1 28 8 11.8 0.2 ( 0.465 ) +0.007 ?.008 0 10 8 0.2 ( 0.315 0.007 ) 13.4 0.3 ( 0.528 ) +0.011 ?.012 0.8 ( 0.031 ) 0.5 0.1 ( 0.02 ) +0.003 ?.004 0.15 0.1 ( 0.006 ) +0.003 ?.004 0.55 ( 0.022 ) 1.27 max ( 0.05 max ) 0.2 0.1 ( 0.008 ) +0.003 ?.004 0 ( 0 ) 15 28 14 1 1.27 ( 0.05 ) 17.8 0.1 ( 0.701 ) 8.4 0.1 ( 0.331 ) +0.003 ?.004 0.4 0.1 ( 0.016 ) +0.003 ?.004 2.9 max ( 0.114 max ) +0.003 ?.004 0.2 ( 0.008 ) 1.7 ( 0.067 ) 0 10 0.15 0.05 ( 0.006 ) +0.001 ?.002 18.1 max ( 0.712 max ) 11.8 0.3 ( 0.465 ) +0.011 ?.012 2.5 0.15 ( 0.098 ) +0.006 ?.005 1 0.3 ( 0.039 ) +0.012 ?.011
srm2b256slmt 55/70/10 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 n characteristics curves normalized i dda ?a normalized i dda ? dd normalized i dda ?requency normalized i dds1 ? dd normalized t acc, t acs ? dd normalized i dds1 ?a normalized i oh ? oh normalized t acc ? acs normalized i ol ? ol 0.7 0.8 0.9 1.0 1.1 1.2 1.3 50 25 0 25 50 75 100 5v 3v ta ( c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 frequency (mhz) 0.7 0.8 0.9 1 1.1 1.2 1.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) ta=25 c v dd (v) ta=25 c v dd (v) ta=25 c v dd (v) ta=25 c v dd (v) ta=25 c 5v 3v 5v 3v 0.0 0.1 1.0 10.0 100.0 50 25 0 25 50 75 100 5v 3v ta ( c) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1 1.5 2 2.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 5v 3v 0.7 0.8 0.9 1.0 1.1 1.2 1.3 50 25 0 25 50 75 100 5v 3v ta ( c) 0.6 0.8 1.0 1.2 1.4 1.6 2.4 1.8 2.0 2.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6. 0 0 0.5 1 1.5 2.0 2.5 3 0.0 0.2 0.4 0.6 0.8 1.0 5v 3v
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