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| ?2004 integrated device technology, inc. 1 dsc-5670/4 !!!""#$%" & '()& '*+ , '%*-./"((-0 1- 1 2 3%3-./"*(-04'%*-./"((-0 4 5 '*+& 2"## 6 ,'() & .7#(89 :)*890 5 ;< = > ? 5 ; ; @( +334" 3+ 45 5 4 s a- busy 2 4 s a- busy 5 & ! idt70t633/1s busy ! s "# $ %& ! s "# $ busy int ' ' (' &' $ ) & ( & * ( + , + -. , %& /0 , int , ! s & ( &( 11 $ + 2 ( ce 0r r/ w r ce 1r lb r ub r 512/256k x 18 memory array address decoder a 18r (1) a 0r address decoder ce 0l r/ w l ce 1l lb l ub l dout0-8_l dout9-17_l dout0-8_r dout9-17_r b e 0 l b e 1 l b e 1 r b e 0 r i/o 0l -i/o 17l i/o 0r -i/o 17r din_l addr_l din_r addr_r oe r oe l arbitration interrupt semaphore logic m/ s r/ w l oe l r/ w r oe r ce 0l ce 1l ce 0r ce 1r 5670 drw 01 a 18l (1) a 0l zz control logic zz l (4) zz r (4) jtag tck trst tms tdi tdo int l (3) sem l busy l (2,3) busy r (2,3) sem r in t r (3) ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 2 ! "#"" $%& " ' " ( ) ' " ! "$% *' " %# +$ #,-+ ! "$%. ' " * / "*&0 " %#+$ #,-+ ! " $% ' " / ** "* " " . 1 . " / " "". " " & 2 2 "/ " "/ " " " 1 1 3 "" * " "1 . / "" " ** & " *" / / ." " '" ' 4 " ce 5+ 6 * "" " . "" " 2 /"' / * & ($ 7 "% / /" " . *' 8" ' 8/ " " / " " "$ w " & . """ " * . " (1 " "" . * 2 & " " 2 " . " & - &- ' " "1 " '"3! & / . " ."2 4- 6 * "&-& 3 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# # ( 3 ++ 4# % * # ( 3 ++ % *5 # /0 & # 4#$, 4# /0 & # #$ # ( 3 ++ 2 * ) 4 0 +6 2 3* ( * (( (( )((, % & (( 3 ' +& & +6 2 + + & +6 2 2 ( 70t633/1bc bc-256 (5,6) 256-pin bga top view e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 nc a14 a 0l a12 a 5l b12 a 4l c11 busy l d12 v ddqr d11 v ddqr c10 sem l b11 nc a11 int l d8 v ddqr c8 nc a9 ce 1l d9 c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 b4 a 18l (4) c4 a 16l d4 v dd a3 nc b3 tdo c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 tdi a1 nc b1 nc c1 nc d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f3 i/o 11r f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 v dd p1 nc p2 i/o 17l p3 tms p4 a 16r r1 nc r2 nc r3 trst r4 a 18r (4) t1 nc t2 tck t3 nc t4 a 17r p5 a 13r r5 a 15r p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 sem r t11 int r p11 busy r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 m/ s t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 nc f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 zz r j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 zz l j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 nc l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5670 drw 02c , 03 / 13 / 03 a 17l v ddql v ddqr ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 4 # ( 3 ++ 4# % * # ( 3 ++ % *5 # /0 & # 4#$, 4# /0 & # #$ # ( 3 ++ 2 ) 4 0 +6 2 3* ( * (( (( )(( & +6 2 + + & +6 2 2 ( 7 ((+ 2 3 & ')) +6 2 7 & + & + '( 6 2 8 & + (3 , -. & ')) +6 2 v ss v ddqr v ss i/o 9l i/o 9r i/o 10l i/o 10r i/o 11l i/o 11r v ddql v ss i/o 12l i/o 12r v ddqr zz r v dd v dd v ss v ss v ddql v ss i/o 13r i/o 13l i/o 14r i/o 14l v ddqr v ss i/o 15r i/o 15l i/o 16r i/o 16l i/o 17r i/o 17l v ss v ddql nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 v d d n c n c a 1 8 r ( 4 ) a 1 7 r a 1 6 r a 1 5 r a 1 4 r a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r u b r l b r c e 1 r c e 0 r v d d v s s s e m r o e r r / w r b u s y r i n t r m / s a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r v d d v s s opt l v ddqr v ss i/o 8l i/o 8r i/o 7l i/o 7r i/o 6l i/o 6r v ss v ddql i/o 5l i/o 5r v ss v ddqr v dd v dd v ss v ss zz l v ddql i/o 4r i/o 4l i/o 3r i/o 3l v ss v ddqr i/o 2r i/o 2l i/o 1r i/o 1l i/o 0r i/o 0l v ss v ddql opt r v d d n c n c a 1 8 l ( 4 ) a 1 7 l a 1 6 l a 1 5 l a 1 4 l a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l u b l l b l c e 1 l c e 0 l v d d v s s s e m l o e l r / w l b u s y l i n t l n c a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l v d d v s s 70t633/1dd dd-144 (5,6,7) 144-pin tqfp top view (8) 5670 drw 02a , 03/13/03 5 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# # ( 3 ++ 4# % * # ( 3 ++ % *5 # /0 & # 4#$, 4# /0 & # #$ # ( 3 ++ 2 ) 4 0 +6 2 3* ( * 4(( 4(( )(( % & 7(( 3 +& & +6 2 + + & +6 2 2 ( & + & + '( 6 2 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 9l nc v ss a 4l int l sem l nc a 8l a 12l a 16l v ss nc opt l a 0l nc v ss nc nc a 1l a 5l busy l v ss ce 0l ce 1l nc a 9l a 13l a 17l i/o 8l v dd qr v ss v dd ql i/o 9r v ddqr v dd a 2l a 6 l r/ w l v ss ub l a 10l a 14 l a 18l (4) nc i/o 8r v dd i/o 11l v ss i/o 10l nc v dd a 3l nc oe l nc i/o 11r v ddqr i/o 10 r v dd ql nc nc v ss nc v ss i/o 12l nc v dd nc v ddqr i/o 12r v dd ql v dd v ss zz r nc i /o 14l v ddqr v dd ql nc i/o 15r v ss i/o 7r v ddql i/o 7l a 15 l a 11l a 7l lb l i/o 6l nc v ss nc v ss i/o 6r nc nc v ddql i/o 5l nc v dd nc v ss i/o 5r zz l v ddqr i/o 3r v ddql i/o 4r v ss i/o 4l v ss i/o 3l nc a 0r a 1r a 2r a 3r a 4r a 5r a 6r i/o 1r nc v ss nc i/o 15 l a 16r a 12r a 8r nc v dd sem r int r v ddqr nc i/o 1l nc v ss nc i/o 17 r a 17r a 13r a 9r nc ce 0r ce 1r v dd v ss busy r v ss v dd v ss v ddql i/o 0r v ddqr nc i/o 17l v ddql nc a 18r (4) a 14r a 10r ub r v ss nc nc v ss i/o 2r nc v ss nc v dd a 15r a 11r a 7r lb r oe r m/ s r/ w r v ddql i/o 2l opt r nc i/o 0l 70t633/1bf bf-208 (5,6) 208-ball bga top view (7) 5670 drw 02b i/o 13l i/o 14r v ss i/o 13r v ss i/o 16r i/o 16l v ddqr nc a b c d e f g h j k l m n p r t u v ss nc nc v ddqr v ss v dd v ss nc v dd v dd tdo tdi tck tms trst v ss 03 / 12 / 03 ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 6 left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (input) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 18l (1) a 0r - a 18r (1) address (input) i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output sem l sem r semaphore enable (input) int l int r interrupt flag (output) busy l busy r busy flag (output) ub l ub r upper byte select (input) lb l lb r lower byte select (input) v ddql v ddqr power (i/o bus) (3.3v or 2.5v) (2) (input) opt l opt r option for selecting v ddqx (2,3) (input) zz l zz r sleep mode pin (4) (input) m/ s master or slave select (input) (5) v dd power (2.5v) (2) (input) v ss ground (0v) (input) tdi test data input tdo test data output tck test logic clock (10mhz) (input) tms test mode select (input) trst reset (initialize tap controller) (input) 5670 tbl 01 # , /0 , # ( 3 2 * 2 !/ /0 +& 2 2 &!/ + & /0 # 4#$,&& 9!/ + % # # (3 #/0 # #$,&& 9!/ + % 4# # (3 4#&/0 &:3&+ # , 3& + 4# , & + # % & & & 4# ) & ( & * ( + , + -. , %& /0 , int , ! s & ( &( 11 $ + 2 ( +(( & 3* + 3 2 ( 4 busy ! s "# $ %& ! s "# $ 7 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# ;<;"# ;=;"# ;>;"9 !"#$ " % oe sem ce 0 ce 1 ub lb r/ w zz upper byte i/o 9-17 lower byte i/o 0-8 mode x h h x x x x l high-z high-z de se lecte d?po we r do wn x h x l x x x l high-z high-z de se lecte d?po we r do wn x h l h h h x l high-z high-z both bytes deselected xhlhhlllhigh-z d in write to lower byte xhlhlhll d in high-z write to upper byte xhlhllll d in d in write to both bytes lhlhhlhlhigh-zd out read lower byte lhlhlhhl d out high-z re ad up pe r byte lhlhllhl d out d out re ad bo th byte s h h l h l l x l high-z high-z outputs disabled xxxxxxxhhigh-zhigh-zhigh-z sleep mode 5670 tbl 02 & ' !"#$ & 2& ( & 2 % !/ ( & !/ !/ '!/ $ & 2& ( & 2 3* ' ce " = ++ %& ce "# ? "# ce " < %& ce "# ! ? "# ? +& 3* + 3* & + ub lb ub ! lb "# inputs (1) outputs mode ce (2) r/ w oe ub lb sem i/o 1-17 i/o 0 hhlll ldata out data out read data in semaphore flag (3) h xxl l x data in write i/o 0 into semaphore flag lxxxx l ______ ______ not allowed 5670 tbl 03 ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 8 !"" ( " ' ) * !"" ( " + * ,-* . /0 ! # ( $ " '# % & & ! 4, %& +& # ( $ " # @ # % & & ! 4, %& +& + 4# &!/ + 2 ,& /0 & (3# #$, # & (3 + 3 2 & & a /=b? > b c . ( * + ( ( 2& +& 2 * + & + & *&+ 3 & + & + & + + ( ? 3 ( (( 2 + ( * + 3 * & *' ( & & % * & +& ( 2 0% d+ 2 + *e &% ,& 2 *!/ + +# 2% * ( (3 ( a & + & & ( & & ; ; + ( grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5670 tbl 04 symbol rating commercial & industrial unit v term (v dd ) v dd te rm in al vo l ta g e with re spe ct to gnd -0.5 to 3.6 v v term (2) (v ddq ) v ddq terminal voltage with re spe ct to gnd -0.3 to v ddq + 0.3 v v te rm (2) (inputs and i/o?s) input and i/o te rminal voltage with respect to gnd -0.3 to v ddq + 0.3 v t bias (3) temperature und er bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddq = 3.3v) dc output current 50 ma i out (for v ddq = 2.5v) dc output current 40 ma 5670 tbl 07 symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high volltag e (address, control & data i/o inputs) (3) 1.7 ____ v ddq + 100mv (2) v v ih input high voltag e _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, opt, m/ s v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v v il input low voltag e - zz, opt, m/ s -0.3 (1) ____ 0.2 v 5670 tbl 05 & ( ( 3* + +& + f , 3 + # + & + + + %& & % +& (##(## + symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 8 pf c out (3) output capacitance v out = 3dv 10.5 pf 5670 tbl 08 !"" ( " + * 11* # ( $ " '# % & & ! 4, %& +& # ( $ " # @ # % & & ! 4, %& +& + # &!/ + 2 ,& /0 & (3# 4#$, # & (3 + 3 symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input hig h voltage (address, control &data i/o inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih input hig h voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input hig h voltage - zz, opt, m/ s v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v v il input low voltage - zz, opt, m/ s -0.3 (1) ____ 0.2 v 5670 tbl 06 9 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# % (2 ( " ' ) * ! symbol parameter test conditions 70t633/1s unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i li | jtag & zz input leakage current (1,2) v dd = max. , v in = 0v to v dd ___ + 30 a |i lo | output leakage current (1,3) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (1) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (1) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (1) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (1) i oh = -2ma, v ddq = min. 2.0 ___ v 5670 tbl 09 % (2 ( " ' ) * ! " , + + / ? 3 $ +*+ 2 & ( (( d+* +*+ ! , 2 ; ? / / ; " ( + +& 2 * / 3* # " 4#, " 4g * , + "$ " ( *$ ) ce "# ( ce "# ? "# ce "# ( ce "# ? "# ce h#( ce h# ? i# '# ce i# '#( ce i# '# ? j# ;>;;=; ;c; 2& 4 , % +& 3* $ & $ 11 ! 11 "# 7 ((+ 2 3 ak'7 a '4 +6 2 * 70t633/1s8 (6) com?l only 70t633/1s10 com?l & ind (6) 70t633/1s12 com?l & ind 70t633/1s15 com?l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (1) com?l s 350 475 300 405 300 355 225 305 ma ind s ____ ____ 300 445 300 395 ____ ____ i sb1 (6) standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com?l s 115 140 90 120 75 105 60 85 ma ind s ____ ____ 90 145 75 130 ____ ____ i sb2 (6) standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f = f max (1) com?l s 240 315 200 265 180 230 150 200 ma ind s ____ ____ 200 290 180 255 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com?ls210210210210 ma ind s ____ ____ 220220 ____ ____ i sb4 (6) full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com?l s 240 315 200 265 180 230 150 200 ma ind s ____ ____ 200 290 180 255 ____ ____ i zz sleep mode current (both ports - ttl level inputs) zz l = zz r = v ih f = f max (1) com?ls210210210210 ma ind s ____ ____ 220220 ____ ____ 5670 tbl 10 # + 3 #!4#$ /0 c 2 + 3 * , trst / ' ( ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 10 . " input pulse levels input rise/fall times input timing reference levels outp ut re fe rence lev els output load gnd to 3.0v / gnd to 2.5v 2ns max. 1.5v/1.25v 1.5v/1.25v figure 1 5670 tbl 11 1.5v/1.25 50 ? 50 ? 5670 drw 03 10pf (tester) data out , 5670 drw 04 20 40 60 80 100 120 140 0 160 0 0.5 1 1.5 2 2.5 3 3.5 4 ? capacitance (pf) from ac test load ? t aa / t ace (typical, ns) ! " # $ 11 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# . % (2 ( " ' ) * ! ( (# ( =% < 2&' ( + 2 % & / = k 2 $ & ( 2 3* + +& + f , 3 + ++ c , ce " # sem "# ++ ( &, ce "# sem "# ? & + ( 3 & ( ce "# %& ce "# ? "# ce "# %& ce "# ! ? "# ) & 2 & % * + !/ + 2 #!4#$ 2 4 7 ((+ 2 3 ak'7 a '4 +6 2 * . % (2 ( " ' ) * symbol parameter 70t633/1s8 (5) com?l only 70t633/1s10 com?l & ind (5) 70t633/1s12 com?l & ind 70t633/1s15 com?l only unit min. max. min. max. min. max. min. max. read cycle t rc re ad cycle time 8 ____ 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 8 ____ 10 ____ 12 ____ 15 ns t ace chip enable access time (3) ____ 8 ____ 10 ____ 12 ____ 15 ns t abe byte enable access time (3) ____ 4 ____ 5 ____ 6 ____ 7ns t aoe outp ut enab le acce ss time ____ 4 ____ 5 ____ 6 ____ 7ns t oh outp ut ho ld from add ress chang e 3 ____ 3 ____ 3 ____ 3 ____ ns t lz output low-z time chip enable and semaphore (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t lzob output low-z time output enable and byte enable (1,2) 0 ____ 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) 03.5040608ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ 0 ____ ns t pd chip disable to po we r down time (2) ____ 7 ____ 8 ____ 8 ____ 12 ns t sop semaphore flag update pulse ( oe or sem ) ____ 4 ____ 4 ____ 6 ____ 8ns t saa semaphore address access time 2 8 2 10 2 12 2 15 ns t soe semaphore output enable access time ____ 5 ____ 5 ____ 6 ____ 7ns 5670 tbl 12 symbol parameter 70t633/1s8 (5) com?l only 70t633/1s10 com?l & ind (5) 70t633/1s12 com?l & ind 70t633/1s15 com?l only unit min. max. min. max. min. max. min. max. write cycle t wc write cycle time 8 ____ 10 ____ 12 ____ 15 ____ ns t ew chip enable to end-of-write (3) 6 ____ 7 ____ 9 ____ 12 ____ ns t aw address valid to end-of-write 6 ____ 7 ____ 9 ____ 12 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 6 ____ 7 ____ 9 ____ 12 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 4 ____ 5 ____ 7 ____ 10 ____ ns t dh data ho ld time 0 ____ 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 3.5 ____ 4 ____ 6 ____ 8ns t ow outp ut active fro m end-o f-write (1,2) 3 ____ 3 ____ 3 ____ 3 ____ ns t swrd sem flag write to read time 4 ____ 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 4 ____ 5 ____ 5 ____ 5 ____ ns 5670 tbl 13 ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 12 +34 +3 + $2 !" ) ( 2 %& +& 2 , oe , ce , lb ub ( 2 %& +& 2 ' ce , oe , lb ub * d * + %& & +( 2 % & ( + k ( busy & ) %& +& ( 2 3+( + 5 , , , , 4 sem "# ce " = ++ %& ce "# ? "# ce " < %& ce "# ! ? "# t rc r/ w ce addr t aa oe ub , lb 5670 drw 06 (4) t ace (4) t aoe (4) t abe (4) t oh (2) t hz (3,4) t bdd data out busy out valid data (4) (6) . (1) t lz /t lzob ce 5670 drw 07 t pu i cc i sb t pd 50% 50% . 13 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# $2 $ ) 56 !# w " $2 $ ) ,6 ce " c! w ce ub lb "# 2 % ++ 2 & $ ce "# c! w "# ((* * % 2 +*+ ( ( & ce c! w sem c! w $ 2 2 <.< & % +*+ ) 2 & , & !/ & 2 ( 3 4 & ce sem "# ++ ( * % & & c! w "# , & ( & < 2&' ( + ( 2 %& +& 3 2 , ce c! w & ( 2 3* + +& + f , 3 + ( (# ( * % & & / = k 2 $ 7 oe "# 2 c! w + % +*+ , & % % & ( 3 & 2 @ $ % & !/ 3 +&3&d oe "# 2 c! w + % +*+ ,& d ( * &% + 3 & & + 8 ++ c , ce "# sem "# ++ ( &, ce "# sem "# ( 3 ( & + ce "# %& ce "# ? "# ce "# %& ce "# ! ? "# r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) ub , lb 5670 drw 10 (9) ce or sem (9) (7) (3) . (7) 5670 drw 11 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub , lb (3) (2) (6) ce or sem (9) (9) . . ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 14 !"$ /" $ ) 0 8 " 2 9 $ * %* 1 " ( ' . . * * " ' 8" ' 8/ " " / " "2 " "$ w 1 ce 1 be " " & $ 7 "% . " " /" "* " 2 " * *' 8" ' 8/ " . * / " "" .. ""8 . " / " 2 1 * . "* " *" * 8"& " /$ 7 "% 1" ."/ " / . '" " " 1 " ."$ w ce be " " " " " 2""&$ w 1 ce 1 be ' " 2 " "" " " '"// " & 5 * "'"8" " *""7 "5 " *4" 61"" * / " "* "'"' & """ " * 4" " 6/ /' . " " " " & " $ 7 "% " 3/ * " "* . " " ." " " $ w ' /& " 7 "5 . " * "' " &: /2 1" " ' // " '"/ / " " & 1 " "/ " " " """* " '*"" " " / "& . " 1 " /' #8/4" 6" $ ; " *4" 61 * "'*"" "$ 7 "% &." " "*" " " "" . 2 ""/ " " " * " * " " "2 " " '"/" / " & 5670 drw 08 t wc t wc t wc t ew t wp t wz t dh t dw t dw t dw t ow t wr address ce or sem (6) be n r/ w data in data out (2) (5) (5) t dh t dh (4) $2 $ ) 16 !"$ /" $ ) oe "# & ( 2 % ( &% oe ( * d # % & ( % + *e !/ % & % * 3 < 2&'1 % ++ 2 & $ ce "# be " # , c! w "# ((* * % 2 +*+ & =/l ce , be , c! w & % d+ & <.< ce , be , c! w ( & % d+ & ce sem "# ++ ( * % & & c! w "# , & ( & < 2&' ( + ) & ( 2 & +*+ + 3 ( ( + d c l % 4 & ( 2 3* + +& + f , 3 + ( (# ( * % & & / = k 2 $ ++ c , ce "# sem "# ++ ( &, ce "# sem "# ( 3 ( & + ce "# %& ce "# ? "# ce "# %& ce "# ! ? "# 15 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# 5670 drw 09 a 0 a 18 t aas t arf t arf (1) $2 ."" !"$ /" $ ) . % 2 ( ! " ' ) * ! !"$ /" $ ) ( 2 2 %& f 2 & c l l *+ symbol parameter min max unit t aas allowable address skew for rapidwrite mode ____ 1ns t arf address rise/fall time for rapidwrite mode 1.5 ____ v/ns 5670 tbl 14 ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 16 $2 ' !" $ 6 % '" " "# , ce " ce " # e ? " ? " # c & 3 ub ! lb + ( 2 & ( 2&0;;( *3 & 2&;a; & (;; & ( ( ( c! w sem 2 2 <.< c! w sem 2 2 <.< ) ,& ( & % * & &, 3 & 2 %& +& % 3 2 & ( & 2 $2 ' $ ce "# ? "# d & 3&&% +*+ & +*+ % (&% 3 c& 3 ub ! lb + ; #=; !/9 !/ '!/ $ d & ( & sem (1) 5670 drw 12 t aw t ew i/o valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd read cycle write cycle a 0 -a 2 oe valid (2) t sop t sop . t soe sem "a" 5670 drw 13 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2) . 17 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# 0'' * &2& c + ( % 2 2 , ; ( 2 l ( l % & 0''0 c busy ! s "# $; & & & % % + + ( & 2 & +, m + $, m + $ ) & & % +*+ & 3 ;a; 2 + ;; 4 & % +*+ +( ;a; + ;; 7 ((+ 2 3 ak'7 a '4 +6 2 * . % (2 ( " ' ) * ! symbol parameter 70t633/1s8 (6) com?l only 70t633/1s10 com?l & ind (6) 70t633/1s12 com?l & ind 70t633/1s15 com?l only unit min. max. min. max. min. max. min. max. busy timing (m/ s =v ih ) t baa busy access time from address match ____ 8 ____ 10 ____ 12 ____ 15 ns t bda busy disable time from address not matched ____ 8 ____ 10 ____ 12 ____ 15 ns t bac busy access time from chip enable low ____ 8 ____ 10 ____ 12 ____ 15 ns t bdc busy disable time from chip enable high ____ 8 ____ 10 ____ 12 ____ 15 ns t aps arbitration priority set-up time (2) 2.5 ____ 2.5 ____ 2.5 ____ 2.5 ____ ns t bdd busy disable to valid data (3) ____ 8 ____ 10 ____ 12 ____ 15 ns t wh write hold after busy (5) 6 ____ 7 ____ 9 ____ 12 ____ ns busy timing (m/ s =v il ) t wb busy input to write (4) 0 ____ 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 6 ____ 7 ____ 9 ____ 12 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 12 ____ 14 ____ 16 ____ 20 ns t ddd write data valid to re ad data de lay (1) ____ 12 ____ 14 ____ 16 ____ 20 ns 5670 tbl 15 . % (2 ( " ' ) * ! symbol parameter 70t633/1s8 (4) com?l only 70t633/1s10 com?l & ind (4) 70t6331s12 com?l & ind 70t633/1s15 com?l only min. max. min. max. min. max. min. max. sleep mode timing (zzx=v ih ) t zzs sleep mode set time 8 ____ 10 ____ 12 ____ 15 ____ t zzr sleep mode reset time 8 ____ 10 ____ 12 ____ 15 ____ t zzpd sleep mode power down time (5) 8 ____ 10 ____ 12 ____ 15 ____ t zzpu sleep mode power up time (5) ____ 0 ____ 0 ____ 0 ____ 0 5670 tbl 15a ( 2 & ( 3& & ( & * ( + , +-. ,%& /0 , int , ! s & ( &( 11 $ + 2 ( +(( & 3 * + 3 2 ( & 2 & % * + !/ + 2 #!4#$ 2 ) 7 ((+ 2 3 ak'7 a '4 +6 2 * 4 & ( 2 3* + +& + f , 3 + ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 18 $2 $ + 33 !" " busy /# s 7 * $2 $ + busy /# s 7 * ( 3 ( 3& busy =#?$ ?c$ busy ;a; 3 +6 2 c! w , busy 2 <.< * & ( & & & % % 2 ! s "# =#?$ ce " ce " # e ? " ? " # oe "# & 2 ) ! s "# $, busy & & ( busy "# busy &% 3 4 ( 2 & ( 2&0;;( *3 && 2&0;a; & (;; 5670 drw 14 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa . 5670 drw 15 r/ w "a" busy "b" t wb (3) r/ w "b" t wh (1) (2) t wp . 19 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# . % (2 ( " ' ) * ! $2 busy . " ) ce /# s 7 * $2 busy . ) " ) ."" / /# s 7 * ( 2 & ( 2& 0 no ( * 3 & & 2& 0 nao & ( no , & busy 2 % 3 & 3 & 2 %& +& busy % 3 ce "# %& ce "# ? "# ce "# %& ce "# ! ? "# ) ce " oe " lb " ub "# ? "# 5670 drw 16 addr "a" and "b" addresses match ce "a" (3) ce "b" (3) busy "b" t aps t bac t bdc (2) . 5670 drw 17 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" 70t633/1s8 (3) com?l only 70t633/1s10 com?l & ind (3) 70t633/1s12 com?l & ind 70t633/1s15 com?l only symbol parameter min.max.min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 8 ____ 10 ____ 12 ____ 15 ns t inr interrupt reset time ____ 8 ____ 10 ____ 12 ____ 15 ns 5670 tbl 16 ( 2 & ( 3& & 2 & % * + !/ + 2 #!4#$ 2 7 ((+ 2 3 ak'7 a '4 +6 2 * ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 20 $2 ( 2 & ( 2& 0 no ( * 3 & & 2& 0 nao & ( no c & 3 ce "# ( ce "# ? "# ce "# ( ce "# ! ? "# ) ( 2 %& +& 3 2 ce c! w $ 4 ( 2 %& +& 3 2 ce c! w $ ' ( busy " busy "# ce " = ( ce "# ? "# busy "# , & +& 2 busy "# , & +& 2 ) int int ( 3 f %' 4 &, kkkk kkk? 5670 drw 18 addr "a" interrupt set address ce "a" (3) r/ w "a" t as t wc t wr (4) (5) t ins (4) int "b" (2) . 5670 drw 19 addr "b" interrupt clear address ce "b" (3) oe "b" t as t rc (4) t inr (4) int "b" (2) . left port right port function r/ w l ce l oe l a 18l -a 0l (5) int l r/ w r ce r oe r a 18r -a 0r (5) int r llx7ffffxxxx x l (2) set right int r flag x x x x x x l l 7ffff h (3) reset right int r flag xxx x l (3) l l x 7fffe x set left int l flag x l l 7fffe h (2) x x x x x reset left int l flag 5670 tbl 17 21 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# 2 "/ "/ " " " 1 3 "" * " " . / "" " ** & " *" / / ." " ' ce & ce 5+ " " / / " "" * "" " 2 "" " "'* / " "4 ce <:=:6&7 " ' 1 " " " ** * ""& ." " " ". " 1** " 4* ' * " 6 " "& ." " " " . 4 int = 6 "/" " "/ "" ** " ;;;+4:+>61/ / " . ce c <$ w c <- = " " ' & ." " " " " " . " ;;;+/ ce = < oe = <- = 1$ w ? 9" ?& , 8/ 1" " " " ". 4 int c 6 "/ " ." "/ "" ** " ;;;;4:+>6" " " " . 4 int c 61" " "* " "** " ;;;;& *4 ' "6";;;+ ;;;;4 ;;;; ;;;+. 6 . " ' #$% " &." " " . " " 1 " ;;;+;;;; " * ' 1' " " ." * ** &$. " " ' . " " " " & * ."" busy . 0 busy busy 3& %& & + 2 ( a& %& + 2 busy & ! &' , / & busy * & 3 % ;=; & & % 3 & 3 & ;<; & & 3+ ( 3 & 3 & (, & busy busy " =/l % busy busy + 3 =/l ( * l & * 2%& busy 2=/l2 + 2 + & l & 2& * 2 %& busy 2 =/l 2 + 2 + & ) +( % 3 ' 4 ce "=( ce "# ? "# ce "<( ce "# ! ? "# * %0 ' '8 & 3 d+ * & 2& ( & & ! & 2& ( & 2 % !/ ( !/9 !/ '!/ $ & 2& ( & 3* ' ce "# , ? " sem "# ++ & ( & c & ( & c !l & 3 inputs outputs function ce l (5) ce r (5) a 0l -a 18l (4) a 0r -a 18r busy l (1) busy r (1) x x no match h h normal hxmatchh hnormal xhmatchh hnormal ll match (2) (2) write inhibit (3) 5670 tbl 18 functions d 0 - d 17 left d 0 - d 17 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5670 tbl 19 ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 22 ) 9 @ , 2 / " ""' " " ."$% 2 "* " ""*" *&" / ." "/ " " " """$% a@ b& busy "' " " " " " " " " * "&./ " " '""*". * " "" 2 busy " 1"/ " " " " 2""/ ". * & . busy " c ' . " & * "*' . " 3$" busy " "" " busy " " " " . "2" . " &."/ " ' ". " . busy " ' 1" busy ' ' ' " " 2 * / ""% s &3 2* " busy " / " ' " " &d * " ' **'" " busy :=:&. 1 "/ " " ' 2"" "'" " busy . "" ",37& busy " " " $% *" * 1 " " " " c " " "& ."$% ' "1"" busy " . " " c " ." d"& &" /" / "& *" 2 1' " ' * "'2 . busy . " ' " ". *"*" '. " " / " ' " "/ ""$ w &; " ' 2" " * " " " / " ' " "" " 2& ' " * ." ! " 5%3##"" $%/ " " " "" ' * . &. / " " ." " ." ! "$%" * 2 2 " " . . " . '""* e ."/ &* 1 " * ' ' " ' " " " . * " ." ! "$% " & ! "$%." ." " *1/ "' " " ' * " " . " & * "" " " 2 " " ." " / /" " * ." " "& @ " " " . " " " 5%3##"" $% ' . * / """ ""*" */ "" ' . " . *" * " / " .1 * " $+ 7$+ .1 * " &#* " " " *' " " *' '" "* *" 2 . " " * " ." ! "$%&2 2 " *" / / ." " ' ce 5+ 1" ! "$% ' 1 sem 1"* ' & ce 1 5+ 1 sem " / / " "" * "" " 2 "" " "' * / " "& #"*/ '" " " * " " " 2 "* / ."/ " ."/ " 2&"* '. " . * . * .. ' " / * ." 1/ 2 8 "* * / " " c * ** & # ."/ 8 '"/ .. "* * * "*. ' "' * "" " ' " 2 . " & " "* . " " " / 1" / " "* " " . ' " "* " " & 2" . * " ""* ** *" . / ' " " ""/ """ 2 " & 2" '*f 2" 2 "*& :+ ' $ * " . " " / " ." ! "$%& " ' " . 1 " 81. * "" " " " """ & * 2 / " . *"*" a 8! " &b" *" 1 """ .* " " 8 " "" & . " ." /" " " 1 " c """ 8'"" " " & " $" %0 + ) 9 /#' 2 .) 7 $% / "/ busy 1 *" " " / ."$% / 2 busy " 1" " """ " & *' . 2" ' "* " *" " busy / " ' " & " $%" busy " " ." " *" 4% s <- < 61" busy " ." " 24% s <- = 6 / ; & ."/ * *" "/ / / "1 " "/ " *" " busy ." " *" " busy " . " & / ' ""/ " " . * ". " ./ ' ""/ " " . *" " ". " " " ."/ & busy ' " " *" ' " ' ! "#$%& 5670 drw 20 master dual port ram busy r ce 0 master dual port ram busy r slave dual port ram busy r slave dual port ram busy r ce 1 ce 1 ce 0 a 19 busy l busy l busy l busy l . 23 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# 2 . " "" " " ' "&. "/ . 1 " " * " 2 " &. "/ " . "" " " 1 "" * """ " "" " . "1"" 8 " & ." " " " c " "" * e "" * 2 " c " . "" * " . * " "8 ""*" " " . " " 8 2 " " "" c & 3 " " c "" 81" ." " & * . " 2,37&" 8 c "' / " g " * " /"* / " " "" " & "* . / " " "** . *" ! "$% & ' / " " sem 4/ " ". "* . 6 " " " 4 1 ce 15+ 1$ w lb ub 6"/ ' " #"" $%&+ .". c / ' ' " " h &7 "* 1 ." " .. "& 7/ " " * 1 " &. / 2 / "" " * " 1"". / '"" g "" " " 4 "' -6& "* / '* . '" / "g & 7 / "" " "* " . *"* 1" . / '"" . ' " 4 * c " . *" " 6" '/ """ '' " & . """" / ' " / "g " * 'c " 8 " / " . * " " /" *8 * . . " ** " &4" " ." ." . / " &6g / "" " "* " . *" " / '" " * c " " . "" " "* . ' ". " & 7* . 1 "2 " "' " "". "" "' ". " g g . * 1" sem 1 be 1 oe " ' " 2&4! . " "' 6&; " * 1 " 2 " " e " " " /"" 9 * "4 sem 1 be 6 " "' 4 oe 6 " 2& 2" /"* . * "" "* . " / " . *" " & c 7$+ $+* "' '"* " " "" "* 2 "" / & c " " '""*" " / " g " * " &."* 1 "* c " " / " g 1""* . / 1. "/ " / 2 .'" 'c " 4' -6&* 1 * / " g " " ." " " . * " & 3 'c " 1" / 2 ."" "/ "" . " "" " / * " 2 " c " &%/ 1 . " " ""*"" / " g " "** . "/ . 1/ '2 . '" . """ / ' . *""* " " 'c " & : c . $+ 7$+ ' "1"* "" ' * 2 "'"/" / " & " * """ """. * c "* "' . /' " " '/ " " "* " & . " " ' 8 "" * * ."* . ; )&/ * c " " . " * . &7 2 " . "" "g " "* . / . " ." * . ,37" " :=:& " / " " / """ "** c " " & . " " * c " " ' / "" " g "*" *1"* . / . 2 " " " / "" " " . " c " " & " . / /",37 " "* c " " / "" " & ; * " " " " ""1 . * c " " / c " " " 1"" "* " / "" " ""* c " " & " .* " * /' " c " " 8'""*" " / "g " """*" *& * " 2 " ' *& . * " c " *1" """ 2"" 8&. "" " *8 " c "1". " " *8" c "/ 2"" 8&. ' " c " 2""*" *1" *"/ ' ' " *" " " " & 3 " "" ' "/ * "" * " " "" " &/ " / . ** " c 1 .* * * " "1 ."/ & " g" . " * " " *" * " ' 2 " " g" *" / &# * c " . / " g * " ' " " 1 * ' " 2 / "" " "* " " g" . * ' " " "" " / ' . /& % &'( ) "* d 5670 drw 21 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 24 i z z i d d 5 6 7 0 d r w 2 2 , z z t z z p d c e 0 d a t a v a l i d a d d r e s s t z z r n o n e w r e a d s o r w r i t e s a l l o w e d n o r m a l o p e r a t i o n n o r m a l o p e r a t i o n s l e e p m o d e n o r e a d s o r w r i t e s a l l o w e d v a l i d d a t a a d d r e s s t z z s t z z p u $2 ' /" ? # ! ( 2 ( = c 2& 25 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# . 3* 2 k 2 2 c ? + + & +( ) -. ++ & & 4 -. + 3 ( ; .< ' tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5670 drw 23 x + " + + , , c + " + + / ; .< . % 70t633/1 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5670 tbl 20 ' /" c / " " / / * ' " "& * ' " " " 2 & * " 1"ii /&7ii 1" "/ " * / "/ 2" /" ' / *" & * " * ** " ""* . " jd * 3 " 1d $ 7 " /# % & ; ." * " * ." 2 . * * 4" " 61/ / " " /&./ " " " 1 " ** * ' "&- " ." ". *"$% "' " ** " ." ii "4 " ' 6& * "$% " *" " " . " " " ' .. & " "/ * i""/ * & " /" " 1' ""$%/ "' " / " . * / "& ! !" "#$%! & &#& '( " & #$ # )!** #$ * #&" '# 26 " ! instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x33b (1) defines idt part number 70t633 idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5670 tbl 21 ') instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. clamp 0011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5670 tbl 23 + " + + / + " + + , , trst & a * + + = 2 2 a =$ & + 3 & %3 %%% +($, 3* + + 2 * + ' ! '= register name bit size instruction (ir) 4 bypass (byr) 1 id entific atio n (idr) 32 boundary scan (bsr) note (3) 5670 tbl 22 + 27 ! !" "#$%! & &#& '( " & #$# )!** #$* #&" '# (" 5670 drw 24 a power 999 speed a package a process/ temperature range blank i commercial (0 cto+70 c) industrial (-40 cto+85 c) bc dd bf 256-ball bga (bc-256) 144-pin tqfp (dd-144) 208-ball fpbga (bf-208) 8 10 12 15 s standard power xxxxx device type 9mbit (512k x 18) 2.5v asynchronous dual-port ram 4mbit (256k x 18) 2.5v asynchronous dual-port ram 70t633 70t631 idt speed in nanoseconds commercial only (1) commercial & industrial (1) commercial & industrial commercial only . & 2 2 ( 62 ++& 2*,+ :)> ) j " "" j ! (5 / *' " 5+ " 5 " " ' !(0"5 / *' . 1 k "5+ " 5 " " ' !(1 1 1 k. " """ """ 2 ' @;@5 8 ! 5 " " / ! 1 k 5" * *' " "5+ " 5 " " ' ! " " " "5$5 + " 5 " " ' ! " " "72. * .$5 / ! )" " * 72. * .#* $." 7 " * 1+ " # / ! k "*" ." " . *" ! 1 )k $ 7 "% 7 "5 ""/2. * j ! 5 "" " &- % & ) )j $* 2! * "" . *" "" )# 2 5 8 - $ ) )) ))() #l 15( .j)) ! ": m "& * ///& "& * 7 ((+ 2 3 ak'7 a '4 +6 2 * |
Price & Availability of 70T631S10BCI
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