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2:1 differential-to-lvpecl multiplexer ics858018 idt? / ics? lvpecl multiplexer 1 ics858018ak rev. a october 3, 2008 general description the ics858018 is a high performance 2:1 differential-to-lvpecl multip lexer and is a member of the hiperclocks? family of high performance clock solutions from idt. the ics858018 differential inputs have internal termination resistors and when used in conjunction with the v t0 /v t1 pins, allow the inputs to interface with several differential signal types. the ics858018 is packaged in a small, 3mm x 3mm vfqfn package, making it ideal for use on space-constrained boards. features ? one lvpecl output ? inx/ninx pairs can accept the fo llowing differential input levels: lvpecl, lvds, cml ? maximum output frequency: 2ghz ? propagation delay: 700ps (maximum) ? part-to-part skew: 250ps (maximum) ? supply voltage range: (lvpecl) v cc = 2.375v to 3.63v, v ee = 0v (ecl) v cc = 0v, v ee = -3.63v to -2.375v ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s ics858018 16-lead vfqfn 3mm x 3mm x 0.925 mm package body g package top view pin assignment block diagram 0 1 q nq in0 v t0 nin0 in1 v t1 nin1 sel 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 in0 nin0 in1 nin1 q v ee v ee nq v t1 sel nc v cc v ee v ee v cc v t0
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 2 ics858018ak rev. a october 3, 2008 table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values table 2. pin characteristics table 3. truth table number name type description 1 in0 input non-inverting differential lvpecl clock input. 2 nin0 input inverting differ ential lvpecl clock input. 3 in1 input non-inverting differential lvpecl clock input. 4 nin1 input inverting differ ential lvpecl clock input. 5, 16 v t1, v t0 input input for termination. both in and nin inputs are terminated to this pin. see application information section, differential input with built-in 50 ? termination interface. 6 sel input pullup select pin. lvcmos/lvttl interface levels. 7 nc unused no connect. 8, 13 v cc power power supply pins. 9, 12 nq, q output differen tial output pair . lvpecl/ecl interface levels. 10, 11, 14, 15 v ee power negative supply pins. symbol parameter test conditio ns minimum typical maximum units r pullup input pullup resistor 37 k ? inputs outputs in0 nin0 in1 nin1 sel q nq 01xx001 10xx010 xx01101 xx10110
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 3 ics858018ak rev. a october 3, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v10% or 2.5v5%, v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 3.3v10% or 2.5v5%, v ee = 0v, t a = -40c to 85 c item rating supply voltage, v cc -0.5v to + 4.0v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma input current, in/nin +50ma v t current, i vt +100ma operating temperature range, t a -40c to 85c storage temperature, t stg -65 c to 150 c package thermal impedance, ja (junction-to-ambient) 88.5 c/w (0 mps) symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.63 v i ee power supply current 21 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current v cc = v in = 3.63v or 2.625v 10 a i il input low current v cc = 3.63v or 2.625v, v in = 0v -150 a
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 4 ics858018ak rev. a october 3, 2008 table 4c. dc characteristics, v cc = 3.3v10% or 2.5v5%, v ee = 0v, t a = -40c to 85 c note 1: guaranteed by design. table 4d. lvpecl dc characteristics, v cc = 3.3v10% or 2.5v5%, v ee = 0v, t a = -40c to 85 c note 1: outputs terminated with 50 ? to v cc ? 2v. ac electrical characteristics table 3. lvpecl ac characteristics, v cc = 3.3v10% or 2.5v5%, v ee = 0v, t a = -40c to 85c all parameters characterized at 1ghz unless otherwise noted t a , ambient temperature applied using forced air flow. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between inputs measured to the same out put at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the output s are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units r in differential input resist ance inx/ninx in to v t 40 50 60 ? v ih input high voltage inx/ninx 1.2 v cc v v il input low voltage inx/ninx 0 v ih ? 0.15 v v in input voltage swing 0.15 2.8 v v diff_in differential input vo ltage swing 0.3 3.4 v in input current; note 1 inx/ninx 35 ma symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.005 v v ol output low voltage; note 1 v cc ? 1.78 v v out output voltage swing 0.6 1.0 v v diff_out differential output voltage swing 1.2 2.0 v parameter symbol test conditions minimum typical maximum units f max output frequency v out 450mv 2 ghz t pd propagation delay, differential; note 1 in0 or in1-to-q 350 700 ps sel-to-q 0.175 1.3 ns t sk(i) input skew; note 2 35 ps t sk(pp) part-to-part skew; note 3, 4 250 ps t r / t f output rise/fall time 20% to 80% 75 375 ps
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 5 ics858018ak rev. a october 3, 2008 parameter measureme nt information output load ac test circuit part-to-part skew single-ended & differential input voltage swing differential input level propagation delay output rise/fall time scope qx nqx lvpecl v ee 2v -1.63v to -0.375v v cc t sk(pp) part 1 part 2 qx nqx qy nqy v in , v out 800mv (typical) v diff_in , v diff_out 1600mv (typical) v cmr cross points v pp inx ninx v cc v ee t pd nq q inx ninx 20% 80% 80% 20% t r t f v swing nq q
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 6 ics858018ak rev. a october 3, 2008 parameter measurement in formation, continued input skew application information recommendations for unused input pins inputs: lvcmos control pins the control pin has an internal pullup; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) nin1 in1 nq q nin0 in0
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 7 ics858018ak rev. a october 3, 2008 3.3v differential i nput with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, lvhstl, cml, sstl and other differential signals. both signals must meet the v in and v ih input requirements. figures 1a to 1d show interface examples for th e hiperclocks in/nin input with built-in 50 ? terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 1a. hiperclocks in/nin input with built-in 50 ? driven by an lvds driver figure 1c. hiperclocks in/nin input with built-in 50 ? driven by a cml driver figure 1b. hiperclocks in/nin input with built-in 50 ? driven by an lvpecl driver figure 1d. hiperclocks in/nin input with built-in 50 ? driven by an sstl driver in nin vt receiver with built-in 50 ? lvds 3.3v 3.3v zo = 50 ? zo = 50 ? in nin vt cml ? open collector receive r with built-in 50 ? 3.3v 3.3v zo = 50 ? zo = 50 ? in nin vt receive r with built-in 50 ? r1 50 lvpecl 3.3v 3.3v zo = 50 ? zo = 50 ? sstl r1 25 r2 25 in nin vt receiver with built-in 50 ? 3.3v 3.3v zo = 50 ? zo = 50 ?
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 8 ics858018ak rev. a october 3, 2008 2.5v lvpecl input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml, sstl and other differential signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the hiperclocks in/nin with built-in 50 ? termination input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use thei r termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. hiperclocks in/nin input with built-in 50 ? driven by an lvds driver figure 2c. hiperclocks in/nin input with built-in 50 ? driven by a cml driver figure 2b. hiperclocks in/nin input with built-in 50 ? driven by an lvpecl driver figure 2d. hiperclocks in/nin input with built-in 50 ? driven by an sstl driver in nin vt receiver with built-in 50 ? lvds 3.3v or 2.5v 2.5v zo = 50 ? zo = 50 ? in nin vt cml receive r with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ? in nin vt receiver with built-in 50 ? r1 18 lvpecl 2.5v 2.5v zo = 50 ? zo = 50 ? sstl r1 25 r2 25 in nin vt receiver with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ?
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 9 ics858018ak rev. a october 3, 2008 2.5v differential i nput with built-in 50 ? termination unused input handling to prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in figure 3a. figure 3a. unused input handling 3.3v differential i nput with built-in 50 ? termination unused input handling to prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in figure3b. figure 3b. unused input handling receiver with built-in 50 ? in nin vt 2.5v 2.5v r2 680 r1 680 receiver with built-in 50 ? in nin vt 3.3v 3.3v r2 1k r1 1k
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 10 ics858018ak rev. a october 3, 2008 termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 11 ics858018ak rev. a october 3, 2008 termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 12 ics858018ak rev. a october 3, 2008 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of am kor?s thermally/electrically enhance leadframe base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 13 ics858018ak rev. a october 3, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics858018. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics858018 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.63v * 21ma = 76.23mw power (outputs) max = 27.83mw w/loaded output pair total power_ max = 76.23mw + 27.83mw = 104.06mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 88.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.0104w * 88.5c/w = 94.2c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 88.5c/w 77.3c/w 69.4c/w
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 14 ics858018ak rev. a october 3, 2008 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 1.005v (v cc_max ? v oh_max ) = 1.005v for logic low, v out = v ol_max = v cc_max ? 1.78v (v cc_max ? v ol_max ) = 1.78v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 1.005v)/50 ? ] * 1.005v = 20mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = [(2v ? 1.78v)/50 ? ] * 1.78v = 7.83mw total power dissipation per output pair = pd_h + pd_l = 27.83mw v out v cc v cc - 2v q1 rl 50
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 15 ics858018ak rev. a october 3, 2008 reliability information table 7. ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ics858018 is: 109 pin compatible with sy58011u package outline and package dimensions package outline - k suffix for 16 lead vfqfn table 8. k package dimensions for 16 lead vfqfn reference document: jede c publication 95, mo-220 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 88.5c/w 77.3c/w 69.4c/w top vie w index a re a d cham fer 4x 0.6 x 0.6 max optional anvil singula t ion a 0. 0 8 c c a3 a1 seating plan e e2 e2 2 l (n -1)x e (r e f.) (ref.) n & n eve n n e d2 2 d2 (ref.) n& n od d 1 2 e 2 (typ.) if n & n are eve n (n -1)x e (re f.) b thermal bas e n or de d de de e all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.0 a1 00.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic d, e 3.0 d2, e2 1.00 1.80 l 0.30 0.50 n d n e 4.0
ics858018 2:1 differential-to-lvpecl multiplexer idt? / ics? lvpecl multiplexer 16 ics858018ak rev. a october 3, 2008 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 858018ak 018a 16 lead vfqfn tube -40 c to 85 c 858018AKT 018a 16 lead vfqfn 2500 tape & reel -40 c to 85 c 858018aklf 18al ?lead-free? 16 lead vfqfn tube -40 c to 85 c 858018aklft 18al ?lead-free? 16 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
ics858018 2:1 differential-to-lvpecl multiplexer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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