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2:1 lvds multiplexer with 1:2 fanout and internal termination ics889474 idt ? / ics ? lvds multiplexer 1 ics889474ak rev. a october 22, 2008 g eneral d escription the ics889474 is a high speed 2-to-1 differential multiplexer with integrated 2 output lvds fanout buffer and internal termination and is a member of the hiperclocks ? family of high performance clock solutions from idt. the ics889474 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the internally terminated differential input and v ref _ ac pins allow other differential signal families such as lvpecl, lvds, lvhstl and cml to be easily interfaced to the input with minimal use of external components. the ics889474 is packaged in a small 4mm x 4mm 24-pin vfqfn package which makes it ideal for use in space-constrained applications. f eatures ? two differential lvds outputs ? inx, ninx pair can accept the following differential input levels: lvpecl, lvds, lvhstl, cml ? 50 internal input termination to v t ? maximum output frequency: 2ghz (maximum) ? additive phase jitter, rms: 0.06ps (typical) ? output skew: 20ps (maximum) ? propagation delay: 700ps (maximum) ? 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-complaint packages b lock d iagram p in a ssignment hiperclocks? ic s in0 v t0 nin0 q0 nq0 q1 nq1 v ref_ac0 ics889474 24-lead vfqfn 4mm x 4mm x 0.925mm package body k package top view 50 50 50 50 0 1 mux sel gnd gnd nc sel gnd v dd v dd in1 vt1 v ref _ ac 1 nin1 v dd 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 q0 nq0 v dd v dd q1 nq1 v dd nin0 v ref _ ac 0 vt0 in0 v dd in1 v t1 nin1 v ref_ac1
idt ? / ics ? lvds multiplexer 2 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. t ruth t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r p u l l u p r o t s i s e r p u l l u p t u p n i 5 2k s t u p n is t u p t u o 0 n i0 n i n1 n i1 n i nl e s1 q : 0 q1 q n : 0 q n 01xx001 10xx 0 10 xx 0 1 10 1 xx 10 1 10 r e b m u ne m a ne p y tn o i t p i r c s e d , 9 , 6 , 1 , 3 1 , 0 1 4 2 , 9 1 v d d r e w o p. s n i p y l p p u s e v i t i s o p 0 2 , 21 n i n , 0 n i nt u p n i0 5 . s t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v o t n o i t a n i m r e t t u p n i l a n r e t n i t . , 3 1 2 v , 0 c a _ f e r v 1 c a _ f e r t u p t u o. s n o i t a c i l p p a d e l p u o c - c a r o f e g a t l o v e c n e r e f e r 2 2 , 4v , 0 t v 1 t t u p n i. s t u p n i n o i t a n i m r e t 3 2 , 51 n i , 0 n it u p n i0 5 . s t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n v o t n o i t a n i m r e t t u p n i l a n r e t n i t . 8 , 70 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 1 , 1 11 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 1 , 4 1d n gr e w o p. d n u o r g y l p p u s r e w o p 5 1l e st u p n ip u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s t u p n i 6 1c nd e s u n u. t c e n n o c o n : e t o n p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r
idt ? / ics ? lvds multiplexer 3 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination t able 4a. p ower s upply dc c haracteristics , v dd = 2.5v 5%; t a = -40c to 85c a bsolute m aximum r atings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, i o (lvds) contin uous current 10ma surge current 15ma input current, inx, ninx 50ma v t current, i vt 100ma input sink/source, i ref_ac 0.5ma operating temperature range, t a -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 49.5c/w (0 mps) (junction-to-ambient) t able 4b. lvcmos/lvttl dc c haracteristics , v dd = 2.5v 5%; t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v dd = 2.5v 5%; t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 8a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 7 . 1v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 07 . 0v i h i t n e r r u c h g i h t u p n iv d d v = n i v 5 2 6 . 2 =5a i l i t n e r r u c w o l t u p n iv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n i e c n a t s i s e r t u p n iv - o t - n i t t v - o t - n i5 40 55 5 r n i _ f f i d e c n a t s i s e r t u p n i l a i t n e r e f f i dx n i n , x n i0 90 0 10 1 1 v h i e g a t l o v h g i h t u p n ix n i n , x n i2 . 1v d d v v l i e g a t l o v w o l t u p n ix n i n , x n i0v n i 1 . 0 ?v v n i g n i w s e g a t l o v t u p n ix n i n , x n i1 . 0v d d v v n i _ f f i d l a i t n e r e f f i d g n i w s e g a t l o v t u p n i x n i n , x n i2 . 0v v n i _ t v - o t - n i t x n i n , x n i8 2 . 1v v c a _ f e r e g a t l o v e c n e r e f e r t u p t u ov d d 4 . 1 ?v d d 3 . 1 ?v d d 2 . 1 ?v
idt ? / ics ? lvds multiplexer 4 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination t able 4d. lvds dc c haracteristics , v dd = 2.5v 5%; t a = -40c to 85c t able 5. ac c haracteristics , v dd = 2.5v 5%; t a = -40c to 85c l o b m y sr e t e m a r a pn o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 4s b p g 1 : 0 q n / 1 : 0 q2z h g t d p , y a l e d n o i t a g a p o r p 1 e t o n ; ) l a i t n e r e f f i d ( q - o t - n i0 0 40 0 7s p q - o t - l e s0 5 20 0 6s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 2s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 2s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b , n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 5 e t o n , z h m 2 5 . 5 5 1 z h m 0 2 ? z h k 2 1 6 0 . 0s p _ x u m n o i t a l o s i n o i t a l o s i x u m 5 5b d t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 70 2 2s p t a d e z i r e t c a r a h c e r a s r e t e m a r a p l l a : e t o n . d e t o n e s i w r e h t o s s e l n u z h g 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n . k c o l c t u p n i e n o y l n o g n i v i r d : 5 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v t u o g n i w s e g a t l o v t u p t u o 0 4 30 0 4v m v t u o _ f f i d g n i w s e g a t l o v t u p t u o l a i t n e r e f f i d 0 8 60 0 8v m v m c o e g a t l o v e d o m n o m m o c t u p t u o 0 1 . 15 3 . 1v v m c o e g a t l o v e d o m n o m m o c n i e g n a h c 0 5 -0 5v m
idt ? / ics ? lvds multiplexer 5 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination a dditive p hase j itter additive phase jitter @ 155.52mhz (12khz to 20mhz) = 0.06ps typical the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. ssb p hase n oise dbc/h z o ffset f rom c arrier f requency (h z )
idt ? / ics ? lvds multiplexer 6 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew p art - to -p art s kew o utput r ise /f all t ime p ropagation d elay gnd nin[0:1] v dd in[0:1] scope qx nqx lv d s 2.5v5% power supply +? float gnd t sk(pp) t sk(o) nqx qx nqy qy pa rt 1 pa rt 2 nqx qx nqy qy 20% 80% 80% 20% t r t f v od t pd nin0, nin1 q0, q1 nq0, nq1 in0, in1 v ih cross points v in v il v dd q0, q1 nq0, nq1
idt ? / ics ? lvds multiplexer 7 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination s ingle e nded & d ifferential i nput v oltage s wing v in , v out 400mv (typical) v diff_in , v diff_out 800mv (typical) o ffset v oltage s etup ? ? ? 100 out out lv d s dc input v od / v od v dd out out lvds dc input ? ? ? v os / v os v dd d ifferential o utput v oltage s etup
idt ? / ics ? lvds multiplexer 8 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination a pplication i nformation lvpecl i nput with b uilt -i n 50 t erminations i nterface the in /nin with built-in 50 terminations accepts lvds, lvpecl, cml and other differential signals. the signal must meet the v pp and v cmr input requirements. figures 1a to 1e show interface examples for the hiperclocks in/nin input with built-in 50 terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. f igure 1a. h i p er c lock s in/nin i nput with b uilt - in 50 d riven by an lvds d river f igure 1b. h i p er c lock s in/nin i nput with b uilt - in 50 d riven by an lvpecl d river in nin vt 2. 5v lvds 3.3v or 2.5v zo = 50 ohm zo = 50 ohm receiver with built-in 50 ohm zo = 50 ohm receiver with built-in 50 ohm zo = 50 ohm in ni n vt 2.5v 2.5v r1 18 2.5v lvpecl f igure 1e. h i p er c lock s in/nin i nput with b uilt - in 50 d riven by an sstl d river f igure 1c. h i p er c lock s in/nin i nput with b uilt - in 50 d riven by a cml d river f igure 1d. h i p er c lock s in/nin i nput with b uilt - in 50 d riven by a cml d river with b uilt -i n 50 p ullup zo = 50 ohm 2.5v zo = 50 ohm in nin vt receiver with built-in 50 ohm 2.5v cml - open collector in nin vt receiver with built-in 50 ohm 2.5v zo = 50 ohm zo = 50 ohm cml - built-in 50 ohm pull-up 2.5v 2.5v 2.5v sstl r1 25 r2 25 in vt nin receiver with built-in 50 zo = 50 ohm zo = 50 ohm
idt ? / ics ? lvds multiplexer 9 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination i nputs : in/nin i nputs for applications not requiring the use of the differential input, both in and nin can be left floating. though not required, but for additional protection, a 1k resistor can be tied from in to ground. r ecommendations for u nused o utput p ins f igure 2. t ypical lvds d river t ermination 2.5v lvds d river t ermination figure 2 shows a typical termination for lvds driver in characteristic impedance of 100 differential (50 single) 2. 5v 100 ohm differential transmission line 2. 5v lvds_driv er r1 100 + - 100 differential transmission line transmission line environment. for buffer with multiple lvds driver, it is recommended to terminate the unused outputs. o utputs : lvds o utputs all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, there should be no trace attached. f igure 3. u nused i nput h andling 2.5v d ifferential i nput with b uilt -i n 50 t ermination u nused i nput h andling to prevent oscillation and to reduce noise, it is recommended to have pull up and pull down connect to true and compliment of the unused input as shown in figure 3. in ni n vt 2. 5v r2 680 receiver with built-in 50 ohm 2.5v r1 680
idt ? / ics ? lvds multiplexer 10 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination f igure 4. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p at h in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base pac kage, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? lvds multiplexer 11 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination ja vs. 0 velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 49.5c/w 43.3c/w 38.8c/w t able 6. t hermal r esistance ja for 24- pin vfqfn, f orced c onvection p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics889474. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics889474 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.625v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 2.625v * 80ma = 210mw ? power dissipation at built-in terminations: assume the input is driven by a 2.5v sstl driver as shown in figure 1e and estimated approximately 1.75v drop across in and nin. total power dissipation for the two 50 built-in terminations is: (1.75v) 2 / (50 + 50 ) = 30.6mw input pair for both inputs is 2 * 30.6mw = 61.2mw total power _max (2.625v, with all outputs switching) = 210mw + 61.2mw = 271.2mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature i n order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 49.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.271w * 49.5c/w = 98.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
idt ? / ics ? lvds multiplexer 12 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination r eliability i nformation t ransistor c ount the transistor count for ics889474 is: 367 pin compatible with sy89474u t able 7. ja vs . a ir f low t able for 24 l ead vfqfn ja vs. 0 velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 49.5c/w 43.3c/w 38.8c/w
idt ? / ics ? lvds multiplexer 13 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination p ackage o utline - k s uffix for 24 l ead vfqfn t able 8. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 4 2 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 6 n e 6 d 4 2 d 0 3 . 25 5 . 2 e 4 2 e 0 3 . 25 5 . 2 l 0 3 . 00 5 . 0 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8 below.
idt ? / ics ? lvds multiplexer 14 ics889474ak rev. a october 22, 2008 ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated de vice technolo gy, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt prod uct for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t k a 4 7 4 9 8 8 a 4749 8n fqfvdael4 2e bu tc 58otc04- t k a 4 7 4 9 8 8 a 4749 8n fqfvdael4 2l eer&epat005 2c 58otc04- f l k a 4 7 4 9 8 8 l a474 9" eerf-dael"nfqfvdael4 2e bu tc 58otc04- t f l k a 4 7 4 9 8 8 l a474 9" eerf-dael"nfqfvdael4 2l eer&epat005 2c 58otc04- . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
ics889474 2:1 lvds multiplexer with 1:2 fanout and internal termination innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia integrated device technology idt (s) pte. ltd. 1 kallang sector, #07-01/06 kolam ayer industrial park singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brand s, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa japan nippon idt kk sanbancho tokyu bld. 7f, 8-1 sanbancho chiyoda-ku, tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax)

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