 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8138 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 low distortion differential adc driver functional block diagram 1 2 3 4 8 7 6 5 ad8138 nc v ocm ?ut v+ nc = no connect +in v ?n +out features easy to use single-ended-to-differential conversion adjustable output common-mode voltage externally adjustable gain low harmonic distortion C94 dbcsecond, rev. c C3C ad8138 specifications ad8138 parameter conditions min typ max unit d in to out specifications dynamic performance ? db small signal bandwidth v out = 0.5 v p-p, c f = 0 pf 280 310 mhz v out = 0.5 v p-p, c f = 1 pf 225 mhz bandwidth for 0.1 db flatness v out = 0.5 v p-p, c f = 0 pf 29 mhz large signal bandwidth v out = 2 v p-p, c f = 0 pf 265 mhz slew rate v out = 2 v p-p, c f = 0 pf 950 v/ s settling time 0.01%, v out = 2 v p-p, c f = 1 pf 16 ns overdrive recovery time v in = 2.5 v to 0 v step, g = +2 4 ns noise/harmonic performance second harmonic v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?0 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?9 dbc v out = 2 v p-p, 70 mhz, r l,dm = 800 ? ?0 dbc third harmonic v out = 2 v p-p, 5 mhz, r l,dm = 800 ? ?00 dbc v out = 2 v p-p, 20 mhz, r l,dm = 800 ? ?2 dbc v out = 2 v p-p, 70 mhz, r l,dm = 800 ? ?3 dbc imd 20 mhz ?4 dbc ip3 20 mhz 35 dbm voltage noise (rti) f = 100 khz to 40 mhz 5 nv/ hz input current noise f = 100 khz to 40 mhz 2 pa/ hz input characteristics offset voltage v os,dm = v out,dm /2; v din+ = v din = v ocm = 2.5 v 2.5 1 +2.5 mv t min ? max variation 4 v/ c input bias current 3.5 7 a t min ? max variation ?.01 a/ c input resistance differential 6 m ? common mode 3 m ? input capacitance 1pf input common-mode voltage 0.3 to 3.2 v cmrr ? v out,dm / ? v in,cm ; ? v in,cm = 1 v ?7 ?0 db output characteristics output voltage swing maximum ? v out ; single-ended output 2.9 v p-p output current 95 ma output balance error ? v out,cm / ? v out,dm ; ? v out,dm = 1 v ?5 db v ocm to out specifications dynamic performance ? db bandwidth 220 mhz slew rate 250 v/ s dc performance input voltage range 1.0 to 3.8 v input resistance 100 k ? input offset voltage v os,cm = v out,cm ; v din+ = v din = v ocm = 2.5 v 5 1 +5 mv input bias current 0.5 a v ocm cmrr [? v out,dm / ? v ocm ]; ? v ocm = 2.5 1 v ?0 db gain ? v out,cm / ? v ocm ; ? v ocm = 2.5 1 v 0.9968 1 1.0032 v/v power supply operating range 2.7 11 v quiescent current 15 20 21 ma t min to t max variation 40 a/ c power supply rejection ratio ? v out,dm / ? v s ; ? v s = 1 v ?0 ?0 db operating temperature range 40 +85 c notes harmonic distortion performance is equal or slightly worse with higher values of r l,dm . see figures tpc 13 and 14 for more information. specifications subject to change without notice. (@ 25 c, v s = 5 v, v ocm = 2.5 v, g = +1, r l,dm = 500 , unless otherwise noted. refer to figure 1 for test setup and label descriptions. all specifications refer to single-ended input and differential outputs unless otherwise noted.) rev. c ad8138 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8138 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v ocm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s internal power dissipation . . . . . . . . . . . . . . . . . . . . 550 mw ja 2 (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 c/w operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above listed in the operational section of this specification is not implied. exposure to absolute maximum ratings for any extended periods may affect device reliability. 2 thermal resistance measured on semi standard 4-layer board. pin function descriptions pin no. name function 1 ?n negative input summing node 2v ocm voltage applied to this pin sets the common- mode output voltage with a ratio of 1:1. for example, 1 v dc on v ocm will set the dc bias level on +out and ?ut to 1 v. 3 v+ positive supply voltage 4 +out positive output. note: the voltage at ? in is inverted at +out. 5 ?ut negative output. note: the voltage at +d in is inverted at ?ut. 6 v negative supply voltage 7 nc no connect 8 +in positive input summing node pin configuration 1 2 3 4 8 7 6 5 ad8138 nc v ocm out v+ nc = no connect +in v in +out ad8138 r f = 499 r g = 499 r g = 499 24.9 r l,dm = 499 49.9 r f = 499 figure 1. basic test circuit ordering guide temperature package package branding model range descriptions options information ad8138ar ?0 c to +85 c 8-lead soic so-8 ad8138ar-reel 1 ?0 c to +85 c 8-lead soic 13" tape and reel ad8138ar-reel7 2 ?0 c to +85 c 8-lead soic 7" tape and reel ad8138arm ?0 c to +85 c 8-lead micro_soic rm-8 hba ad8138arm-reel 3 ?0 c to +85 c 8-lead soic 13" tape and reel hba AD8138ARM-REEL7 2 ?0 c to +85 c 8-lead soic 7" tape and reel hba ad8138-eval evaluation board soic notes 1 13" reels of 2500 each. 2 7" reels of 1000 each. 3 13" reels of 3000 each. rev. c C5C ad8138 frequency mhz gain db 9 1 1000 0 10 100 6 3 3 6 v s = 5v v in = 0.2v p-p c f = 0pf v s = +5v tpc 1. small signal frequency response frequency mhz gain db 9 1 1000 0 10 100 6 3 3 6 v s = 5v v in = 2v p-p c f = 0pf v s = +5v tpc 4. large signal frequency response fundamental frequency mhz 010 70 20 30 40 50 60 distortion dbc 50 120 90 100 110 70 80 hd2(v s = +5v) 60 hd2(v s = 5v) v out ,dm = 2v p-p r l = 800 hd3(v s = +5v) hd3(v s = 5v) tpc 7. harmonic distortion vs. frequency frequency mhz gain db 9 1 1000 0 10 100 6 3 3 6 c f = 1pf v s = 5v v in = 0.2v p-p c f = 0pf tpc 2. small signal frequency response frequency mhz gain db 9 1 1000 0 10 100 6 3 3 6 c f = 1pf v in = 2v p-p v s = 5v c f = 0pf tpc 5. large signal frequency response fundamental frequency mhz 010 70 20 30 40 50 60 distortion dbc 50 90 100 110 70 80 hd2(v s = +5v) 60 hd2(v s = 5v) v out ,dm = 4v p-p r l = 800 40 hd3(v s = 5v) hd3(v s = +5v) tpc 8. harmonic distortion vs. frequency frequency mhz gain db 0.5 1 0.1 10 100 0.3 0.1 0.3 0.5 c f = 1pf v s = 5v v in = 0.2v p-p c f = 0pf tpc 3. 0.1 db flatness vs. frequency frequency mhz gain db 10 1 1000 10 10 100 0 v s = 5v c f = 0pf v out ,dm = 0.2v p-p r g = 499 g = 10, r f = 4.99k 20 30 g = 5, r f = 2.49k g = 2, r f = 1k g = 1, r f = 499 tpc 6. small signal frequency response for various gains v ocm dc output volts 4 33 2 1012 distortion dbc 50 90 100 70 80 60 hd2(v s = 5) hd2(v s = +5) v out ,dm = 2v p-p r l = 800 f o = 20mhz 40 30 4 hd3(v s = 5) hd3(v s = +5) tpc 9. harmonic distortion vs. v ocm unless otherwise noted, gain = 1, r g = r f = r l,dm = 499 , t a = 25 c; refer to figure 1 for test setup. typical performance characteristics rev. c ad8138 C6C differential output voltage v p - p 0 6 distortion dbc 120 90 100 110 70 80 60 hd3(f = 5mhz) v s = 5v r l = 800 5 4 3 2 1 hd3(f = 20mhz) hd2(f = 5mhz) hd2(f = 20mhz) tpc 10. harmonic distortion vs. differential output voltage r load 200 distortion dbc 90 100 110 70 80 60 hd3(f = 5mhz) v s = +5v v out ,dm = 2v p-p hd3(f = 20mhz) hd2(f = 5mhz) hd2(f = 20mhz) 600 1000 1400 1800 tpc 13. harmonic distortion vs. r load frequency mhz 0 intercept dbm 30 v s = +5v 20 v s = 5v 25 35 40 45 40 60 80 r l = 800 tpc 16. third order intercept vs. frequency differential output voltage v p - p 0 distortion dbc 120 90 100 110 70 80 60 hd3(f = 5mhz) v s = +5v r l = 800 1 hd3(f = 20mhz) hd2(f = 5mhz) hd2(f = 20mhz) 234 tpc 11. harmonic distortion vs. differential output voltage r load 200 distortion dbc 90 100 110 70 80 60 hd3(f = 5mhz) hd3(f = 20mhz) hd2(f = 5mhz) hd2(f = 20mhz) v s = 5v v out ,dm = 2v p-p 600 1000 1400 1800 120 tpc 14. harmonic distortion vs. r load 5ns 1v v +din v out,dm v s = 5v v out+ v out tpc 17. large signal transient response differential output voltage v p - p 0.25 distortion dbc 90 100 110 70 80 60 hd3(f = 5mhz) v s = +3v r l = 800 hd3(f = 20mhz) hd2(f = 5mhz) hd2(f = 20mhz) 0.50 0.75 1.00 1.25 1.50 1.75 tpc 12. harmonic distortion vs. differential output voltage frequency mhz 49.5 p out dbm 50 90 110 70 f c = 50mhz v s = 5v 30 10 10 49.7 49.9 50.1 50.3 50.5 tpc 15. intermodulation distortion v out,dm = 0.2v p-p v s = 5v c f = 0pf c f = 1pf 5ns 40mv tpc 18. small signal transient response rev. c C7C ad8138 v out,dm = 2v p-p c f = 0pf v s = 5v v s = +5v 5ns 400mv tpc 19. large signal transient response v s = 5v f = 20mhz v +din = 8v p-p g = 3(r f = 1500) 30ns 4v v out,dm v +din tpc 22. output overdrive frequency mhz cmrr db 11k 10 100 20 v s = 5v v out,dm / v in , cm 30 40 50 60 70 80 tpc 25. cmrr vs. frequency v out,dm = 2v p-p v s = 5v c f = 0pf 5ns 400mv c f = 1pf tpc 20. large signal transient response ad8138 499 499 499 49.9 24.9 453 24.9 24.9 c l 499 tpc 23. test circuit for cap load drive ad8138 499 499 499 49.9 24.9 249 249 499 tpc 26. test circuit for output balance v s = 5v c f = 1pf 4ns 1v v out,dm v +din 200 v tpc 21. settling time 2.5ns 400mv v s = 5v c f = 0pf c l = 5pf c l = 20pf c l = 10pf tpc 24. large signal transient response for various cap loads frequency mhz balance error db 11k 10 100 20 v s = 5v 30 40 50 60 70 v s = +5v v in = 2v p-p tpc 27. output balance error vs. frequency rev. c ad8138 C8C frequency mhz psrr db 11k 10 100 20 30 40 50 60 70 10 80 90 +psrr (v s = +5v, 0v and 5v) psrr (v s = 5v) v out,dm / v s tpc 28. psrr vs. frequency temperature c 40 20 100 020 40 60 80 bias current a v s = 5v, +5v v s = +3v 2 4 5 1 3 tpc 31. input bias current vs. temperature frequency mhz impedance 100 0.1 1 10 100 1 10 v s = 5v v s = +5 single-ended output tpc 29. output impedance vs. frequency temperature c 40 20 100 020 40 60 80 supply current ma v s = 5v v s = +3v 10 5 v s = +5v 15 20 25 30 tpc 32. supply current vs. temperature temperature c 40 20 100 020 40 60 80 differential output offset mv 5.0 v s = 5v v s = +5v v s = +3v 2.5 0 2.5 5.0 tpc 30. output referred differential offset voltage vs. temperature frequency mhz gain db 9 11k 0 10 100 6 3 3 6 v s = 5v v s = +5v tpc 33. v ocm frequency response 5ns 400mv v s = 5v v ocm = 1v to +1v v out,cm tpc 34. v ocm transient response rev. c ad8138 C9C operational description definition of terms ad8138 c f +in in r f c f r f r g r g +d in v ocm d in r l,dm +out v out ,dm out figure 2. circuit definitions differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or equivalently output differential-mode voltage) is defined as: v out,dm = ( v +out ?v ?ut ) v +out and v ?ut refer to the voltages at the +out and out terminals with respect to a common reference. common-mode voltage refers to the average of two node volt- ages. the output common-mode voltage is defined as: v out,cm = ( v +out + v ?ut ) / 2 balance is a measure of how well differential signals are m atched in amplitude and exactly 180 degrees apart in phase. balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the mag- nitude of the signal at the divider? midpoint with the magn itude of the differential signal. (see tpc 26.) by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential-mode voltage: output balance error v v out cm out dm = , , theory of operation the ad8138 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions. like an op amp, it relies on high open loop gain and negative feedback to force these outputs to the desired voltages. the ad8138 behaves much like a standard voltage feedback op amp and makes it easy to perform single-ended-to-differential conversion, common-m ode level-shifting, and amplification of differential sign als. also like an op amp, the ad8138 has high input imped- ance and low output impedance. previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers, and two independent feedback loops, one to control each of the outputs. when these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. dc common-mode level-shifting has also been difficult with previous differential drivers. level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. excellent performance over a wide frequency range has proven difficult with this approach. the ad8138 uses two feedback loops to separately control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differen- tial output voltage. the common-mode feedback controls only the common-mode output voltage. this architecture makes it easy to arbitrarily set the output common-mode level. it is forced, by internal common-mode feedback, to be equal to the voltage applied to the v ocm input, without affecting the differential output voltage. the ad8138 architecture results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. the common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. the result is nearly perfectly balanced differential outputs, of identical amplitude and exactly 180 degrees apart in phase. analyzing an application circuit the ad8138 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and in in figure 2. for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common- mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed loop gain neglecting the capacitors c f , the differential mode gain of the circuit in figure 2 can be determined to be described by the following equation: v v r r out dm in dm f s g s , , = this assumes the input resistors, r g s and feedback resistors, r f s on each side are equal. estimating the output noise voltage similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +in and in, by the circuit noise gain. the noise gain is defined as: g r r n f g =+ ? ? ? ? ? ? 1 to compute the total output referred noise for the circuit of figure 2, consideration must also be given to the contribution of the resistors r f and r g . refer to t able i for estimated output noise voltage densities at various closed-loop gains. table i r g r f bandwidth output noise output noise gain ( )( ) ? db 8138 only 8138 + r g , r f 1 499 499 320 mhz 10 nv/ hz 11.5 nv/ hz 2 499 1.0 k 180 mhz 15 nv/ hz 16.6 nv/ hz 5 499 2.49 k 70 mhz 30 nv/ hz 31.6 nv/ hz 10 499 4.99 k 30 mhz 55 nv/ hz 56.6 nv/ hz rev. c ad8138 C10C the impact of mismatches in the feedback networks as mentioned previously, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop will still force the outputs to remain balanced. the ampli- tudes of the signals at each output will remain equal and 180 degrees out of phase. the input-to-output differential-mode gain will vary proportionately to the feedback mismatch, but the output balance will be unaffected. ratio m atching errors in the external resistors will result in a degradation of the circuit s ability to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. also, if the dc levels of the input and output common-mode voltages are different, matching errors will result in a small differential-mode output offset voltage. for g = 1 case, with a ground referenced input signal and the output common-mode level set for 2.5 v, an output offset of as much as 25 mv (1% of the difference in common-mode levels) can result if 1% toler- ance resistors are used. resistors of 1% tolerance will result in a worst case input cmrr of about 40 db, worst-case differen- tial mode output offset of 25 mv due to 2.5 v level-shift, and no significant degradation in output balance error. calculating an application circuit? input impedance the effective input impedance of a circuit such as that in figure 2, at +d in and d in , will depend on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, the input impedance (r in ,dm) between the inputs (+d in and d in ) is simply: r in,dm = 2 r g in the case of a single-ended input signal (for example if d in is grounded and the input signal is applied to +d in ), the input impedance becomes: r r r rr in dm g f gf , = ? + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 the circuit s input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single supply applications the ad8138 is optimized for level-shifting ground referenced input signals. for a single-ended input this would imply, for example, that the voltage at d in in figure 1 would be zero volts when the amplifier s negative power supply voltage (at v ) was also set to zero volts. setting the output common-mode voltage the ad8138 s v ocm pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on v+ and v ). relying on this internal bias will result in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external sou rce, or resistor divider (made up of 10 k ? resistors), be used. the output common-mode offset specified on pages 2 and 3 assume the v ocm input is driven by a low impedance voltage source. driving a capacitive load a purely capacitive load can react with the pin and bondwire inductance of the ad8138 resulting in high frequency ringing in the pulse response. one way to minimize this effect is to place a small capacitor across each of the feedback resistors. the added capacitance should be small to avoid destabilizing the amplifier. an alternative technique is to place a small resistor in series with the amplifier s outputs as shown in tpc 23. layout, grounding and bypassing as a high speed part, the ad8138 is sensitive to the pcb envi ronment in which it has to operate. realizing its superior specifications requires attention to various details of good high speed pcb design. the first requirement is for a good solid ground plane that cov- ers as much of the board area around the ad8138 as possible. the only exception to this is that the two input pins (pins 1 and 8) should be kept a few mm from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. this will minimize the stray capacitance on these nodes and help preserve the gain flatness versus frequency. the power supply pins should be bypassed as close as possible to the device to the nearby ground plane. good high frequency ceramic chip capacitors should be used. this bypassing should be done with a capacitance value of 0.01 f to 0.1 f for each supply. further away, low frequency bypassing should be provided with 10 f tantalum capacitors from each supply to ground. the signal routing should be short and direct in order to avoid parasitic effects. wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. when running differential signals over a long distance, the traces on pcb should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. this will reduce the radiated energy and make the circuit less suscep- tible to interference. rev. c ad8138 C11C balanced transformer driver transformers are among the oldest devices that have been used to perform a single-ended-to-differential conversion (and vice versa). transformers also can perform the additional functions of galvanic isolation, step-up or step-down of voltages and impedance transformation. for these reasons, transformers will always find uses in certain applications. however, when driving a transformer single-endedly and then looking at its output, there is a fundamental imbalance due to the parasitics inherent in the transformer. the primary (or driven) side of the transformer has one side at dc potential (usually ground), while the other side is driven. this can cause problems in systems that require good balance of the transformer s differential output signals. if the interwinding capacitance (c stray ) is assumed to be uni- formly distributed, a signal from the driving source will couple to the secondary output terminal that is closest to the primary s driven side. on the other hand, no signal will be coupled to the opposite terminal of the secondary, because its nearest primary terminal is not driven. (see figure 3.) the exact amount of this imbalance will depend on the particular parasitics of the trans- former, but will mostly be a problem at higher frequencies. the balance of a differential circuit can be measured by connecting an equa l-valued resistive voltage divider across the differential outputs and then measuring the center point of the circuit with respect ground. since the two differential outputs are supposed to be of equal amplitude, but 180 degrees opposite phase, there should be no signal present for perfectly balanced outputs. the circuit in figure 3 shows a minicircuits t1-6t trans- former connected with its primary driven single-endedly and the secondary connected with a precision voltage divider across its terminals. the voltage divider is made up of two 500 ? , 0.005% precision resistors. the voltage v unbal , which is also equal to the ac common-mode voltage, is a measure of how closely the outputs are balanced. the plots in figure 5 show a comparison between the case where the transformer is driven single-endedly by a signal gen- erator and driven differentially using an ad8138. the top signal trace of figure 5 shows the balance of the single-ended configu- ration, while the bottom shows the differentially driven balance response. the 100 mhz balance is 35 db better when using the ad8138. the well-balanced outputs of the ad8138 will provide a drive signal to each of the transformer s primary inputs that are of equal amplitude and 180 degrees out of phase. thus, depending on how the polarity of the secondary is connected, the signals that conduct across the interwinding capacitance will either both assist the transformer s secondary signal equally, or both buck the secondary signals. in either case, the parasitic effect will be symmetrical and provide a well-balanced transformer output. (see figure 5.) primary c stray c stray no signal is coupled on this side signal will be coupled on this side via c stray 52.3 secondary v diff 500 0.005% 500 0.005% v unbal figure 3. transformer single-ended-to-differential con- verter is inherently imbalanced v diff 500 0.005% 500 0.005% v unbal c stray c stray ad8138 +in in 499 out+ out 499 499 499 49.9 49.9 figure 4. ad8138 forms a balanced transformer driver frequency mhz 0 0.3 500 output balance error db 1 10 100 20 40 60 80 100 v unbal , differential drive v unbal , for transformer with single-ended drive figure 5. output balance error for circuits of figures 3 and 4 rev. c ad8138 C12C high-performance adc driving the circuit in figure 6 shows a simplified front-end connec tion for an ad8138 driving an ad9224, a 12-bit, 40 msps a/d converter. the a/d works best when driven differentially, which minimizes its distortion as described in its data sheet. the ad8138 eliminates the need for a transformer to drive the adc and performs single-ended-to-differential conversion, com- mon-mode level-shifting and buffering of the driving signal. the positive and negative outputs of the ad8138 are connected to the respective differential inputs of the ad9224 via a pair of 49.9 ? resistors to minimize the effects of the switched-capacitor front-end of the ad9224. for best distortion performance it is run from supplies of 5 v. the ad8138 is configured with unity gain for a single-ended input-to-dif ferential output. the additional 23 ? , 523 ? total, at the input to in is to balance the parallel impedance of the 50 ? source and its 50 ? termination that drives the noninverting input. the signal generator has a ground-referenced, bipolar output, i.e., it drives symmetrically above and below ground. connecting v ocm to the cml pin of the ad9224 sets the output common- mode of the ad8138 at 2.5 v, which is the midsupply level for the ad9224. t his voltage is bypassed by a 0.1 f capacitor. the full-scale analog input range of the ad9224 is set to 4 v p-p, by shorting the sense terminal to avss. this has been deter- mined to be the scaling to provide minimum harmonic distortion. for the ad8138 to swing a 4 v p-p, each output swings 2 v p-p, while providing signals that are 180 degrees out of phase. with a common-mode voltage at the output of 2.5 v, this means that each ad8138 output will swing between 1.5 v and 3.5 v. a ground-referenced 4 v p-p, 5 mhz signal at d in + was used to test the circuit in figure 6. when the combined-device circuit was run with a sampling rate of 20 mhz msps, the sfdr (spurious free dynamic range) was measured at 85 dbc. 49.9 0.1pf 523 499 49.9 499 499 vinb +5v drvdd avdd avss drvss vina 0.1pf 0.1pf digital outputs +5v ad9224 v ocm ad8138 5v sense cml 50 source + 49.9 figure 6. ad8138 driving an ad9224, a 12-bit, 40 msps a/d converter rev. c ad8138 C13C 3 v operation the circuit in figure 7 shows a simplified front end connection for an ad8138 driving an ad9203, a 10-bit, 40 msps a/d converter that is specified to work on a single 3 v supply. the a/d works best when driven differentially to make the best use of the signal swing available within the 3 v supply. the appro- priate outputs of the ad8138 are connected to the appropriate differential inputs of the ad9203 via a low-pass filter. the ad8138 is configured for unity gain for a single-ended input to differential output. the additional 23 ? at the input to in is to balance the impedance of the 50 ? source and its 50 ? termination that drives the noninverting input. the signal generator has ground-referenced, bipolar output, i.e., it can drive symmetrically above and below ground. even though the ad8138 has ground as its negative supply, it can still function as a level-shifter with such an input signal. the output common-mode is raised up to midsupply by the voltage divider that biases v ocm . in this way, the ad8138 pro- vides dc-coupling and level-shifting of a bipolar signal, without inverting the input signal. the low-pass filter between the ad8138 and the ad9203 provides filtering that helps to improve the signal-to-noise ratio. lower noise can be realized by lowering the pole fre- quency, but the bandwidth of the circuit will be lowered. 49.9 0.1 f 10k 523 499 10k 20pf 49.9 20pf 499 499 0.1 f ainn +3v drvdd avdd avss drvss ainp 0.1 f 0.1 f digital outputs +3v 49.9 ad8138 + ad9203 figure 7. ad8138 driving an ad9203, a 10-bit, 40 msps a/d converter the circuit was tested with a 0.5 dbfs signal at various frequencies. figure 8 shows a plot of the total harmonic distor- tion (thd) vs. frequency at signal amplitudes of 1 v and 2 v differential drive levels. frequency mhz 40 0 thd dbc 5 10152025 45 50 55 60 65 70 75 80 ad8138-2v ad8138-1v figure 8. ad9203 thd @ C0.5 dbfs ad8138 figure 9 shows the signal to noise plus distortion (sinad) under the same conditions as above. for the smaller signal swing, the ad8138 performance is quite good, but its performance degrades when trying to swing too close to the supply rails. frequency mhz 65 0 sinad dbc 5 10152025 63 61 59 57 55 53 51 45 49 47 ad8138-1v ad8138-2v figure 9. ad9203 sinad @ C0.5 dbfs ad8138 rev. c ad8138 C14C 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead micro_soic (rm-8) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84) outline dimensions dimensions shown in inches and (mm). ad8138 revision history location page data sheet changed from rev. b to rev. c. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 C15C C16C c01073C0C6/01(c) printed in u.s.a. |
Price & Availability of AD8138ARM-REEL7
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |