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92706 / 12606 ms ot b8-6272 no.7619-1/14 LA5679T overview the LA5679T is an 3ch switching regulator control ic. functions ? operable on low voltage, min 1.8v. ? out1 to drive an external pnp. ? out2 to 3 to drive an external npn. ? 3ch independent standby circuit incorporated. ? reference voltage accuracy 1%. ? mos transistor driving possible. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 14 v allowable power dissipation pd max independent ic 0.4 w operating temperature topr -20 to +85 c storage temperature tstg -55 to +150 c operating conditions at ta = 25c parameter symbol conditions ratings unit supply voltage 1 v cc 1.8 to 11 v supply voltage 2 vbias 1.8 to 11 v output sync current isink max 0 to 30 ma reference voltage output current iref 0 to 1 ma timing resistor rt 3 to 30 k ? timing capacity ct 100 to 1000 pf triangular wave frequency f osc 0.1 to 1 mhz ordering number : en7619 monolithic linear ic 3ch switching regulator control ic any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
LA5679T no.7619-2/14 electrical characteristics at ta = 25c, v cc = vstby1 to 3 = 3v, scp = 0v ratings parameter symbol conditions min typ max unit [error amplifier] in+pin internal bias voltage vb_ in+ in2+, in3+ pin 0.500 0.506 0.512 v ch1 vlow_fb1 in1- = 0.5v, in1+ = 0v, ifb1 = 20 a 1 v output ?low? voltage ch2, ch3 vlow_fb2 in2, 3- = 1v 0.2 v ch1 vhi_fb1 in1- = 0.5v, in1+ = 2v, ifb1 = -20 a2.25 v output ?hi? voltage ch2, ch3 vhi_fb2 in2, 3- = 0v 0.81 v common-mode input voltage range ch1 vicm_in 0 2 v [protection circuit] threshold voltage vscp 1.1 1.25 1.4 v [scp pin current] iscp 3.8 a [still period adjusting section] input bias current ib_dtc -15 -3 a threshold voltage 1 ch1 vth1_dtc fb1 = 0. 5v duty cycle = 100% 0.35 0.4 0.45 v threshold voltage 2 ch1 vth2_dtc fb1 = 0. 5v duty cycle = 0% 0.67 0.77 0.87 v threshold voltage 3 ch2, ch3 vth3_dtc fb2, 3 = 1v duty cycle = 100% 0.80 0.88 0.96 v threshold voltage 4 ch2, ch3 vth4_dtc fb2, 3 = 1v duty cycle = 0% 0.40 0.45 0.50 v [output block 1 (ch1)] out pin source current i out 1_sour fb1 = 2v, dtc1 = 0v, rset1 = 3.3 ? , v out 1 = 2.7v, icaph = 0.5ma 10 ma out pin sync current i out 1_sink fb1 = 0.5v, dtc1 = 0v, rset1 = 3.3 ? , v out 1 = 2.3v 20 30 40 ma iset pin voltage viset fb1 = 0.5v, dtc1 = 0v, rset1 = 3.3 ? , v out 1 = 2.3v 0.065 0.1 0.135 v [output block 2 to 3 (ch2 to ch3)] out pin source current i out 23_sour rset2, 3 = 680 ? , v out 2, 3 = 0.9v, dtc2, 3 = 1v, fb2, 3 = 1v 20 30 40 ma out pin sync current i out 23_sink rset2, 3 = 680 ? , v out 2, 3 = 0.3v, dtc2, 3 = 1v, fb2, 3 = 0v 30 ma out pin high voltage v out 23_hi rset2, 3 = 680 ? , i out 2, 3= -10ma, dtc2, 3 = 1v, fb2, 3 = 1v 2 v out pin low voltage v out 23_low rset2, 3 = 680 ? , i out 2, 3 = 10ma, dtc2, 3=1v, fb2, 3 = 0v 0.2 v iset pin voltage viset23 rset2, 3 = 680 ? , v out 2, 3 = 0.9v, dtc2, 3 = 1v, fb2, 3 = 1v 0.230 0.350 0.470 v [triangular wave generator] current setting pin voltage vt_rt rt = 5.6k ? 1.190 1.260 1.330 v output current i oh _ct vct = 0.5v, rt = 5.6k ? 230 a output current ratio ? i o _ct 0.8 1.0 1.2 oscillation frequency f osc 1 200 260 320 khz [reference voltage block] reference voltage vref iref = -1ma 1.244 1.257 1.270 v line regulation vln_ref v cc = 1.8v to 11v 10 mv load regulation vld_ref iref = -0.1ma to -1ma 10 mv [stby circuit] on voltage von_stby 1.15 v off voltage voff_stby 0.2 v pin input current i in _stby vstby1 to 3 = 3v 70 a [all circuit] operating current dissipation (i cc +ibias1 to 3) i cc 1 fb1 = 0.5v, fb2, 3 = 1v dtc1 = 0v, dtc2, 3 = 1v rset2, 3 = 680 ? , rset1 = 3.3 ? 12 15 ma standby current dissipation (i cc +ibias1 to 3) i cc 2 vstby1 to 3 = 0v 1 a
LA5679T no.7619-3/14 package dimensions unit : mm 3253b
LA5679T no.7619-4/14 pin assignment in3- stby3 ct2 ct1 rt sgnd scp capl1 caph1 gnd1 iset1 out1 vbias1 dtc1 fb1 vref stby1 in1- in1+ v cc fb3 dtc3 iset3 vbias3 out3 nc gnd3 gnd2 nc out2 vbias2 iset2 dtc2 fb2 stby2 in2- 13 14 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 21 22 23 24 25 26 27 30 28 29 31 32 33 34 35 36 LA5679T top view
LA5679T no.7619-5/14 block diagram note) soft start of ch2 and ch3 may not occur in certain condition. for details, refer to ?ch2 and ch3 soft start? of the specification. osc in1+ in1- dtc1 35 + - 30 34 capl1 out1 to v o 1 vbias1 vref scp stby v o 1 v o 2 4 v cc fb1 in2- dtc2 fb2 in3- dtc3 fb3 out2 vbias2 out3 vbias3 stby1 stby2 stby3 rt ct1 ct2 sgnd vref scp iset1 iset2 iset3 220k ? 130k ? 0.1 f 100? 5.1k ? 0.47 f 1 f 1000pf 100 f 3v 1000pf 1000 p f 5.6k ? 0.01 f 5.1k ? 5v 5v q1 q2 t1 10 h 0.1 f 220k ? 130k ? 5.1k ? t1 :873ac-1046 (toko sha made) q1 :cph3106 q2,q3 :cph3206 0.01 f + + - - + - + 13 31 1 3 15 18 16 22 21 20 19 33 2 17 36 14 12 6 5 7 29 27 28 24 32 23 5.1? + + - + + - 6.2k ? 4.3 k ? 0.1 f 220k ? 130k ? 0.1 f 0.1 f caph1 25 gnd1 26 680? gnd2 9 680? gnd3 10 200? v o 3 5v q3 10 h
LA5679T no.7619-6/14 output stage (1) for ch1 output current i out 1 (sink) of ch1 can be set freely by means of the resistance of iset1 to gnd and can be represented as follows: i out 1 = [a] with vbe1 = vbe2, i out 1 = [a] as vbe2 changes with i out 1 and thus vbe1 = vbe2 is not necessarily established, refer to the i out (sink)- rset characteristics for setting of rset1. i out 1 sink current (2) for ch2 (and for ch3) output current i out 2 (source) can be set freely by means of the resistance of iset2 to gnd and can be represented as follows: i out 2 = 61.4 [a] when vbe1=vbe2, i out 2 = 61.4 [a] * the equation is for ch2. the same applies to ch3. as vbe2 varies with iset2, vbe1 is not always equal to vbe2. besides, the current magnification of 61.4 varies slightly with vset2 and i out 2. refer to i out (source)-rset characteristic when setting rset. 0.1+vbe1 ? vbe2 rset2 0.1 rset2 vbias1 out1 capl caph 0.1v iset1 vbe1 vbe2 i out 1 rset1 vset 0.4+vbe1 ? vbe2 rset2 0.4 rset2
LA5679T no.7619-7/14 i out 2 source current * figure shows a case with ch2 as well as a case with ch3. scp pin with fb1 being low (fb2 and 3 hi) because of load short-ci rcuit, scp charge begins. if fb1 is not reset within the set time, t scp , a protective circuit is activated. (the entire out is turned off when this circuit is activated.) scp charge t scp = [s] vbias2 out2 sw iset2 0.4v vbe1 vbe2 vset rset2 i out 2 scp [v] scp operation charge 1.25 [v] t scp charge with i scp c scp v scp i scp
LA5679T no.7619-8/14 setting the dead time (1) for ch1 the dead time of ch1 can be set with the dtc1 voltage. duty d1 is represented as follows: d1 = (1 ? ) 100 [%] (2) for ch2 (and ch3) the dead time of ch2 can be set with the voltage of dtc2. * figure shows a case with ch2 as well as a case with ch3. duty d2 is represented as follows: d2 = 100 [%] * the equation is for ch2. the same applies to ch3. vth1_ dtc dtc1 vref vdtc1 vth2_ dtc triangular input waveform of pwm comparator vdtc1 vdtc ? vth2_ dtc vth1_ dtc ? vth2_ dtc vth3_ dtc dtc2 vref vdtc2 vth4_ dtc triangular input waveform of pwm comparator vdtc2 vdtc2 ? vth4_ dtc vth3_ dtc ? vth4_ dtc
LA5679T no.7619-9/14 method to set the soft start time (1) for ch1 the ch1 soft start time is set with a ca pacity connected between dtc pin and vref. t soft1 = 1n [s] (2) for ch2 (and ch3) the ch2 soft start time is set with a capacity connected between dtc2 and 3 pins and gnd. * figure shows a case with ch2 as well as a case with ch3. t soft2 = ? c soft2 r2 1n (1 ? ) [s] * the equation is for ch2. the same applies to ch3. c soft1 r1r2 r1+r2 vdtc1 (r1+r2) ? r2vref r1vref vdtc2 vref ? vdtc2 r1 r2 vth1_ dtc dtc1 vref vdtc1 vth2_ dtc triangular input waveform of pwm comparator vdtc1 waveform vref soft start time t soft r1 r2 c soft1 vth3_ dtc dtc2 vref vdtc2 vth4_ dtc triangular input waveform of pwm comparator vdtc2 waveform soft start time t soft r1 r2 c soft2
LA5679T no.7619-10/14 typical circuit using vbias1 as the power to the output stage is supplied with vbaiasi, the application shown in the figure can be made. the voltage of 5v stepped up with ch2 is applied to vbaiasi to obtain v o 1 = 3.3v. this is stepped up/down against the change of v cc = 2 to 4v. * use the emitter of external pnp and vbais1 on the same potential. typical use of vbisa1 typical circuit using vbias2 (and vbias3) as the power to the output stage is supplied with vbaias2, the application shown in the figure can be made. the voltage of v o 1 = 5v stepped up with ch1 is applied to vbaias2. as the voltage of about vbias2-1v is generated, mos transistor can be driven even when vbatt is low as sh own in the typical circuit. typical vbias2 circuit * figure shows a case with vbias2 as well as for a case with vbias3. during operation at low voltage (for v cc , vbias1 to 3, 1.8 v or less) a circuit to turn off the output when detecting v cc and vbias1 to 3 during low voltage is not inserted. turn off the output in stby below the operation range. vbias1 out1 caph iset2 rset2 v o 1=3.3v to in1+ to out2 vbatt=2 to 4v v o 2=5v to in2- note: use the emitter of external pnp and vbias1 on the same potential. capl to v cc to in2+ vbatt=2v v o 2=3.3v to out1 to v cc vbias2 out2 sw rset v o 1 5v to in1+ vout2 mch3406 10 h
LA5679T no.7619-11/14 ct1 and ct2 ct1 and ct2 have the waveform mutually displaced by 180 degrees in the phase. independent frequency setting is impossible. set the same value for capacitors to be connected, ct1 and ct2. relationship between short-circuit protection and soft start the soft start condition is judged to be a short-circuit condition and charge to c scp is continued. set the soft start time t soft shorter than the set time t scp for short-circuit protection. use in the step-down circuit (ch1) the step-down application as shown below is judged to be the short-circuit condition withvbias1 lower than the set voltage of v o +vf and scp is activated. with vbias1 < v o +vf at step-down use of the step-up circuit (ch2, ch3) as shown in the figure, the step-up application forms a through via a v cc l d route in the stby off mode, so that the voltage remains in v o . similarly, the voltage remains in v o in the scp run mode. if necessary, cut off the through route with a switch. when a chopper step-up circuit is used vbias1=v o +vf v o 1 v o 1 in+ out vbias1 1.8v vbias1 vf vf (diode forward voltage) scp activated v cc out v o in- ioff l d
LA5679T no.7619-12/14 soft start of ch2 and ch3 ch2 and ch3 cannot perform soft start when vref is started in advance b ecause a dtc discharge circuit is not provided. provide this discharge circuit. plan with an external dtc pin discharge circuit resistance between the base and emitter of external pnp transistor (or between the gate and source in the case of mos transistor) during light-load operation, the switching speed of transistor on the sink side of output stage is delayed, so that the external transistor cannot be turned off completely, resu lting in increase in the current drain. insert resistance between the base and emitter of external pnp transistor (or between the gate and source of mos transistor) to ensure switching-off under light load and to pr event increase in th e current drain. to stby2 27k ? to vref to dtc2 to stby3 to vref to dtc3 to gnd q1 q2 q3 q4 51k ? 27k ? 51k ? 100k ? 100k ? set q1 and q3 to the threshold value of 0.89 v while assuming vbe = 0.7v. out resistance vbias1
LA5679T no.7619-13/14 resistance between capl and gnd during mos drive v out develops chattering with vbias1 at about -3v. this is considered due to the high impedance condition sensitive to noise in the course of change of the inverter ou tput shown below from hi to low. provide a resistor to capl - gnd to improve the high impedance condition to eliminate chattering. vbias1 chattering vbias1-3v v out waveform vbias1 v out waveform (resistor between capl and gnd) vbias1 out capl iset i out rset caph inverter output passes through the impedance condition during change from hi to low. capl - gnd resistor
LA5679T ps no.7619-14/14 specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of january, 2006. specifications and information herein are subjec t to change without notice.

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