View MT18VDDF12872Y-335XX_6754414.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm features pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 1 ?2003 micron technology, inc. all rights reserved. ddr sdram rdimm mt18vddf6472 ? 512mb 1 mt18vddf12872 ? 1gb for component data sheets, refer to micron?s web site: www.micron.com features ? 184-pin, registered dual in-line memory module (rdimm) ? fast data transfer rates: pc2100, pc2700, or pc3200 ? 512mb (64 meg x 72) and 1gb (128 meg x 72) ? supports ecc error detection and correction ?v dd = v dd q = +2.5v (-40b: v dd = v dd q = +2.6v) ?v ddspd = +2.3v to +3.6v ? 2.5v i/o (sstl_2-compatible) ? internal, pipelined double data rate (ddr) 2n -prefetch architecture ? bidirectional data strobe (dqs) transmitted/ received with data?that is, source-synchronous data capture ? differential clock inputs (ck and ck#) ? multiple internal device banks for concurrent operation ? single rank ? selectable burst lengths (bl): 2, 4, or 8 ? auto precharge option ? auto refresh and self refresh modes: 7.8125s maximum average periodic refresh interval ? serial presence-detect (spd) with eeprom ? selectable cas latency (cl) for maximum compatibility ? gold edge contacts 184-pin rdimm (mo-206) figures figure 1: r/c j (-40b) pcb height: 28.58mm (1.125in) figure 2: r/c c (-335, -265) notes: 1. not recommended for new designs. 2. contact micron for industrial temperature module offerings. 3. cl = cas (read) latency; registered mode will add one clock cycle to cl. options marking ? operating temperature 2 ? commercial (0c t a +70c) none ? industrial (?40c t a +85c) i ?package ? 184-pin dimm (standard) g ? 184-pin dimm (pb-free) y ? memory clock, speed, cas latency 3 ? 5.0ns (200 mhz), 400 mt/s, cl = 3 -40b ? 6.0ns (167 mhz), 333 mt/s, cl = 2.5 -335 ? 7.5ns (133 mhz), 266 mt/s, cl = 2.5 1 -265 pcb height: 28.58mm (1.125in)
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 2 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm features notes: 1. the values of t rcd and t rp for -335 modules show 18ns to a lign with industry specifications; actual ddr sdram device specifications are 15ns. notes: 1. the data sheets for the base devi ces can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown) that desi gnates component and pcb revisions. consult factory for curre nt revision codes. example: mt18vddf12872y-335f 1 . table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) notes cl = 3 cl = 2.5 cl = 2 -40b pc3200 400 333 266 15 15 55 -335 pc2700 ? 333 266 18 18 60 1 -26a pc2100 ? 266 266 20 20 65 -265 pc2100 ? 266 200 20 20 65 table 2: addressing parameter 512mb 1gb refresh count 8k 8k row address 8k (a0?a12) 8k (a0?a12) device bank address 4 (ba0, ba1) 4 (ba0, ba1) device configuration 256mb (64 meg x 4) 512mb (128 meg x 4) column address 2k (a0?a9, a11) 4k (a0?a9, a11, a12) module rank address 1 (s0#) 1 (s0#) table 3: part numbers and timing parameters ? 512mb modules base device: mt46v64m4, 1 256mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18vddf6472g-40b__ 512mb 64 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vddf6472y-40b__ 512mb 64 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vddf6472g-335__ 512mb 64 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3 mt18vddf6472y-335__ 512mb 64 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3 mt18vddf6472g-265__ 512mb 64 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2.5-3-3 table 4: part numbers and timing parameters ? 1gb modules base device: mt46v128m4, 1 512mb ddr sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt18vddf12872g-40b__ 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vddf12872y-40b__ 1gb 128 meg x 72 3.2 gb/s 5.0ns/400 mt/s 3-3-3 mt18vddf12872g-335__ 1gb 128 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3 mt18vddf12872y-335__ 1gb 128 meg x 72 2.7 gb/s 6.0ns/333 mt/s 3-3-3 mt18vddf12872g-26a__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/266 mt/s 2-3-3 mt18vddf12872g-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/ 266 mt/s 2.5-3-3 mt18vddf12872y-265__ 1gb 128 meg x 72 2.1 gb/s 7.5ns/ 266 mt/s 2.5-3-3
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 3 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm pin assignments and descriptions pin assignments and descriptions table 5: pin assignments 184-pin ddr rdimm front 184-pin ddr rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 dqs8 70 v dd 93 v ss 116 v ss 139 v ss 162 dq47 2 dq0 25 dqs2 48 a0 71 nc 94 dq4 117 dq21 140 dqs17 163 nc 3v ss 26 v ss 49 cb2 72 dq48 95 dq5 118 a11 141 a10 164 v dd q 4 dq1 27 a9 50 v ss 73 dq49 96 v dd q 119 dqs11 142 cb6 165 dq52 5dqs028dq1851 cb3 74 v ss 97 dqs9 120 v dd 143 v dd q 166 dq53 6 dq2 29 a7 52 ba1 75 nc 98 dq6 121 dq22 144 cb7 167 nc 7v dd 30 v dd q 53 dq32 76 nc 99 dq7 122 a8 145 v ss 168 v dd 8 dq3 31 dq19 54 v dd q77v dd q100v ss 123 dq23 146 dq36 169 dqs15 9 nc 32 a5 55 dq33 78 dqs6 101 nc 124 v ss 147 dq37 170 dq54 10 reset# 33 dq24 56 dqs4 79 dq50 102 nc 125 a6 148 v dd 171 dq55 11 v ss 34 v ss 57 dq34 80 dq51 103 nc 126 dq28 149 dqs13 172 v dd q 12 dq8 35 dq25 58 v ss 81 v ss 104 v dd q 127 dq29 150 dq38 173 nc 13 dq9 36 dqs3 59 ba0 82 nc 105 dq12 128 v dd q 151 dq39 174 dq60 14 dqs1 37 a4 60 dq35 83 dq56 106 dq13 129 dqs12 152 v ss 175 dq61 15 v dd q38 v dd 61 dq40 84 dq57 107 dqs10 130 a3 153 dq44 176 v ss 16 nc 39 dq26 62 v dd q85 v dd 108 v dd 131 dq30 154 ras# 177 dqs16 17 nc 40 dq27 63 we# 86 dqs7 109 dq14 132 v ss 155 dq45 178 dq62 18 v ss 41 a2 64 dq41 87 dq58 110 dq15 133 dq31 156 v dd q 179 dq63 19 dq10 42 v ss 65 cas# 88 dq59 111 nc 134 cb4 157 s0# 180 v dd q 20 dq11 43 a1 66 v ss 89 v ss 112 v dd q 135 cb5 158 nc 181 sa0 21 cke0 44 cb0 67 dqs5 90 nc 113 nc 136 v dd q 159 dqs14 182 sa1 22 v dd q 45 cb1 68 dq42 91 sda 114 dq20 137 ck0 160 v ss 183 sa2 23 dq16 46 v dd 69 dq43 92 scl 115 a12 138 ck0# 161 dq46 184 v ddspd
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 4 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm pin assignments and descriptions table 6: pin descriptions symbol type description a0?12 input address inputs: provide the row address for active commands, and th e column address and auto precharge bit (a10) for read/write co mmands, to select one location out of the memory array in the respective device ba nk. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0 and ba1) or all device bank s (a10 high). the addres s inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode re gister) is loaded during the load mode register command. ba0?ba1 input bank address: ba0 and ba1 define the device bank to which an active, read, write, or precharge command is being applied. ck0, ck0# input clock: ck and ck# are differential clock inputs . all control, command , and address input signals are sampled on the crossi ng of the positive edge of ck and the negative edge of ck#. cke0 input clock enable: cke enables (registered high) and cke disables (registered low) the internal clock, input buffers, and output drivers. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low wh en reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s0# input chip select: s# enables (registered lo w) and disables (regi stered high) the command decoder. sa0?sa2 input presence-detect address inputs: these pins are used to configure the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: scl is used to synchroniz e the presence-detect data transfer to and from the module. cb0?cb7 i/o check bits. dq0?dq63 i/o data input/output: data bus. dqs0?dqs17 i/o data strobe: output with read data. edge-aligned with read data. inpu t with write data. center-aligned with write da ta. used to capture data. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence-detect po rtion of the module. v dd /v dd q supply power supply: +2.5v 0.2v. v ddspd supply spd eeprom power supply: +2.3v to +3.6v. v ref supply sstl_2 reference voltage (v dd /2). v ss supply ground. nc ? no connect: these pins are not connected on the module.
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 5 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm functional block diagrams functional block diagrams figure 3: functional block diagram (r/c j, -40b) u1 dq dq dq dq dq0 dq1 dq2 dq3 dqs cs# dm u24 dq dq dq dq dq60 dq61 dq62 dq63 dqs cs# dm u2 dq dq dq dq dq8 dq9 dq10 dq11 dqs cs# dm u23 dq dq dq dq dq52 dq53 dq54 dq55 dqs cs# dm u3 dq dq dq dq dq16 dq17 dq18 dq19 dqs cs# dm u22 dq dq dq dq dq44 dq45 dq46 dq47 dqs cs# dm u4 dq dq dq dq dq24 dq25 dq26 dq27 dqs cs# dm u21 dq dq dq dq dq36 dq37 dq38 dq39 dqs cs# dm u5 dq dq dq dq cb0 cb1 cb2 cb3 dqs cs# dm u20 dq dq dq dq cb4 cb5 cb6 cb7 dqs cs# dm u8 dq dq dq dq dq32 dq33 dq34 dq35 dqs cs# dm u18 dq dq dq dq dq28 dq29 dq30 dq31 dqs cs# dm u9 dq dq dq dq dq40 dq41 dq42 dq43 dqs cs# dm u17 dq dq dq dq dq20 dq21 dq22 dq23 dqs cs# dm u10 dq dq dq dq dq48 dq49 dq50 dq51 dqs cs# dm u16 dq dq dq dq dq12 dq13 dq14 dq15 dqs cs# dm u11 dq dq dq dq dq56 dq57 dq58 dq59 dqs cs# dm u15 dq dq dq dq dq4 dq5 dq6 dq7 pll ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 register x 2 ck0 ck0# dqs cs# dm dqs0 sa0 sda sa1 sa2 ras# cas# cke0 we# a0?a12 ba0, ba1 s0# rras#: ddr sdram rcas#: ddr sdram rcke0: ddr sdram rwe#: ddr sdram ra0?ra12: ddr sdram rba0, rba1: ddr sdram rs0#: ddr sdram r e g i s t e r s scl dqs1 dqs2 dqs3 dqs8 dqs4 dqs6 dqs7 dqs5 dqs9 dqs10 dqs11 dqs12 dqs17 dqs13 dqs14 dqs15 dqs16 reset# rs0# v ss u7 u6, u19 v ref v ss ddr sdram ddr sdram eeprom v dd ddr sdram v ddspd spd eeprom v dd v dd ck ck# a0 spd eeprom a1 a2 wp u12 v ss
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 6 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm functional block diagrams figure 4: functional block diagram (r/c c, -335, -265) u1 dq dq dq dq dq0 dq1 dq2 dq3 dqs cs# dm u22 dq dq dq dq dq60 dq61 dq62 dq63 dqs cs# dm u2 dq dq dq dq dq8 dq9 dq10 dq11 dqs cs# dm u21 dq dq dq dq dq52 dq53 dq54 dq55 dqs cs# dm u3 dq dq dq dq dq16 dq17 dq18 dq19 dqs cs# dm u20 dq dq dq dq dq44 dq45 dq46 dq47 dqs cs# dm u4 dq dq dq dq dq24 dq25 dq26 dq27 dqs cs# dm u19 dq dq dq dq dq36 dq37 dq38 dq39 dqs cs# dm u5 dq dq dq dq cb0 cb1 cb2 cb3 dqs cs# dm u18 dq dq dq dq cb4 cb5 cb6 cb7 dqs cs# dm u8 dq dq dq dq dq32 dq33 dq34 dq35 dqs cs# dm u15 dq dq dq dq dq28 dq29 dq30 dq31 dqs cs# dm u9 dq dq dq dq dq40 dq41 dq42 dq43 dqs cs# dm u14 dq dq dq dq dq20 dq21 dq22 dq23 dqs cs# dm u10 dq dq dq dq dq48 dq49 dq50 dq51 dqs cs# dm u13 dq dq dq dq dq12 dq13 dq14 dq15 dqs cs# dm u11 dq dq dq dq dq56 dq57 dq58 dq59 dqs cs# dm u12 dq dq dq dq dq4 dq5 dq6 dq7 pll ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 ddr sdram x 2 register x 2 ck0 ck0# dqs cs# dm dqs0 sa0 sda sa1 sa2 ras# cas# cke0 we# a0?a12 ba0, ba1 s0# rras#: ddr sdram rcas#: ddr sdram rcke0: ddr sdram rwe#: ddr sdram ra0?ra12: ddr sdram rba0, rba1: ddr sdram rs0#: ddr sdram r e g i s t e r s scl dqs1 dqs2 dqs3 dqs8 dqs4 dqs6 dqs7 dqs5 dqs9 dqs10 dqs11 dqs12 dqs17 dqs13 dqs14 dqs15 dqs16 reset# rs0# v ss u6 u7, u16 v ref v ss ddr sdram ddr sdram eeprom v dd ddr sdram v ddspd spd eeprom v dd v dd ck ck# a0 spd eeprom a1 a2 wp u17 v ss
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 7 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm general description general description the mt18vddf6472 and mt18vddf12872 are high-speed, cmos dynamic random access 512mb and 1gb memory modules organized in a x72 configuration. these modules use 256mb and 512mb ddr sdram devices with four internal banks. ddr sdram modules use a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for ddr sdram modu les effectively consists of a single 2n -bit-wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr sdram modules operate from differential clock inputs (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. control, command, and address signals are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. register and pll operation these ddr sdram modules operate in regist ered mode, where the control, command, and address input signals are latched in the regi sters on the rising clock edge and sent to the ddr sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differ- ential clock signals (ck, ck#) to the ddr sd ram devices. the register(s) and pll reduce control, command, address, and clock sign als loading by isolating dram from the system controller. pll clock timing is defi ned by jedec specifications and ensured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. serial presence-d etect operation ddr sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are progra mmed by micron to identify the module type and various ddr sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by th e customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/eeprom addr esses. write protect (wp) is connected to v ss , permanently disabling hardware write protect.
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 8 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm electrical specifications electrical specifications stresses greater than those listed in ta ble 7 may cause perman ent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. exposure to absolute maximum rating cond itions for extended periods may adversely affect reliability. notes: 1. for further information, refer to technical note tn-00-08: ?thermal applications,? available on micron?s web site. table 7: absolute maximum ratings symbol parameter min max units v dd /v dd qv dd /v dd q supply voltage relative to v ss ?1.0 +3.6 v v in , v out voltage on any pin relative to v ss ?0.5 +3.2 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 1.35v (all other pins not under test = 0v) address inputs, ras#, cas#, we#, ba, s#, cke ?5 +5 a ck, ck# ?10 +10 i oz output leakage current; 0v v out v dd q; dq are disabled dq, dqs ?5 +5 a t a dram ambient operating temperature 1 commercial 0 +70 c industrial ?40 +85 c
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 9 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm electrical specifications dram operating conditions recommended ac operating conditions are given in the ddr component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 8. design considerations simulations micron memory modules are designed to op timize signal integr ity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good sign al integrity starts at the system level. micron encourages designers to simulate th e signal characteristics of the system?s memory bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram , not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. table 8: module and component speed grades ddr components meet or exceed the listed module speed grades module speed grade component speed grade -40b -5b -335 -6 -26a -75z -265 -75
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 10 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm electrical specifications i dd specifications ta bl e 9 : i dd specifications and conditions ? 512mb (die revision ?k?) values are shown for the mt46v64m 4 ddr sdram only and are computed from values specified in the 256mb (64 meg x 4) component data sheet parameter/condition symbol -40b -335 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 1,800 1,620 ma operating one bank active-read-precharge current: bl = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 2,160 2,070 ma precharge power-down standby current: all device banks idle; power-down mode; t ck = t ck (min); cke = low i dd 2p 72 72 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once pe r clock cycle; v in =v ref for dq, dm, and dqs i dd 2f 900 900 ma active power-down standby current: one device bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 630 540 ma active standby current: cs# = high; cke = high; one device bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 1,080 990 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out =0ma i dd 4r 3,240 2,880 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 3,240 2,880 ma auto refresh current t refc = t rfc (min) i dd 5 2,880 2,880 ma t refc = 7.8125s i dd 5a 108 108 ma self refresh current: cke 0.2v i dd 67272ma operating bank interleave read current: four device bank interleaving reads (bl = 4) with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 5,220 4,860 ma
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 11 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm electrical specifications table 10: i dd specifications and conditions ? 512mb (all other die revisions) values are shown for the mt46v64m 4 ddr sdram only and are computed from values specified in the 256mb (64 meg x 4) component data sheet parameter/condition symbol -40b -335 -265 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 2,430 2,250 2,160 ma operating one bank active-read-precharge current: bl = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 3,060 3,060 2,610 ma precharge power-down standby current: all device banks idle; power- down mode; t ck = t ck (min); cke = low i dd 2p 72 72 72 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in =v ref for dq, dm, and dqs i dd 2f 1,080 900 810 ma active power-down standby current: one device bank active; power- down mode; t ck = t ck (min); cke = low i dd 3p 720 540 540 ma active standby current: cs# = high; cke = high; on e device bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 1,260 1,080 900 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out =0ma i dd 4r 3,600 3,150 2,700 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address and con trol inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 3,510 3,150 2,700 ma auto refresh current t refc = t rfc (min) i dd 5 4,680 4,590 4,410 ma t refc = 7.8125s i dd 5a 108 108 108 ma self refresh current: cke 0.2v i dd 6727272ma operating bank interleave read current: four device bank interleaving reads (bl = 4) with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 8,460 7,380 6,570 ma
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 12 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm electrical specifications table 11: i dd specifications an d conditions ? 1gb values are shown for the mt46v128m4 ddr sdram only and are computed from va lues specified in the 512mb (128 meg x 4) component data sheet parameter/condition symbol -40b -335 -26a/ -265 units operating one bank active-precharge current: t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 2,790 2,340 2,070 ma operating one bank active-read-precharge current: bl = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 3,330 2,880 2,610 ma precharge power-down standby current: all device banks idle; power- down mode; t ck = t ck (min); cke = low i dd 2p 90 90 90 ma idle standby current: cs# = high; all device banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in =v ref for dq, dm, and dqs i dd 2f 990 810 720 ma active power-down standby current: one device bank active; power- down mode; t ck = t ck (min); cke = low i dd 3p 810 630 540 ma active standby current: cs# = high; cke = high; on e device bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 1,080 900 810 ma operating burst read current: bl = 2; continuous burst reads; one device bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out =0ma i dd 4r 3,420 2,970 2,610 ma operating burst write current: bl = 2; continuous burst writes; one device bank active; address and con trol inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 3,510 3,150 2,430 ma auto refresh current t refc = t rfc (min) i dd 5 6,210 5,220 5,040 ma t refc = 7.8125s i dd 5a 198 180 180 ma self refresh current: cke 0.2v i dd 6909090ma operating bank interleave read current: four device bank interleaving reads (bl = 4) with auto precharge; t rc = t rc (min); t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 8,100 7,290 6,300 ma
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 13 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm register and pll specifications register and pll specifications notes: 1. timing and switching specifications for the register listed above are cr itical for proper oper- ation of the ddr sdram rdimms . these are meant to be a su bset of the parameters for the specific device used on th e module. detailed information for this register is available in jedec standard jesd82. table 12: register specifications sstv16859 devices or equivalent jesd82-4b parameter symbol pins condition min max units dc high-level input voltage v ih ( dc ) control, command, address sstl_25 v ref ( dc ) + 150 ? mv dc low-level input voltage v il ( dc ) control, command, address sstl_25 ? v ref ( dc ) - 150 mv ac high-level input voltage v ih ( ac ) control, command, address sstl_25 v ref ( dc ) + 310 v dd mv ac low-level input voltage v il ( ac ) control, command, address sstl_25 ? v ref ( dc ) - 310 mv output high voltage v oh parity output lvcmos v dd - 0.2 ? v output low voltage v ol parity output lvcmos ? 0.2 v input current i i all pins v i = v dd q or v ss q ?5.0 +5.0 a static standby i dd all pins reset# = v ss q (i o = 0) ? 100 a static operating i dd all pins reset# = v ss q; v i =v ih ( ac ) or v il ( dc ) i o =0 ?varies by manufacturer ma dynamic operating (clock tree) i ddd n/a reset# = v dd , v i =v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle ?v a r i e s b y manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd , v i =v ih ( ac ) or v il ( ac ), i o = 0; ck and ck# switching 50% duty cycle; one data input switching at t ck/2, 50% duty cycle ?v a r i e s b y manufacturer a input capacitance (per device, per pin) c i all inputs except reset# v i =v ref 250mv; v dd q=1.8v 2.5 3.5 pf input capacitance (per device, per pin) c i reset# v i =v dd q or v ss q?v a r i e s b y manufacturer pf
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 14 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm register and pll specifications notes: 1. pll timing and switching specifications ar e critical for proper operation of the ddr dimm. this is a subset of parameters for the specific pll used. detailed pll in formation is available in jedec standard jesd82-1a. table 13: pll specifications cvf857 device or eq uivalent jesd82-1a parameter symbol min max units dc high-level input voltage v ih 1.7 v dd q + 0.3 v dc low-level input voltage v il ?0.3 0.7 v input voltage (limits) v in ?0.3 v dd q + 0.3 v input differential-pair cross voltage v ix (v dd q/2) - 0.2 (v dd q/2) + 0.2 v input differential voltage v id ( dc )0 . 3 6 v dd q + 0.6 v input differential voltage v id ( ac )0 . 7 0 v dd q + 0.6 v input current i i ?10 +10 a dynamic supply current i ddpd ?2 0 0 a dynamic supply current i ddq ?3 0 0 a dynamic supply current i add ?1 2m a input capacitance c in 2.0 3.5 pf table 14: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l?1 0 0 s input clock slew rate t slr(i) 1.0 4.0 v/ns ssc modulation frequency ? 30 50 khz ssc clock input frequency deviation ? 0 ?0.50 % pll loop bandwidth (?3db from unity gain) ? 2.0 ? mhz
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 15 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. serial presence-detect data for the latest serial presence-detec t data, refer to micron?s spd page: www.micron.com/spd . table 15: serial presence-detect eeprom dc operating conditions parameter/condition symbol min max units supply voltage v ddspd 2.3 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?1.0 v ddspd 0.3 v output low voltage: i out = 3ma v ol ?0 . 4v input leakage current: v in = gnd to v dd i li ?1 0 a output leakage current: v out = gnd to v dd i lo ?1 0 a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i sb ?3 0 a power supply current: sc l clock frequency = 100 khz i cc ?2 . 0m a table 16: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda fall time t f?300ns2 sda rise time t r?300ns2 data-in hold time t hd:dat 0 ? s start condition hold time t h:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 16 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm module dimensions module dimensions figure 5: 184-pin ddr rdimm (r/c j, -40b) notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. 28.73 (1.131) 28.42 (1.119) pin 1 17.78 (0.7) typ 2.5 (0.098) d (2x) 2.3 (0.091) typ 6.35 (0.25) typ 120.65 (4.75) typ 1.27 (0.05) typ 2.2 (0.087) typ 1.02 (0.04) typ 2.0 (0.079) r (4x) 0.9 (0.035) r pin 92 front view 1.37 (0.054) 1.17 (0.046) 133.5 (5.256) 133.2 (5.244) 64.77 (2.55) typ 49.53 (1.95) typ 10.0 (0.39) typ 3.99 (0.157) max pin 184 pin 93 back view u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 3.8 (0.15) typ 73.3 (2.88) typ
8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of thei r respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 512mb, 1gb (x72, ecc, sr) 184-pin ddr sdram rdimm module dimensions pdf: 09005aef8074e85b/source: 09005aef8072fe49 micron technology, inc., reserves the right to change products or specifications without notice. ddf18c64_128x72.fm - rev. f 9/08 en 17 ?2003 micron technology, inc. all rights reserved. figure 6: 184-pin ddr rdimm (r/c c, -335, -265) notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is fo r reference only. refer to the jedec mo document for addi- tional design dimensions. u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 28.73 (1.131) 28.42 (1.119) pin 1 17.78 (0.7) typ 2.5 (0.098) d (2x) 2.3 (0.091) typ 6.35 (0.25) typ 120.65 (4.750) typ 1.27 (0.05) typ 1.02 (0.04) typ 2.0 (0.079) r (4x) 0.90 (0.035) r front view 1.37 (0.054) 1.17 (0.046) 133.5 (5.256) 133.2 (5.244) 64.77 (2.55) typ 49.53 (1.95) typ 10.0 (0.39) typ 3.99 (0.157) max pin 184 pin 93 back view 2.2 (0.087) typ pin 92 73.3 (2.88) typ 3.8 (0.15) typ

▲Up To Search▲

Price & Availability of MT18VDDF12872Y-335XX

	To Download MT18VDDF12872Y-335XX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .