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tb62725ap/af/afn 2003-04-10 1 toshiba bi-cmos integrated circuit silicon monolithic tb62725ap,TB62725AF,TB62725AFn 8-bit constant-current led driver of the 3.3-v and 5-v power supply voltage operation the tb62725ap, TB62725AF and TB62725AFn are comprised of constant-current drivers designed for leds and led displays. the output current value can be set using an external resistor. as a result, all outputs will have virtually the same current levels. this driver incorporates a 8-bit constant-current output, a 8-bit shift register, a 8-bit latch circuit and a 8-bit and-gate circuit. these drivers have been designed using the bi-cmos process. features output current capability and number of outputs: 90 ma 8 outputs constant current range: 2 to 80 ma application output voltage: 0.7 v (output current 2 to 80 ma) 0.4 v (output current 2 to 40 ma) for anode-common leds input signal voltage level: 3.3-v and 5-v cmos level (schmitt trigger input) maximum output terminal voltage: 17 v serial data transfer rate: 20 mhz (max, cascade connection) operating temperature range: t opr = ? 40 to 85c package: type p: dip16-p-300-2.54a type f: ssop16-p-225-1.00a type fn: ssop16-p-225-0.65b package and pin layout: pin layout and functionality are similar to those of the tb62705. (each characteristic value is different.) constant-current accuracy (all outputs on) output voltage current error between bits current error between ics output current 0.4 v 2 to 40 ma 0.7 v 6% 15% 2 to 90 ma tb62725ap TB62725AF TB62725AFn weight dip16-p-300-2.54a: 1.11 g (typ.) ssop16-p-225-1.00a: 0.14 g (typ.) ssop16-p-225-0.65b: 0.07 g (typ.)
tb62725ap/af/afn 2003-04-10 2 pin assignment (top view) pin layout and functionality are similar to those of the tb62705c. (each characteristic value is different.) block diagram truth table clock latch enable serial-in out0 ??? out5 ??? out7 serial-out h l dn dn ??? dn 5 ??? dn 7 dn 7 l l dn 1 no change dn 6 h l dn 2 dn 2 ??? dn 3 ??? dn 5 dn 5 x l dn 3 dn 2 ??? dn 3 ??? dn 5 dn 5 x h dn 3 off dn 5 note 1: out0 to out7 on when dn h; out1 to out7 off when dn l. in order to ensure that the level of the power supply voltate is correct, an external resistor must be connected between r-ext and gnd. serial-in latch out0 r-ext enable i-reg q l d q l d d q ck q l d d q ck d q ck clock out1 out7 serial-out gnd serial-in latch cloc k out0 out1 out2 out3 vdd r-ext serial-out enable out7 out6 out5 out4
tb62725ap/af/afn 2003-04-10 3 timing diagram warning: latch circuit is leveled-latch circuit. be careful because it is not triggered-latch circuit. note 2: the latches circuit holds data by pulling the latch terminal low. and, when latch terminal is a high-level, latch circuit doesn?t hold data, and it passes from the input to the output. when enable terminal is a low-level, output terminal out0 to out7 respond to the data, and on and off does. attention: this ic can be used in 3.3 v or 5.0 v. however, use the v dd power supply and the input level in the same voltage system. serial-in latch clock out0 out1 out3 serial-out enable out7 3.3 v/5 v 0 v n 0 1 2 3 4 5 6 7 3.3 v/5 v 0 v 3.3 v/5 v 0 v 3.3 v/5 v 0 v on off on off on off on off 3.3 v/5 v 0 v off off off off on off off off off off on off
tb62725ap/af/afn 2003-04-10 4 terminal description pin no. pin name function 1 gnd gnd terminal for control logic. 2 serial-in input terminal for serial data for data shift register. 3 clock input terminal for clock for data shift on rising edge. 4 latch input terminal for data strobe. when the latch input is driven high, data is latched. when it is pulled low, data is hold. 5 to 12 out0 to out7 constant-current output terminals. 13 enable input terminal for output enable. all outputs ( out0 to out7 ) are turned off, when the enable terminal is driven high. and are turned on, when the terminal is driven low. 14 serial-out output terminal for serial data input on serial-in terminal. 15 r-ext input terminal used to connect an external resistor. this regulated the output current. 16 v dd 3.3-v and 5-v supply voltage terminal. equivalent circuits for inputs and outputs 1. enable terminal 2. latch terminal 3. clock, serial-in terminal 4. serial-out terminal 5. out0 to out7 terminals v dd enable gnd 200 k 100 r (up) v dd latch gnd 100 r (down) 250 k clock, serial-in v dd gnd 100 v dd gnd 100 serial-out parasitic diode out0 to out7 gnd
tb62725ap/af/afn 2003-04-10 5 maximum ratings (t opr 25c) characteristics symbol rating unit supply voltage v dd 6 v input voltage v in 0.2 to v dd 0.2 v output current i out 90 ma/ch output voltage v out 0.2 to 17 v p-type (when not mounted) p d1 1.47 af/afn-type (when not mounted) 0.37 power dissipation (note 3) af/afn-type (on pcb) p d2 0.78 w p-type (when not mounted) r th (j-a) 1 85 af/afn-type (when not mounted) r th (j-a) 2 330 thermal resistance (note 3) af/afn-type (on pcb) r th (j-a) 3 160 c/w operating temperature t opr 40 to 85 c storage temperature t stg 55 to 150 c note 3: p-type: power dissipation is derated by 11.76 mw/c if device is mounted on pcb and ambient temperature is above 25c. f- and fn-type: power dissipation is derated by 7.69 mw/c if device is mounted on pcb and ambient temperature is above 25c. with device mounted on glass-epoxy pcb of less than 40% cu and of dimensions 50 mm 50 mm 1.6 mm recommended operating conditions (t opr 40c to 85c unless otherwise specified) characteristics symbol test condition min typ. max unit supply voltage v dd 3 5.5 v output voltage v out 0.7 4 v i out each dc 1 circuit 2 80 ma/ch i oh serial-out 1 output current i ol serial-out 1 ma v ih 0.7 v dd v dd 0.15 input voltage v il 0.15 0.3 v dd ma clock frequency f clk cascade connected 20 mhz latch pulse width latch w t 50 ns i out 20 ma 2000 enable pulse width (note 4) enable w t i out
20 ma 3000 ns clock pulse width t wclock 25 set-up time for clock terminal t setup1 10 hold time for clock terminal t hold 10 set-up time for latch terminal t setup2 50 ns note 4: when the pulse of the low level is inputted to the enable terminal held in the high level.
tb62725ap/af/afn 2003-04-10 6 electrical characteristics (v dd 5 v, ta 25c unless otherwise specified) characteristics symbol test condition min typ. max unit supply voltage v dd normal operation 4.5 5 5.5 v i out1 v out 0.4 v, v dd 3.3 v r ext 490 29.84 35.10 40.36 i out2 v out 0.4 v, v dd 5 v r ext 250 29.58 34.80 40.02 i out3 v out 0.7 v, v dd 3.3 v r ext 490 58.40 68.70 79.00 output current i out4 v out 0.7 v, v dd 5 v r ext 250 57.55 67.70 77.85 ma i out1 v out 0.4 v, all outputs on r ext 490 1.5 6 output current error between bits i out2 v out 0.7 v, all outputs on r ext 250 1.5 6 % output leakage current i oz v out 15 v 1 5 a v ih 0.7 v dd v dd input voltage v il gnd 0.3 v dd v i oh 1.0 ma, v dd 3.3 v 0.3 sout terminal v ol i oh 1.0 ma, v dd 5 v 0.3 v i ol 1.0 ma, v dd 3.3 v 3 output voltage v oh i oh 1.0 ma, v dd 5 v 4.7 v output current supply voltage regulation %/v dd v dd 3 v 5.5 v 1.5 5.0 % pull-up resistor r (up) enable terminal 100 200 400 k pull-down resistor r (down) latch terminal 125 250 500 k i dd (off) 1 v out 15.0 v r ext open 0.1 0.5 i dd (off) 2 v out 15.0 v, all outputs off r ext 490 1 3 5 i dd (off) 3 v out 15.0 v, all outputs off r ext 250 3 6 8 v out 0.7 v, all outputs on r ext 490 6 9 i dd (on) 1 same as the above, t opr 40c 15 v out 0.7 v, all outputs on 12 17 supply current i dd (on) 2 same as the above, t opr 40c r ext 250 29 ma
tb62725ap/af/afn 2003-04-10 7 switching characteristics (t opr 25c unless otherwise specified) characteristics symbol test condition min typ. max unit t plh1 clk to outn , latch ?h?, enable ?l? 150 300 t plh2 latch to outn , enable ?l? 140 300 t plh3 enable to outn , latch ?h? 140 300 t plh clk to serial out 2 5 t phl1 clk to outn , latch ?h?, enable ?l? 170 340 t phl2 latch to outn , enable ?l? 170 340 t phl3 enable to outn , latch ?h? 170 340 propagation delay time t phl clk to serial out 2 5 ns output rise time t or 10 to 90% of voltage waveform 40 85 150 ns output fall time t of 90 to 10% of voltage waveform 40 70 150 ns maximum clock rise time t r 5 us maximum clock fall time t f cascade connection isn?t guarantee. (note 5) 5 us conditions: (refer to test circuit.) t opr 25c, v dd v ih 5 v, v out 0.7 v, v il 0 v, r ext 490 , v l 5.0 v, r l 100 , c l 10.5 pf note 5: if the device is connected in a cascade and t r /t f for the waveform is large, it may not be possible to achieve the timing required for data transfer. please consider the timings carefully. test circuit gnd serial-in latch clock out0 v dd r-ext serial-out enable out7 function generator i ol v ih , v hl i ref c l v l r l c l logic input waveform v dd v ih 5 v v il 0 v t r t f 10 ns (10% to 90%) i dd
tb62725ap/af/afn 2003-04-10 8 timing waveforms 1. clock, serial-in, serial-out 2. clock, serial-in, latch , enable , outn 3. outn t of 10% 90% 10% 90% t of outn off on t hold t plh /t phl t wclk 50% 50% 50% 50% t setup1 serial-in clock serial-out 50% t wena 50% t setup2 serial-in clock 50% 50% 50% 50% 50% t setup3 t phl1 / lh1 t phl2 / lh2 t phl3 / lh3 t wlat enable latch outn
tb62725ap/af/afn 2003-04-10 9 output current ? duty (led turn-on rate) duty ? turn on rate (%) i out (ma) duty ? turn on rate (%) i out ? duty on pcb i out (ma) i out ? duty on pcb duty ? turn on rate (%) i out (ma) i out ? duty on pcb 100 80 60 40 20 0 0 20 40 60 80 100 t opr 85c v dd 5.0 v v ce 1.0 v tj 120c (max) TB62725AF/afn tb62725ap ambient temperature ta ( c ) p d ?t opr power dissipation p d (w/ic) 100 80 60 40 20 0 0 20 40 60 80 100 TB62725AF/afn tb62725ap t opr 55c v dd 5.0 v v ce 1.0 v tj 120c (max) 100 80 60 40 20 0 0 20 40 60 80 100 t opr 25c v dd 5.0 v v ce 1.0 v tj 120c (max) TB62725AF/afn tb62725ap r ext ( ) i out (ma) i out ? r ext 90 80 60 40 20 0 70 50 30 10 100 1000 10000 t opr 25c v ce 0.7 v 5000 500 i out (ma) (1.15 r ext ( )) 14.9 1.6 1.2 1.0 0.6 0 0 100 1.4 0.8 0.2 0.4 20 40 60 80 af/afn (on pcb) ap (when not mounted)
tb62725ap/af/afn 2003-04-10 10 application circuit (example 1): the general composition in static lighting of led. more than v led (v) v f (total max) 0.7 is recommended with the following application circuit with the led power supply v led . r1: the setup resistance for the setup of output current of every ic. r2: the variable resistance for the brightness control of every led module. 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn c.u. serial-in enable latch clock scan r1 100 (min) v led serial-out serial-out r1 100 (min) r2 example) td62m8600f: 8-bit multi-chip pnp transistor array, which is not used in static li g htin g s y stem. serial-in enable latch clock o0 o1 o2 o5 o6 o7 o0 o1 o2 o5 o6 o7
tb62725ap/af/afn 2003-04-10 11 application circuit (example 2): when the condition of v led is v led 17 v. the unnecessary voltage is one effective technique as to making the voltage descend with the zenor diode. 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn c.u. serial-in enable latch cloc k scan r1 100 v led serial-out serial-out r1 100 r2 example) d62m8600f: 8-bit multi-chip pnp transistor array, which is not used in static li g htin g s y stem. serial-in enable latch cloc k o0 o1 o2 o5 o6 o7 o0 o1 o2 o5 o6 o7
tb62725ap/af/afn 2003-04-10 12 application circuit (example 3): when the condition of v led is v f 0.7 v led 17 v. v out v led v f 0.7 to 1.0 v is the most suitable for v out . surplus v out causes an ic fever and the useless consumption electric power. it is the one way of being effective to build in the r3 in this problem. r3 can make a calculation to the formula r3 (ohms) surplus v out /i out . though the resistance parts increase, the fixed constant current performance is kept. 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn c.u. serial-in enable latch clock scan r1 100 v led 15 v serial-out serial-out r1 100 r2 example) td62m8600f: 8-bit multi-chip pnp transistor array, which is not used in static li g htin g s y stem. r3 r3 serial-in enable latch clock o0 o1 o2 o5 o6 o7 o0 o1 o2 o5 o6 o7 8-bit sipo, latches and constant-sink-current drivers tb62725ap/af/afn
tb62725ap/af/afn 2003-04-10 13 notes operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena. to counter this, it is recommended that the ic be situated as close as possible to the led module. if overvoltage is caused by inductance between the led and the output terminals, both the led and the terminals may suffer damage as a result. there is only one gnd terminal on this device when the inductance in the gnd line and the resistor are large, the device may malfunction due to the gnd noise when output switching by the circuit board pattern and wiring. to achieve stable operation, it is necessary to connect a resistor between the rext terminal and the gnd line. fluctuation in the output waveform is likely to occur when the gnd line is unstable or when a capacitor (of more than 50 pf) is used. therefore, take care when designing the circuit board pattern layout and the wiring from the controller. this application circuit is a reference example and is not guaranteed to work in all conditions. be sure to check the operation of your circuits. this device does not include protection circuits for overvoltage, overcurrent or overtemperature. if protection is necessary, it must be incorporated into the control circuitry. the device is likely to be destroyed if a short-circuit occurs between either of the power supply pins and any of the output terminals when designing circuits, pay special attention to the positions of the output terminals and the power supply terminals (v dd and v led ), and to the design of the gnd line.
tb62725ap/af/afn 2003-04-10 14 package dimensions weight: 1.11 g (typ.)
tb62725ap/af/afn 2003-04-10 15 package dimensions weight: 0.14 g (typ.)
tb62725ap/af/afn 2003-04-10 16 package dimensions weight: 0.07 g (typ.)
tb62725ap/af/afn 2003-04-10 17 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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