View NJU3610_6943462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJU3610 -1- ver.2009.12.4 co nfi de n t i a l 1bit delta-sigma stereo adc general description the NJU3610 is the stereo analog to digital convector (adc) that covers from 8 to 192 khz sampling frequency. the NJU3610 provides 1bit delta-sigma technology with high accuracy and low power consumption. the analog inputs are differential signal and stereo 4-1 selectors are provided. the NJU3610 provides two power-supply 1.8v / 3.3v(typical) or single power-supply 3.3v(typical) application. features 1bit delta-sigma stereo adc 64fs over sampling (mck=256fs, 384fs) 32fs over sampling (mck=128fs) digital filter high-pass filter stereo 4-1 selectors sampling rate : 8 to 192khz dynamic range : 100db(typ@3.3v, 96khz) s/n : 100db(typ@3.3v, 96khz) s/(n+d) : 90db(typ@3.3v, 48khz, -1.0dbfs) master clock : 128fs(8 to 192khz), 256fs / 384fs(8 to 96khz) power supply : single power supply 3.0 to 3.6v(3.3vtyp) built-in regulator using together : two power supply 3.0 to 3.6v(analog, i/o:3.3vtyp) 1.65 to 2.0v(digital:1.8vtyp) digital audio format : 24/16bit left-justified, i 2 s master/slave operating temperature : -40 to +85 c package : lqfp48-r3 (pb-free) package NJU3610fr3
NJU3610 - 2 - ver. 2009.12.4 co nfi de n t i a l function block diagram ainlp1 ainln1 ainlp2 ainln2 ainlp3 ainln3 ainlp4 ainln4 ainrp1 ainrn1 ainrp2 ainrn2 ainrp3 ainrn3 ainrp4 ainrn4 decimation digital filter with high-pass filter serial audio interface sel0 sel1 vcom 4-1 selector lch 5th order delta-sigma modulator lch 1bit pdm 4-1 selector rch 5th order delta-sigma modulator rch 1bit pdm 24bit pcm 24bit pcm vregi vrego voltage regulator each analog blocks power control clock and timing control mck bck lrck sdo fmt0 mode0 mode1 hpf resetb pdnb avdd avss vdd18 vdd33 vss fmt1 avdd/avss : analog power supply (typ:3.3v) vdd18 : digital logic (typ:1.8v) vdd33 : digital i/o (typ:3.3v) vss : digital gnd and regulator gnd feedback 1bit dac rch feedback 1bit dac lch clock(64 or 32fs) / control signal power power reference reflp refln refrp refrn reference fig. 1 NJU3610 block diagram
NJU3610 -3- ver.2009.12.4 co nfi de n t i a l pin configuration fig.2 NJU3610 pin configuration 24 23 22 21 20 19 18 17 16 15 14 37 38 39 40 41 42 43 44 45 46 47 36 35 34 33 32 31 30 29 28 27 26 25 13 48 1 2 3 4 5 6 7 8 9 10 11 12 NJU3610fr3 sdo lrck bck hpf vss vdd18 vdd33 mck fmt0 fmt1 sel0 sel1 ainln4 ainlp4 reflp refln test avss avdd vcom refrn refrp ainrp4 ainrn4 ainrp3 ainrn3 ainrp2 ainrn2 ainrp1 ainrn1 aivss avdd mode1 mode0 resetb pdnb ainlp3 ainln3 ainlp2 ainln2 ainlp1 ainln1 avss avdd vdd33 vss vregi vrego
NJU3610 - 4 - ver. 2009.12.4 co nfi de n t i a l pin description table.1 pin description pin no. symbol i/o description 1 ainlp3 ai lch analog positive input 3 pin 2 ainln3 ai lch analog negative input 3 pin 3 ainlp2 ai lch analog positive input 2 pin 4 ainln2 ai lch analog negative input 2 pin 5 ainlp1 ai lch analog positive input 1 pin 6 ainln1 ai lch analog negative input 1 pin 7 avss ag analog ground pin 8 avdd ap analog power s upply pin, 3.3v 9 vdd33 dp digital power supply pin, 3.3v 10 vss dg digital ground pin 11 vregi ri built-in regulator input pin, 3.3v 12 vrego ro built-in regulator output pin, 1.8v (typ) 13 sdo do audio serial data output pin 14 lrck dio lr clock 15 bck dio bit clock 16 hpf di hpf for off-set cancel (?h?: on, ?l?: off) 17 vss dg digital ground pin 18 vdd18 dl digital power supply pin, 1.8v 19 vdd33 dp digital power supply pin, 3.3v 20 mck di master clock input pin 21 fmt0 di control serial data format 0 pin 22 fmt1 di control serial data format 1 pin 23 sel0 di control input selector 0 pin 24 sel1 di control input selector 1 pin 25 pdnb di power down mode pin (?h?: power up, ?l?: power down) 26 resetb di reset pin (?h?: reset off, ?l?: reset on) 27 mode0 di control mode 0 pin 28 mode1 di control mode 1 pin 29 avdd ap analog power s upply pin, 3.3v 30 avss ag analog ground pin 31 ainrn1 ai rch analog negative input 1 pin 32 ainrp1 ai rch analog positive input 1 pin 33 ainrn2 ai rch analog negative input 2 pin 34 ainrp2 ai rch analog positive input 2 pin 35 ainrn3 ai rch analog negative input 3 pin 36 ainrp3 ai rch analog positive input 3 pin 37 ainrn4 ai rch analog negative input 4 pin 38 ainrp4 ai rch analog positive input 4 pin 39 refrp ai rch voltage reference input pin, avdd 40 refrn ai rch voltage reference input pin, gnd 41 vcom ao common voltage output pin, avdd/2 connected to avss with a 10uf electrolytic capacitor. 42 avdd ap analog power s upply pin, 3.3v 43 avss ag analog ground pin 44 test ai test pin (connected to avss) 45 refln ai lch voltage reference input pin, gnd 46 reflp ai lch voltage reference input pin, a vdd 47 ainlp4 ai lch analog positive input 4 pin 48 ainln4 ai lch analog negative input 4 pin * ap : analog power supply, 3.3v ag : analog ground ai : analog input ao : analog output dp : digital power supply, 3.3v dl : digital power supply, 1.8v dg : digital ground and built-in regulator ground ri : built-in regulator input ro : built-in regulator output di : digital input do : digital output dio : bi-directional of digital
NJU3610 -5- ver.2009.12.4 co nfi de n t i a l absolute maximum ratings table 2. absolute maximum ratings (vss=avss=0v=gnd, ta=25 c) parameter symbol rating units analog avdd vdd33 -0.3 to +4.2 digital vdd18 -0.3 to +2.3 built-in regulator input vregi -0.3 to +4.2 power supplies built-in regulator output vrego -0.3 to +2.3 digital input v x(in) -0.3 to +5.5 (vdd33 ? 3.0v) -0.3 to +4.2 (vdd33<3.0v) digital output v x(out) -0.3 to vdd33 + 0.3 analog input v x(ain) pin voltage vcom output v x(vcom) -0.3 to avdd + 0.3 power dissipation p d 800 mounted on two-layer board of based on the jedec. mw operating temperature t opr -40 to +85 c storage temperature t str -40 to +125 c * avdd : 8, 29, 42pin * vdd33 : 9pin * vdd18 : 18pin * vregi : 11pin * vrego : 12pin * v x(in) : 16, 20-28pin, and 14-15pin (set in the state of the input.) * v x(out) : 13pin, and 14-15pin (set in the state of the output.) * v x(ain) : 1-6, 31-40, 44-48pin * v x(vcom) : 41pin note 1) if the lsi is used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electrical characteristics conditions will cause malfunction and poor reliability. note 2) please do not open the digital input terminal. moreover, please do not open the digital i/o terminal set in the state of the input. recommended operating conditions table 3. recommended operating conditions parameter symbol recommended operating conditions units analog avdd *1 vdd33 *1 3.0 to 3.6 av d d 3 3 ? vdd33 digital vdd18 *2 1.65 to 2.0 (or, a built-in regulator supplies the voltage.) power supplies built-in regulator input vregi *3 3.0 to vdd33 v *1 vdd33 is recommended to be turned on from avdd and simultaneous or avdd back. *2 the power up sequence vdd18 is not critical. *3 when a built-in regulator is used, vregi is connected with vdd33. when a built-in regulator is not used, vregi and vrego are connected with vss. v
NJU3610 - 6 - ver. 2009.12.4 co nfi de n t i a l electric characteristics table 4. analog characteristics parameter condition min. typ. max. units ain*** pin (differential one side) avdd x 0.7 full-scale voltage level *1 ain*** pin (between differential motions) avdd x 1.4 vpp s/(n+d) (-1.0dbfs) fs=48khz fs=96khz fs=192khz 85 - - 90 90 90 - - - db dynamic range (-60dbfs, a-weighted) fs=48khz fs=96khz fs=192khz 93 - - 99 100 100 - - - db s/n (a-weighted) fs=48khz fs=96khz fs=192khz 93 - - 99 100 100 - - - db cross talk (during the selection and non-selection) fs=48khz, 1khz bpf - 110 - db channel separation (between l and r) fs=48khz, 1khz bpf 97 110 - db equivalent input impedance (selection input terminal) fs=48khz fs=96khz fs=192khz - - - 100 50 50 - - - kohm input impedance *2 (non-selection input terminal) fs=48khz fs=96khz fs=192khz 40 40 40 58 58 58 - - - kohm gain mismatch fs=48khz -0.1 - 0.1 db (ta=25 c, avdd=vdd33=3.3v, vdd18=vrego, hpf=on, input signal=1khz(ainl*4/ainr*4), bck=64fs, mck=256fs(48/96khz), 128fs(192khz), measurement frequency=20hz-20khz at fs=48khz, 20hz-40khz at fs=96khz, 20hz-40khz at fs=192khz) *1 the full-scale voltage level indicates full-scale value (0dbfs) of the analog input voltage. a full-scale voltage is proportional to the avdd voltage. the meaning between differential motions is an operation result of the differential input signal. the input voltage of the terminal is up to avdd voltage. *2 the analog input terminal of non-selection does the bias to vcom by the resistance of this value. table 5. power supply current ta=25 c, avdd=vdd33=3.3v, vdd18=1.8v parameter condition min. typ. max. units 3.3v, power supply current: i dd + i dda (not contain a built-in regulator) fs=48khz fs=96khz fs=192khz - - - 7.0 8.0 8.0 - - 12 ma 1.8v, power supply current: i ddl (not contain a built-in regulator) fs=48khz fs=96khz fs=192khz - - - 2.0 4.0 8.0 - - 10 ma power down mode: i ddq +i ddlq (not contain a built-in regulator) clock stop pdnb=low - - 100 m a built-in regulator current: i rin vregi=3.3v i out =0ma - 50 70 m a
NJU3610 -7- ver.2009.12.4 co nfi de n t i a l table 6. digital dc characteristics (ta=25 c, vdd33=3.3v, vdd18=1.8v) parameter symbol condition min. typ. max. units high-level input voltage v ih 2.2 - vdd33 *1 v low-level input voltage v il 0 - 0.8 v high-level output voltage v oh i oh =-1ma vdd33 x 0.8 - vdd33 v low-level output voltage v ol i ol =1ma 0 - vdd33 x 0.2 v input leakage current i in v in =vss, vdd -10 - 10 m a *1 the digital input terminal and the input digital i/o terminal are 5v tolerant only at vdd33 ratings. table 7. reset ac characteristics ( ta=25 c, vdd33=3.3v, vdd18=1.8v) parameter symbol condition min. typ. max. units reset time t resetb resetb 100 - - ns table 8. digital filter characteristics ( ta=25 c, vdd33=3.3v, vdd18 l =1.8v) parameter condition min. typ. max. units cut-off frequency (hpf=high) -3.0db - fs/44100 - hz lpf pass band 0 - 0.454 fs lpf pass band ripple - - ? 0.005 db lpf stop band 0.546 - - fs lpf stop band attenuation -80 - - db group delay - 27 - 1/fs
NJU3610 - 8 - ver. 2009.12.4 co nfi de n t i a l table 9. clock timing ( ta=25 c, vdd33=3.3v, vdd18=1.8v) parameter symbol condition min. typ. max. units mck frequency *1 f mck 128fs 256fs 384fs 1.024 2.048 3.072 - - - 24.576 24.576 36.864 mhz bck frequency *2 f sck slave 0.256 - 12.288 mhz lrck frequency *2 f lrck slave 8.0 - 192 khz mck pulse width low mck pulse width high t mil t mih 0.475/f mck 0.475/f mck 0.5/f mck 0.5/f mck 0.525/f mck 0.525/f mck ns bck pulse width low bck pulse width high t sil t sih slave slave 35 35 0.5/f mck 0.5/f mck - - ns bck to lrck *3 t sli slave 20 - - ns lrck to bck *3 t lsi slave 20 - - ns *1 for fs=8 to 192khz at 128fs mode. for fs=8 to 96khz at 256fs/384fs mode. *2 mck should synchronized with bck and lrck. (not necessary to phase it.) *3 bcki rising edge must not occur at the same time as lrck edge fig.3 mck timing diagram fig.4 bck, lrck timing diagram table 10. serial audio output timing ( ta=25 c vdd33=3.3v, vdd18=1.8v) parameter symbol condition min. typ. max. units bck to lrck time *1 t slo cl=25pf -20 - 20 ns data output delay t dod cl=25pf - - 20 ns *1 it is regulation in master mode. fig.5 serial audio output timing diagram mck t mil t mih lrck bck t sih t lsi t sil t sli sdo t do d lrck bck t s l
NJU3610 -9- ver.2009.12.4 co nfi de n t i a l 1. power-supply, reset , power down 1.1 power-supply the power-supply should be used under the recommended condition. the power-on level procedure should increase monotonously. during the operation, the power-supply should not become out of the recommended condition. the large size decoupling capacitor should be implemented near the NJU3610. the analog/digital power line should be taken from this large capacitor. also the power-supply terminals should have enough decoupling capacitors to the terminals. the reflp, refln, refrp, refrn are the reference voltage terminals of the 1bit-feedback-dac. the reflp and refrp should be connected to avdd power line. the reflpn and refrn should be connected to avss line. these terminals affect the analog performance, so the decoupling capacitor is very important. the vcom output is the half of the avdd voltage level with the voltage-follower buffer. the vcom voltage level is the internal reference. the non-selected input terminals are pull-upped to the internal reference via 58k-ohm resistors. the 10uf capacitor is recommended to improve noise and channel separation performance. this terminal output is available for the analog reference level of the input circuit. the NJU3610 provides the internal voltage regulator for internal digital circuit. the vregi terminal is the input to the internal regulator. the input to vregi should be the same voltage as vdd33 input. the output of the internal voltage regulator is vrego. if the vrego output is connected to vdd18, no other 1.8v power-supply is necessary. if the internal voltage regulator is used, put the capacitor (around 4.7 to 10uf) between vrego and vss. if the internal voltage regulator is not used, connect both vregi and vrego to vss. the internal voltage regulator is provided for the NJU3610 circuit, do not use it for the other circuit. if the vdd33 and avdd are different power-supply, follow the next power-on procedure. first power on analog power-supply (avdd). next power on digital power-supply (vdd33). also it is possible to power on analog and digital power-supply simultaneously. power-on timing condition: avdd (before) ? vdd33 (same or after) there is no constraining on vdd18 power-on procedure. also there is no constraining on power-down procedure for all power-supplies.
NJU3610 - 10 - ver. 2009.12.4 co nfi de n t i a l 1.2 digital input terminal all digital input terminals are 5v tolerant under the recommended vdd33 power-on condition. also bck and lrck that are assigned as input mode are 5v tolerant under the recommended vdd33 power-on condition. input/output setting of bck and lrck are defined by fmt1 terminal. these terminals are input mode in case of fmt1 = ?low? and output mode in case of fmt1 = ?high?. during resetb terminal = ?low?, bck and lrck are input mode regardless of fmt1 condition. 1.3 reset and power down during resetb terminal = ?low?, digital filter and analog integrator are initialized and sdo output is low level. the internal reference voltage generator is operating during resetb terminal = ?low?. if the terminal setting or clock is changed under adc operation, resetb should be initialized again. in case of pdnb = ?low?, all analog circuit become power-down mode. the digital filter is operating under pdnb = ?low?, but the clock to analog circuit is stopped. if power-down mode is not used, pdnb should be ?high?. after power-on, the next reset procedure should be done at least one time to initialize the NJU3610. resetb should be ?low? level and become ?high? level again. changing pdnb from ?low ?level to ?high? level makes vcom reference level generated. the setup time of vcom-reference-level depends on the attached capacitor. the procedure to change resetb level (?low? to ?high?) should be done, after vcom level becomes stable. the procedure of sdo audio data output is as following: first reset is released from ?low? to ?high? level. after reset release, wait 136 ? 8fs period and sdo generates audio data. but to get the accurate output data, vcom reference level should become half of avdd level. if the high pass filter is used to cancel offset (hpf=?high?), some more time (max. 8192fs) after generating audio data is necessary to get accurate output data. in order to power down the NJU3610 completely, pdnb should be ?low? and, also clocks to mck, bck and lrck should be stopped. notice: the internal regulator does not provide power-down mode. as far as power is supplied to vreg1, it generates output voltage with consuming power.
NJU3610 -11- ver.2009.12.4 co nfi de n t i a l 2. adc function 2.1 clock and digital audio interface the NJU3610 requires mck, bck and lrck audio clock. bck and lrck can be generated by mck in master mode. mck, bck and lrck are synchronized in master mode. in slave mode, bck and lrck are inputted from the outside. in slave mode, mck, bck and lrck should be synchronized. but it is not necessary that the phase of these three clocks are synchronized. mck frequency should be one of 128fs, 256fs or 384fs. if fs>96khz, mck should be 128fs. the adc operates with the next frequency. the operate frequency is 64fs in case of fs ? 96khz. the operate frequency is 32fs in case of fs>96khz. mode0 and mode1 terminals select the mck frequency and adc operating frequency. in case that adc operating frequency is 32fs, the effective bandwidth is 1/4fs. between 1/4fs and 1/2fs, adc shaping noise exists. the NJU3610 digital audio format provides left-justified and i 2 s 24bit(bck=64clocks/fs) in master mode. the NJU3610 digital audio format provides left-justified, i 2 s 16bit (bck=32clocks/fs) and i 2 s 24bit(bck=64clocks/fs) in slave mode. fmt0 and fmt1 terminals select the above digital audio format. when fmt0, fmt1, mode0 and mode1 are changed, reset should be done again. mck, bck and lrck frequency is shown in table11. digital audio format and operation mode is shown in table12. in master mode, bck and lrck terminals generate clocks. bck output clock is fixed at 64fs in master mode. in slave mode, bck and lrck terminals are assigned input. ta b le 11 . mck, bck, lrck (1) lrck(khz) master: generation from mck slave: from outside mck (mhz) bck(mhz) 128fs 256fs 384fs 32fs slave only: from outside 64fs master: generation from mck slave: from outside 8 - *2 2.048 3.072 0.256 0.512 16 - *2 4.096 6.144 0.512 1.024 22.05 - *2 5.6448 8.4672 0.7056 1.4112 32 - *2 8.192 12.288 1.024 2.048 44.1 - *2 11.2896 16.9344 1.4112 2.8224 48 - *2 12.288 18.432 1.536 3.072 64 - *2 16.384 24.576 2.048 4.096 88.2 - *2 22.5792 33.8688 2.8224 5.6448 96 - *2 24.576 36.864 3.072 6.144 176.4 *1 22.5792 - - 5.6448 11.2896 192 *1 24.576 - - 6.144 12.288 *1 it is only a setting of ?ckmode[1:0]=10,11?. at this time, frequency bandwidth is up to 1/4fs. the shaping noise of the adc is included in the band from 1/4fs to 1/2fs. *2 because an effective bandwidth is limited, it is not practicable.
NJU3610 - 12 - ver. 2009.12.4 co nfi de n t i a l table 12. mck,bck,lrck (2) cmkode fmt 1 0 1 0 master / slave a/d mode mck (fs) format 0 0 0 0 i 2 s (32 or 64fs) 0 0 0 1 slave left-justified(32 or 64fs) 0 0 1 0 i 2 s (64fs) 0 0 1 1 master 64fs 256fs ( ? 96khz) left-justified(64fs) 0 1 0 0 i 2 s (32 or 64fs) 0 1 0 1 slave left-justified(32 or 64fs) 0 1 1 0 i 2 s (64fs) 0 1 1 1 master 64fs 384fs ( ? 96khz) left-justified(64fs) 1 0 0 0 i 2 s (32 or 64fs) 1 0 0 1 slave left-justified(32 or 64fs) 1 0 1 0 i 2 s (64fs) 1 0 1 1 master 32fs 256fs (>96khz) left-justified(64fs) 1 1 0 0 i 2 s (32 or 64fs) 1 1 0 1 slave left-justified(32 or 64fs) 1 1 1 0 i 2 s (64fs) 1 1 1 1 master 32fs 128fs (>96khz) left-justified(64fs) fig.6 left-justified data format 64fs, 24bit data fig.7 i 2 s data format 64fs, 24bit data fig.8 left-justified data format 32fs, 16bit data fig.9 i 2 s data format 32fs, 16bit data 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 left channel right channel msb m sb lsb lsb 32 clocks 32 clocks lrck bck sdo 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel ri ght channel ms b m sb lsb lsb 32 clocks 32 clocks lrck bck sdo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel m sb msb lsb lsb 16 clocks 16 clocks lrck bck sdo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 left channel right channel msb m sb lsb lsb 16 clocks 16 clocks lrck bck sdo
NJU3610 -13- ver.2009.12.4 co nfi de n t i a l 2.2 high pass filter for offset-cancel the NJU3610 provides high pass filter (digital filter) to cancel offset. normally hpf terminal is set ?high?. in case of hfp=?high?, high pass filter is active. the frequency characteristics are shown in table 8. the cutoff frequency is set at low frequency. but sampling rate changes the cutoff frequency. hfp terminal setting can be changed during NJU3610 operating. but changing hpf setup makes pop noise that is caused by offset change. 2.3 analog input and 4-1 selector the NJU3610 provides four differential-stereo-inputs. sel0 and sel1 terminals select one of four stereo-input. after this selector, input signal goes to adc input. sel0 and sel1 combination is shown in table13. table 13. sel1, sel0 combination -di 3di 4&- 4&- /posfwfstjoh joqvu 3fwfstjoh joqvu /posfwfstjoh joqvu 3fwfstjoh joqvu "*/-1 "*/-/ "*/31 "*/3/ "*/-1 "*/-/ "*/31 "*/3/ "*/-1 "*/-/ "*/31 "*/3/ "*/-1 "*/-/ "*/31 "*/3/ each differential-signal input should be biased with vcom reference level. the half of avdd level is available instead of vcom reference level. input full-scale level (0dbfs) is ?avddx0.7vpp?. in differential signal, input full-scale level is ?avddx1.4vpp?. maximum available input range is from gnd to avdd with distortion. but in this case, the distortion occurs. when amp with high voltage power-supply is used before the adc, the input level should not exceed the adc input range. sel0 and sel1 settings are taken in at mck rising edge. in case of resetb=?low?, ainlp1, ainln1, ainrp1 and ainrn1 are selected regardless of sel0/sel1 settings. in case that pdnb level is changed from ?high? to ?low?, the latest condition is maintained. the terminals that are not selected by sel0/sel1 are pull-upped by vcom bias via 58ohm resisters. the analog input terminals that are not used should be left open or adds the capacitors between terminals and gnd. if these terminals connect directly to power-supply or gnd, vcom fluctuates and the NJU3610 does not operate properly. the NJU3610 operates with 32fs over sampling at mode1=?high?. the NJU3610 operates with 64fs over sampling at mode1=?low?. if noise exists around over sampling frequency, the noise folds back. to avoid this folding back noise, passive rc filter is required. the example of input buffer circuit is shown in figure10. vcom output is used for bias level. the j1 selects rca or xlr input. the rc-passive-filter is consist of ra/rb(220ohm), ca/cb(100pf) and cc(200pf). the cutoff frequency of rc-passive-filter is 1447khz. this input buffer circuit should be implemented to analog input terminals as far as short distance. the layout pattern should be symmetric. "*// "*/1 3 $ 3 3b 3c $bq $cq $dq 7$0.@065 #*"4 7 %%" y
3 $ 3 #*"4 #*"4 /+6 3$" 9-3 + fig.10 input buffer example
NJU3610 - 14 - ver. 2009.12.4 co nfi de n t i a l package dimension lqfp48-r3 (pb-free) plating: sn-bi ?ty t???? ???? ????? ????? ??t ??? ?y??? ? ? ?? t y ? ? ??? t??? t??? ??? ? ???? [caution] the specifications on this data book are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this data book are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. mold

▲Up To Search▲

Price & Availability of NJU3610

	To Download NJU3610 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .