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scdct2512pcb rev a features ? ct2512-pcb replaces ddc bus-65112 and bus-65117 ? ct2513-pcb replaces ddc bus-65113 and bus-65118 ? ct2510-pcb replaces ddc bus-65110 and bus-65120 ? ct2511-pcb replaces ddc bus-65111 and bus-65121 ? functions as a complete remote terminal unit ? supports 13 mode codes, illegalization of codes allowed ? transfers data with dma type handshaking ? latched outputs for command word and word count ? 14 bit built-ln-test word register ? 4 error flag outputs ? advanced low power vlsi technology ? cots pcb construction ? designed for commercial, indust rial and aerospace applications general description aeroflex?s ct2512-pcb contains 2 transceivers, 2 encoder/ decoders, bit processors an d complete remote terminal (rt) logic. the device is constructed using aeroflex advanced vlsi custom chip and hybrid technology. it functions as a complete dual redundant mil-std-1553b rt unit suppo rting all 13 mode codes for dual redundant operation. the ct2512-pcb is a pin-for-pin functional equivalent of the ddc bus-65112/117 and performs parallel data transfers with a dma type handshake. mu ltiple error flag outputs and host access to many of the rt status word bits are just some of the features that ma ke this part ideal for many rt appli cations. the unit has an operating range of -55c to +125c. see "ordering information" (last sheet) for ct2513-pcb / ct2510-pcb / ct2511-pcb. ct2512-pcb/2513-pcb/2511-pcb/2511-pcb standard products dual redundant remote terminal september 21, 2005 for mil-std-1553b in pcb style figure 1 ? functional block diagram db0-db15 a0-a11 error flag timing flags status bits mil-std-1553b protocol and bit processing logic encoder/ decoder encoder/ decoder dual transceiver data bus a data bus b i/o interface www.aeroflex.com/avionics
2 scdct2512pcb rev a absolute maximum ratings parameter limits units power supply voltage (v cc ) (pins 18, 76) -0.3 to +18.0 volts power supply voltage (v ee ) (pins 38, 57) +0.3 to -18.0 volts power supply voltage (v ccl ) (pins 37, 58 / 51) -0.3 to +7.0 volts receiver differential input (pins 20, 59 / 74, 36) 20 (40vp-p) volts receiver input voltage (pins 20, 59 / 74, 36) 15 volts driver output current (pins 56, 17 / 39, 77) +200 ma transmission duty cycle at t pcb = 100c 1 / 100 % operating temperature range -55 to +125 c note: 1 / t pcb is pcb bottom surface temperature under transceiver. power and thermal data (single transceiver and logic section) parameter/conditions symbol min typ max units power supply voltage v cc v ee v ccl 14.25 -14.25 4.5 15 -15 5 15.75 -15.75 5.5 v v v thermal resistance, most critical device 4 / ? jc -10- c/w power dissipation of most critical (hottest) device during continuous transmission (100% duty cycle) 1 / p c -2- w total supply current standby mode, or transmitting at less than 1% duty cycle (e.g. 20us of transmission every 2ms or longer interval) i cc i ee 2 / i ccl 2 / - - - 0 12 20 5 20 50 ma ma ma total supply current transmitting at 1mhz into a 35-ohm load at point a in figure 2 3 / i cc @ 25% i cc @ 100% - - 90 180 100 200 ma ma notes 1 / decreases linearly to zero at zero duty cycle. 2 / limit does not change with m ode of operation or duty cycle. 3 / decreases linearly to applicable "standby" values at zero duty cycle. 4 / referenced to t pcb electrical characteristics (receiver section) parameter/conditions sy mbol min max units differential input impedance dc to 1mhz point a point b z in 2k 1k - - differential voltage range v dir 20v - vpeak input common mode voltage range v icr 10v - vpeak common mode rejection ratio (from point a, figure 1) cmmr 40 - db threshold characteristics, sine wave at 1mhz note: threshold voltages refer to point a or point b - figure 2. point a point b v th 0.6 0.4 1.2 0.86 vp-p vp-p
3 scdct2512pcb rev a electrical characteristics (transmitter section) parameter/conditions symbol min typ max units differential output level, figure 1 (145 ohm load) point a point b v o 6 18 7.5 20 9 27 vp-p vp-p rise and fall times (10% to 90% of p-p out put) point a or point b t r 100 - 300 ns output offset, figure 2 (35-ohm load) 2.5us after mid-bit crossing of pari ty bit of last word of a 660us message point a point b v os -90 -250 - - +90 +250 mvpeak mvpeak differential output noise point a point b v noi - - - - 5 14 mvp-p mvp-p logic characteristics symbol parameter min typ max units conditions v ih input "1" 2.4 - - v dc v il input "0" --0.7v dc i il input l -650 - -100 a note 1a i ih input l -650 - -100 a note 1b i il input l -20 - +20 a note 2a i ih input l -20 - +20 a note 1b v oh output "1" 2.7 - - v dc note 3a/4a v ol output "0" --0.4v dc note 3b/4b note 1: for input pins 12,13,14,15, 53, 54, 55. v cc = 5.5v a. @ v il = 0.4v b. @ v ih = 2.4v note 2: all remaining inputs other than in note 1. vcc = 5.5v a. @ v il = 0.4v b. @ v ih = 2.4v note 3: for output pins 4 through 11 and 43 through 50. a. @ v cc = 4.5v and i oh = 3ma b. @ v cc = 2.4v and i ol = 6ma note 4: all remaining outputs other than in note 3. a. @ v cc = 4.5v and i oh = 2ma b. @ v cc = 5.5v and i ol = 4ma
4 scdct2512pcb rev a terminal connections and pin functions plug-in pkg flat pkg function description 1 2 a9 latched output of the most significant bit (m sb) in the subaddress field of the command word. 24 a7 latched output of the third most significant bit in the subaddress field of the command word. 3 6 a5 latched output of the least significant bit (l sb) in the subaddress field of the command word. 4 8 db1 bidirectional parallel data bus bit 1. 5 10 db3 bidirectional parallel data bus bit 3. 6 12 db5 bidirectional parallel data bus bit 5. 7 14 db7 bidirectional parallel data bus bit 7. 8 16 db9 bidirectional parallel data bus bit 9. 9 18 db11 bidirectional parallel data bus bit 11. 10 20 db13 bidirectional parallel data bus bit 13. 11 22 db15 bidirectional parallel data bus bit 15 (msb). 12 24 bro ena broadcast enable - when high, this input allows recognition of an rt address of all ones in the command word as a broadcast message. when lo w, it prevents response to rt address 31. 13 26 addre input of the msb of the assigned terminal address. 14 28 addrc input of the 3rd msb of the assigned terminal address. 15 30 addra input of the 3rd msb of the assigned terminal address. 16 32 rtadd err output signal used to inform subsystem of an address parity error. if low, indicates parity error and the rt will not respond to any command address to a single terminal. it will still receive broadcast co mmands if bro ena is high. 17 34 txdataout b low output to the primary side of the co upling transformer that connects to the b channel of the 1553 bus. 18 36 v cc b +12 / +15 volt input power supply connection for the b channel transceiver. 19 38 gnd b power supply return connection fo r the b channel transceiver. 20 40 rxdatain b input from the high side of the primary side of the coupling transf ormer that connects to the b channel of the 1553 bus. 21 81 a3 multiplexed address line output. when incmd is low, or a5 through a9 are all zeroes or all ones (mode command), it represents the latched output of the 2nd msb in the word count field of the command word. when incmd is high and a5 through a9 are not all zeroes or all ones, it represents the 2nd msb of the current word counter. (see note 1). 22 79 a1 multiplexed address line output. when incmd is low, or a5 through a9 are all zeroes or all ones (mode command), it represents the latched output of the 2nd lsb in the word count field of the command word. when incmd is high and a5 through a9 are not all zeroes or all ones, it represents the 2nd ls b of the current word counter. (see note 1). 23 77 dtgrt data transfer grant - active low input signal from the subsystem that informs the rt, when dtreq is asserted, to start the transfer. once the transfer is started, dtgrt can be removed. 24 75 incmd in command - high level output signal used to inform the subsystem that the rt is presently servicing a command. when low, a0-a4 (see note 1) represent the word count of the present command. when high, a0-a4 represent the current word counter of non-mode commands.
5 scdct2512pcb rev a 25 73 hs fail handshake fail - output signal that goes low and stays low whenever the subsystem fails to supply dtgrt in time to do a successful tr ansfer. cleared by the next nbgt . 26 71 dtstr data strobe - a low level output pulse (166 ns) present in the middle of every data word transfer over the parallel data bus. used to latch or strobe the data into memory, fifos, registers, etc. recommend using the ri sing edge to clock data in. (see note 2). 27 69 dat/cmd address line output that is low whenever the command word is being transferred to the subsystem over the parallel data bus, a nd is high whenever da ta words are being transferred. 28 67 rt fail remote terminal failure - latched active low output signal to the subsystem to flag detection of a remote terminal continuous self-test failure. also set if the watchdog timeout circuit is activated. cleared by the start of the ne xt message transmission (status word) and set if proble m is again detected. 29 65 dtreq data transfer request - active low output signal to the subsystem indicating that the rt has data for or needs data from the subsystem and requests a data transfer over the parallel data bus. will stay low until transfer is completed or transfer until transfer is completed or transfer timeout has occurred. 30 63 adbc accept dynamic bus control - active low input signal from subsystem used to set the dynamic bus control acceptance b it in the status register if the command word was a valid, legal mode command for dynamic bus control. 31 61 test 2 factory test point - do not use. (see note 3). 32 59 a10 latched output of the t/r bit in the command word. 33 57 ill cmd illegal command - active low input signal from the subsystem, strobed in on the rising edge of incmd. used to define the command word as illegal and to set the message error bit in the status register. 34 55 ss req subsystem service request - input from the s ubsystem used to control the service request bit in the status register. if low when the status word is updated, the service request bit will be set; if high, it will be cleared. 35 53 biten built-in-test word enable - low level output pulse (500 ns), present when the built-in-test word is enabled on the parallel data bus. (see note 4). 36 51 rxdatain a input from the low side of the primary side of the couplin g transformer that connects to the a channel of the 1553 bus. 37 49 v l a +5 volt input power supply connection for the a channel transceiver. 38 47 v ee a -12 / -15 volt input power supply connection for the a channel transceiver. (see note 7). 39 45 txdataout a high output to the primary side of the coupling transformer that connects to the a channel of the 1553 bus. 40 43 nbgt new bus grant - low level output pulse (166 ns) used to indicate the start of a new protocol sequence in response to the co mmand word just recei ved. (see note 2). 41 3 a8 latched output of the 2nd msb in the subaddress field of the command word. 42 5 a6 latched output of the 2nd lsb in the subaddress field of the command word. 43 7 db0 bidirectional parallel data bus bit 0 (lsb). 44 9 db2 bidirectional parallel data bus bit 2. 45 11 db4 bidirectional parallel data bus bit 4. 46 13 db6 bidirectional parallel data bus bit 6. 47 15 db8 bidirectional parallel data bus bit 8. terminal connections and pin functions (con?t) plug-in pkg flat pkg function description
6 scdct2512pcb rev a 48 17 db10 bidirectional parallel data bus bit 10. 49 19 db12 bidirectional parallel data bus bit 12. 50 21 db14 bidirectional parallel data bus bit 14. 51 23 v l +5 volt input power supply connection for rtu digital logic section. 52 25 gnd power supply return for rtu digital logic section. 53 27 addrd input of the 2nd msb of the assigned terminal address. 54 29 addrb input of the 2nd lsb of the assigned terminal address. 55 31 addrp input of address parity bit. the combina tion of assigned termin al address and addrp must be odd parity for the rt to work. 56 33 txdataout b high, output to the primary side of the coupling transformer that connects to the b channel of the 1553 bus. 57 35 v ee b -12 / -15 volt input power supply connection fo r the b channel transceiver. (see note 7). 58 37 v l b +5 volt input power supply connection for the b channel transceiver. 59 39 rxdatain b input from the low side of primary side of the coupling transformer that connects to the b channel of the 1553 bus. 60 80 a2 multiplexed address line output. when incm d is low, or a5 thro ugh a9 are all zeroes or all ones (mode command), it represents th e latched output of the 3rd msb in the word count field of the command word. when incmd is high and a5 through a9 are not all zeroes or all ones, it represents the 3rd msb of the current word counter. (see note 1). 61 78 a0 multiplexed address line output. when incm d is low, or a5 thro ugh a9 are all zeroes or all ones (mode command), it represents the latched output of the lsb in the word count field of the command. when incmd is high and a5 through a9 are not all zeroes or all ones, it represents the lsb of the current word counter. (see note 1). 62 76 dtack data transfer acknowledge - active low output signal during data transfers to or from the subsystem indicating the rtu has received the dtgrt in response to dtreq and is presently doing the transfer. can be connected directly pins 67 on plug-in pkg or pin 66 on flat pkg (buf ena ) for control of 3-state data buff ers; and to 3-state address buffer control lines, if they are used. 63 74 a4 multiplexed address line output . when incmd is low or a5 through a9 are all zeroes or all ones (mode command), it represents the latched output of the msb in the word count field of the command word. when incmd is high and a5 through a9 are not all zeroes or all ones, it represents the msb of the current word co unter. (see note 1). 64 72 r/w read/write - output signal that controls the direction of the internal data bus buffers. normally, the signal is low and the buffers driv e the data bus. when data is needed from the subsystem, it goes high to turn the buffers around and the rt now appears as an input. the signal is high only when dtreq is active (low). 65 70 gbr good block received - low level output pulse (5 00 ns) used to flag the subsystem that a valid, legal, non-mode receive command with the correct number of data words has been received without a message error and successf ully transferred to the subsystem. (see note 4). 66 68 12 mhz 12 mhz clock input - input for the master clock used to run rtu circuits. 67 66 buf ena buffer enable - input used to enable or 3-state the internal data bus buffers when they are driving the bus. when low, the data bus buffers are enabled. could be connected to dtack , (pin 62, plug-in pkg), (pin 76, flat pkg) if rt is sharing the same data bus as the subsystem. (see note 5). 68 64 reset input resets entire rt when low. terminal connections and pin functions (con?t) plug-in pkg flat pkg function description
7 scdct2512pcb rev a 69 62 rt flag remote terminal flag - input signal used to control the terminal flag bit in the status register. if low when the status word is updated, the terminal flag bit would be set; if high, it would be cleared. normally connected to rtfail ; (pin 28, plug-in pkg); (pin 67, flat pkg). 70 60 test 1 factory test point - do not use. (see note 6). 71 58 busy subsystem busy - input from the subsystem used to control the busy bit in the status register. if low when the status word is updated, the busy bit will be set; if high, it will be cleared. if the busy bit is set in the stat us register, no data will be requested from the subsystem in response to a transmit command. on receive commands, data will still be transferred to subsystem. 72 56 ss flag subsystem flag - input from the subsystem used to control the subsystem flag bit in the status register. if low when the status word is updated, the subsystem flag will be set; if high, it will be cleared. 73 54 mess err message error - output signal that goes low an d stays low whenever there is a format or word error with the received message over the 1553 data bus. cleared by the next nbgt . 74 52 rxdatain a input from the high side of the primary side of the coupling transf ormer that contacts to the a channel of the 1553 bus. 75 50 gnd a power supply return connection for the a channel transceiver. 76 48 v cc a +12 / +15 volt input power supply connection for the a channel transceiver. 77 46 txdataout a low output to the primary side of the coup ling transformer that connects to the a channel of the 1553 bus. 78 44 staten status word enable - low level active output signal present when the status word is enabled on the parallel data bus. notes: 1. when incmd is low during the dtstr immediately following nbgt , a0 through a4 are valid and equal to wc0 through wc4 of the received command word. the remaini ng time while incmd is low and a5 through a9 are not all zeros or ones (i.e. mode), a0 through a4 are equal to the last current word count pl us one. when incmd is high and a5 through a9 are not mode, a0 through a4 represent the current word counter. if a5 through a9 are equal to mode, a0 through a4 are equal to wc0 through wc4 of th e received command word, independent of the state of incmd. 2. pulse width is typically 166 ns. 3. do not connect. 4. pulse width is typically 500 ns. 5. pin 67 for plug-in pkg, and pin 66 for flat pkg - buf ena : this pin is typically tied to dtack , causing the device to drive the shared data bus only while dtack is active. if desired buf ena can be gounded. the data will remain latched on the data bus pins for 19 s from dtsrb and 4 s for the last word of a message as the devices status word or bit word is transferred to the bc (staten or biten low). once the status or bit word transfer is complete, the data bus will automatically again contain the last data word. the device will automatically switch the direction of the internal buffers duri ng a transmit operation. 6. do not connect. 7. for flat pkg, pins 1, 41, 42, and 82 are no connections. terminal connections and pin functions (con?t) plug-in pkg flat pkg function description
8 scdct2512pcb rev a figure 2 ? typical bus coupling 1.4 :1 55 55 2 : 1 data tx/rx r r 1 : 1.41 transformer coupled stubs direct coupled stubs b a a data tx/rx data tx/rx data tx/rx zo zo stub isolation stub 2512pcb 2512pcb r = 0.75zo
9 scdct2512pcb rev a figure 3 ? timing diagram, transmit one word nbgt incmd dtreq dtgrt dtack staten a5 (d/c ) dtstb a11 (t/r ) r/w a6 - a10 a0 - a4 db0 - db4 buffena tristate command word illcmd strobed in 3 s (status bits strobed in) (srq,busy,ssflag,rdbc,rtflag) tristate tristate word count status word data word from subsystem address = 00h address = 01h sub address previous state 4.5 s 1 s 160n s 250n s max 2.5 s max 4.5 0.5 s 11 s .75 s 16 s max 250n s max data word from subsystem strobed in don?t care 5 s 0.5s status sync 15 14 13 0 p data sync 15 14 13 0 p command sync 15 14 13 1 0 p
10 scdct2512pcb rev a 9.5 s 0.75 s nbgt incmd dtreq dtgrt dtack staten a5 (d/c ) dtstb a11 (t/r ) r/w a6 - a10 a0 - a4 db0 - db15 buffena tristate command word illcmd strobed in 3 s (status bits strobed in) (srq,busy,ssflag,rdbc,rtflag) tristate tristate word count status word receive data word address = 00h address = 01h sub address previous state 1 s 160n s 250n s max 2.5 s max 4.5 0.5 s 16 s max 250n s max 5 s 0.5s gbr status word 4.5 s for handshakes < 3.5 s don?t care status sync 8 7 6 5 0 p 4.5 0.5 s 250n s for handshakes > 3.5 s figure 4 ? timing diagram, receive one word command sync 1 0 p data sync 15 14 13 12 11 0 p
11 scdct2512pcb rev a nbgt incmd dtreq dtgrt dtack staten a5 (d/c ) dtstb gbr r/w a6 - a10 a11 (t/r ) db0 - db15 buffena tristate command word word count address = 00h sub address previous state 160n s 2.25 s max 4.5 0.5 s 250n s max don?t care tx status sync 15 14 13 tristate tristate tristate tx command word 4.0 0.5 s 250n s max 1s a0 - a4 transmitting rt response time figure 5a ? timing diagram, rt to rt receive one word (part a) rx command sync 15 14 13 1 0 p tx command sync 15 14 13 12 11 10 0 p
12 scdct2512pcb rev a 0 p data sync 15 14 13 1 0 p status sync 8765 10p nbgt incmd dtreq dtgrt dtack staten a5 (d/c ) dtstb gbr r/w a6 - a10 a11 (t/r) db0 - db15 buffena 500n s typ 4.5 0.5 s 250n s max don?t care tristate 250n s for handshakes > 3.5s a0 - a4 tristate tx rt status response receive data word status word address = 01h 4.5 0.5 s 4.5 s for handshakes < 3.5s 5 0.5 s 16 s max 9.5 s 0.75s figure 5b ? timing diagram, rt to rt receive one word (part b)
13 scdct2512pcb rev a figure 6 ? timing diagram, command word transfer 166ns 0ns min 2.25s max 250ns max 500ns 166ns 666ns 1s 166ns 166ns when t/r = 0 valid sub address address = 00h or mode word count tristate tristate tristate 75ns max 75ns max 75ns max 75ns max command word note: 1. r/w = logic 0 buffena db0 - db15 a0 - a4 a6 - a10 a5 (d/c ) a11 (t/r ) incmd dtstb dtack dtgrt dtreq nbgt
14 scdct2512pcb rev a figure 7 ? timing diagram, status word transfer tristate tristate staten gbr dtstb db0 - db15 buffena receive only 500ns 166ns 166ns 75ns 75ns note: 1. r/w = 0 tristate tristate biten dtstb db0 - db15 buffena 500 ns 166ns 166ns 75ns 75ns note: 1. r/w = 0 status bit word figure 8 ? timing diagram, bit word transfer
15 scdct2512pcb rev a 500ns typ 0ns min don?t care 250ns max 166ns typ 166ns typ 75ns max 75ns max 50ns max received data word address or mode *address +1 valid tristate buffena db0 - db15 a0 - a4 dtstb dtack dtgrt dtreq figure 9 ? timing diagram, data to subsystem 500ns typ 0ns min don?t care 250ns max 166ns typ 166ns typ address or mo de *address +1 db0 - db15 a0 - a4 dtstb dtack dtgrt dtreq figure 10 ? timing diagram, data from subsystem r/w 50ns min 50ns max 50ns max transmit data word valid notes: 1. r/w = logic 0 2. (*) = non-mode only 3. buffena = dtack notes: 1. (*) = non-mode only 2. word count for mode code 3. buffena = don?t care
16 scdct2512pcb rev a figure 11 ? timing diagram, data tr ansfers to subsystem (no handshake) 166ns typ 250ns min 250ns min valid don?t care don?t care received data tristate address or mode field tristate dtstb buffena db0 - db15 a0 - a4 notes: 1. r/w = logic 0 2. dtgrt = dtreq = logic 1 3. incmd = dat/cmd are logic 1
17 scdct2512pcb rev a 21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40 1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20 a10 a9 a8 a7 a6 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 +5v bro ena gnd addre addrd addrc addrb addra addrp rtaderr txdata b txdata b -15v b +15v b +5v b gnd b rxdata b rxdata b a3 a2 a1 a0 dtgrt dtack incmd a4 hsfail r/w distr gbr a5(dat/cmd ) 12mhz in rtfail buf ena dtreq reset adbc rtflag tp2 tp1 a11(t/r ) busy illcmd ssflag srq me biten rxdata a rxdata a gnd a +5va +15va -15va txdata a txdata a staten nbgt ct2512-pcb pin out description (pcb ddip) pin # function pin # function 1a1040nbgt 2a841 a9 3a642 a7 4db143 db0 5db344 db2 6db545 db4 7db746 db6 8db947 db8 9 db11 48 db10 10 db13 49 db12 11 db15 50 db14 12 bro ena 51 +5v 13 addre 52 gnd 14 addrc 53 addrd 15 addra 54 addrb 16 rtaderr 55 addrp 17 txdata b 56 txdata b 18 +15v b 57 -15v b 19 gnd b 58 +5v b 20 rxdata b 59 rxdata b 21 a3 60 a2 22 a1 61 a0 23 dtgrt 62 dtack 24 incmd 63 a4 25 hsfail 64 r/w 26 dtstr 65 gbr 27 a5 (dat/cmd )66 12mhz in 28 rtfail 67 buf ena 29 dtreq 68 reset 30 adbc 69 rtflag 31 tp2 (nc) 70 tp1 (nc) 32 a11 (t/r )71 busy 33 illcmd 72 ssflag 34 srq 73 me 35 biten 74 rxdata a 36 rxdata a 75 gnd a 37 +5v a 76 +15v a 38 -15v a 77 txdata a 39 txdata a 78 staten ct2512-pcb mil-std-1553b remote terminal protocol unit figure 12 ? pcb ddip pin connection diagram and pinout table
18 scdct2512pcb rev a 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 a10 a9 a8 a7 a6 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 +5v br0 ena gnd addre addrd addrc addrb addra addrp rtaderr txdata b txdata b -15v b +15v b +5v b gnd b rxdata b rxdata b a3 a2 a1 a0 dtgrt dtack incmd a4 hsfail r/w distr gbr a5(dat/cmd ) 12mhz in rtfail buf ena dtreq reset adbc rtflag tp2 tp1 a11(t/r ) busy illcmd ssflag srq me biten rxdata a rxdata a gnd a +5va +15va -15va txdata a txdata a staten nbgt CT2512-FP-PCB pin out description (pcb flat pack) pin # function pin # function 1nc42 nc 2 a10 43 nbgt 3a944staten 4 a8 45 txdata a 5a746txdata a 6 a6 47 -15v a 7 db0 48 +15v a 8 db1 49 +5v a 9db250gnd a 10 db3 51 rxdata a 11 db4 52 rxdata a 12 db5 53 biten 13 db6 54 me 14 db7 55 srq 15 db8 56 ssflag 16 db9 57 illcmd 17 db10 58 busy 18 db11 59 a11 (t/r ) 19 db12 60 tp1 20 db13 61 tp2 21 db14 62 rtflag 22 db15 63 adbc 23 +5v 64 reset 24 bro ena 65 dtreq 25 gnd 66 bu f ena 26 addre 67 rtfail 27 addrd 68 12mhz in 28 addrc 69 a5 (dat/cmd ) 29 addrb 70 gbr 30 addra 71 dtstr 31 addrp 72 r/w 32 rtaderr 73 hsfail 33 txdata b 74 a4 34 txdata b 75 incmd 35 -15v b 76 dtack 36 +15v b 77 dtgrt 37 +5v b 78 a0 38 gnd b 79 a1 39 rxdata b80 a2 40 rxdata b 81 a3 41 nc 82 nc CT2512-FP-PCB mil-std-1553b remote terminal protocol unit figure 13 ? pcb flat package pin connection diagram and pinout table 1 2 n/c n/c n/c n/c 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 82 81
19 scdct2512pcb rev a .100 2.110 1.500 typ lead 1 & esd designator 1.900 1.800 pin 19 pin 20 pin 59 pin 41 pin 2 .050 typ 1.650 1.880 .100 .110 pin 1 .250 .250 max pin 39 pin 40 pin 78 pin 22 pin 21 pin 60 .018 dia typ .105 .250 max .010 .002 .018 2.000 .095 pin 41 2.200 max lead 1 & esd designator 1.610 max designator max .400 min .050 lead centers 41 leads/side (4 places) pin 82 flat package outline plug in package outline .050 see plug-in pcb outline page 17 max max
20 scdct2512pcb rev a plug-in pcb typical outline 1.870 2.100 1.650 1.500 1.900 1.800 xcvr xcvr protocol fpga pin 20 pin 59 pin 78 pin 40 pin 21 pin 60 pin 41 pin 1
21 scdct2512pcb rev a flat pcb typical outline 1.610 2.000 pin 82 pin 1 2.200 .050 lead centers 41 leads/side pin 42 pin 41
22 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. scdct2512pcb rev a ordering information model number power supply package ct2512-pcb +5v, 15v plug-in pcb CT2512-FP-PCB flat pcb * ct2513-pcb +5v, 12v plug-in pcb * ct2513-fp-pcb flat pcb * ct2510-pcb +5v, -15v plug-in pcb * ct2510-fp-pcb flat pcb * ct2511-pcb +5v, -12v plug-in pcb * ct2511-fp-pcb flat pcb * contact factory

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