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the connection of a 0.1 f bypass capacitor between pins 5 and 8 is recommended. hcpl-5300, hcpl-5301, hcpl-530k, 5962-96852 caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 8 7 6 1 3 shield 5 2 4 20 k ? schematic diagram truth table led v o on l off h intelligent power module and gate drive interface hermetically sealed optocouplers data sheet features performance specified over full military temperature range: -55 c to +125 c fast maximum propagation delays t phl = 450 ns, t plh = 650 ns minimized pulse width distortion (pwd = 450 ns) high common mode rejection (cmr): 10 kv/ s at v cm = 1000 v ctr > 30% at i f = 10 ma 1500 vdc withstand test voltage manufactured and tested on a mil-prf-38534 certified line hermetically sealed packages dual marked with device part number and dscc drawing number qml-38534, class h and k hcpl-4506 function compatibility applications military and space high reliability systems harsh industrial environments transportation, medical, and life critical systems ipm isolation isolated igbt/mosfet gate drive ac and brushless dc motor drives industrial inverters description the hcpl-530x devices consist of a gaasp led optically coupled to an integrated high gain photo detector in a hermetically sealed package. the products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full mil-prf-38534 class level h or k testing or from the dscc drawing 5962-96852. all devices are manufactured and tested on a mil-prf-38534 certified line and are included in the dscc qualified manufacturers list qml-38534 for hybrid microcircuits. minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. an on chip 20 k ? output pull-up resistor can be enabled by shorting output pins 6 and 7, thus eliminating the need for an external pull-up resistor in common ipm applica- tions. specifications and performance plots are given for typical ipm applications.
2 selection guide-lead configuration options avago part # and options commercial hcpl-5300 mil-prf-38534, class h hcpl-5301 mil-prf-38534, class k hcpl-530k standard lead finish gold plate solder dipped* option #200 butt cut/gold plate option #100 gull wing/soldered* option #300 class h smd part # prescript for all below 5962- either gold or solder 9685201hpx gold plate 9685201hpc solder dipped* 9685201hpa butt cut/gold plate 9685201hyc butt cut/soldered* 9685201hya gull wing/soldered* 9685201hxa class k smd part # prescript for all below 5962- either gold or solder 9685201kpx gold plate 9685201kpc solder dipped* 9685201kpa butt cut/gold plate 9685201kyc butt cut/soldered* 9685201kya gull wing/soldered* 9685201kxa *solder contains lead. outline drawing 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches).
3 device marking hermetic optocoupler options option description 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). 200 lead finish is solder dipped rather than gold plated. this option is available on commercial and hi-rel product in 8 pin dip. dscc drawing part numbers contain provisions for lead finish. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is available on commercial and hi-rel product in 8 pin dip (see drawings below for details). this option has solder dipped leads. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5? max. 4.57 (0.180) max. 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxxxxx xxx xxx 50434 country of mfr. avago cage code* avago designator dscc smd* pin one/ esd ident avago p/n dscc smd* * qualified parts only note: solder contains lead.
4 absolute maximum ratings parameter symbol min. max. units storage temperature t s -65 +150 c operating temperature t a -55 +125 c junction temperature t j +175 c lead solder temperature 260 for 10 sec c average input current i f(avg) 25 ma peak input current (50% duty cycle, 1 ms pulse width) i f(peak) 50 ma peak transient input current ( 1 s pulse width, 300 pps) 1.0 a reverse input voltage (pin 3-2) v r 5v average output current (pin 6) i o(avg) 15 ma resistor voltage (pin 7) v 7 -0.5 v cc v output voltage (pin 6-5) v o -0.5 30 v supply voltage (pin 8-5) v cc -0.5 30 v output power dissipation p o 100 mw total power dissipation p t 145 mw esd classification (mil-std-883, method 3015) ( ), class 1 recommended operating conditions parameter symbol min. max. units power supply voltage v cc 4.5 30 volts output voltage v o 03 0v olts input current (on) i f(on) 10 20 ma input voltage (off) v f(off) -5 0.8 v
5 electrical specifications over recommended operating conditions (t a = -55 c to +125 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v) unless otherwise specified. group a parameter symbol subgroups [12] min. typ.* max. units test conditions fig. note current transfer ctr 1, 2, 3 30 90 % i f = 10 ma, v o = 0.6 v 1 ratio low level output i ol 1, 2, 3 3.0 9.0 ma i f = 10 ma, v o = 0.6 v 1, 2 current low level output v ol 1, 2, 3 0.3 0.6 v i o = 2.4 ma v oltage input threshold i th 1, 2, 3 1.5 5.0 ma v o = 0.8 v, 1 7 current i o = 0.75 ma high level i oh 1, 2, 3 5 75 av f = 0.8 v 3 output current high level supply i cch 1, 2, 3 0.6 1.5 ma v f = 0.8 v, v o = open 7 current low level supply i ccl 1, 2, 3 0.6 1.5 ma i f = 10 ma, v o = open 7 current input forward v f 1, 2, 3 1.0 1.5 1.8 v i f = 10 ma 4 v oltage temperature ? v f / ? t a -1.6 mv/ ci f = 10 ma coefficient of forward voltage input reverse bv r 1, 2, 3 5 v i r = 100 a breakdown voltage input capacitance c in 90 pf f = 1 mhz, v f = 0 v input-output i i-o 11.0 a rh 65%, t = 5 sec, 2 insulation leakage v i-o = 1500 vdc, current t a = 25 c resistance r i-o 10 12 ? v i-o = 500 vdc 2 (input-output) capacitance c i-o 2.4 pf f = 1 mhz 2 (input-output) internal pull-up r l 1142 028k ? t a = 25 c 4, 5, resistor 6 internal pull-up ? r l / ? t a 0.014 k ? / c resistor temperature coefficient *all typical values at 25 c, v cc = 15 v.
6 switching specifications (r l = 20 k ? external) over recommended operating conditions: (t a = -55 c to +125 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v) unless otherwise specified. group a parameter symbol subgrps. [12] min. typ.* max. units test conditions fig. note propagation t phl 9, 10, 11 30 180 450 ns c l =i f(on) = 10 ma, 5, 7, 3, 4, delay time to 100 pf v f(off) = 0.8 v, 9-12 5, 6, low output 100 ns c l =7 level 10 pf propagation t plh 9, 10, 11 250 350 650 ns c l = delay time to 100 pf high output 130 c l = level 10 pf pulse width pwd 9, 10, 11 150 450 ns c l =11 distortion 100 pf propagation t plh - 9, 10, 11 -170 140 500 ns 8 delay t phl difference between any two parts output high |cm h |9 10 17 kv/ si f = 0 ma, v cc = 15.0 v, 6, 17, 9, 13 level common v o > 3.0 v c l = 100 pf, 18, 21 mode v cm = 1000 v p-p immunity t a = 25 c transient output low |cm l |9 10 17 kv/ si f = 10 ma 10, 13 level common v o < 1.0 v mode transient immunity *all typical values at 25 c, v cc = 15 v. v cc = 15.0 v, v thlh = 2.0 v, v thhl = 1.5 v
7 switching specifications (r l = internal pull-up) over recommended operating conditions: (t a = -55 c to +125 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v) unless otherwise specified. group a parameter symbol subgrps. [12] min. typ.* max. units test conditions fig. note propagation t phl 9, 10, 11 20 185 500 ns i f(on) = 10 ma, 5, 8, 3, 4, delay time to v f(off) = 0.8 v, 5, 6, low output v cc = 15.0 v, 7 level c l = 100 pf, propagation t plh 9, 10, 11 220 415 750 ns delay time to high output level pulse width pwd 9, 10, 11 150 600 ns 11 distortion propagation t plh - 9, 10, 11 -225 150 650 ns 8 delay t phl difference between any two parts output high |cm h |10kv/ si f = 0 ma, v cc = 15.0 v, 6, 21 9 level common v o > 3.0 v c l = 100 pf, mode transient v cm = 1000 immunity t a = 25 c output low |cm l |10kv/ si f = 16 ma 10 level common v o < 1.0 v mode transient immunity power supply psr 1.0 v p-p square wave, t rise , t fall 7 rejection > 5 ns, no bypass capacitors. *all typical values at 25 c, v cc = 15 v. notes: 1. current transfer ratio in percent is defined as the ratio of output collector current (i o ) to the forward led input current (i f ) times 100. 2. device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. 3. pulse: f = 20 khz, duty cycle = 10% 4. the internal 20 k ? resistor can be used by shorting pins 6 and 7 together. 5. due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performan ce can be improved by using an external 20 k ? 1% load resistor. for more information on how propagation delay varies with load resistance, see figure 8. 6. the r l = 20 k ? , c l = 100 pf represents a typical ipm (intelligent power module) load. 7. use of a 0.1 f bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise. 8. the difference in t plh and t phl between any two parts under the same test condition. (see ipm dead time and propagation delay specifications section.) 9. common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). 10. common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 11. pulse width distortion (pwd) is defined as the difference between t plh and t phl for any given device. 12. standard parts receive 100% testing at 25 c (subgroups 1 and 9). hi-rel and smd parts receive 100% testing at 25 c, +125 c, and -55 c (subgroups 1 and 9, 2 and 10, 3 and 11 respectively). 13. parameters are tested as part of device initial characterization and after design and process changes. parameters are guaran teed to limits specified for all lots not specifically tested. v thlh = 2.0 v v thhl = 1.5 v
8 led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 14. the hcpl-530x improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and the optocoupler output pins and output ground as shown in figure 15. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off) during common mode transients. for example, the recommended application circuit (figure 13), can achieve 10 kv/ s cmr while minimizing component complexity. note that a cmos gate is recommended in figure 13 to keep the led off when the gate is in the high state. another cause of cmr failure for a shielded optocoupler is direct coupling to the optocoupler output pins through c ledo1 and c ledo2 in figure 15. many factors influence the effect and magnitude of the direct coupling including: the use of an internal or external output pull-up resistor, the position of the led current setting resistor, the connection of the unused input package pins, and the value of the capacitor at the optocoupler output (cl). techniques to keep the led in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. cmr with the led on (cmr l ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. the recommended minimum led current of 10 ma provides adequate margin over the maximum i th of 5.0 ma (see figure 1) to achieve 10 kv/ s cmr. capacitive coupling is higher when the internal load resistor is used (due to c ledo2 ) and an i f = 16ma is required to obtain 10 kv/ s cmr. the placement of the led current setting resistor affects the ability of the drive circuit to keep the led on during transients and interacts with the direct coupling to the optocoupler output. for example, the led resistor in figure 16 is connected to the anode. figure 17 shows the ac equivalent circuit for figure 16 during common mode transients. during a +dv cm/dt in figure 17, the current available at the led anode (i total ) is limited by the series resistor. the led current (i f ) is reduced from its dc value by an amount equal to the current that flows through c ledp and c ledo1 . the situation is made worse because the current through c ledo1 has the effect of trying to pull the output high (toward a cmr failure) at the same time the led current is being reduced. for this reason, the recommended led drive circuit (figure 13) places the current setting resistor in series with the led cathode. figure 18 is the ac equivalent circuit for figure 13 during common mode transients. in this case, the led current is not reduced during a +dv cm/dt transient because the current flowing through the package capacitance is supplied by the power supply. during a -dv cm/dt transient, however, the led current is reduced by the amount of current flowing through c ledn . but better cmr performance is achieved since the current flowing in c ledo1 during a negative transient acts to keep the output low. coupling to the led and output pins is also affected by the connection of pins 1 and 4. if cmr is limited by perturbations in the led on current, as it is for the recommended drive circuit (figure 13), pins 1 and 4 should be connected to the input circuit common. however, if cmr performance is limited by direct coupling to the output when the led is off, pins 1 and 4 should be left unconnected. cmr with the led off (cmr h ) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a +dv cm/dt transient in figure 18, the current flowing through c ledn is supplied by the parallel combination of the led and series resistor. as long as the voltage
9 developed across the resistor is less than v f(off) the led will remain off and no common mode failure will occur. even if the led momentarily turns on, the 100 pf capacitor from pins 6-5 will keep the output from dipping below the threshold. the recommended led drive circuit (figure 13) provides about 10 v of margin between the lowest optocoupler output voltage and a 3 v ipm threshold during a 10 kv/ s transient with v cm = 1000 v. additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in figure 18, to clamp the voltage across the led below v f(off) . since the open collector drive circuit, shown in figure 19, cannot keep the led off during a +dv cm/dt transient, it is not desirable for applications requiring ultra high cmr h performance. figure 20 is the ac equivalent circuit for figure 16 during common mode transients. essentially all the current flowing through c ledn during a +dv cm/dt transient must be supplied by the led. cmr h failures can occur at dv/dt rates where the current through the led and c ledn exceeds the input threshold. figure 21 is an alternative drive circuit which does achieve ultra high cmr performance by shunting the led in the off state. ipm dead time and propagation delay specifications these devices include a propagation delay difference specification intended to help designers minimize ?ead time?in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 22) are off. any overlap in q1 and q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. to minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the ipm igbt gate drive circuit. considering only the delay characteristics of the optocoupler (the characteristics of the ipm igbt gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn- on (t phl ) and turn-off (t plh ) propagation delay specifi- cations, preferably over the desired operating temperature range. the limiting case of zero dead time occurs when the input to q1 turns off at the same time that the input to q2 turns on. this case determines the minimum delay between led1 turn-off and led2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in figure 23. a minimum dead time of zero is achieved in figure 23 when the signal to turn on led2 is delayed by (t plh max - t phl min ) from the led1 turn off. this delay is the maximum value for the propagation delay difference specification which is specified at 500 ns for the hcpl-530x over an operating temperature range of -55 c to +125 c. delaying the led signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time occurs in the highly unlikely case where one opto- coupler with the fastest t plh and another with the slowest t phl are in the same inverter leg. the maximum dead time in this case becomes the sum of the spread in the t plh and t phl propagation delays as shown in figure 24. the maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. the maximum dead time (due to the optocouplers) for the hcpl-530x is 670 ns (= 500 ns - (-170 ns)) over an operating temperature range of -55 c to +125 c.
10 i o ?output current ?ma 0 i f ?forward led current ?ma 6 4 2 5 10 10 15 20 v o = 0.6 v 8 0 125 ? 25 ? -55 ? figure 5. propagation delay test circuit figure 1. typical transfer characteristics figure 2. normalized output current vs. temperature figure 3. high level output current vs. temperature 0.1 ? v cc = 15 v 20 k ? i f(on) =10 ma v out c l * + *total load capacitance + i f v o v thhl t phl t plh t f t r 90% 10% 90% 10% v thlh 8 7 6 1 3 shield 5 2 4 5 v 20 k ? i f ?forward current ?ma 1.10 0.001 v f ?forward voltage ?volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25? i f v f + 0.01 100 figure 4. input current vs. forward voltage normalized output current t a ?temperature ?? 0.8 0.7 0.5 i f = 10 ma v o = 0.6 v 0.9 1.0 0 0.6 0406 0 100 -60 -20 20 80 -40 120 140 i oh ?high level output current ?? t a ?temperature ?? 20 10 5 25 0 v f = 0.8 v v cc = v o = 30 v 15 0406 0 100 -60 -20 20 80 -40 120 140
11 t p ?propagation delay ?ns t a ?temperature ?? 500 300 200 600 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k ? (internal) 100 0406 0 100 -60 -20 20 80 -40 120 140 400 figure 11. propagation delay vs. supply voltage figure 10. propagation delay vs. load capacitance t p ?propagation delay ?ns 0 cl ?load capacitance ?pf 800 600 400 100 1400 200 300 400 i f = 10 ma v cc = 15 v rl = 20 k ? t a = 25? 200 1000 t plh t phl 1200 0 500 t p ?propagation delay ?ns 0 v cc ?supply voltage ?v 800 600 400 10 1400 15 20 25 i f = 10 ma cl = 100 pf rl = 20 k ? t a = 25? 200 1000 t plh t phl 530 1200 t p ?propagation delay ?ns rl ?load resistance ?k ? 600 400 200 30 50 800 010 20 40 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf t a = 25 ? figure 7. propagation delay with external 20 k ? rl vs. temperature figure 8. propagation delay with internal 20 k ? rl vs. temperature figure 9. propagation delay vs. load resistance figure 6. cmr test circuit. typical cmr waveform v cm ? t ov v o v o switch at a: i f = 0 ma switch at b: i f = 10 ma v cc v ol v cm ? t v t = t p ?propagation delay ?ns t a ?temperature ?? 500 300 200 600 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k ? (external) 100 0406 0 100 -60 -20 20 80 -40 120 140 400 0.1 ? v cc = 15 v 20 k ? a i f v out 100 pf* + *100 pf total capacitance + + b v ff v cm = 1000 v 8 7 6 1 3 shield 5 2 4 20 k ?
12 figure 12. propagation delay vs. input current t p ?propagation delay ?ns 100 i f ?forward led current ?ma 300 10 500 15 v cc = 15 v cl = 100 pf rl = 20 k ? t a = 25? 200 400 t plh t phl 5 020 figure 15. optocoupler input to output capacitance model for shielded optocouplers figure 16. led drive circuit with resistor connected to led anode (not recommended) 8 7 6 1 3 shield 5 2 4 c ledp c ledn c led01 c led02 20 k ? 0.1 ? v cc = 15 v 20 k ? cmos 310 ? +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k ? figure 13. recommended led drive circuit figure 14. optocoupler input to output capacitance model for unshielded optocouplers 0.1 ? v cc = 15 v 20 k ? cmos 310 ? +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k ? 8 7 6 1 3 shield 5 2 4 c ledp c ledn 20 k ?
13 figure 21. recommended led drive circuit for ultra high cmr +5 v 8 7 6 1 3 shield 5 2 4 20 k ? 20 k ? * the arrows indicate the direction of current flow for +dv cm /dt transients. 300 ? v out 100 pf + i total* v cm 8 7 6 1 3 shield 5 2 4 20 k ? c ledn c led01 c led02 i cledp i f c ledp i cled01 20 k ? * the arrows indicate the direction of current flow for +dv cm /dt transients. ** optional clamping diode for improved cmh performance. v r < v f (off) during +dv cm /dt. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k ? c ledp c ledn c led01 c led02 i cledn* 300 ? + v r ** figure 17. ac equivalent circuit for figure 16 during common mode transients figure 18. ac equivalent circuit for figure 13 during common mode transients figure 19. not recommended open collector led drive circuit q1 +5 v 8 7 6 1 3 shield 5 2 4 20 k ? 20 k ? * the arrows indicate the direction of current flow for +dv cm /dt transients. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k ? c ledp c ledn c led01 c led02 i cledn* q1 figure 20. ac equivalent circuit for figure 19 during common mode transients
14 0.1 ? 20 k ? cmos 310 ? +5 v v out1 i led1 v cc1 m hcpl-5300 hcpl-5300 hcpl-5300 hcpl-5300 hcpl-5300 q2 q1 -hv +hv ipm 8 7 6 1 3 shield 5 2 4 20 k ? hcpl-5300 0.1 ? 20 k ? cmos 310 ? +5 v v out2 i led2 v cc2 8 7 6 1 3 shield 5 2 4 20 k ? hcpl-5300 figure 22. typical application circuit figure 23. minimum led skew for zero dead time v out1 v out2 i led2 t plh max. pdd* max. = (t plh- t phl ) max. = t plh max. - t phl min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference note: the propagation delays used to calculate pdd are taken at equal temperatures.
15 figure 24. waveforms for dead time calculations v out1 v out2 i led2 t plh min. maximum dead time (due to optocoupler) = (t plh max. - t plh min. ) + (t phl max. - t phl min. ) = (t plh max. - t phl min. ) - (t plh min. - t phl max. ) = pdd* max. - pdd* min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference t plh max. t phl max. pdd* max. max. dead time note: the propagation delays used to calculate the maximum dead time are taken at equal temperatures. mil-prf-38534 class h, class k, and dscc smd test program avago technologies hi-rel optocouplers are in compliance with mil-prf-38534 classes h and k. class h and class k devices are also in compliance with dscc drawing 5962-96852. testing consists of 100% screening and quality conformance inspection to mil-prf-38534.
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries . data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes 5967-5808e 5968-9402e june 19, 2007

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