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84329am-01 www.icst.com/products/hiperclocks.html rev. c april 3, 2003 1

ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer g eneral d escription the ics84329-01 is a general purpose, single out- put high frequency synthesizer and a member of the hiperclocks? family of high performance clock solutions from ics. the vco operates at a frequency range of 200mhz to 700mhz. the vco frequency is programmed in steps equal to the value of the crystal frequency divided by 16. the vco and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. the output can be configured to divide the vco frequency by 1, 2, 4, and 8. output frequency steps as small as 125khz to 1mhz can be achieved using a 16mhz crystal depending on the output dividers. hiperclocks? ,&6 ics84329-01 28-lead soic 7.5mm x 18.05mm x 2.25mm package body m package top view m0 m1 m2 m3 m4 m5 m6 m7 m8 n0 n1 v ee test v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 np_load v cc xtal2 xtal1 nc nc v cca s_load s_data s_clock v cc fout nfout v ee p in a ssignment b lock d iagram ics84329-01 28-lead plcc 11.6mm x 11.4mm x 4.1mm v package top view 25 24 23 22 21 20 19 5 6 7 8 9 10 11 26 27 28 1 2 3 4 18 17 16 15 14 13 12 s_clock s_data s_load v cca nc nc xtal1 n1 n0 m8 m7 m6 m5 m4 v ee test v cc v ee nfout fout v cc m3 m2 m1 m0 np_load vcc xtal2 f eatures ? ? ? ? ? ? ? ? ? ? ? c to 70 c ambient operating temperature ? pll test configuration interface logic
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f unctional d escription note: the functional description that follows describes operation using a 16mhz crystal. valid pll loop divider values for different crystal or input frequencies are defined in the input frequency characteristics, table 6, note 1. the ics84329-01 features a fully integrated pll and therefore requires no external components for setting the loop band- width. a series-resonant, fundamental crystal is used as the input to the on-chip oscillator. the output of the oscillator is divided by 16 prior to the phase detector. with a 16mhz crystal this provides a 1mhz reference frequency. the vco of the pll operates over a range of 200mhz to 700mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output frequency to be m times the reference frequency 16 by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cyc le. the programmable features of the ics84329-01 support two input modes to program the m divider and n output divider. the two input operational modes are parallel and serial. figure 1 shows the timing diagram for each mode. in parallel mode the np_load input is low. the data on inputs m0 through m8 and n0 through n1 is passed directly to the m divider and n output divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. the test output is mode 000 (shift register out) when operating in the parallel input mode. the relationship between the vco frequency, the crystal frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b, programmable vco frequency function table. valid m values for which the pll will achieve lock are defined as 200 t2 t1 t0 test output 0 0 0 shift register out 0 0 1 high 0 1 0 pll reference xtal 16 0 1 1 vco m (non 50% duty m divider) 100 fout lvcmos output frequency < 200mhz 1 0 1 low 1 1 0 s_clock m (non 50% duty cycle m divider) 1 1 1 fout 4 fout fout fout fout fout fout fout s_clock n divider fout time s erial l oading p arallel l oading m, n t s t h t s t h t s f igure 1. p arallel & s erial l oad o perations s_clock s_data s_load np_load m0:m8, n0:n1 np_load t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? ? e m a ne p y tn o i t p i r c s e d , 3 m , 2 m , 1 m , 0 m 8 m , 7 m , 6 m , 5 m , 4 m t u p n ip u l l u p . t u p n i d a o l _ p n f o n o i t s i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 n , 0 nt u p n ip u l l u p . e l b a t n o i t c n u f c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o n s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l v e e r e w o p. s n i p y l p p u s e v i t a g e n t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i d e s u s i h c i h w t u p t u o t s e t . s l e v e l e c a f r e t n i l t t v l / s o m c v l v c c r e w o p. s n i p y l p p u s e r o c t u o f , t u o f nt u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s e h t s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o a t a d _ st u p n in w o d l l u p . k c o l c _ s f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l d a o l _ st u p n in w o d l l u p . r e d i v i d m e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l v a c c r e w o p. n i p y l p p u s g o l a n a c nd e s u n u. t c e n n o c o n 2 l a t x , 1 l a t xt u p n i . t u p t u o e h t s i 2 l a t x . t u p n i e h t s i 1 l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c d a o l _ p nt u p n ip u l l u p o t n i d e d a o l s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p . e u l a v r e d i v i d t u p t u o n e h t s t e s 0 n : 1 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m e h t . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 3a. p arallel and s erial m ode f unction t able s t u p n i s n o i t i d n o c d a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s xxxx x x . h g i h t e s l l a e r a s t i b n d n a m . t e s e r la t a da t a dx x x d n a r e d i v i d m o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . 0 0 0 e d o m t s e t . r e d i v i d t u p t u o n t able 3b. p rogrammable vco f requency f unction t able y c n e u q e r f o c v ) z h m ( r e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 0 20 0 2 0 1100 1000 1 0 21 0 2011001001 2 0 22 0 2 0 1 10 0 10 10 3 0 23 0 2 0 1100 10 11 9 0 59 0 5 11111110 1 0 1 50 1 5 111111110 1 1 51 1 5 111111111 . z h m 6 1 f o y c n e u q e r f l a t s y r c a o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n t able 3c. p rogrammable o utput d ivider f unction t able s t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 1 n0 nm u m i n i mm u m i x a m 00 1 0 0 20 0 7 01 2 0 0 10 5 3 10 4 0 55 7 1 11 8 5 25 . 7 8
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 4c. lvpecl dc c haracteristics , v cc = v cca = 3.3v5%, t a = 0 c to 70 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu ov cc 4.1 -v cc 0.1 -v v lo 1eton;egatlovwoltuptu ov cc 0.2 -v cc 7.1 -v v gniws gniwsegatlovtuptuokaep-ot-kaep 6. 05 9. 0v 05htiwdetanimretstuptuo:1eton ? t able 4a. p ower s upp l y dc c haracteristic s , v cc = v cca = 3.3v5%, t a = 0 c to 70 c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = 3.3v5%, t a = 0 c to 70 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupni ,daol_pn,daol_s ,kcolc_s,atad_s 1n:0n,8m:0m 2v cc 3.0 +v v li egatlovwoltupni ,daol_pn,daol_s ,kcolc_s,atad_s 1n:0n,8m:0m 3.0 -8 . 0v i hi tnerruchgihtupni ,1n,0n,8m-0m daol_pn v cc v= ni v564.3 =5a ,daol_s kcolc_s,atad_s v cc v= ni v564.3 =0 5 1a i li tnerrucwoltupni ,1n,0n,8m-0m daol_pn v cc v,v564.3= ni v0 =0 51 -a ,daol_s kcolc_s,atad_s v cc v,v564.3= ni v0 =5 -a v ho 1eton;egatlovhgihtuptuo 6. 2v v lo 1eton;egatlovwoltuptuo 5. 0v 05htiwdetanimretstuptuo:1eton ? lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppuseroc 531. 33 . 35 64. 3v v acc egatlovylppusgolana 531. 33 . 35 64. 3v i ee tnerrucylppusrewop 01 1a m i acc tnerrucylppusgolana 5 1a m a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, v o -0.5v to v cc + 0.5v package thermal impedance,
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 6. i nput f requency c haracteristics , v cc = v cca = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; l a t x0 17 1z h m 2 , 1 e t o n ; l a t x7 15 2z h m k c o l c _ s 0 5z h m y c n e u q e r f o c v m u m i x a m r o m u m i n i m e h t e v e i h c a o t t e s e b t s u m e u l a v m e h t e g n a r y c n e u q e r f l a t s y r c e h t r o f : 1 e t o n 0 2 3 e r a m f o s e u l a v d i l a v z h m 0 1 f o y c n e u q e r f m u m i n i m e h t g n i s u . z h m 0 0 7 r o z h m 0 0 2 f o e g n a r t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 0 15 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 7 ? t able 7. ac c haracteristics , v cc = v cca = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 7z h m t ) r e p ( t i j2 , 1 e t o n ; s m r , r e t t i j d o i r e p t u o f <
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p arameter m easurement i nformation p eriod j itter c ycle - to -c ycle j itter 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v cc , v cca = 2v ? ? ? ? odc & t p eriod t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 s etup and h old v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 o utput r ise /f all t ime t hold t hold t set-up t set-up t set-up s_data s_clock s_load m0:m8 n0:n1 np_load
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer a pplication i nformation the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 3b. lvpecl o utput t ermination 3.3v f out f in 5 2 z o z o 5 2 z o 3 2 z o 3 2 z o = 50 ? ? f igure 3a. lvpecl o utput t ermination rtt = 1 (v oh + v ol / v cc ? 2) ? 2 z o 50 ? ? ? ? t ermination for lvpecl o utputs as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics84329-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 ? f igure 2. p ower s upply f iltering 10 ? p ower s upply f iltering t echniques z o = 50 ? ?
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer 60 50 40 30 20 10 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 output frequency (mhz) time (ps) f igure 4b. c ycle - to -c ycle j itter vs . fout ( using a 16mh z xtal) f igure 4a. rms j itter vs . fout ( using a 16mh z xtal) 14 12 10 8 6 4 2 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 output frequency (mhz) time (ps)
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f igure 5a. c rystal i nterface note: for crystal frequencies higher than 17mhz, a series tuning capacitor is required for proper operation. the ics84329-01 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. the oscillator is a series resonant, multi-vibrator type design. this design provides better stability and eliminates the need for large on chip capacitors. though a series resonant crystal is preferred, a parallel resonant crystal can be used. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. a few hundred ppm translates to khz inaccuracy. in general computing applications, this level of inaccuracy is irrelevant. if better ppm accuracy is required, an external capacitor can be added to a quartz crystal in series to xtal1. figure 5a shows how to interface with a crystal. figures 5a and 5b show various crystal parameters which are recommended only as guidelines. figure 5a shows how to inter- face a capacitor with a parallel resonant crystal. figure 5b shows the capacitor value needed for the optimum ppm performance over various series resonant crystal frequencies. for ia64/32 platforms which required a raltron parallel resonant quartz crystal part #as-16.66-18-smd-t-m1, a 7pf series capacitor can be used to better the ppm accuracy. xtal2 xtal1 ics84329-01 f igure 5b. recommended tuning capacitance for various series resonant crystals. c rystal i nput and o scillator i nterface 10.000 14.318 12.000 24.000 20.000 16.000 0 5 10 15 20 25 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 series resonant crystal frequency (mhz) series capacitor (pf)
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f igure 6a. s chematic of r ecommended l ayout vcc=3.3v n1 npload c16 10u m7 n1 rd0 1k r1 50 sp = space (i.e. not intstalled) r7 10 fout = 200 mhz m7 m1 rd8 sp c3 0.1u m4 m8 n[1:0] =01 (divide by 2) vcc vcca m6 ru10 1k x1 16mhz vcc m1 m[8:0]= 110010000 (400) rd10 sp m8 c2 0.1u ru0 sp m5 m0 zo = 50 ohm ru8 1k n2 rd6 1k n0 u1 84329_01_plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 27 26 25 24 23 22 21 28 vcca nc nc xtal1 xtal2 vcc np_load m0 m1 m2 m3 m4 m5 m6 m7 m8 n0 n1 vee test s_data s_clock vcc fout nfout vee vcc s_load rd7 sp c1 0.1uf vcc rd9 1k ru1 sp m2 ru9 sp m0 m3 npload r2 50 ru7 1k r3 50 zo = 50 ohm ru11 sp rd1 1k vcc c11 0.01u the schematic of the ics84329-01 layout example used in this layout guideline is shown in figure 6a. the ics84329-01 recommended pcb board layout for this example is shown in figure 6b. this layout example is used as a general guideline. l ayout g uideline the layout in the actual system will depend on the selected com- ponent types, the density of the components, the density of the traces, and the stack up of the p.c. board.
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f igure 6b. pcb b oard l ayout for ics84329-01 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c1, c2 and c3, as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v cca pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. the differential 50 ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. make sure no other signal traces are routed between the clock trace pair. the matching termination resistors should be located as close to the receiver input pins as possible. c rystal the crystal x1 should be located as close as possible to the pins 24 (xtal1) and 25 (xtal2). the trace length between the x1 and u1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. other signal traces should not be routed near the crystal traces. r7 pin 2 signals traces u1 via c2 c11 50 ohm traces vcca x1 vcca vcc c1 pin 1 c3 gnd c16
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics84329-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics84329-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? 381.2mw ? 30.2mw/loaded output pair if all outputs are loaded, the total power is 1 * 30.2mw = 30.2mw total power _max (3.465v, with all outputs switching) = 381.2mw + 30.2mw = 411.4mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125 c. the equation for tj is as follows: tj = c/w per table 8a below. therefore, tj for an ambient temperature of 70 c with all outputs switching is: 70 c + 0.411w * 39.7 c/w = 86.3 c. this is well below the limit of 125 c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 8a. t hermal r esistance ja for 28- pin soic, f orced c onvection t able 8b. t hermal r esistance ja for 28- pin plcc, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 76.2 c/w 60.8 c/w 53.2 c/w multi-layer pcb, jedec standard test boards 46.2 c/w 39.7 c/w 36.8 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 37.8 c/w 31.1 c/w 28.3 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in the figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? for logic high, v out = v oh_max = v cc_max ? 1.0v (v cc_max - v oh_max ) = 1.0v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 1v)/50 ? ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ? 30.2mw f igure 7. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer r eliability i nformation t ransistor c ount the transistor count for ics84329-01 is: 4408 t able 9a. ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 76.2 c/w 60.8 c/w 53.2 c/w multi-layer pcb, jedec standard test boards 46.2 c/w 39.7 c/w 36.8 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. 0 200 500 multi-layer pcb, jedec standard test boards 37.8 c/w 31.1 c/w 28.3 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity (linear feet per minute) t able 9b.
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ackage o utline - m s uffix t able 10a. p ackage d imensions reference document: jedec publication 95, ms-013, mo-119 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 2 a- -5 6 . 2 1 a0 1 . 0- - 2 a5 0 . 25 5 . 2 b3 3 . 01 5 . 0 c8 1 . 02 3 . 0 d0 7 . 7 10 4 . 8 1 e0 4 . 70 6 . 7 ec i s a b 7 2 . 1 h0 0 . 0 15 6 . 0 1 h5 2 . 05 7 . 0 l0 4 . 07 2 . 1 0 8
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ackage o utline - v s uffix n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 8 2 a 9 1 . 47 5 . 4 1 a 9 2 . 25 0 . 3 2 a 7 5 . 11 1 . 2 b 3 3 . 03 5 . 0 c 9 1 . 02 3 . 0 d 2 3 . 2 17 5 . 2 1 1 d 3 4 . 1 18 5 . 1 1 2 d 5 8 . 46 5 . 5 e 2 3 . 2 17 5 . 2 1 1 e 3 4 . 1 18 5 . 1 1 2 e 5 8 . 46 5 . 5 t able 10b. p ackage d imensions reference document: jedec publication 95, ms-018
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 11. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 0 - m a 9 2 3 4 8 s c i1 0 - m a 9 2 3 4 8 s c ic i o s d a e l 8 2e b u t r e p 6 2c 0 7 o t c 0 t 1 0 - m a 9 2 3 4 8 s c i1 0 - m a 9 2 3 4 8 s c il e e r d n a e p a t n o c i o s d a e l 8 20 0 0 1c 0 7 o t c 0 1 0 - v a 9 2 3 4 8 s c i1 0 - v a 9 2 3 4 8 s c ic c l p d a e l 8 2e b u t r e p 8 3c 0 7 o t c 0 t 1 0 - v a 9 2 3 4 8 s c i1 0 - v a 9 2 3 4 8 s c il e e r d n a e p a t n o c c l p d a e l 8 20 0 5c 0 7 o t c 0 while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments.
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ics84329-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b6 t6 2 1 - e l b a t s c i t s i r e t c a r a h c y c n e u q e r f t u p n i . x a m z h m 0 2 o t . x a m z h m 5 2 m o r f l a t x d e t a d p u 2 d n a 1 s e t o n e d u l c n i o t w o r l a t x r e h t o n a d e d d a . n o i t c e s e c a f r e t n i r o t a l l i c s o d n a t u p n i l a t s y r c d e d d a 2 0 / 4 1 / 2 0 b1 t 2 3 . m a r g a i d s n o i t a r e p o d a o l l a i r e s & l e l l a r a p d e t a d p u v d e g n a h c c c . s n o i t p i r c s e d l a t s y r c d n a . t a m r o f d e t a d p u 2 0 / 8 1 / 2 1 c 6 t 1 6 0 1 . s r e d i v i d h t i w n d e c a l p e r , m a r g a i d k c o l b o t t i m i l . n i m z h m 0 2 d e g n a h c d n a . x a m z h m 7 1 o t t i m i l . x a m z h m 0 2 d e g n a h c . 2 e t o n d e s i v e r . n i m z h m 7 1 y c n e u q e r f l a t s y r c e m a s d e d d a , n o i t c e s e c a f r e t n i r o t a l l i c s o & t u p n i l a t s y r c . e t o n 3 0 / 3 / 4

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