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rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram ddr2 unbuffered sdram module revision 0.6 october 2003 240pin unbuffered module based on 512mb b-die 64/72-bit non-ecc/ecc
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram revision history revision 0.3 (sep. 2003) - initial release revision 0.4 (sep. 2003) - removed x16 base ecc udimm product revision 0.5 (oct. 2003) - removed d4 speed bin(400 4-4-4) revision 0.6 (oct. 2003) - added operation temperature condition - changed setup/hold time va lues(tls/tds , tih/tdh) - added notes for setup/hol d time(tis/tds, tih/tdh) - added trefi values by t case (85 c/95 c)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram ddr2 unbuffered dimm ordering information note: 1. speed bin is in order of cl-trcd-trp part number density organization component composition number of rank height x64 non ecc m378t3354bg0-ce6/d5/cc 256mb 32mx 64 32mx16(k4t51163qb)*4 1 30.00mm m378t3354bg0-le6/d5/cc 256mb 32mx 64 32mx16(k4t51163qb)*4 1 30.00mm m378t6553bg0-ce6/d5/cc 512mb 64 mx64 64mx8(k4t51083qb)*8 1 30.00mm m378t6553bg0-le6/d5/cc 512mb 64 mx64 64mx8(k4t51083qb)*8 1 30.00mm m378t2953bg0-ce6/d5/cc 1gb 128mx 64 64mx8(k4t51083qb)*16 2 30.00mm m378t2953bg0-le6/d5/cc 1gb 128mx 64 64mx8(k4t51083qb)*16 2 30.00mm x72 ecc m391t6553bg0-ce6/d5/cc 512mb 64 mx72 64mx8(k4t51083qb)*9 1 30.00mm m391t6553bg0-le6/d5/cc 512mb 64mx 72 64mx8(k4t51083qb)*9 1 30.00mm m391t2953bg0-ce6/d5/cc 1gb 128mx72 64mx8(k4t51083qb)*18 2 30.00mm m391t2953bg0-le6/d5/cc 1gb 128mx72 64mx8(k4t51083qb)*18 2 30.00mm features ? performance range ? jedec standard 1.8v 0.1v power supply ? vddq = 1.8v 0.1v ? 200 mhz f ck for 400mb/sec/pin, 267mhz f ck for 533mb/sec/pin, 333mhz f ck for 667mb/sec/pin ? 4 bank ? posted cas ? programmable cas latency: 3, 4, 5 ? programmable additive lat ency: 0, 1 , 2 , 3 and 4 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? average refesh period 7.8us at lower then t case 85c, 3.9us at 85c < t case < 95 c ? serial presence detect with eeprom ? ddr2 sdram package: 60ball fbga - 64mx8, 84ball fbga - 32mx16 e6(ddr2-667) d5(ddr2-533) cc(ddr2-400) unit speed@cl3 400 400 400 mbps speed@cl4 533 533 400 mbps speed@cl5 533 - -mbps speed@cl6 667 - -mbps cl-trcd-trp 4-4-4 4-4-4 3-3-3 ck
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram x64 dimm pin configurations (front side/back side) nc = no connect, rfu = reserved for future use 1. pin196(a13) is used for x4/x8 base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard memory module products (dimms.) pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4dq1124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0126 nc 36 dqs 3 156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7dqs0127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 nc 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 nc 162 nc 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 nc 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 nc 73 we 193 s 0 104 dqs 6 224 nc 15 dqs 1 135 nc 45 nc 165 nc 74 cas 194 v ddq 105 dqs6 225 v ss 16 dqs1 136 v ss 46 nc 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 nc 76 s 1196 a13 1 107 dq50 227 dq55 18 nc 138 ck 1 48 nc 168 nc 77 odt1 197 v dd 108 dq51 228 v ss 19 nc 139 v ss 49 nc 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7 233 nc 24 dq16 144 dq21 54 nc 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 vddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss samsung electronics co., ltd. reserves the right to change products and spec ifications without notice. address configuration organization row address column ad dress bank address auto precharge 64mx8(512mb) based module a0-a13 a0-a9 ba0-ba1 a10 32mx16(512mb) based module a0-a12 a0-a9 ba0-ba1 a10
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram x72 dimm pin configurations (front side/back side) nc = no connect, rfu = reserved for future use 1. pin196(a13) is used for x4/x8 base unbuffered dimm. 2. the test pin is reserved for bus analysis tools and is not connected on standard memory module products (dimms.) pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5 2 v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5 v ss 125 dm0 35 v ss 155 dm3 key 95 dq42 215 dq47 6dqs 0 126 nc 36 dqs 3 156 nc 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8 v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 ck2 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 ck 2 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc, test 2 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6 14 v ss 134 dm1 44 v ss 164 dm8 73 we 193 s 0 104 dqs 6 224 nc 15 dqs 1 135 nc 45 dqs 8 165 nc 74 cas 194 v ddq 105 dqs6 225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 ck1 47 v ss 167 cb6 76 s 1 196 a13 107 dq50 227 dq55 18 nc 138 ck 1 48 cb2 168 cb7 77 odt1 197 v dd 108 dq51 228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4 113 dqs 7 233 nc 24 dq16 144 dq21 54 nc 174 nc 83 dqs 4 203 nc 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 vddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description *the vdd and vddq pins are tied to the single power-plane on pcb. pin name description pin name description a0-a13 ddr2 sdram address bus ck0, ck1, ck2 ddr2 sdram clocks (positive line of differential pair) ba0, ba1 ddr2 sdram bank select ck 0, ck 1, ck 2 ddr2 sdram clocks (negative line of differential pair) ras ddr2 sdram row address strobe scl i 2 c serial bus clock for eeprom cas ddr2 sdram column address strobe sda i 2 c serial bus data line for eeprom we ddr2 sdram wirte enable sa0-sa2 i 2 c serial address select for eeprom s 0, s 1 dimm rank select lines v dd * ddr2 sdram core power supply cke0,cke1 ddr2 sdram clock enable lines v ddq * ddr2 sdram i/o driver power supply odt0, odt1 on-die termination control lines v ref ddr2 sdram i/o reference supply dq0 - dq63 dimm memory data bus v ss power supply return (ground) cb0 - cb7 dimm ecc check bits v dd spd serial eeprom positive power supply dqs0 - dqs8 ddr2 sdram data strobes nc spare pins(no connect) dm(0-8) ddr2 sdram data masks reset not used on udimm dqs 0-dqs 8 ddr2 sdram differential data strobes test used by memory bus analysis tools (unused on memory dimms)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram symbol type polarity function ck0-ck2 ck 0-ck 2 sstl_1.8 differential crossing ck and ck are differential clock inputs. all the sd ram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is reference to the crossing of ck and ck (both directions of crossing) cke0-cke1 sstl_1.8 active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates th e powe down mode, or the self-refresh mode s 0-s 1 sstl_1.8 active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disbled, new command are ignored but previous operations continue. this signal provides for external rank selection on systems with multiple ranks ras , cas , we sstl_1.8 - ras , cas , and we ( along with cs) define the command being entered. odt0-odt1 sstl_1.8 tbd when high, termination resistance is enabled for all dq, dq and dm pins, assuming the function is enabled in the extended mode register set (emrs). v ref supply - reference voltage for sstl 18 inputs. v ddq supply - power supply for the ddr ii sdram output buffers to provide improved noise immunity. for all current ddr2 unbuffered dimm designs, vddq shares the same power plane as vdd pins. ba0-ba1 sstl_1.8 - selects which sdram bank of four is activated. a0-a13 sstl_1.8 - during a bank activate command cycle, address input defines the row address (ra0- ra13) during a read or write command cycle, address input defines the colum address, in addi- tion to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, auto precharge is disbled. during a precharge com- mand cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1. if ap is low, ba0, ba1are used to define which bank to precharge. dq0-dq63 cb0-cb7 sstl_1.8 - data and check bit input/output pins. dm0-dm8 sstl_1.8 active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply - power and ground for ddr2 sdram input buffer s, and core logic. vdd and vddq pins are tied to v dd /v ddq planes on these modules. dqs0-dqs8 dqs 0-dqs 8 sstl_1.8 differential crossing data strobe for input and output data. for rawcards using x16 orginized drams dq0-7 connect to the ldqs pin of the drams and dq 8-17 connect to the udqs pin of the dram sa0-sa2 - - these signals and tied at the system planar to either v ss or v dd to configure the serial spd eerpom address range. sda - - this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to vdd to act as a pullup on the system board. scl - - this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to vdd to act as a pullup onthe system board. v dd spd supply - power supply for spd eeprom. this supply is separate from the v dd /v ddq power plane. eeprom supply is operable from 1.7v to 3.6v. input/output functional description
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm nu/ cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 5.1 ohms 5%. functional block diagram: 512mb, 64mx64 module (populated as 1 rank of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 2 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d7 cas cas : ddr2 sdrams d0 - d7 we we : ddr2 sdrams d0 - d7 cke0 cke : ddr2 sdrams d0 - d7 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d7 odt0 odt : ddr2 sdrams d0 - d7 (m378t6553bg0)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 5.1 ohms 5%. functional block diagram: 512mb, 64mx72 ecc module (populated as 1 rank of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 3 ddr2 sdrams 3 ddr2 sdrams 3 ddr2 sdrams v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd serial pd dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 a0 - a13 a0-a13 : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d8 cas cas : ddr2 sdrams d0 - d8 we we : ddr2 sdrams d0 - d8 cke0 cke : ddr2 sdrams d0 - d8 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d8 odt0 odt : ddr2 sdrams d0 - d8 (m391t6553bg0)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3 ohms 5%. functional block diagram: 1gb, 128mx64 module (populated as 2 ranks of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 4 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d15 we we : ddr2 sdrams d0 - d15 cke1 cke : ddr2 sdrams d8 - d15 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d15 odt0 odt : ddr2 sdrams d0 - d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 s 1 cke0 cke : ddr2 sdrams d0 - d7 ras ras : ddr2 sdrams d0 - d15 cas cas : ddr2 sdrams d0 - d15 odt1 odt : ddr2 sdrams d8 - d15 (m378t2953bg0)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 2. bax, ax, ras , cas , we resistors : 3 ohms 5%. functional block diagram: 1gb, 128mx72 ecc module (populated as 2 ranks of x8 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 6 ddr2 sdrams 6 ddr2 sdrams 6 ddr2 sdrams v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd serial pd a0 - a13 a0-a13 : ddr2 sdrams d0 - d17 we we : ddr2 sdrams d0 - d17 cke1 cke : ddr2 sdrams d9 - d17 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d17 odt0 odt : ddr2 sdrams d0 - d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 s 1 cke0 cke : ddr2 sdrams d0 - d8 ras ras : ddr2 sdrams d0 - d17 cas cas : ddr2 sdrams d0 - d17 odt1 odt : ddr2 sdrams d9 - d17 dqs 8 dqs8 dm8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 (m391t2953bg0)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram s 0 dqs 1 dqs1 dm1 cs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 notes : 1. dq,dm, dqs/dqs resistors : 22 ohms 5%. 4. bax, ax, ras , cas , we resistors : 10 ohms 5%. functional block diagram: 256mb, 32mx64 module (populated as 1 rank of x16 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp *wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 nc 2 ddr2 sdrams 2 ddr2 sdrams v ss d0 - d3 v dd /v ddq d0 - d3 d0 - d3 vref v ddspd serial pd a0 - a12 a0-a12 : ddr2 sdrams d0 - d3 we we : ddr2 sdrams d0 - d3 ba0 - ba1 ba0-ba1 : ddr2 sdrams d0 - d3 odt0 odt : ddr2 sdrams d0 - d3 cke0 cke : ddr2 sdrams d0 - d3 ras ras : ddr2 sdrams d0 - d3 cas cas : ddr2 sdrams d0 - d3 ldqs ldos ldm dqs 0 dqs0 dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udos udm dqs 5 dqs5 dm5 cs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 ldqs ldos ldm dqs 4 dqs4 dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udos udm dqs 3 dqs3 dm3 cs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 ldqs ldos ldm dqs 2 dqs2 dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udos udm dqs 7 dqs7 dm7 cs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 ldqs ldos ldm dqs 6 dqs6 dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udos udm (m378t3354bg0)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram absolute maximum dc ratings ac & dc operating conditions recommended dc operating conditions (sstl - 1.8) symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in , v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1 1. stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at th ese or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to abso lute maximum rating conditions for extended periods may affect r eli- ability. 2. storage temperature is the case surface te mperature on the center/top side of the dram. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v vddl supply voltage for dll 1.7 1.8 1.9 v 4 vddq supply voltage for output 1.7 1.8 1.9 v 4 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 1.2 vtt termination voltage v ref -0.04 v ref v ref +0.04 v 3 there is no specific device vdd supply voltage requirement for sstl-1.8 compliance. however under all conditions vddq must be less than or equal to vdd. 1. the value of vref may be selected by the user to provide optim um noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq tracks with vdd, vddl tracks with vdd. ac parame ters are measured with vdd, vddq and vdddl tied together.
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram operating temperature condition note : 1. operating temperature is the case surface temp erature on the center/top side of the dram. 2. the operation temperature range ar e the temperature where all dram s pecification will be supported. input dc logic level input ac logic level ac input test conditions note : 1. setup (tis & tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vih(dc)min a nd the first cross- ing of vih(ac)min. setup (tis & tds) nominal slew rate for a falling signal is defined as the sl ew rate between the last cross ing of vil(dc)max and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?dc to ac region?, use nominal slew rate for derating value (see fig a.) if the ac tual signal is later than the nominal slew rate line anywhere b etween shaded ?dc to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating valu e (see fig b.) 2. hold (tih & tdh) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of vil(dc)max an d the first crossing of vref. hold (tih & tdh) nominal slew rate for a falling sig nal is defined as the slew rate between the last crossing of vih( dc)min and the first crossing of vref. if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref region?, use nominal slew rate for derating value (see fig a.) if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref region?, the slew rate of a tangent line to the actual signal from the dc le vel to vref level is used for derating value (see fig b.)input w aveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. symbol parameter rating units notes toper operating temperature 0 to 95 c 1, 2 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter min. max. units notes v ih (ac) ac input logic high v ref + 0.250 - v v il (ac) ac input logic low -v ref - 0.250 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram v ss dqs dqs hold setup hold setup slew rate setup slew rate rising signal falling signal setup setup vil(dc)max - vil(ac)max setup delta tf vih(ac)min - vih(dc)min setup delta tr = v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max setup dc to ac region dc to ac region hold delta tf delta tf delta tr hold delta tr = hold slew rate hold slew rate falling signal rising signal vref - vil(dc)max hold delta tr = vih(dc)min - vref hold delta tf = v ss ck ck setup slew rate setup slew rate rising signal falling signal setup setup tangent line[vil(dc)max - vil(ac)max] setup delta tf = tangent line[vih(ac)min - vih(dc)min] setup delta tr = v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max dc to ac region dc to ac region hold hold hold slew rate tangent line [ vih(dc)min - vref ] hold delta tf = falling signal hold slew rate tangent line [ vref - vil(dc)max ] hold delta tr = rising signal delta tf delta tr delta tr delta tf time time time time hold time hold time setup time setup time
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram differential input ac logic level 1. v in(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id(dc ) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih(dc) - v il(dc) . notes: 1. v id(ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac) . 2. the typical value of v ix(ac) is expected to be about 0.5 * vddq of the transmitting device and v ix(ac) is expected to track variations in vddq . v ix(ac) indicates the voltage at which differential input signals must cross. differential ac output parameters notes: 1. the typical value of v ox(ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox(ac ) is expected to track variations in vddq . v ox(ac) indicates the voltage at whitch diff erential output signals must cross. symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units notes v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram output buffer levels (@ component) output ac test conditions output dc current drive ocd default characteristics note 1: absolute specifications (0c t case +tbdc; vdd = +1.8v 0.1 v, vddq = +1.8v 0.1v) note 2: impedance measurement condition for output so urce dc current: vddq = 1.7v; vout = 1420mv; (vout- vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq-280mv. impedance mea- surement condition for output sink dc current: vddq = 1. 7v; vout = 280mv; vout/iol must be less than 23.4 ohms for values of vout between 0v and 280mv. note 3: mismatch is absolute value between pull-up and pul l-dn, both are measured at same temperature and voltage. note 4: slew rate measured from vil(ac) to vih(ac). note 5: the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. note 6 : this represents the step size when the ocd is near 18 ohms at nominal conditions across all process and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd imped- ance is 18 ohms +/- 0.75 ohms under nominal conditions. symbol parameter class ii units notes v oh minimum required output pull-up under ac test load v tt + 0.603 v v ol maximum required output pull-down under ac test load v tt - 0.603 v v otr output timing measurement reference level 0.5 * v ddq v1 1. the vddq of the device under test is referenced. symbol parameter class ii units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 an d 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. description parameter min nom max unit notes output impedance 12.6 18 23.4 ohms 1,2 output impedance step size for o cd calibration 01.5ohms6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate tbd tbd v/ns 1,4,5
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram output slew rate load : 25 ohms v tt output (v out) reference point input/output capacitance (v dd =1.8v, v ddq =1.8v, t a =25 o c, f=1mhz) note: dm is internally loaded to match dq and dqs identically. parameter symbol min max min max min max units non-ecc m470t6554bg0 m470t6553bg0 m470t3354bg0 input capacitance, ck and ck cck0 - tbd - tbd - tbd pf cck1 - tbd - tbd - tbd input capacitance, cke and cs ci 1 - tbd - tbd - tbd input capacitance, addr, ras , cas , we ci 2 - tbd - tbd - tbd input/output capacitance, dq, dm, dqs, dqs cio - tbd - tbd - tbd non-ecc tbd input capacitance, ck and ck cck0 - tbd pf cck1 - tbd cck2 - tbd input capacitance, cke and cs ci 1 - tbd input capacitance, addr, ras , cas , we ci 2 - tbd input/output capacitance, dq, dm, dqs, dqs cio - tbd
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram idd specification parameters definition (idd values are for full operating ra nge of voltage and temperature) symbol proposed conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid com- mands; address bus inputs are switch ing; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid commands; address businputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputsare sta- ble; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd5b burst auto refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram m378t2953bg0 : 1gb(64mx8 *16) module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 tbd tbd tbd ma idd1 tbd tbd tbd ma idd2p tbd tbd tbd ma idd2q tbd tbd tbd ma idd2n tbd tbd tbd ma idd3p tbd tbd tbd ma idd3n tbd tbd tbd ma idd4w tbd tbd tbd ma idd4r tbd tbd tbd ma idd5b tbd tbd tbd ma idd6 normal tbd tbd tbd ma low power tbd tbd tbd ma optional idd7 tbd tbd tbd ma operating current table(1-1) (t a =0 o c, vdd= 1.9v) m378t6553bg0 : 512mb(64mx8 *8) module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 tbd tbd tbd ma idd1 tbd tbd tbd ma idd2p tbd tbd tbd ma idd2q tbd tbd tbd ma idd2n tbd tbd tbd ma idd3p tbd tbd tbd ma idd3n tbd tbd tbd ma idd4w tbd tbd tbd ma idd4r tbd tbd tbd ma idd5b tbd tbd tbd ma idd6 normal tbd tbd tbd ma low power tbd tbd tbd ma optional idd7 tbd tbd tbd ma
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram m391t6553bg0 : 512mb( 64mx8 *9) ecc module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 tbd tbd tbd ma idd1 tbd tbd tbd ma idd2p tbd tbd tbd ma idd2q tbd tbd tbd ma idd2n tbd tbd tbd ma idd3p tbd tbd tbd ma idd3n tbd tbd tbd ma idd4w tbd tbd tbd ma idd4r tbd tbd tbd ma idd5b tbd tbd tbd ma idd6 normal tbd tbd tbd ma low power tbd tbd tbd ma optional idd7 tbd tbd tbd ma operating current table(1-2) (t a =0 o c, vdd= 1.9v) m378t3354bg0 : 256mb(32mx16 *4) module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 tbd tbd tbd ma idd1 tbd tbd tbd ma idd2p tbd tbd tbd ma idd2q tbd tbd tbd ma idd2n tbd tbd tbd ma idd3p tbd tbd tbd ma idd3n tbd tbd tbd ma idd4w tbd tbd tbd ma idd4r tbd tbd tbd ma idd5b tbd tbd tbd ma idd6 normal tbd tbd tbd ma low power tbd tbd tbd ma optional idd7 tbd tbd tbd ma
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram m391t2953bg0 : 1gb(64mx8 *18) ecc module * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol e6 (ddr2-667@cl=5) d5 (ddr2-533@cl=4) cc (ddr2-400@cl=3) unit notes idd0 tbd tbd tbd ma idd1 tbd tbd tbd ma idd2p tbd tbd tbd ma idd2q tbd tbd tbd ma idd2n tbd tbd tbd ma idd3p tbd tbd tbd ma idd3n tbd tbd tbd ma idd4w tbd tbd tbd ma idd4r tbd tbd tbd ma idd5b tbd tbd tbd ma idd6 normal tbd tbd tbd ma low power tbd tbd tbd ma optional idd7 tbd tbd tbd ma operating current table(1-3) (t a =0 o c, vdd= 1.9v)
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram electrical characteristics & ac timing for ddr2-667/533/400 (0 c < t case < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) refresh parameters by device density speed bins and cl, trcd, trp, trc and tras for corresponding bin timing parameters by speed grade (refer to notes for informations re lated to this table at the bottom) parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/r efresh command time trfc 75 105 127.5 195 tbd ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s speed ddr2-667(e6) ddr2-533(d5) ddr2-400(cc) units bin (cl - trcd - trp) 5 - 5- 5 4 - 4 - 4 3 - 3 - 3 parameter min max min max min max tck, cl=3 5 8 5 8 5 8 ns tck, cl=4 3.75 8 3.75 8 5 8 ns tck, cl=5 3 8 - - - - ns trcd 15 15 15 ns trp 15 15 15 ns trc 55 55 55 ns tras 40 70000 40 70000 40 70000 ns parameter symbol ddr2-667 ddr2-533 ddr2-400 units notes min max min max min max dq output access time from ck/ck tac -450 +450 -500 +500 -600 +600 ps dqs output access time from ck/ck tdqsck -400 +400 -450 +450 -500 +500 ps ck high-level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) x min(tcl, tch) x min(tcl, tch) x ps 19,20 clock cycle time, cl=x tck 3000 8000 3750 8000 5000 8000 ps 23 dq and dm input hold time tdh tbd x 225 x275x ps 14,15, 16 dq and dm input setup time tds tbd x 100 x150 x ps 14,15, 16 control & address input pulse width for each input tipw 0.6 x 0.6 x0.6x tck
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram dq and dm input pulse width for each input tdipw 0.35 x 0.35 x0.35 x tck data-out high-impedance time from ck/ck thz x tac max x tac max x tac max ps data-out low-impedance time from ck/ck tlz tac min tac max tac min tac max tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq x tbd x300x350 ps 21 dq hold skew factor tqhs x tbd x400x450 ps 20 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x tck dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x tck mode register set command cycle time tmrd 2 x 2 x 2 x tck write preamble setup time twpres 0 x 0 x 0 x ps write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 18 write preamble twpre tbd x 0.4 x 0.4 x tck address and control input hold time tih tbd x375 x 475 x ps 13,15, 17 address and control input setup time tis tbd x250 x 350 x ps 13,15, 17 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck active to active command period for 1kb page size products trrd 7.5 x7.5 x 7.5 x ns 12 active to active command period for 2kb page size products trrd 10 x10 x 10 x ns 12 cas to cas command delay tccd 2 2 2 tck write recovery time twr 15 x15 x 15 x ns auto precharge write recovery + precharge time tdal twr+trp* x twr+trp* x twr+trp * x tck 22 internal write to read command delay twtr 7.5 x7.5 x10 x ns internal read to precharge command delay trtp 7.5 7.5 7.5 ns 11 exit self refresh to a non- read command txsnr trfc + 10 trfc + 10 trfc + 10 ns
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram exit self refresh to a read command txsrd 200 200 200 tck exit precharge power down to any non-read command txp 2 x 2 x 2 x tck exit active power down to read command txard 2 x 2 x 2 x tck 9 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al 6 - al tck 9, 10 cke minimum pulse width (high and low pulse width) t cke 3 33tck odt turn-on delay t aond 222222 tck odt turn-on t aon tac(min) tac(max) +0.7 tac(min) tac(max) +1 tac(min) tac(max) +1 ns 13, 24 odt turn-on(power-down mode) t aonpd tac(min)+ 2 2tck+tac (max)+1 tac(min)+ 2 2tck+tac (max)+1 tac(min) +2 2tck+ta c(max)+1 ns odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn-off t aof tac(min) tac(max) + 0.6 tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns 25 odt turn-off (power-down mode) t aofpd tac(min)+ 2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+ tac(max) +1 tac(min) +2 2.5tck+ tac(max) +1 ns odt to power down entry latency tanpd 3 3 3 tck odt power down exit latency taxpd 8 8 8 tck ocd drive mode output delay toit 0 12 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+ti h tis+tck+ti h tis+tck+t ih ns 23
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram physical dimensions: 64mbx8 based 64mx64/x72 module(1 rank) 131.35 units : millimeters 133.35 10.00 1.270 0.10 2.7 spd n/a (for x72) 128.95 (2) 2.50 (2x)4.00 30.00 2.30 17.80 (for x64) ecc the used device is 64m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t51083qb-gc/l##. (m378/91t6553bg0) a b 63.00 55.00 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram 2.50 physical dimensions: 64mbx8 based 128mx64/x72 module(2 ranks) 131.35 units : millimeters 133.35 10.00 1.270 0.10 4.00 128.95 (2) 2.50 (2x)4.00 2.30 17.80 n/a (for x64) (for x72) ecc the used device is 64m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t51083qb-gc/l##. spd (m378/91t2953bg0) 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 a b 63.00 55.00 30.00 n/a (for x72) (for x64) ecc
rev. 0.6 oct. 2003 256mb,512mb,1gb unbuffered dimms preliminary ddr2 sdram physical dimensions: 32mbx16 based 32mx64/x72 module(1 rank) 131.35 units : millimeters 133.35 10.00 128.95 (2) 2.50 (2x)4.00 30.00 2.30 17.80 spd 1.270 0.10 2.7 the used device is 32m x16 ddr2 sdram, fbga. ddr2 sdram part no : k4t51163qb-gc/l##. (m378t3354bg0) 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 a b 63.00 55.00

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