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ds04132013ae data sheet 1 copyright ? 1995 by fujitsu limited quick pro tm is a trademark of fujitsu limited linear ic cmos 8 bit 4-channel d/a converter mb86022 cmos 8-bit 4-channel d/a converter the fujitsu mb86022 is a 8-bit 4-channel digital to analog converter which is fabricated with fujitsu cmos technology. the data latch and output buffer circuitry are provided on each channel which can operate independently selected by 2bit data. ? resolution : 8-bits (4-channels) ? conversion rate : 200k sps ? digital input voltage : ttl level ? power supply voltage : +5v ? low power dissipation : 14mw typ. at +5v ? each channel operates independently ? on-chip data initialization & power down function ? reference voltage mode selection: on-chip or external generation ? easy to take interface with micro processor (parallel data input) plastic package dip-24p-m03 this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. plastic package fpt-24p-m02 pin assignment (top view) d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 wr ce reset pd v dd vr2 vr1 ao0 ao1 ao2 ao3 n.c. ag dg 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ ___ ___ ___
mb86022 2 absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rating symbol pin name unit digital input voltage v v dd v di max typ min power supply voltage analog input voltage v 1 , v 2 analog output voltage v ao analog output current 10 i ao storage temperature 125 tstg c v v v ma v dd +0.3 v dd +0.3 v dd +0.3 7 10 40 gnd0.3 gnd0.3 gnd0.3 gnd0.3 v dd all digital input pins vr1,vr2 ao0,ao1,ao2,ao3 ao0,ao1,ao2,ao3 parameter
mb86022 3 block diagram ao3 ao2 ao1 ao0 d0 to d7 ___ c0,c1 vr2 vr1 ___ ______ ___ 2 8 buffer amp. buffer amp. buffer amp. buffer amp. + + + + 8-bit pd reset ce wr dac 8-bit dac 8-bit dac 8-bit dac 8-bit data channel v ref circuit latch 8-bit data latch 8-bit data latch 8-bit data latch select & control logic dg ag v dd
mb86022 4 pin description middle point of reference voltage input pin. reference voltage (h level) input pin. v dd is given by internal reference voltage cir- cuitry to this pin when internal reference voltage mode. in this case, the capacitor be- tween this pin and ag pin is required to limit noise generation. in case of external refer- ence voltage mode, the reference voltage should be given from this pin. system pin number symbol descriptions 22 v dd power supply voltage 5v 13 dg 14 ag 9 10 1 2 c0 c1 d0 d1 3 4 5 6 d2 d3 d4 d5 7 8 d6 d7 gnd for digital system gnd for analog system channel selection signal pin. channels are selected by following table. ttl interface. data input signal pin. the digital data is read by the channel which is selected by c0 and c1 pins when the rising edge of wr (l h), and analog output is shown correspond to that digital code. d0 is lsb and d7 is msb. code is set at 10000000 when reset. ttl interface. 23 ___ pd power down control signal pin. the circuit is set power down when this pin goes to alo. this pin is pulled up by high resistance. ttl interface. 24 ______ reset reset input signal pin. the data at all channels is initialized when this pin goes to alo. at this time, the d/a output is set at d(a)=128. this pin is pulled up by high resistance. ttl interface. 12 ___ ce chip enable signal pin. the data can be written when this pin goes to alo. this pin is pulled up by high resistance. ttl interface. 11 ___ wr data write pin. the data from d0 to d7 is written when the rising edge (l h) of this pin. ttl interface. c1 c0 channel ll 0 lh 1 hl 2 hh 3 power supply digital input 21 vr 2 20 vr 1 reference voltage (h level) input pin. v dd is given by internal reference voltage circuit- ry to this pin when internal reference voltage mode. in this case, the capacitor between this pin and ag pin is required to limit noise generation. in case of external reference voltage mode, the reference voltage should be given from this pin. 1 ___ 2 analog input
mb86022 5 system pin number symbol descriptions 16 ao3 analog output pin of channel 3. this pin is set to highimpedance state at power down. 17 analog output ao2 analog output pin of channel 2. this pin is set to highimpedance state at power down. 18 ao1 analog output pin of channel 1. this pin is set to highimpedance state at power down. 19 ao0 analog output pin of channel 0. this pin is set to highimpedance state at power down. 15 n.c. no connection pin (continued)
mb86022 6 recommended operating conditions unit value parameter symbol pin name min typ max v 4.75 5.0 5.25 power supply voltage v 0 digital input voltage v dd all digital input pins analog input voltage v 1.2 3.75 3.8 v 2.5 vr1 vr2 20 analog output load pf 50 analog output load 20 70 operating temperature ao0, ao1, ao2, ao3 resistance capacitance c k w ______ ______ v 1 +1.2 2 v 1 +3.8 2 v dd v dd v di v 1 v 2 r al c al ta
mb86022 7 electrical characteristics (v dd =4.75v to 5.25v, ta=20 c to 70 c) load unit value parameter symbol pin name min typ max conditions 2.8 5.5 m a v dd power supply current digital pull up current ___ digital input alo width data set up time 1 wr aho width ___ wr alo width data set up time 2 ___ ce set up time data hold time 1 data hold time 2 ___ ce hold time input no pd=aho pd=alo v di =gnd v di =v dd v di =gnd ref. to timing chart 0.5 0 0.8 2.2 10 10 10 10 100 50 25 200 200 500 100 100 0 50 50 0 m a m a ma ma v v ns ns ns ns ns ns ns ns ns v dd ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart all digital input pins d0 to d7, wr pd, ce, reset wr wr reset, pd d0 to d7, wr c0, c1, wr ce, wr d0 to d7, wr c0, c1, wr ce, wr ___ ______ ___ ___ ___ ___ ______ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ alo voltage aho voltage alo current aho current i dd1 i dd2 v il v ih i il i ih i plu t whwr t wlwr t wlrp t sd1 t sd2 t sce t hd1 t hd2 t hce
mb86022 8 unit value parameter symbol min typ max conditions pin name rising time 1 0 wr ___ ref. to timing chart 50 ns falling time 1 0 wr ___ 50 ns ref. to timing chart rising time 2 ref. to timing chart 0 50 ns falling time 2 0 50 ns ref. to timing chart resolution 8 bits analog output min. voltage analog output max. voltage code input no external vr input d(a)= 0 code input d(a)= 255 vr1=open vr2=open external vr input vr1=v 1 vr2=v 2 no external vr input vr1=open vr2=open external vr input vr1=v 1 vr2=v 2 (typ.) 0.1 v v v v 2xv 2 v 1 v 1 (typ.) +0.1 analog input 30 50 200 resistance vr 1 , vr 2 k w linearity error 1.5 1.5 no external vr input vr1=open vr2=open linearity error 1 1 lsb lsb setting time 5 full scale change (ref. to timing chart) m s ao0, ao1, ao2, ao3 (typ.) 0.1 (typ.) 0.1 (typ.) 0.1 ____ 4 v dd (typ.) +0.1 (typ.) +0.1 (typ.) +0.1 ____ 512 383 x v dd _____ 128 v 1 v 2 differential ao0, ao1, ao2, ao3 d0 to d7, c0, ___ ___ ______ c1, ce, reset, pd d0 to d7, c0, ___ ___ ______ c1, ce, reset, pd t r1 t f1 t r2 t f2 res v aol1 v aol2 r i le d le t s v aoh1 v aoh2 (continued) (v dd =4.75v to 5.25v, ta=20 c to 70 c)
mb86022 9 function description truth table ___ 0 ______ x ___ x ___ x pd reset ce wr 1 0 x x 1 1 1 x 1 1 0 c0, c1 d0 to d7 function power down initialization no analog output change channel selectiion no data input analog output change data input d0 to d7 c0, c1 ___ ce ___ wr data is read. analog output is changed. data is not read. analog output is not changed. fig. 1 data set timing diagram
mb86022 10 setting of analog output voltage vr1=v 1 vr2=open (external vr1 input) d(a) 255 d7 1 d6 1 d5 1 d4 1 d3 1 d2 1 d1 1 d0 1 data analog output voltage 254 1 1 1 1 1 1 1 0 253 1 1 1 1 1 1 0 1 129 1 0 0 0 0 0 0 1 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 126 0 1 1 1 1 1 1 0 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1lsb 256 + ____ 512 129 ____ 4 256 x 127 + ______ 128 x 125 2xv 1 v dd ____ 512 x (d(a)128) + ____ 512 v dd v dd ____ 512 130 ____ 512 254 ____ 512 255 ____ 2 v dd ____ 512 257 v dd ____ 2 v dd vr1=open vr2=open (no external vr input) vr1=v 1 vr2=v 2 (external vr input) ____ 512 382 ____ 512 381 ____ 2 v dd 256 x 126 + ____ 2 2xv 1 v dd v dd 256 x 125 + ____ 2 2xv 1 v dd v dd 256 x (d(a) 128) ____ 2 2xv 1 v dd v dd + 2xv 1 v dd ____ 2 v dd ____ 2 v dd ________ 256 x (1) + ____ 2 2xv 1 v dd v dd 256 x (2) + ____ 2 2xv 1 v dd v dd ________ 256 x (126) + ____ 2 2xv 1 v dd v dd ________ 256 x (127) + ____ 2 2xv 1 v dd v dd v dd v 1 ________ 256 2xv 1 v dd ______ 128 v 1 v 2 (v 1 v 2 ) + v 2 ______ 128 x (127) v 1 v 2 ______ 128 x (126) v 1 v 2 ______ 128 x (2) v 1 v 2 ______ 128 x (1) v 1 v 2 v 2 ______ 128 v 1 v 2 ______ 128 x (d(a)128) + v 1 v 2 v 1 v 2 ______ 128 x 126 v 1 v 2 ______ 128 x 127 + v 2 v 1 v 2 * code is set at o10000000o when reset mode. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ____ 512 383 x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v dd ________ _________ _________ _________ _________ _________ + v 2 + v 2 v 2 + v 2 + v 2 + v 2 + v 2 + v 2
mb86022 11 analog output voltage range v dd ag ____ 512 383 x v dd v aoh ____ 512 v dd 1lsb v aol d/a output range __ 4 3 x v dd ____ 4 v dd ____ 2 v dd fig. 2 on-chip reference voltage mode (no external vr input) (vr1=v 1 , vr2=1/2xv dd ) v dd ag x 127 + v aoh 1lsb v aol (v dd v 1 ) d/a output range (vr1) v 1 ____ 2 v dd __________ 256 2 x v 1 v dd ____ 2 v dd __________ 256 2 x v 1 v dd fig. 3 external reference voltage mode (vr1=v 1 , vr2=v 2 ) 1lsb ______ 128 v 1 v 2 v dd ag v aoh v aol (v 1 v 2 ) + v 2 d/a output range (vr1) v 1 (vr2) v 2 ____ 128 127 x (v 1 v 2 ) + v 2 fig. 4 external reference voltage mode
mb86022 12 typical application circuit for each mode 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ reset ___ pd d0 to d7 ___ ce ___ wr c1 c0 ao0 to 3 +5v (v dd ) n.c. + 1 m f + 1 m f fig. 5 on-chip reference voltage mode (vr1=v 1 , vr2=1/2xv dd ) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ reset ___ pd d0 to d7 ___ ce ___ wr c1 c0 ao0 to 3 +5v (v dd ) n.c. v 1 + 1 m f fig. 6 external reference voltage mode (vr1=v 1 , vr2=v 2 ) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ reset ___ pd d0 to d7 ___ ce ___ wr c1 c0 ao0 to 3 +5v (v dd ) n.c. v 1 v 2 fig. 7 external reference voltage mode
mb86022 13 timing diagram t r1 v ih v il v ih v il v ih v il v ih v il v ih v il t f1 t r2 t f2 t r2 t f2 t whwr t wlwr t sd1 t hd1 t sd2 t hd2 t f2 t r2 t sce t hce 1lsb 1lsb t s t wlrp ___ wr ___ ce ______ reset, pd ___ ao0 to ao3 d0 to d7 c0, c1
mb86022 14 package dimensions dimensions in inches (millimeters) 24-lead plastic dual in-line package (case no.: dip-24p-m03) ? 1991 fujitsu limited d24017s-3c 1.170 +.008 .012 (29.72 ) +0.20 0.30 .034 +.020 0 (0.86 ) +0.50 0 .260 .010 (6.60 0.25) index-1 .020(0.51)min .172(4.36)max .118(3.00)min .300(7.62) typ 15 max .050 +.020 0 (1.27 ) +0.50 0 index-2 .050(1.27) max .100(2.54) typ .010 .002 (0.25 0.05) .018 .003 (0.46 0.08)
mb86022 15 dimensions in inches (millimeters) 24-lead plastic flat package (case no.: fpt-24p-m02) ? 1991 fujitsu limited f24008s-4c .004(0.10) ? .005(0.13) m .402 .016 (10.20 0.40) .299 .012 (7.60 0.30) .050(1.27) typ aao .018 .004 (0.45 0.10) .110(2.80) max (mounting height) .002(0.05) min (stand off height) .362 .012 (9.20 0.30) .020 .008 (0.50 0.20) +.002 .001 +0.05 0.02 .006 (0.15 ) details of aao part .008(0.20) .024(0.60) .007(0.18) max .027(0.68) max .600 index .550(13.97) ref (15.24 ) +0.25 0.20 +.010 .008 all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. complete information sufficient for construction purposes is not necessarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu.
mb86022 16 for further information please contact: japan north and south america europe asia pacific fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 951341804, usa tel: (408) 9229000 fax: (408) 4329044/9045 i9502 ? fujitsu limited printed in japan fujitsu limited electronic devices international operations department kawasaki plant, 1015 kamikodanaka, nakaharaku, kawasakishi, kanagawa 211, japan tel: (044) 7543753 fax: (044) 7543332 fujitsu microelectronics asia pte limited no. 51 bras basah road, plaza by the park, #0604 to #0607 singapore 0718 tel: 3361600 fax: 3361609 fujitsu mikroelektronik gmbh am siebenstein 610 63303 dreieichbuchschlag, germany tel: (06103) 6900 fax: (06103) 690122

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