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| rev.1.0 rev.1.0 cmos 16-bit single chip micr ocontr oller s1c17554/564 t ec hnical man ual
? seiko epson corporation 2010, all rights reserved. no tice no part of this material may be reproduced or duplicated in an y form or by an y means without the written permission of seik o epson. seik o epson reserv es the right to mak e changes to this material without notice. seik o epson does not assume an y liability of an y kind arising out of an y inaccuracies contained in this material or due to its application or use in an y product or circuit and, furth er , there is no representation that this material is applicable to products requiring high le v el reliability , such as medical prod- ucts. moreo v er , no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or w arranty that an ything made in accordance with this material will be free from an y patent or cop yright infringement of a third party . this material or portions thereof may contain technology or the subject relating to strate gic products under the control of the f oreign exchange and f oreign t rade la w of japan and may require an e xport license from the ministry of economy , t rade and industry or other appro v al from another go v ernment agenc y . all brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies. devices s1 c 17xxx f 00e1 packing specifications 00 : besides tape & reel 0a : tcp bl 2 directions 0b : t ape & reel ba ck 0c : tcp br 2 directions 0d : tcp bt 2 directions 0e : tcp bd 2 directions 0f : t ape & reel fr ont 0g : tcp bt 4 directions 0h : tcp bd 4 directions 0j : tcp sl 2 directions 0k : tcp sr 2 directions 0l : t ape & reel left 0m : tcp st 2 directions 0n : tcp sd 2 directions 0p : tcp st 4 directions 0q : tcp sd 4 directions 0r : t ape & reel right 99 : specs not fix ed specification package d: die form; f: qfp, b: bga model number model name c: microcomputer, digital products product classification s1: semiconductor development tools s5u1 c 17000 h2 1 packing specifications 00: standard packing version 1: version 1 tool type hx : ice dx : evaluation board ex : rom emulation board mx : emulation memory for external rom tx : a socket for mounting cx : compiler package sx : middleware package yx : writer software corresponding model number 17xxx: for s1c17xxx tool classification c: microcomputer use product classification s5u1: development tool for semiconductor products 00 00 configuration of product number contents s1c17554/564 technical manual seiko epson corporation i C contents C 1 over vie w ........................................................................................................................ 1-1 1.1 f eatures ........................................................................................................................... 1-1 1.2 bloc k diag r am ........................................................................................... ....................... 1-3 1.3 pins .................................................................................................................................. 1-5 1.3.1 s1c17554 pin configur ation diag r ams ............................................................. 1-5 1.3.2 s1c17564 pin configur ation diag r am ............................................................... 1-9 1.3.3 pin descr iptions ................................................................................................ 1-12 2 cpu ................................................................................................................................ 2-1 2.1 f eatures of the s1c17 core ............................................................................................ 2-1 2.2 cpu registers ........ ......................................................................................................... 2-2 2.3 instr uction set .................................................................................................................. 2-2 2.4 reading psr ................................................................................................................... 2-5 2.5 processor inf o r mation ...................................................................................................... 2-6 3 memor y map, bus contr ol ........................................................................................... 3-1 3.1 bus cycle ......................................................................................................................... 3-1 3.1.1 restr ictions on acce ss siz e ............................................................................... 3-2 3.1.2 restr ictions on instr uction ex ecution cycles ..................................................... 3-2 3.2 flash area ........................................................................................................................ 3-2 3.2.1 embedded flash memor y ................................... ............................................... 3-2 3.2.2 flash prog r amming ........................................................................................... 3-2 3.2.3 protect bits ........................................................................................................ 3-3 3.2.4 flash memor y read w ait cycle setting .......................................................... . 3-3 flashc read w ait control register (flashc_w ait) ........................................................... 3-3 3.3 inter nal ram area ............................................................................................................ 3-4 3.3.1 embedded ram ................................................................................................ 3-4 iram siz e register (misc_iramsz) . ...................................................................................... 3-4 3.4 inter nal p er ipher al area ................................................................................................... 3-5 3.4.1 inter nal p er ipher al area 1 (0x4000C) ................................................................. 3-5 3.4.2 inter nal p er ipher al area 2 (0x5000C) ....................... .......................................... 3-5 3.5 s1c17 core i/o area ....................................................................................................... 3-5 4 p o wer suppl y ................................................................................................................ 4-1 4.1 core p o w er supply v oltage (l v dd ) ....................................................... ............................ 4-1 4.2 i/o p o w er supply v oltage (hv dd ) ..................................................................................... 4-1 4.3 analog p o w er supply v oltage (a v dd ) ............................................................................... 4-1 4.4 flash prog r amming p o w er supply v oltage (v pp ) ............................................................. 4-1 4.5 emb edded regulator (s1c17564) ................................................................................... 4-2 4.6 control register details (s1c17564) ............................................................................... 4-2 v d1 control register (vd1_ctl) ............................................................................................... 4-2 4.7 precautions on p o w er supply .. ........................................................................................ 4-3 5 initial reset ................................................................................................................... 5-1 5.1 initial reset sources ........................................................................................................ 5-1 5.1.1 #reset pin ...................... ................................................................................. 5-1 5.1.2 p0 p or t k e y-entr y reset ................................................................................... 5-1 5.1.3 resetting b y the w atchdog timer ...................................................................... 5-1 5.2 initial reset sequence .......................................................... ........................................... 5-2 5.3 initial settings after an initial reset ................................................................................ 5-2 contents ii seiko epson corporation s1c17554/564 technical manual 6 interrupt contr oller (itc) ............................................................................................. 6-1 6.1 itc module ov er vie w ....................................................................................................... 6-1 6.2 v ector t ab le ...................................................................................................................... 6-2 v ect or t ab le address lo w/high registers (misc_ttbrl, misc_ttbrh) .............................. 6-4 6.3 control of maskab le interr upts ......................................................................................... 6-4 6.3.1 interr upt control bits in p er ipher al modules ...................................................... 6-4 6.3.2 itc interr upt request processing ............................. ........................................ 6-4 6.3.3 interr upt processing b y the s1c17 core ........................................................... 6-5 6.4 nmi ................................................................................................................................... 6-6 6.5 softw are interr upts ................................................................................. .......................... 6-6 6.6 hal t and sleep mode cancellation .............................................................................. 6-6 6.7 control register details ................................................................................................... 6-6 interr upt le v el setup register x (itc_l vx) ............................................................................. .. 6-7 7 cloc k generator (clg) ................................................................................................. 7-1 7.1 clg module ov er vie w ..................................................................................................... 7-1 7.2 clg input/output pins ..................................................................................................... 7-2 7.3 oscil lators ........................................................................................................................ 7-2 7.3.1 osc3 oscillator ................................................................................................. 7-2 7.3.2 osc1 oscillator ................................................................................................. 7-4 7.3.3 iosc oscillator ( s1c17564) .............................................................................. 7-5 7.4 system cloc k switching ................................................................................................... 7-6 7.5 cpu core cloc k (cclk) control ..................................................................................... 7-7 7.6 p er ipher al module cloc k (pclk) control ............ ............................................................. 7-8 7.7 cloc k exter nal output (fout a, foutb) ......................................................................... 7-9 7.8 control register details .................................................................................................. 7-10 cloc k source select register (clg_src) ............................................... ............................... 7-10 oscillation control register (clg_ctl) .................................................................................. 7-11 noise filter enab le register (clg_nfen) .............................................................................. 7-13 fout a control register (clg_fout a) .................................................................................. 7 -14 foutb control register (clg_foutb) ................................................................................. 7-15 iosc control register (clg_iosc) ........................................................................................ 7-16 pclk control register (clg_pclk) ....................................................................................... 7-16 cclk control register (clg_c clk) ....................................................................................... 7-17 8 i/o p or ts (p) ................................................................................................................... 8-1 8.1 p module ov er vie w .......................................................................................................... 8-1 8.2 input/output pin function selecti on (p or t mux) .............................................................. 8-2 8.3 data input/output ............................................................................................................. 8-3 8.4 pull-up control ................................................................................................................. 8-3 8.5 p0Cp3 p or t chatter ing filter function ...... ....................................................................... 8-4 8.6 p or t input interr upt ........................................................................................................... 8-4 8.7 p0 p or t k e y-entr y reset ................................................................................................. 8-5 8.8 control register details .............................. ..................................................................... 8-5 px p or t input data registers (px_in) ........................................................................................ 8-7 px p or t output data registers (px_out) ................................................................................. 8-7 px p or t output enab le registers (px_oen) .................................... ......................................... 8-7 px p or t pull-up control registers (px_pu) ............................................................................... 8-8 px p or t interr upt mask registers (px_imsk) ............................................................................ 8-8 px p or t interr upt edge select registers (px_edge) ............................................................ .... 8-9 px p or t interr upt flag registers (px_iflg) ............................................................................... 8-9 px p or t chatter ing filter control registers (px_cha t) ........................................................... 8-10 p0 p or t k e y-entr y reset configur ation register (p0_krst) .................................................. 8-10 px p or t input enab le registers (px_ien) . ................................................................................ 8-11 contents s1c17554/564 technical manual seiko epson corporation iii p0[3:0] p or t function select register (p00_03pmux) ............................................................ 8-11 p1[3:0] p or t function select register (p10_13pmux) ............................................................ 8-12 p1[7:4] p or t function select register (p14_17pmux) ............................................................ 8-13 p2[3:0] p or t function select register (p20_23pmux) .... ........................................................ 8-14 p2[7:4] p or t function select register (p24_27pmux) ............................................................ 8-15 p3[3:0] p or t function select register (p30_33pmux) ............................................................ 8-16 p3[7:4] p or t function select register (p34_37pmux) ........................................................... . 8-17 p4[3:0] p or t function select register (p40_43pmux) ............................................................ 8-18 p4[5:4] p or t function select register (p44_45pmux) ............................................................ 8-18 p5[3:0] p or t function select register (p50_53pmux) ............................................................ 8-19 p5[5:4] p or t function select register (p54_55pmux) ............................................................ 8-20 9 16-bit timer s (t16) ........................................................................................................ 9-1 9.1 t16 module ov er vie w ...................................................................................................... 9-1 9.2 count cloc k .......................................................... ............................................................ 9-2 9.3 count mode ...................................................................................................................... 9-2 9.4 reload data register and underflo w cycle ..................................................................... 9-2 9.5 timer reset ................................................................. ..................................................... 9-3 9.6 timer r un/st op control ................................................................................................ 9-3 9.7 t16 output signals ........................................................................................................... 9-4 9.8 t16 interr upts ............................................................... .................................................... 9-4 9.9 control register details ................................................................................................... 9-5 t16 ch.x count cloc k select registers (t16_clkx) ................................................................ 9-5 t16 ch.x reload data registers (t16_trx) ......................................................... .................... 9-6 t16 ch.x counter data registers (t16_tcx) ........................................................................... 9-6 t16 ch.x control registers (t16_ctlx) ................................................................................... 9-6 t16 ch.x interr upt control registers (t16_intx) ..................................................................... 9-7 10 fine mode 16-bit timer s (t16f) ................................................................................ 10-1 10.1 t16f module ov er vie w ................................................................................................. 10-1 10.2 count cloc k ................................................................................................................... 10-2 10.3 count mode ............ ....................................................................................................... 10-2 10.4 reload data register and underflo w cycle .................................................................. 10-2 10.5 timer reset ................................................................................................................... 10-3 10.6 timer r un/st op control .......... ................................................................................... 10-3 10.7 t16f output signals ..................................................................................................... 10-4 10.8 fine mode ..................................................................................................................... 10-4 10.9 t16f interr upts ....................... ....................................................................................... 10-5 10.10 control register details .............................................................................................. 10-6 t16f ch.x count cloc k select registers (t16f_clkx) .......................................................... 10-6 t16f ch.x reload data registers (t16f_trx) ....................... ................................................ 10-6 t16f ch.x counter data registers (t16f_tcx) ...................................................................... 10-7 t16f ch.x control registers (t16f_ctlx).............................................................................. 10-7 t16f ch.x interr upt control registers (t16f_intx) ........................................................... ..... 10-8 11 16-bit pwm timer s (t16a) ......................................................................................... 11-1 11.1 t16a module ov er vie w ................................................................................................. 11-1 11.2 t16a input/output pins ................................................................................................. 11-2 11.3 count cloc k ................................................................................................................... 11-3 11.4 t16a oper ating modes ................................................................................................. 11-4 11.4.1 compar ator mode and capture mode ............................................................ 11-4 11.4.2 repeat mode and one-shot mode ... .............................................................. 11-6 11.4.3 nor mal channel mode and multi-compar ator/capture mode ........................ 11-6 contents iv seiko epson corporation s1c17554/564 technical manual 11.5 counter control ............................................................................................................ 11-8 11.5.1 counter reset ................................................................................................. 11-8 11.5.2 counter r un/st op control ........................................................................... 11-8 11.5.3 reading counter v alues ................................................................................. 11-8 11.5.4 timing char ts .................................................................................................. 11-8 11.6 timer output control ..................................................................................................... 11-9 11.7 t16a interr upts ..................................... ........................................................................ 11-10 11.8 control register details ............................................................................................... 11-12 t16a cloc k control register ch.x (t16a_clkx) .................................................................... 11-13 t16a counter ch.x control registers (t16a_ctlx) .......................... .................................... 11-14 t16a counter ch.x data registers (t16a_tcx) .................................................................... 11-15 t16a compar ator/capture ch.x control registers (t16a_ccctlx) ..................................... 11-16 t16a compar ator/capture ch.x a data registers (t16a_ccax) .......................................... 11-18 t16a compar ator/capture ch.x b dat a registers (t16a_ccbx) .......................................... 11-18 t16a compar ator/capture ch.x interr upt enab le registers (t16a_ienx) ............................. 11-19 t16a compar ator/capture ch.x interr upt flag registers (t16a_iflgx) ............................... 11-20 12 cloc k timer (ct) ....................................................................................................... . 12-1 12.1 ct module ov er vie w ..................................................................................................... 12-1 12.2 oper ation cloc k ............................................................................................................. 12-1 12.3 timer reset ................................................................................................................. .. 12-1 12.4 timer r un/st op control ............................................................................................. 12-1 12.5 ct interr upts ................................................................................................................. 12-2 12.6 control register details ................................................................................................ 12-3 cloc k timer control register (ct_ctl) ................................................................................... 12-3 cloc k timer counter register (ct_cnt) ................................................................................. 12-3 cloc k timer interr upt mask register (ct_imsk) ..................................................................... 12-4 cloc k timer interr upt flag regist er (ct_iflg) ........................................................................ 12-4 13 stopwatc h timer (swt) ............................................................................................. 13-1 13.1 swt module ov er vie w ................................................................................................. 13-1 13.2 oper ation cloc k ........................................ ..................................................................... 13-1 13.3 bcd counters ............................................................................................................... 13-1 13.4 timer reset ................................................................................................................... 13-2 13.5 timer r un/st op control ........................... .................................................................. 13-2 13.6 swt interr upts .............................................................................................................. 13-3 13.7 control register details ................................................................................................ 13-4 stopw atch timer control register (swt_ctl) ..................... ................................................... 13-4 stopw atch timer bcd counter register (swt_bcnt) ........................................................... 13-4 stopw atch timer interr upt mask register (swt_imsk) .......................................................... 13-5 stopw atch timer interr upt flag register (swt_iflg) ............................................................. 13-5 14 w a tc hdog timer (wdt) .............................................................................................. 14-1 14.1 wdt module ov er vie w ................................................................................................. 14-1 14.2 oper ation cloc k ............................................................................................................. 14-1 14.3 wdt control .... .............................................................................................................. 14-1 14.3.1 nmi/reset mode selection ............................................................................. 14-1 14.3.2 wdt run/stop control ................................................................................... 14-1 14.3.3 wdt reset ...................................... ............................................................... 14-2 14.3.4 oper ations in hal t and sleep modes ......................................................... 14-2 14.4 control register details ................................................................................................ 14-2 w atchdog timer control register (wdt_ctl) ........................................................ ................ 14-2 w atchdog timer status register (wdt_st) ............................................................................ 14-3 contents s1c17554/564 technical manual seiko epson corporation v 15 u ar t ........................................................................................................................... 15-1 15.1 u ar t module ov er vie w ................................................................................................ 15-1 15.2 u ar t input/output pins ................................................................................................ 15-2 15.3 ba ud rate gener ator .................................................................................................... 15-2 15.4 t r ansf er data settings ................................................................................................... 15-4 15.5 data t r ansf er control .................................................................................................... 15-5 15.6 receiv e errors ............................................................................................................... 15-7 15.7 u ar t interr upts ............................................................................................................ 15-8 15.8 ird a interf ace ................................................................................................................ 15-9 15.9 co ntrol register details ................................................................................................ 15-9 u ar t ch.x status registers (u ar t_stx) .............................................................................. 15-10 u ar t ch.x t r ansmit data registers (u ar t_txdx) ................................................................ 15-12 u ar t ch.x receiv e data registers (u ar t_rxd x) ................................................................ 15-12 u ar t ch.x mode registers (u ar t_modx) ........................................................................... 15-12 u ar t ch.x control registers (u ar t_ctlx) .......................................................................... 15-13 u ar t ch.x expansion registers (u ar t_expx) .................................................. ................... 15-14 u ar t ch.x baud rate registers (u ar t_brx) ....................................................................... 15-14 u ar t ch.x fine mode registers (u ar t_fmdx) .................................................................... 15-15 u ar t ch.x cloc k control registers (u ar t_clkx) ................................................................ 15-16 16 spi ..................... .......................................................................................................... 16-1 16.1 spi module ov er vie w .................................................................................................... 16-1 16.2 spi input/output pins .................................................................................................... 16-1 16.3 spi cloc k ............ .......................................................................................................... 16-2 16.4 data t r ansf er condition settings ................................................................................... 16-2 16.5 data t r ansf er control .................................................................................................... 16-3 16.6 spi interr upts ........... ..................................................................................................... 16-5 16.7 control register details ................................................................................................ 16-6 spi ch.x status registers (spi_stx) ...................................................................................... 16-6 spi ch.x t r ansmit data registers (spi_ txdx) ........................................................................ 16-7 spi ch.x receiv e data registers (spi_rxdx) ........................................................................ 16-7 spi ch.x control registers (spi_ctlx) ................................................................................... 16-7 17 i 2 c master (i2cm) .................................................... ................................................... 17-1 17.1 i2cm module ov er vie w ................................................................................................. 17-1 17.2 i2cm input/output pins ................................................................................................. 17-1 17.3 synchronization cloc k ........................................................... ........................................ 17-2 17.4 settings bef ore data t r ansf er ....................................................................................... 17-2 17.5 data t r ansf er control .................................................................................................... 17-2 17.6 i2cm interr upts ........................................................................... .................................. 17-6 17.7 control register details ................................................................................................ 17-7 i 2 c master enab le register (i2cm_en) ................................................................................... 17-7 i 2 c master control register (i2cm_ctl) .................................................................... ............. 17-8 i 2 c master data register (i2cm_d a t) ..................................................................................... 17-9 i 2 c master interr upt control register (i2cm_ictl) ................................................................ 17-10 18 i 2 c sla ve (i2cs) .......................................................................................................... 18-1 18.1 i2 cs module ov er vie w ................................................................................................. 18-1 18.2 i2cs input/output pins ................................................................................................. 18-1 18.3 oper ation cloc k ............................................................................................................. 18-2 18.4 initializi ng i2cs ............................................................................................................. 18-2 18.4.1 reset .............................................................................................................. 18-2 18.4.2 setting sla v e address ..................................................................................... 18-2 contents vi seiko epson corporation s1c17554/564 technical manual 18.4.3 optional functions .......................................................................................... 18-2 18.5 data t r ansf er control .................................................................................................... 18-3 18.6 i2cs interr upts .............................................................................................................. 18-8 18.7 contr ol register details ................................................................................................ 18-9 i 2 c sla v e t r ansmit data register (i2cs_trns) ...................................................................... 18-9 i 2 c sla v e receiv e data register (i2cs_recv) ..................................................................... 18-10 i 2 c sla v e address setup register (i2cs_sadr s) ................................................................. 18-10 i 2 c sla v e control register (i2cs_ctl) .................................................................................. 18-10 i 2 c sla v e status register (i2cs_st a t) .................................................................................. 18-13 i 2 c sla v e access status register (i2cs_ast a t) ............................... .................................... 18-15 i 2 c sla v e interr upt control register (i2cs_ictl) ................................................................... 18-16 19 univer sal serial interface (usi) [s1c17564] ............................................................ 19-1 19.1 usi module ov er vie w .................................................................................................. 1 9-1 19.2 usi pins ........................................................................................................................ 19-2 19.3 usi cloc k sources ........................................................................................................ 19-2 19.4 usi module settings ................................................................................................... . 19-4 19.4.1 usi module softw are reset ............................................................................ 19-4 19.4.2 interf ace mode ................................................................................................ 19-4 19.4.3 gener al settings f or all interf ace modes ........................................................ 19-4 19.4.4 settings f or u ar t mode ................. ............................................................... 19-4 19.4.5 settings f or spi master mode ........................................................................ 19-5 19.4.6 settings f or i 2 c mode ..................................................................................... 19-6 19.5 data t r ansf er control ....................................................................... ............................. 19-6 19.5.1 data t r ansf er in u ar t mode .......................................................................... 19-6 19.5.2 data t r ansf er in spi master mode .................................................................. 19-7 19.5.3 data t r ansf er in i 2 c mode ............................................................................... 19-9 19.6 receiv e errors ...... ........................................................................................................ 19-19 19.7 usi interr upts ............................................................................................................... 19-19 19.7.1 interr upts in u ar t mode ............................................................................... 19-20 19.7.2 interr upts in spi master mode ....................................................................... 19-20 19.7.3 interr upts in i 2 c master mode ........................................................................ 19-21 19.7.4 interr upts in i 2 c sla v e mode .......................................................................... 19-22 19.8 control register details .............................................................. ................................. 19-22 usi ch.x global configur ation registers (usi_gcfgx) ......................................................... 19-23 usi ch.x t r ansmit data buff er registers (usi_tdx) ............................................................... 19-23 usi ch.x receiv e data buff er registers (usi_rdx) ............................................................... 19-24 usi ch.x u ar t mode configur ation registers (usi_ucfgx) ................................................ 19-24 usi ch.x u ar t mode interr upt enab le registers (usi_uiex) ................................................ 19-25 usi ch.x u ar t mode interr upt flag registers (usi_uifx) .................................................... 19-25 usi ch.x spi master mode configur ation registers (usi_scfgx) ....................... ................. 19-27 usi ch.x spi master mode interr upt enab le registers (usi_siex) ........................................ 19-28 usi ch.x spi master mode interr upt flag registers (usi_sifx) ............................................ 19-29 usi ch.x spi master mode receiv e data mask registers (usi_smskx) .............................. 19-30 usi ch.x i 2 c master mode t r igger registers (usi_imtgx) ..... ............................................... 19-30 usi ch.x i 2 c master mode interr upt enab le registers (usi_imiex) ....................................... 19-31 usi ch.x i 2 c master mode interr upt flag registers (usi_imifx) ........................................... 19-31 usi ch.x i 2 c sla v e mode t r igger registers (usi_istgx) ....................................................... 19-32 usi ch.x i 2 c sla v e mode interr upt enab le registers (usi_isiex) .......................................... 19-33 usi ch.x i 2 c sla v e mode interr upt flag registers (usi_isifx) .............................................. 19-34 19.9 precautions .................................................................................................................. 19-35 20 ir remote contr oller (remc) .......................... ......................................................... 20-1 20.1 remc module ov er vie w ............................................................................................... 20-1 20.2 remc input/output pins ............................................................................................... 20-1 contents s1c17554/564 technical manual seiko epson corporation vii 20.3 carr ier gener ation ........................................................................................................ 20-1 20.4 data length counter cloc k settings ............................................................................. 20-2 20.5 data t r ansf er control .................................................................................................... 20-3 20.6 remc in terr upts ........................................................................................................... 20-5 20.7 control register details ................................................................................................ 20-6 remc configur ation register (remc_cfg) ........................................................................... 20-6 remc carr ier length setup regis ter (remc_car) ............................................................... 20-7 remc length counter register (remc_lcnt) ..................................................................... 20-8 remc interr upt control register (remc_int) ........................................................................ 20-9 21 a/d con ver ter (adc10) ............................................................ ................................. 21-1 21.1 adc10 module ov er vie w .............................................................................................. 21-1 21.2 adc10 input pins .......................................................................................................... 21-2 21.3 a/d con v er ter settings ........................................................................... ...................... 21-2 21.3.1 a/d con v ersion cloc k setting ......................................................................... 21-2 21.3.2 selecting a/d con v ersion star t and end channels ........................................ 21-3 21.3.3 a/d con v ersion mode setting ......................................................................... 21-3 21.3.4 t r igger selection .................... ........................................................................ 21-4 21.3.5 sampling time setting ................................................................................... 21-4 21.3.6 setting con v ersion result stor ing mode ........................................................ 21-5 21.4 a/d con v ersion control and oper ations ....................................................... ................ 21-5 21.4.1 activ ating a/d con v er ter ................................................................................. 21-5 21.4.2 star ting a/d con v ersion .................................................................................. 21-5 21.4.3 reading a/d con v ersion results ................................................................... 21-6 21.4.4 t er minating a/d con v ersion ........................................................................... 21-6 21.4.5 timing char ts .................................................................................................. 21-6 21.5 a/d con v er ter interr upts .............................................................................................. 21-7 21.6 control register details .................................... ............................................................ 21-8 a/d con v ersion result register (adc10_add) ..................................................................... 21-8 a/d t r igger/channel select register (adc10_trg) .............................................................. 21-9 a/d control/status register (adc10_ctl) ................................................................ ............ 21-10 a/d cloc k control register (adc10_clk) ............................................................................. 21-12 a/d compar ator setting register (adc10_com) .................................................................. 21-13 22 on-c hip deb ug g er (dbg) .......................................................................................... 22-1 22.1 resource requireme nts and deb ugging t ools ............................................................. 22-1 22.2 deb ug break oper ation status ..................................................................................... 22-1 22.3 additional deb ugging function ..................................................................................... 22-2 22.4 control register details ............................... ................................................................. 22-2 deb ug mode control register 1 (misc_dmode1) ................................................................. 22-2 deb ug mode control register 2 (misc_dmode2) ................................................................. 22-3 iram siz e select register (misc_iramsz) ................................................................. .......... 22-3 deb ug ram base register (dbram) ...................................................................................... 22-4 deb ug control register (dcr) ................................................................................................. 22-4 instr uction break address register 2 (ibar2) ......................................................................... 22-5 instr uction break address register 3 (ibar3) ......................................................................... 22-5 instr uction break address register 4 (ibar4) ......................................................................... 22-6 23 multiplier/divider (copr o) ....................................................................................... 23-1 23.1 ov er vie w ............................... ........................................................................................ 23-1 23.2 oper ation mode and output mode ................................................................................ 23-1 23.3 multiplication ................................................................................................................. 23-2 23.4 division .................................. ........................................................................................ 23-3 23.5 ma c .............................................................................................................................. 23-4 contents viii seiko epson corporation s1c17554/564 technical manual 23.6 reading results ............................................................................................................ 23-6 24 electrical characteristics .......................................................................................... 24-1 24.1 absolute maxim um ratings .......................................................................................... 24-1 24.2 recommende d oper ating conditions ........................................................................... 24-1 24.3 current consumption .................................................................................................... 24-2 24.4 dc regulator char acter istics ........................................................................................ 24-3 24.5 oscillation char acter istics ....... ...................................................................................... 24-4 24.6 exter nal cloc k input char acter istics ............................................................................. 24-5 24.7 system cloc k char acter istics ....................................................................................... 24-5 24.8 input/output pin char acter istics ..................... .............................................................. 24-6 24.9 spi char acter istics ........................................................................................................ 24-7 24.10 i 2 c char acter istics ...................................................................................................... 24-7 24.11 usi char acter istics (s1c17564) ............................. .................................................... 24-8 24.12 a/d con v er ter char acter istics ..................................................................................... 24-9 24.13 flash memor y char acter istics .................................................................................... 24-10 25 basic external connection dia gram ........................................................ ................ 25-1 26 p ac ka g e ...................................................................................................................... 26-1 appendix a list of i/o register s ................................................................................ ap-a-1 0x4100C0x4107, 0x506c u ar t (with ird a) ch.0 ................................................ ap-a-5 0x4120C0x4127, 0x506d u ar t ( with ird a) ch.1 ................................................ ap-a-6 0x4200C0x4208 fine mode 16-bit timer ch.0 ...................................... ap-a-7 0x4220C0x4228 16-bit timer ch.0 ........................................................ ap-a-8 0x4240C0x4248 16-bit timer ch.1 ........................................................ ap-a-8 0x4260C0x4268 16-bit timer ch.2 ........................ ................................ ap-a-9 0x4280C0x4288 fine mode 16-bit timer ch.1 ...................................... ap-a-9 0x4306C0x431c interr upt controller ..................................................... ap-a-10 0x4320C0x4326 spi ch.0 .................................................................... ap-a-11 0x4340C0x4346 i 2 c master ........................................................... ....... ap-a-11 0x4360C0x436c i 2 c sla v e .................................................................... ap-a-11 0x4380C0x4386 spi ch.1 .................................................................... ap-a-12 0x43a0C0x43a6 spi ch.2 .................................................................... ap-a-12 0x5000C0x5003 cloc k timer ................................................................ a p-a-13 0x5020C0x5023 stopw atch timer ........................................................ ap-a-13 0x5040C0x5041 w atchdog timer ......................................................... ap-a-13 0x5060C0x5081 cloc k gener ator ........................................................ ap-a-14 0x50c0C0x50cf usi ch.0 .................................................................... ap-a-15 0x50e0C0x50ef usi ch.1 .................................................................... ap-a-17 0x5121 p o w er gener ator ....................................................... ap-a-19 0x5200C0x52ab p p or t & p or t mux ..................................................... ap-a-19 0x4020, 0x5322C0x532c misc registers ......................................................... ap-a-26 0x5340C0x5346 ir remote controller ....... .......................................... ap-a-27 0x5380C0x5388 a/d con v er ter ............................................................ ap-a-27 0x5068, 0x5400C0x540c 16-bit pwm timer ch.0 ............................................. ap-a-28 0x5069, 0x5420C0x542c 16-bit pwm timer ch.1 ............................................. ap-a-30 0x506a, 0x5440C0x544c 16-bit pwm timer ch.2 .................... ......................... ap-a-31 0x506b , 0x5460C0x546c 16-bit pwm timer ch.3 ............................................. ap-a-33 0x54b0 flash controller ......................................................... ap-a-34 0xffff84C0xffffd0 s1c17 core i/o ......................................................... ap-a-34 contents s1c17554/564 technical manual seiko epson corporation ix appendix b p o wer sa ving .......................................................................................... ap-b-1 b .1 cloc k control p o w er sa ving ......................................................................................... ap-b-1 b .2 reducing p o w er consumption via p o w er supply control ........................................... ap-b-2 appendix c mounting precautions .............. .............................................................. ap-c-1 appendix d initialization routine .............................................................................. ap-d-1 appendix e recommended resonator s ................................................................... ap-e-1 re vision histor y 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-1 ov er view 1 features 1.1 the main features of the s1c17554/564 are listed belo w . 1.1 f eatures t ab le 1. model s1c17554 s1c17564 cpu cpu core seik o epson or iginal 16-bit risc cpu core s1c17 multiplier/divider (copr o) ? ? ? embed ded flash memor y capacity 128k b ytes (f or both instr uctions and data) er ase/prog r am count min. 1 time other ? ? ? embed ded ram capacity 16k b ytes cloc k g enerator system cloc k source 2 sources (osc3/osc1) 3 sources (iosc/osc3/osc1) iosc oscillator circuit 2/4/8/12 mhz(typ .) inter nal oscillator circuit osc3 oscillator circuit 24 mhz (max.) cr ystal or cer amic oscillator circuit suppor ts an e xter nal cloc k input. osc1 oscillator circu it 32.768 khz (typ .) cr ystal oscillator circuit suppor ts an e xter nal cloc k input. other ? ? i/o por ts number of gener al-pur pose i/o por ts max. 40 bits (tqfp13-64pin pac kage) max. 34 bits (wcsp-48 pac kage) (pins are shared with the per ipher al i/o .) max. 40 bits (pins are shared with the per ipher al i/o .) serial interfaces spi 3 channels i 2 c master (i2cm) 1 channel i 2 c sla v e (i2cs) 1 channel u ar t 2 channels (ird a1.0 suppor ted) ir remote controller (remc) 1 channel univ ersal ser ial interf ace (usi) 2 channels (usab le as a u ar t , spi, or i 2 c) timer s 16-bit timer (t16) 3 channels fine mode 16-bit timer (t16f) 2 channels 16-bit pwm timer (t16a) 4 channels cloc k timer (ct) 1 channel stopw atch timer (swt) 1 channel w atchdog timer (wdt) 1 channel a/d con ver ter con v ersion m ethod successiv e appro ximation type number of analog input channels 4 channels (max.) resolution 10 bits interrupts reset interr upt #reset pin nmi w atchdog timer prog r ammab le interr upts 23 systems (8 le v els) p o wer suppl y v olta g e core v oltage (l v dd ) 1.65 v to 1.95 v 1.65 v to 1.95 v (not required when the regulator is used.) i/o v oltage (hv dd ) 1.65 v to 5.5 v 2.0 v to 5.5 v (regulator used) 1.65 v to 5.5 v (regulator not used) analog v oltage (a v dd ) 2.7 v to 5.5 v flash prog r amming v oltage (v pp ) 7 v 1 o ver view 1-2 seiko epson corporation s1c17554/564 t echnical m anual model s1c17554 s1c17564 regulator input v oltage 2.0 v to 5.5 v output v oltage 1.8 v other enab les the system to oper ate with a 3.3 v or 5.0 v single po w er supply . operating temperature oper ating temper ature r ange -40c to 85c current consumption (t yp v alue , l v dd = hv dd = 1.8 v) sleep state 0.8 a (osc1 = off , osc3 = off) 1.2 a (osc1 = off , iosc = off , osc3 = off) hal t state 2.7 a (osc1 = 32 khz, osc3 = off) 3.1 a (osc1 = 32 khz, iosc = off , osc3 = off) run state 16 a (osc1 = 32 khz, osc3 = off) 16 a (osc1 = 32 khz, iosc = off , osc3 = off) 3000 a (osc1 = off , osc3 = 8 mhz cer amic) 3000 a (osc1 = off , iosc = off , osc3 = 8 mhz cer amic) 4500 a (osc1 = off , iosc = 12 mhz, osc3 = off) a/d con v ersion 380 a (a v dd = 3.6 v , 100 khz sampling, fsel[1:0] = 0x0, xpd[1:0] = 0x3) shipping f orm 1 tqfp13-64pin (10 mm 10 mm 1 .0 mm, lead pitch: 0.5 mm) 2 die f or m (3.137 mm 3.137 mm, pad pitch: 140 m) 3 wcsp-48 (3.137 mm 3.137 mm 0.72 mm, ball pitch: 0.4 mm) 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-3 bloc k dia gram 1.2 s1c17554 cpu core s1c17 internal ram (16k bytes) i 2 c master 16-bit timer (3 ch.) clock generator (with oscillators) clock timer stopwatch timer watchdog timer 16-bit pwm timer (4 ch.) ir remote controller misc register flash memory (128k bytes) 32 bits 16 bits interrupt system 8/16 bits dclk, dst2, dsio osc1C2, osc3C4 fouta, foutb exclx, capx, toutx remi, remo pxx #reset sinx, soutx, sclkx sdix, sdox, spiclkx, #spissx sda0, scl0 reset circuit 8/16 bits i/o 2 (0x5000C) interrupt controller uart (2 ch.) spi (3 ch.) i/o 1 (0x4000C) i/o port/ port mux a/d converter i 2 c slave sda1, scl1, #bfr fine mode 16-bit timer (2 ch.) test test circuit av dd ainx, #adtrg 2.1 s1c17554 bloc k diag r am figure 1. 1 o ver view 1-4 seiko epson corporation s1c17554/564 t echnical m anual s1c17564 cpu core s1c17 internal ram (16k bytes) i 2 c master 16-bit timer (3 ch.) clock generator (with oscillators) clock timer stopwatch timer watchdog timer 16-bit pwm timer (4 ch.) ir remote controller misc register regulator flash memory (128k bytes) 32 bits 16 bits interrupt system 8/16 bits dclk, dst2, dsio v in , v out , regen osc1C2, osc3C4 fouta, foutb exclx, capx, toutx remi, remo pxx #reset sinx, soutx, sclkx sdix, sdox, spiclkx, #spissx sda0, scl0 reset circuit 8/16 bits i/o 2 (0x5000C) interrupt controller uart (2 ch.) spi (3 ch.) i/o 1 (0x4000C) i/o port/ port mux a/d converter i 2 c slave sda1, scl1, #bfr fine mode 16-bit timer (2 ch.) test test circuit usi (2 ch.) us_sdix, us_sdox, us_sckx, us_ssix av dd ainx, #adtrg 2.2 s1c17564 bloc k diag r am figure 1. 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-5 pins 1.3 s1c17554 pin configuration dia grams 1.3.1 wcsp-48 (s1c17554) a b c d e f g a b c d e f g 7654321 1234567 a1 corner a1 corner index t op v iew t op v iew bottom v iew a b c d e f g 1 v ss v ss v pp hv dd hv dd lv dd av dd lv dd p10 sdi0 p01 ain1 p03 ain3 p17 scl0 p45 (excl0) sd a0 p40 sin0 t out6 cap6 #reset p00 ain0 p02 ain2 p32 t out4 cap4 fout a p42 sclk0 t out1 cap1 p41 sout0 t out7 cap7 dclk p35 p23 (excl2) sdi2 p11 sdo0 p12 spiclk0 p21 t out3 cap3 p13 #spiss0 t out5 cap5 p15 sout1 sdo1 osc4 p22 (excl1) foutb p20 t out2 cap2 p14 sin1 sdi1 p44 scl1 remo p16 sclk1 spiclk1 osc3 p43 sd a1 remi p25 #bfr #spiss2 osc2 p24 (excl3) sdo2 p27 scl1 osc1 p34 remo #spiss1 p33 remi spiclk2 test dsio p36 p31 #bfr #adtrg dst2 p37 p30 t out0 cap0 p26 sd a1 234567 3.1.1 s1c17554 pin configur ation diag r am (wcsp-48) figure 1. 1 o ver view 1-6 seiko epson corporation s1c17554/564 t echnical m anual tqfp13-64pin (s1c17554) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 sdi0/p10 v ss sdo0/p11 spiclk0/p12 #spiss0/tout5/cap5/p13 lv dd hv dd sin1/sdi1/p14 p51 sout1/sdo1/p15 sclk1/spiclk1/p16 sda1/remi/p43 scl1/remo/p44 sdo2/p24(excl3) #bfr/#spiss2/p25 v ss v ss hv dd lv dd p23(excl2)/sdi2 p22(excl1)/foutb p21/tout3/cap3 p20/tout2/cap2 hv dd osc4 osc3 v pp osc2 osc1 v ss p55 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p54 p34/remo/#spiss1 p33/remi/spiclk2 dclk/p35 test dsio/p36 dst2/p37 p31/#bfr/#adtrg p53 lv dd p30/tout0/cap0 hv dd v ss p27/scl1 p26/sda1 p52 #reset lv dd sin0/tout6/cap6/p40 sout0/tout7/cap7/p41 sclk0/tout1/cap1/p42 sda0/p45(excl0) hv dd v ss scl0/p17 tout4/cap4/fouta/p32 n.c. av dd ain3/p03 ain2/p02 ain1/p01 ain0/p00 3.1.2 s1c17554 pin configur ation diag r am (tqfp13-64pin) figure 1. 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-7 chip (s1c17554) y x (0, 0) 3.137 mm 3.137 mm p50 sdi0/p10 v ss sdo0/p11 spiclk0/p12 #spiss0/tout5/cap5/p13 lv dd hv dd sin1/sdi1/p14 p51 sout1/sdo1/p15 sclk1/spiclk1/p16 sda1/remi/p43 scl1/remo/p44 hv dd sdo2/p24(excl3) #bfr/#spiss2/p25 v ss n.c. v ss n.c. n.c. lv dd p23(excl2)/sdi2 p22(excl1)/foutb p21/tout3/cap3 p20/tout2/cap2 hv dd osc4 v ss osc3 v pp osc2 osc1 v ss p55 p54 p34/remo/#spiss1 p33/remi/spiclk2 dclk/p35 test dsio/p36 lv dd dst2/p37 p31/#bfr/#adtrg p53 lv dd p30/tout0/cap0 hv dd v ss v ss p27/scl1 p26/sda1 p52 #reset lv dd sin0/tout6/cap6/p40 sout0/tout7/cap7/p41 sclk0/tout1/cap1/p42 sda0/p45(excl0) hv dd v ss scl0/p17 tout4/cap4/fouta/p32 n.c. av dd av dd ain3/p03 ain2/p02 ain1/p01 ain0/p00 n.c. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 die no. cj554d0b0 3.1.3 s1c17554 p ad configur ation diag r am figure 1. chip siz e x = 3.137 mm, y = 3.137 mm p ad opening no . 1 to 18, 37 to 54: x = 122 m, y = 85 m no . 19 to 36, 55 to 72: x = 85 m, y = 122 m chip thic kness 400 m 1 o ver view 1-8 seiko epson corporation s1c17554/564 t echnical m anual 3.1.1 s1c17554 p ad coordinates t ab le 1. no. name x (mm) y (mm) no. name x (mm) y (mm) 1 p50 -1190 -1455.5 37 p55 1190 1455.5 2 p10/sdi0 -1050 -1455.5 38 v ss 1050 1455.5 3 v ss -910 -1455.5 39 osc1 910 1455.5 4 p11/sdo0 -770 -1455.5 40 osc2 770 1455.5 5 p12/spiclk0 -630 -1455.5 41 v pp 630 1455.5 6 p13/#spiss0/t out5/cap5 -490 -1455.5 42 osc3 490 1455.5 7 lv dd -350 -1455.5 43 v ss 350 1455.5 8 hv dd -210 -1455.5 44 osc4 210 1455.5 9 p14/sin1/sdi1 -70 -1455.5 45 hv dd 70 1455.5 10 p51 70 -1455.5 46 p20/t out2/cap2 -70 1455.5 11 p15/sout1/sdo1 210 -1455.5 47 p21/t out3/cap3 -210 1455 .5 12 p16/sclk1/spiclk1 350 -1455.5 48 p22(excl1)/foutb -350 1455.5 13 p43/sd a1/remi 490 -1455.5 49 p23(excl2)/sdi2 -490 1455.5 14 p44/scl1/remo 630 -1455.5 50 lv dd -630 1455.5 15 hv dd 770 -1455.5 51 n.c . -770 1455.5 16 p24(excl3)/sdo2 910 -1455.5 52 n.c . -910 1455.5 17 p25/#bfr/spiss2 1050 -1455.5 53 v ss -1050 1455.5 18 v ss 1190 -1455.5 54 n.c . -1190 1455.5 19 p52 1455.5 -1190 55 #reset -1455.5 1190 20 p26/sd a1 1455.5 -1050 56 lv dd -1455.5 1050 21 p27/scl1 1455.5 -910 57 p40/sin0/t out6/cap6 -1455.5 910 22 v ss 1455.5 -770 58 p41/sout0/t out 7/cap7 -1455.5 770 23 v ss 1455.5 -630 59 p42/sclk0/t out1/cap1 -1455.5 630 24 hv dd 1455.5 -490 60 p45(excl0)/sd a0 -1455.5 490 25 p30/t out0/cap0 1455.5 -350 61 hv dd -1455.5 350 26 lv dd 1455.5 -210 62 v ss -1455.5 210 27 p53 1455.5 -70 63 p17/scl0 -1455.5 70 28 p31/#bfr/adtrg 1455.5 70 64 p32/t out4/cap4/fout a -1455.5 -70 29 dst2/p37 1455.5 210 65 n.c . -1455.5 -210 30 lv dd 1455.5 350 66 av dd -1455.5 -350 31 dsio/p36 1455.5 490 67 av dd -1455.5 -490 32 test 1455.5 630 68 p03/ain3 -1455.5 -630 33 dclk/p35 1455.5 770 69 p02/ain2 -1455.5 -770 34 p33 /remi/spiclk2 1455.5 910 70 p01/ain1 -1455.5 -910 35 p34/remo/#spiss1 1455.5 1050 71 p00/ain0 -1455.5 -1050 36 p54 1455.5 1190 72 n.c . -1455.5 -1190 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-9 s1c17564 pin configuration dia gram 1.3.2 tqfp13-64pin (s1c17564) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 us_sdi0/p50 sdi0/p10 v ss sdo0/p11 spiclk0/p12 #spiss0/tout5/cap5/p13 lv dd hv dd sin1/sdi1/p14 us_sdo0/p51 sout1/sdo1/p15 sclk1/spiclk1/p16 sda1/remi/p43 scl1/remo/p44 sdo2/p24(excl3) #bfr/#spiss2/p25 regen v ss v in v out p23(excl2)/sdi2 p22(excl1)/foutb p21/tout3/cap3 p20/tout2/cap2 hv dd osc4 osc3 v pp osc2 osc1 v ss p55/us_sck1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p54/us_sdo1 p34/remo/#spiss1 p33/remi/spiclk2 dclk/p35 test dsio/p36 dst2/p37 p31/#bfr/#adtrg p53/us_sdi1 lv dd p30/tout0/cap0 hv dd v ss p27/scl1 p26/sda1 p52/us_sck0 #reset lv dd sin0/tout6/cap6/p40 sout0/tout7/cap7/p41 sclk0/tout1/cap1/p42 sda0/p45(excl0) hv dd v ss scl0/p17 tout4/cap4/fouta/p32 n.c. av dd ain3/us_ssi1/p03 ain2/us_ssi0/p02 ain1/p01 ain0/p00 3.2.1 s1c17564 pin configur ation diag r am (tqfp13-64pin) figure 1. 1 o ver view 1-10 seiko epson corporation s1c17554/564 t echnical m anual chip (s1c17564) y x (0, 0) 3.137 mm 3.137 mm us_sdi0/p50 sdi0/p10 v ss sdo0/p11 spiclk0/p12 #spiss0/tout5/cap5/p13 lv dd hv dd sin1/sdi1/p14 us_sdo0/p51 sout1/sdo1/p15 sclk1/spiclk1/p16 sda1/remi/p43 scl1/remo/p44 hv dd sdo2/p24(excl3) #bfr/#spiss2/p25 v ss regen v ss v in v out lv dd p23(excl2)/sdi2 p22(excl1)/foutb p21/tout3/cap3 p20/tout2/cap2 hv dd osc4 v ss osc3 v pp osc2 osc1 v ss p55/us_sck1 p54/us_sdo1 p34/remo/#spiss1 p33/remi/spiclk2 dclk/p35 test dsio/p36 lv dd dst2/p37 p31/#bfr/#adtrg p53/us_sdi1 lv dd p30/tout0/cap0 hv dd hv dd v ss p27/scl1 p26/sda1 p52/us_sck0 #reset lv dd sin0/tout6/cap6/p40 sout0/tout7/cap7/p41 sclk0/tout1/cap1/p42 sda0/p45(excl0) hv dd v ss scl0/p17 tout4/cap4/fouta/p32 n.c. av dd av dd ain3/us_ssi1/p03 ain2/us_ssi0/p02 ain1/p01 ain0/p00 n.c. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 die no. cj554d0b0 3.2.2 s1c17564 p ad configur ation diag r am figure 1. chip siz e x = 3.137 mm, y = 3.137 mm p ad opening no . 1 to 18, 37 to 54: x = 122 m, y = 85 m no . 19 to 36, 55 to 72: x = 85 m, y = 122 m chip thic kness 400 m 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-11 3.2.1 s1c17564 p ad coordinates t ab le 1. no. name x (mm) y (mm) no. name x (mm) y (mm) 1 p50/us_sdi0 -1190 -1455.5 37 p55/us_sck1 1190 1455.5 2 p10/sdi0 -1050 -1455.5 38 v ss 1050 1455.5 3 v ss -910 -1455.5 39 osc1 910 1455.5 4 p11/sdo0 -770 -1455.5 40 osc2 770 1455.5 5 p12/spiclk0 -630 -1455.5 41 v pp 630 1455.5 6 p13/#spiss0/t out5/cap5 -490 -1455.5 42 osc3 490 1455.5 7 lv dd -350 -1455.5 43 v ss 350 1455.5 8 hv dd -210 -1455.5 44 osc4 210 1455.5 9 p14/sin1/sdi1 -70 -1455.5 45 hv dd 70 1455.5 10 p51/us_sdo0 70 -1455.5 46 p20/t out2/cap2 -70 1455.5 11 p15/sout1/sdo1 210 -1455 .5 47 p21/t out3/cap3 -210 1455.5 12 p16/sclk1/spiclk1 350 -1455.5 48 p22(excl1)/foutb -350 1455.5 13 p43/sd a1/remi 490 -1455.5 49 p23(excl2)/sdi2 -490 1455.5 14 p44/scl1/remo 630 -1455.5 50 lv dd -630 1455.5 15 hv dd 770 -1455.5 51 v out -770 1455.5 16 p24(excl3)/sdo2 910 -1455.5 52 v in -910 1455.5 17 p25/#bfr/spiss2 1050 -1455.5 53 v ss -1050 1455.5 18 v ss 1190 -1455.5 54 regen -1190 1455.5 19 p52/us_sck0 1455.5 -1190 55 #reset -1455.5 1190 20 p26/sd a1 1455.5 -1050 56 lv dd -1455.5 1050 21 p27/scl1 1455.5 -910 57 p40/sin0/t out6/cap6 -1455.5 910 22 v ss 1455.5 -770 58 p41/sout0/t out7/cap7 -1455.5 770 23 hv dd 1455.5 -630 59 p42/sclk0/t out1/cap1 -1455.5 630 24 hv dd 1455.5 -490 60 p45(excl0)/sd a0 -1455.5 490 25 p30/t out0/cap0 1455.5 -350 61 hv dd -1455.5 350 26 lv dd 1455.5 -210 62 v ss -1455.5 210 27 p53/us_sdi1 1455.5 -70 63 p17/scl0 -1455.5 70 28 p31/#bfr/adtrg 1455.5 70 64 p32/t out4/cap4/fout a -1455.5 -70 29 dst2/p37 1455.5 210 65 n.c . -1455.5 -210 30 lv dd 1455.5 350 66 av dd -1455.5 -350 31 dsio/p36 1455.5 490 67 av dd -1455.5 -490 32 test 1455.5 630 68 p03/ain3/us_ssi1 -1455.5 - 630 33 dclk/p35 1455.5 770 69 p02/ain2/us_ssi0 -1455.5 -770 34 p33/remi/spiclk2 1455.5 910 70 p01/ain1 -1455.5 -910 35 p34/remo/#spiss1 1455.5 1050 71 p00/ain0 -1455.5 -1050 36 p54/us_sdo1 1455.5 1190 72 n.c . -1455.5 -1190 1 o ver view 1-12 seiko epson corporation s1c17554/564 t echnical m anual pin descriptions 1.3.3 note: the pin names descr ibed in boldf ace type are def ault settings . 3.3.1 pin descr iptions t ab le 1. name i/o default status function a v ailab le ( )/una v ailab le (C) s1c17554 s1c17564 wcsp tqfp/ chip tqfp/ chip hv dd C C i/o po w er supply pins (1.65 to 5.5 v) lv dd C C core po w er supply pins (1.65 to 1.95 v) v ss C C gnd pins v pp C C flash prog r amming po w er supply pin (7 v) (lea v e the pin open dur ing nor mal oper ation.) av dd C C analog po w er supply pin (2.7 to 5.5 v) v in C C regulator input pin (2.0 to 5.5 v) C C v out C C regulator output pin (1.8 v) C C regen i i regulator enab le input pin C C osc3 i i osc3 oscillator input or e xter nal cloc k (l v dd le v el) input pin osc4 o o osc3 oscillator output pin osc1 i i osc1 oscillator input or e xter nal cloc k (l v dd le v el) input pin osc2 o o osc1 oscillator output pin #reset i i(pull-up) initial reset input pin test i i(pull-do wn) t est input pin (connect to v ss f or nor mal oper ation.) p00 i/o i(pull-up) i/o por t pin ain0 i a/d con v er ter ch.0 analog signal input pin p01 i/o i(pull-up) i/o por t pin ain1 i a/d con v er ter ch.1 analog signal input pin p02 i/o i(pull-up) i/o por t pin ain2 i a/d con v er ter ch.2 analog signal input pin us_ssi0 i/o u s i c h . 0 s l a v e s e l e c t s i g n a l i n p u t o r d a t a i n p u t / o u t p u t p i n ( s 1 c 1 7 5 6 4 ) C C p03 i/o i(pull-up) i/o por t pin ain3 i a/d con v er ter ch.3 analog signal input pin us_ssi1 i/o u s i c h . 1 s l a v e s e l e c t s i g n a l i n p u t o r d a t a i n p u t / o u t p u t p i n ( s 1 c 1 7 5 6 4 ) C C p10 i/o i(pull-up) i/o por t pin sdi0 i spi ch.0 data input pin p11 i/o i(pull-up) i/o por t pin sdo0 o spi ch.0 data output pin p12 i/o i(pull-up) i/o por t pin spiclk0 i/o spi ch.0 cloc k input/output pin p13 i/o i(pull-up) i/o por t pin #spiss0 i spi ch.0 sla v e select signal input pin t out5 o t16a ch.2 t out b signal output pin cap5 i t16a ch.2 capture b tr igger signal input pin p14 i/o i(pull-up) i/o por t pin sin1 i u ar t ch.1 data input pin sdi1 i spi ch.1 data input pin p15 i/o i(pull-up) i/o por t pin sout1 o u ar t ch.1 data output pin sdo1 o spi ch.1 data output pin p16 i/o i(pull-up) i/o por t pin sclk1 i u ar t ch.1 e xter nal cloc k input pin spiclk1 i/o spi ch.1 cloc k input/output pin p17 i/o i(pull-up) i/o por t pin scl0 i/o i 2 c master scl input/output pin p20 i/o i(pull-up) i/o por t pin t out2 o t16a ch.1 t out a signal output pin cap2 i t16a ch.1 capture a tr igger signal input pin p21 i/o i(pull-up) i/o por t pin t out3 o t16a ch.1 t out b signal output pin cap3 i t16a ch.1 capture b tr igger signal input pin p22 (excl1) i/o i(pull-up) i/o por t pin (t16a ch.1 e xter nal cloc k input pin) foutb o cloc k output pin p23 (excl2) i/o i(pull-up) i/o por t pin (t16a ch.2 e xter nal cloc k input pin) sdi2 i spi ch.2 data input pin p24 (excl3) i/o i(pull-up) i/o por t pin (t16a ch.3 e xter nal cloc k input pin) sdo2 o spi ch.2 data output pin 1 o ver view s1c17554/564 t echnical m anual seiko epson corporation 1-13 name i/o default status function a v ailab le ( )/una v ailab le (C) s1c17554 s1c17564 wcsp tqfp/ chip tqfp/ chip p25 i/o i(pull-up) i/o por t pin #bfr i i 2 c sla v e b us free request input pin #spiss2 i spi ch.2 sla v e select signal input pin p26 i/o i(pull-up) i/o por t pin sd a1 i/o i 2 c sla v e data input/output pin p27 i/o i(pull-up) i/o por t pin scl1 i/o i 2 c sla v e scl input/output pin p30 i/o i(pull-up) i/o por t pin t out0 o t16a ch.0 t out a signal output pin cap0 i t16a ch.0 capture a tr igger signal input pin p31 i/o i(pull-up) i/o por t pin #bfr i i 2 c sla v e b us free request input pin #adtrg i a/d con v er ter e xter nal tr igger input pin p32 i/o i(pull-up) i/o por t pin t out4 o t16a ch.2 t out a signal output pin cap4 i t16a ch.2 capture a tr igger signal input pin fout a o cloc k output pin p33 i/o i(pull-up) i/o por t pin remi i remc input pin spiclk2 i/o spi ch.2 cloc k input/output pin p34 i/o i(pull-up) i/o por t pin remo o remc output pin #spiss1 i spi ch.1 sla v e select signal input pin dclk o o(h) on-chip deb ugger cloc k output pin p35 i/o i/o por t pin dsio i/o i(pull-up) on-chip deb ugger data input/output pin p36 i/o i/o por t pin dst2 o o(l) on-chip deb ugger status output pin p37 i/o i/o por t pin p40 i/o i(pull-up) i/o por t pin sin0 i u ar t ch.0 data input pin t out6 o t16a ch.3 t out a signal output pin cap6 i t16a ch.3 capture a tr igger signal input pin p41 i/o i(pull-up) i/o por t pin sout0 o u ar t ch.0 data output pin t out7 o t16a ch.3 t out b signal output pin cap7 i t16a ch.3 capture b tr igger signal input pin p42 i/o i(pull-up) i/o por t pin sclk0 i u ar t ch.0 e xter nal cloc k input pin t out1 o t16a ch.0 t out b signal output pin cap1 i t16a ch.0 capture b tr igger signal input pin p43 i/o i(pull-up) i/o por t pin sd a1 i/o i 2 c sla v e data input/output pin remi i remc input pin p44 i/o i(pull-up) i/o por t pin scl1 i/o i 2 c sla v e scl input/output pin remo o remc output pin p45 (excl0) i/o i(pull-up) i/o por t pin (t16a ch.0 e xter nal cloc k input pin) sd a0 i/o i 2 c master data input/output pin p50 i/o i(pull-up) i/o por t pin C us_sdi0 i/o usi ch.0 data input/output pin (s1c17564) C p51 i/o i(pull-up) i/o por t pin C us_sdo0 o usi ch.0 data output pin (s1c17564) C p52 i/o i(pull-up) i/o por t pin C us_sck0 i/o usi ch.0 cloc k input/output pin (s1c17564) C p53 i/o i(pull-up) i/o por t pin C us_sdi1 i/o usi ch.1 data input/output pin (s1c17564) C p54 i/o i(pull-up) i/o por t pin C us_sdo1 o usi ch.1 data output pin (s1c17564) C p55 i/o i(pull-up) i/o por t pin C us_sck1 i/o usi ch.1 cloc k input/output pin (s1c17564) C 2 cpu s1c17554/564 t echnical m anual seiko epson corporation 2-1 cpu 2 the s1c17554/564 contains the s1c17 core as its core processor . the s1c17 core is a seik o epson original 16-bit risc-type processor . it features lo w po wer consumption, high-speed operation, lar ge address space, main instructions e x ecutable in one clock c ycle, and a small sized design. the s1c17 core is suitable for embedded applications such as controllers and sequencers for which an eight-bi t cpu is commonly used. f or details of the s1c17 core, refer to the s1c17 f amily s1c17 core manual. features of the s1c17 core 2.1 pr ocessor type ? seik o epson original 16-bit risc processor ? 0.35C0.15 m lo w po wer cmos process technology instruction set ? code length: 16-bit f ix ed length ? number of instructions: 111 basic instructions (184 including v ariations) ? ex ecution c ycle: main instructions e x ecuted in one c ycle ? extended immediate instructions: immediate e xtended up to 24 bits ? compact and f ast instruction set optimized for de v elopment in c language register set ? eight 24-bit general-purpose re gisters ? t w o 24-bit special re gisters ? one 8-bit special re gister memor y space and b us ? up to 16m bytes of memory space (24-bit address) ? harv ard architecture using separated instruction b us (16 b its) and data b us (32 bits) interrupts ? reset, nmi, and 32 e xternal interrupts supported ? address misaligned interrupt ? deb ug interrupt ? direct branching from v ector table to interrupt handler routine ? programmable softw are interrupts with a v ector number specif ied (all v ector numbers specif iable) p o wer sa ving ? hal t (halt instruction) ? sleep (slp instruction) copr ocessor interface ? 16-bit 16-bit multipl ier ? 16-bit 16-bit di vider ? 16-bit 16-bit + 32-bit multiply and accumulation unit 2 cpu 2-2 seiko epson corporation s1c17554/564 t echnical m anual cpu register s 2.2 the s1c17 core contains eight general-purpose re gisters and three special re gisters. r4 r5 r6 r7 r3 r2 r1 r0 bit 23 bit 0 general-purpose registers pc bit 23 7 6 5 4 3 2 1 0 bit 0 psr sp special registers il[2:0] 765 ie 4 c 3 v 2 z 1 n 0 2.1 registers figure 2. instruction set 2.3 the s1c17 core instruction codes are all f ix ed to 16 bits in length which, combined with pipelined processing, al- lo ws most important instructions to be e x ecuted in one c ycle. f or details, refer to the s1c17 f amily s1c17 core manual. 3.1 list of s1c17 core instr uctions t ab le 2. classification mnemonic function data tr ansf er ld.b %rd,%rs gener al-pur pose register (b yte) gener al-pur pose register (sign-e xtended) %rd,[%rb] memor y (b yte) gener al-pur pose register (sign-e xtended) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (b yte) gener al-pur pose register (sign-e xtended) %rd,[imm7] memor y (b yte) gener al-pur pose register (sign-e xtended) [ %rb],%rs gener al-pur pose register (b yte) memor y memor y address post-increment, post-decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (b yte) stac k [imm7],%rs gener al-pur pose register (b yte) memor y ld.ub %rd,%rs gener al-pur pose register (b yte) gener al-pur pose register (z ero-e xtended) %rd,[%rb] memor y (b yte) gener al-pur pose register (z ero-e xtended) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (b yte) gener al-pur pose register (z ero-e xtended) %rd,[imm7] memor y (b yte) gener al-pur pose register (z ero-e xtended) ld %rd,%rs gener al-pur pose register (16 bits) gener al-pur pose register %rd,sign7 immediate gener al-pur pose register (sign-e xtended) %rd,[%rb] memor y (16 bits) gener al-pur pose register memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (16 bits) gener al-pur pose register %rd,[imm7] memor y (16 bits) gener al-pur pose register [%rb],%rs gener al-pur pose register (16 bits) memor y memor y address post-increment, post-decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (16 bits) stac k [imm7],%rs gener al-pur pose register (16 bits) memor y ld.a %rd,%rs gener al-p ur pose register (24 bits) gener al-pur pose register %rd,imm7 immediate gener al-pur pose register (z ero-e xtended) 2 cpu s1c17554/564 t echnical m anual seiko epson corporation 2-3 classification mnemonic function data tr ansf er ld.a %rd,[%rb] memor y (32 bits) gener al-pur pose register (*1) memor y address post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] stac k (32 bits) gener al-pur pose register (*1) %rd,[imm7] memor y (32 bits) gener al-pur pose register (*1) [%rb],%rs gener al-pur pose register (32 bits , z ero-e xtended) memor y (*1) memor y address post-increment, post -decrement, and pre-decrement functions can be used. [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs gener al-pur pose register (32 bits , z ero-e xtended) stac k (*1) [imm7],%rs gener al-pur pose register (32 bits , z ero-e xtended) memor y (*1) %rd,%sp sp gener al-pur pose register %rd,%pc pc gener al-pur pose register %rd,[%sp] stac k (32 bits) gener al-pur pose register (*1) stac k pointer post-increment, post-decrement, and pre-decrement functions can be used. %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp] [%sp],%rs gener al-pur pose register (32 bits , z ero-e xtended) stac k (*1) stac k pointer post-increment, post-decrement, and pre-decrement functions can be used. [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs gener al-pur pose register (24 bits) sp %sp,imm7 immediate sp integer ar ithmetic oper ation add %rd,%rs 16-bit addition betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). add/c add/nc add %rd,imm7 16-bit addition of g ener al-pur pose register and immediate add.a %rd,%rs 24-bit addition betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). add.a/c add.a/nc add.a %sp,%rs 24-bit addition of sp and gener al-pur pose register %rd,imm7 24-bit addition of gener al-pur pose register and immediate %sp,imm7 24-bit addition of sp and immediate adc %rd,%rs 16-bit addition with carr y betw een gener al-pur pose registers suppor ts condit ional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). adc/c adc/nc adc %rd,imm7 16-bit addition of gener al-pur pose register and immediate with carr y sub %rd,%rs 16-bit subtr action betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sub/c sub/nc sub %rd,imm7 16-bit subtr action of gener al-pur pose register and immediate sub.a %rd,%rs 24-bit subtr action betw een gener al-pur pose registers supp or ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sub.a/c sub.a/nc sub.a %sp,%rs 24-bit subtr action of sp and gener al-pur pose register %rd,imm7 24-bit subtr action of gener al-pur pose register and immediate %sp,imm7 24-bit subtr action of sp and immediate sbc %rd,%rs 16-bit subtr action with carr y betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). sbc/c sbc/nc sbc %rd,imm7 16-bit subtr action of gener al-pur pose register and immediate with carr y cmp %rd,%rs 16-bit compar ison betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmp/c cmp/nc cmp %rd,sign7 16-bit compar ison of gener al-pur pose register and immediate cmp.a %rd,%rs 24-bit compar ison betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmp.a/c cmp.a/nc cmp.a %rd,imm7 2 4-bit compar ison of gener al-pur pose register and immediate cmc %rd,%rs 16-bit compar ison with carr y betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). cmc/c cmc/nc cmc %rd,sign7 16-bit compar ison of gener al-pur pose register and immediate with carr y 2 cpu 2-4 seiko epson corporation s1c17554/564 t echnical m anual classification mnemonic function logical oper ation and %rd,%rs logical and betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). and/c and/nc and %rd,sign7 logical and of gener al-pur pose register and immediate or %rd,%rs logical or betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). or/c or/nc or %rd,sign7 logical or of gener al-pur pose r egister and immediate xor %rd,%rs exclusiv e or betw een gener al-pur pose registers suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). xor/c xor/nc xor %rd,sign7 exclusiv e or of gener al-pur pose register and immediate not %rd,%rs logical in v ersion betw een gener al-pur pose registers (1's complement) suppor ts conditional e x ecution (/c: e x ecuted if c = 1, /nc: e x ecuted if c = 0). not/c not/nc not %rd,sign7 logical in v ersion of gener al-pur pose register and immediate (1's complement) shift and s w ap sr %rd,%rs logical shift to the r ight with the n umber of bits speci?ed b y the register %rd,imm7 logical shift to the r ight with the n umber of bits speci?ed b y immediate sa %rd,%rs ar ithmetic shift to the r ight with the n umber of bits speci?ed b y the register %rd,imm7 ar ithmetic shift to the r ight with the n umber of bits speci?ed b y immediate sl %rd,%rs logical shift to the lef t with the n umber of bits speci?ed b y the register %rd,imm7 logical shift to the left with the n umber of bits speci?ed b y immediate swap %rd,%rs byte wise s w ap on b yte boundar y in 16 bits i m m e d i a t e e x t e n s i o n ext imm13 extend oper and in the f ollo wing instr uction con v ersion cv.ab %rd,%rs con v er ts signed 8-bit data into 24 bits cv.as %rd,%rs con v er ts signed 16-bit data into 24 bits cv.al %rd,%rs con v er ts 32-bit data into 24 bits cv.la %rd,%rs con v er ts 24-bit data into 3 2 bits cv.ls %rd,%rs con v er ts 16-bit data into 32 bits br anch jpr jpr.d sign10 pc relativ e jump dela y ed br anching possib le %rb jpa jpa.d imm7 absolute jump dela y ed br anching possib le %rb jrgt jrgt.d sign7 pc relativ e conditional jump br anch condition: !z & !(n ^ v) dela y ed br anching possib le jrge jrge.d sign7 pc relativ e conditional jump br anch condition: !(n ^ v) dela y ed br anching possib le jrlt jrlt.d sign7 pc relativ e conditional jump br anch condition: n ^ v dela y ed br anching possib le jrle jrle.d sign7 pc re lativ e conditional jump br anch condition: z | n ^ v dela y ed br anching possib le jrugt jrugt.d sign7 pc relativ e conditional jump br anch condition: !z & !c dela y ed br anching possib le jruge jruge.d sign7 pc relativ e conditional jump br anch condition: !c dela y ed br anching possib le jrult jrult.d sign7 pc relativ e conditional jump br anch condition: c dela y ed br anching possib le jrule jrule.d sign7 pc relativ e conditional jump br anch condition: z | c dela y ed br anching possib le jreq jreq.d sign7 p c relativ e conditional jump br anch condition: z dela y ed br anching possib le jrne jrne.d sign7 pc relativ e conditional jump br anch condition: !z dela y ed br anching possib le call call.d sign10 pc relativ e subroutine call dela y ed call possib le %rb calla calla.d imm7 absolute subroutine call dela y ed call possib le %rb ret ret.d retur n from subroutine dela y ed retur n possib le int imm5 softw are interr upt intl imm5,imm3 softw are interr upt with interr upt le v el setting reti reti.d retur n from interr upt handli ng dela y ed call possib le brk deb ug interr upt 2 cpu s1c17554/564 t echnical m anual seiko epson corporation 2-5 classification mnemonic function br anch retd retur n from deb ug processing system control nop no oper ation halt hal t mode slp sleep mode ei enab le interr upts di disab le interr upts coprocessor control ld.cw %rd,%rs t r ansf er data to coprocessor %rd,imm7 ld.ca %rd,%rs t r ansf er data to coprocessor and get results and ?ag statuses %rd,imm7 ld.cf %rd,%rs t r ansf er data to coprocessor and get ?ag statuses %rd,imm7 *1 the ld.a instr uction accesses memor ies in 32-bit length. dur ing data tr a nsf er from a register to a memor y , the 32-bit data in which the eight high-order bits are set to 0 is wr itten to the memor y . dur ing reading from a memor y , the eight high-order bits of the read data are ignored. the symbols in the abo v e table each ha v e the meanings specif ied belo w . 3.2 symbol meanings t ab le 2. symbol description %rs gener al-pur pose register , source %rd gener al-pur pose register , destination [%rb] memor y addressed b y gener al-pur pose register [%rb]+ memor y addressed b y gener al-pur pose register with address post-incremented [%rb]- memor y addressed b y gener al-pur pose register with address post-decremented -[%rb] memor y addressed b y gener al-pur pose register with address pre-decremented %sp stac k pointer [%sp],[%sp+imm7] stac k [%sp]+ stac k with a ddress post-incremented [%sp]- stac k with address post-decremented -[%sp] stac k with address pre-decremented imm3,imm5,imm7,imm13 unsigned immediate (n umer als indicating bit length) sign7,sign10 signed immediate (n umer als indicating bit length) reading psr 2.4 the s1c17554/564 includes the misc_psr re gister for reading the contents of the psr (processor status re gis- ter) in the s1c17 core. reading the contents of this re gister mak es it p ossible to check the contents of the psr us- ing the application softw are. note that data cannot be written to the psr. psr register (misc_psr) register name ad dress bit name function setting init. r/w remarks psr register (misc_psr) 0x532c (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C5 psril[2:0] psr interr upt le v el (il) bits 0x0 to 0x7 0x0 r d4 psrie psr interr upt enab le (ie) bit 1 1 (enab le) 0 0 (disab le) 0 r d3 psrc psr carr y (c) flag 1 1 (set) 0 0 (cleared) 0 r d2 psrv psr o v erflo w (v) flag 1 1 (set) 0 0 (cleared) 0 r d1 psrz psr z ero (z) flag 1 1 (set) 0 0 (cleared) 0 r d0 psrn psr negativ e (n) flag 1 1 (set) 0 0 (cleared) 0 r d[15:8] reserved d[7:5] psril[2:0]: psr interrupt level (il) bits the v alue of the psr il (interrupt le v el) bits can be read out. (def ault: 0x0) d4 psrie: psr interrupt enable (ie) bit the v alue of the psr ie (interrupt enable) bit can be read out. 1 (r): 1 (interrupt enabled) 0 (r): 0 (interrupt disabled) (def ault) 2 cpu 2-6 seiko epson corporation s1c17554/564 t echnical m anual d3 psrc: psr carry (c) flag bit the v alue of the psr c (carry) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d2 psrv: psr overflow (v) flag bit the v alue of the psr v (o v erflo w) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d1 psrz: psr zero (z) flag bit the v alue of the psr z (zero) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) d0 psrn: psr negative (n) flag bit the v alue of the psr n (ne g ati v e) flag can be read out. 1 (r): 1 0 (r): 0 (def ault) pr ocessor inf ormation 2.5 the s1c17554/564 has the idir re gister sh o wn belo w that allo ws the application softw are to identify cpu core type. pr ocessor id register (idir) register name ad dress bit name function setting init. r/w remarks processor id register (idir) 0xffff84 (8 bits) d7C0 idir[7:0] processor id 0x10: s1c17 core 0x10 0x10 r this is a read-only re gister that contains the id code to represent a processor model. the s1c17 core s id code is 0x10. 3 memor y map , b us contr ol s1c17554/564 t echnical m anual seiko epson corporation 3-1 memory map, bus contr ol 3 figure 3.1 sho ws the s1c17554/564 memory map. flash area (128k bytes) (device size: 16 bits) vector table internal peripheral area 2 (4k bytes) internal peripheral area 1 (1k bytes) reserved for core i/o area (1k bytes) reserved reserved reserved 0xff ffff 0xff fc00 0xff fbff 0x02 8000 0x02 7fff 0x00 8000 0x00 7fff 0x00 6000 0x00 5fff 0x00 5000 0x00 4fff 0x00 4400 0x00 43ff 0x00 4000 0x00 3fff 0x00 3fc0 0x00 0000 0x43c0C0x43ff 0x4380C0x43bf 0x4360C0x437f 0x4340C0x435f 0x4320C0x433f 0x42e0C0x431f 0x4280C0x42df 0x4220C0x427f 0x4200C0x421f 0x4140C0x41ff 0x4100C0x413f 0x4040C0x40ff 0x4020C0x403f 0x4000C0x401f reserved spi ch.1C2 i 2 c slave i 2 c master spi ch.0 interrupt controller fine mode 16-bit timer ch.1 16-bit timer ch.0C2 fine mode 16-bit timer ch.0 reserved uart ch.0C1 reserved misc registers reserved debug ram area (64 bytes) internal ram area (16k bytes) (device size: 32 bits) 0x5500C0x5fff 0x5480C0x54ff 0x5400C0x547f 0x53a0C0x53ff 0x5380C0x539f 0x5360C0x537f 0x5340C0x535f 0x5320C0x533f 0x52c0C0x531f 0x52a0C0x52bf 0x5280C0x529f 0x5200C0x527f 0x5140C0x51ff 0x5120C0x513f 0x5100C0x511f 0x50c0C0x50ff 0x50a0C0x50bf 0x5060C0x509f 0x5040C0x505f 0x5020C0x503f 0x5000C0x501f reserved flash controller 16-bit pwm timer ch.0C3 reserved a/d converter reserved ir remote controller misc registers reserved port mux reserved p ports reserved power generator (s1c17564) reserved usi ch.0C1 (s1c17564) reserved clock generator watchdog timer stopwatch timer clock timer C (16 bits) (16 bits) C (16 bits) C (16 bits) (16 bits) C (8 bits) C (8 bits) C (8 bits) C (8 bits) C (8 bits) (8 bits) (8 bits) (8 bits) C (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) C (8 bits) C (8 bits) C peripheral function (device size) 1 s1c17554/564 memor y map figure 3. bus cyc le 3.1 the cpu uses the system clock for b us access operations. f or more information on the system clock, see system clock switching in the clock generator (clg) chapter . note that the flash area and other areas require dif ferent number of system clocks for one b us c ycle as follo ws: instruction/data read from areas other than the flash area: one system clock per one b us c ycle instruction read from the flash area: one to three system clocks or equi v alent per one b us c ycle data read from the flash area: t w o to four system clocks per one b us c ycle furthermore, the number of b us accesses depends on the cpu instruction (access size) and de vice size. 3 memor y map , b us contr ol 3-2 seiko epson corporation s1c17554/564 t echnical m anual 1.1 number of bus accesses t ab le 3. de vice siz e cpu access siz e number of b us accesses 8 bits 8 bits 1 16 bits 2 32 bits* 4 16 bits 8 bits 1 16 bits 1 32 bits* 2 32 bits 8 bits 1 16 bits 1 32 bits* 1 * handling the eight high-order bits dur ing 32-bit accesses the size of the s1c17 core general-purpose re gisters is 24 bits. during writing, the eight high-order bits are written as 0. during reading from a memory , the eight high-order bits are ignored. ho we v er , the stack operation in an interrupt handling reads/writes 32-bit data that consists of the psr v alue as the high-order 8 bits and the return address as the lo w order 24 bits. f or more information, refer to the s1c17 core manual. restrictions on access siz e 3.1.1 the peripheral modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. ho we v er , reading for an unnec- essary re gis ter may change the peripheral module status and it may cause a problem. therefore, use the appropriate instructions according to the de vice size. restrictions on instruction ex ecution cyc les 3.1.2 an instruction fetch and a data access are not performed simultaneously under one of the conditions listed belo w . this prolongs the instruction fetch c ycle for the number of data area b us c ycles. ? when th e s1c17554/564 e x ecutes the instruction stored in the flash area and accesses data in the flash area ? when the s1c17554/564 e x ecutes the instruction stored in the internal ram area and accesses data in the inter - nal ram area flash area 3.2 embed ded flash memor y 3.2.1 the 128k-byte area from address 0x8000 to address 0x27f f f contains a flash memory (4k bytes 32 sectors) for storing application pro grams and data. address 0x8000 is def ined as the v ector table base address, therefore a v ec- tor table (see v ector t able in the interrupt controller (itc) chapter) must be placed from the be ginning of the area. the v ector table base address can be modif ied with the misc_ttbrl/misc_ttbrh re gisters. flash pr ogramming 3.2.2 the s1c17554/564 supports on-board programming of the flash memory , it ma k es it possible to program the flash memory with the application programs/data by using the deb ugger through an icdmini. the flash memory sup- ports sector erase method. f or the flash programming using the deb ugger , see the s5u1c17001c manual included in the s1c17 f amily c compiler p ackage. f or the self-programming controlled by the user program, see the self-programming (fls) application notes for the s1c17554/564. 3 memor y map , b us contr ol s1c17554/564 t echnical m anual seiko epson corporation 3-3 pr otect bits 3.2.3 in order to protect the memory contents, the flash memory pro vides tw o protection features, write protection and data read protection, that can be conf igured for e v ery 16k-byte areas. the write protection disables writing data to the conf igured area and erasing the sectors (e xcept the sector that includes the protect bits). the data-read protec- tion disables reading data from th e conf igured area (the read v alue is al w ays 0x0000). ho we v er , it does not disable the instruction fetch operation by the cpu. the flash memory pro vides the protect bits listed belo w . program the protect bit corresponding to the area to be protected to 0. the protection can only be disabled using the deb ugger . flash pr otect bits ad dress bit function setting init. r/w remarks 0x27ffc (16 bits) d15C8 reser v ed C C C d7 reser v ed 1 1 r/w alw a ys set to 1. d6 flash wr ite-protect bit f or 0x20000C0x23fff 1 wr itab le 0 protected 1 r/w d5 flash wr ite-protect bit f or 0x1c000C0x1ffff 1 wr itab le 0 protected 1 r/w d4 flash wr ite-protect bit f or 0x18000C0x1bfff 1 wr itab le 0 protected 1 r/w d3 flash wr ite-protect bit f or 0x14000C0x17fff 1 wr itab le 0 protected 1 r/w d2 flash wr ite-protect bit f or 0x10000C0x13fff 1 wr itab le 0 protected 1 r/w d1 f lash wr ite-protect bit f or 0xc000C0xffff 1 wr itab le 0 protected 1 r/w d0 flash wr ite-protect bit f or 0x8000C0xbfff 1 wr itab le 0 protected 1 r/w 0x27ffe (16 bits) d15C8 reser v ed C C C d7 flash data-read-protect bit f or 0x24000C0x27fff 1 readab le 0 protected 1 r/w d6 flash data-read-protect bit f or 0x20000C0x23fff 1 readab le 0 protected 1 r/w d5 flash data-read-protect bit f or 0x1c000C0x1ffff 1 readab le 0 protected 1 r/w d4 flash data-read-protect bit f or 0x18000C0x1bfff 1 readab le 0 protected 1 r/w d3 flash data-read-protect bit f or 0x14000C0x17fff 1 readab le 0 protected 1 r/w d2 flash data-read-protect bit f or 0x10000C0x13fff 1 readab le 0 protected 1 r/w d1 flash data-read-protect bit f or 0xc000C0xffff 1 readab le 0 protected 1 r/w d0 reser v ed 1 1 r/w alw a ys set to 1. notes: ? the protection can be disab led b y er asing the sector that includes the protect bits . ? be sure not to locat e the area with data-read protection into the .data and .rodata sections . ? be sure to set d0 of address 0x27ff e to 1. if it is set to 0, the prog r am cannot be booted. flash memor y read w ait cyc le setting 3.2.4 in order to read data from the flash memory properly , set the appropriate number of w ait c ycles according to the system clock frequenc y using the rd w ait[1:0]/flashc_w ait re gister . flashc read wait control register (flashc_wait) register name ad dress bit name function setting init. r/w remarks flashc read wait control register (flashc_ wait) 0x54b0 (16 bits) d15C2 C reser v ed C C C 0 when being read. d1C0 rdwait [1:0] flash read w ait cycle rd w ait[1:0] w ait 0x3 r/w 0x3 0x2 0x1 0x0 2 w ait 1 w ait no w ait reser v ed d[1:0] rdwait[1:0]: flash read wait cycle bits sets the number of w ait c ycles for reading from the flash memory . one w ait insertion prolongs b us c ycles by one system clock c ycle. f or the conf igurable w ait c ycles, see the electrical characteristics chapter . bus c ycle when no w ait is selected instruction read: 1 b us c ycle = 1 system clock c ycle or equi v alent data read: 1 b us c ycle = 2 system clock c ycles note: be sure to a v oid setting a n umber of w ait cycles that e xceeds the maxim um allo w ab le system cloc k frequency , as it ma y cause a malfunction. 3 memor y map , b us contr ol 3-4 seiko epson corporation s1c17554/564 t echnical m anual internal ram area 3.3 embed ded ram 3.3.1 the s1c17554/564 contains a ram in the 16k-byte area from address 0x0 to address 0x3f f f. the ram allo ws high-speed e x ecution of the instruction codes copied into it as well as storing v ariables and other data. note: t h e 64- b y t e a r e a a t t h e e n d o f t h e r a m (0x3f c0C0x3f f f ) i s r e s e r v e d f o r t h e o n - c h i p d e b u g g e r . when using the deb ug functions under application de v el opment, do not access this area from the application prog r am. this area can be used f or applications of mass-produced de vices that do not need deb ugging. the s1c17554/564 enables the ram size used to apply restrictions to 16kb, 12kb, 8kb, 4kb, 2kb, 1kb, or 512b. f or e xample, when using the s1c17554/564 to de v elop an application for a b uilt-in r om model, you can set the ram size to match that of th e tar get model, pre v enting creating programs that seek to access areas outside the ram areas of the tar get product. the ram size is selected using iramsz[2:0]/misc_iramsz re gister . iram size register (misc_iramsz) register name ad dress bit name function setting init. r/w remarks iram size register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x6 (= 16kb) 0x6 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x6 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 16kb 512b 1kb 2kb 4kb 8kb 12kb d[6:4] iramactsz[2:0]: iram actual size bits indicates the actual internal ram size embedded. (def ault: 0x6) d[2:0] iramsz[2:0]: iram size select bits selects the internal ram size used. 3.1. 1 selecting inter nal ram siz e t ab le 3. iramsz[2:0] internal ram siz e 0x7 reser v ed 0x6 16kb 0x5 512b 0x4 1kb 0x3 2kb 0x2 4kb 0x1 8kb 0x0 12kb (def ault: 0x6) note: the misc_iramsz register is wr ite-protected. the wr ite-protection m ust be o v err idden b y wr iting 0x96 to the misc_pr o t register . note that the misc_pr o t register should nor mally be set to a v a l u e o t h e r t h a n 0 x 9 6 , e x c e p t w h e n w r i t i n g t o t h e m i s c _ i r a m s z r e g i s t e r . u n n e c e s s a r y p r o g r a m s ma y result in sys tem malfunctions . 3 memor y map , b us contr ol s1c17554/564 t echnical m anual seiko epson corporation 3-5 internal p eripheral area 3.4 the i/o and control re gisters for the internal peripheral modules are located in the 1k-byte area be ginning with ad- dress 0x4000 and the 4k-byte area be ginning with address 0x5000. f or details of each control re gister , see the i/o re gister list in appendix or description for each peripheral module. internal p eripheral area 1 (0x4000C) 3.4.1 the internal peripheral area 1 be ginning with address 0x4000 contains the i/o memory for the peripheral functions listed belo w . ? misc re gister (misc, 8-bit de vice) ? u ar t (u ar t , 8-bit de vice) ? fine mode 16-bit timers (t16f , 16-bit de vice) ? 16-bit timers (t16, 16-bit de vice) ? interrupt controller (itc, 16-bit de vice) ? spi (spi, 16-bit de vice) ? i 2 c master (i2cm, 16-bit de vice) ? i 2 c sla v e (i2cs, 16-bit de vice) internal p eripheral a rea 2 (0x5000C) 3.4.2 the internal peripheral area 2 be ginning with address 0x5000 contains the i/o memory for the peripheral functions listed belo w . ? clock timer (ct , 8-bit de vice) ? stopw atch timer (swt , 8-bit de vice) ? w atchdog timer (wdt , 8-bit de vice) ? clock generator (clg, 8-bit de vice) ? uni v ersal serial interf ace (usi, 8-bit de vice) a v ailable only in s1c17564 ? po wer generator (vd1, 8-bit de vice) a v ailable only in s1c17564 ? i/o port & port mux (p , 8-bit de vice) ? misc re gister (misc, 16-bit de vice) ? ir remote controller (remc, 16-bit de vice) ? a/d con v erter (adc10, 16-bit de vice) ? 16-bit pwm timers (t16a, 16-bit de vice) ? flash controller (flashc, 16-bit de vice) s1c17 core i/o area 3.5 the 1k-byte area from address 0xf f fc00 to address 0xf f f f f f is the i/o area for the cpu core in which the i/o re gis- ters listed in the table belo w are located. 5.1 i/o map (s1c17 core i/o area) t ab le 3. p eripheral ad dress register name function s1c17 core i/o 0xffff84 idir processor id register indicates the processor id . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register deb ug control 0xffffb4 ibar1 instr uction break address register 1 instr uction break address #1 setting 0xffffb8 ibar2 instr uction break address register 2 instr uction break address #2 settin g 0xffffbc ibar3 instr uction break address register 3 instr uction break address #3 setting 0xffffd0 ibar4 instr uction break address register 4 instr uction break address #4 setting s e e p r o c e s s o r i n f o r m a t i o n i n t h e c p u c h a p t e r f o r m o r e i n f o r m a t i o n o n i d i r . s e e t h e o n - c h i p d e b u g g e r (dbg) chapter for more information on other re gisters. this area includes the s1c17 core re gisters, in addition to those des cribed abo v e. f or more information on these re gisters, refer to the s1c17 core manual. 4 po wer suppl y s1c17554/564 t echnical m anual seiko epson corporation 4-1 p o wer supply 4 core p o wer suppl y v olta g e (l v 4.1 dd ) the cpu core and internal logic circuits operate with a v oltage supplied between the l v dd and v ss pins. supply a v oltage within the range sho wn belo w to the l v dd pins with the v ss pins as the gnd le v el. l v dd = 1.65 v to 1.95 v (v ss = gnd) the s1c17554/564 pro vides tw o or more l v dd and v ss pins. do not lea v e an y po wer supply pins open and be sure to connect them to + po wer source and gnd. the s1c17564 is able to operate with a 2.0 v or higher single po wer supply (e.g., 3.3 v or 5 v). in this case, the core po wer v oltage can be generated using the embedded 1.8 v re gulator and supplied as the l v dd v oltage. i/o p o wer suppl y v olta g e (hv 4.2 dd ) the hv dd v oltage is used for interf acing with e xternal i/o signals. supply a v oltage within the range sho wn belo w to the hv dd pins with the v ss pins as the gnd le v el. hv dd = 1.65 v to 5.50 v (v ss = gnd) the s1c17554/564 pro vides tw o or more hv dd pins. do not lea v e an y po wer supply pins open and be sure to con- nect them to the po wer source. note: when an e xter nal cloc k is input to the osc3 or osc1 pin, the cloc k signal le v el m ust be l v dd . analog p o wer suppl y v olta g e (a v 4.3 dd ) the analog po wer supply pin (a v dd ) is pro vided separately from the hv dd pin in order that the digital circuits do n o t a f f e c t t h e a n a l o g c i r c u i t s ( a / d c o n v e r t e r ) . s u p p l y a v o l t a g e w i t h i n t h e r a n g e s h o w n b e l o w t o t h e a v d d p i n s w i t h the v ss pins as the gnd le v el. a v dd = 2.7 v to 5.5 v (v ss = gnd) note: be sure to supply the same v oltage as hv dd to the a v dd pin when the analog circuit is not used. noise on the analog po wer lines decre ase the a/d con v erting precision, so use a stabilized po wer supply and mak e the board pattern with consideration gi v en to that. flash pr ogramming p o wer suppl y v olta g e (v 4.4 pp ) the v pp v oltage is used for erasing/programming the embedded flash memory . supply a v oltage sho wn belo w to the v pp pin with the v ss pins as the gnd le v el to program the flash memory . v pp = 7 v (v ss = gnd) note: lea v e the v pp pin open dur ing nor mal oper ation. 4 po wer suppl y 4-2 seiko epson corporation s1c17554/564 t echnical m anual embed ded regulator (s1c17564) 4.5 the s1c17564 includes a v oltage re gulator that allo ws use of a 2 v or higher single po wer supply for ic opera- tions. re gulator input (v in ): 2.0 v to 5.5 v re gulator output (v out ): 1.8 v when a single po wer supply is used, supply the v oltage within the range sho wn abo v e to the v in , hv dd , and a v dd pins. also the same v oltage should be supplied to the regen pin to enabl e the re gulator to operate. the re gulator generates a 1.8 v (typ.) v oltage and outputs it to the v out pin. by supplying the output v oltage to the l v dd pin, the core and internal circuits can be operated. f or po wer supply connection e xamples, see the basic external connection diagram chapter . the embedded re gulator supports economy mode (po wer sa ving mode) to reduce current consumption in the re g u- lator during lo w-speed (32 khz) operation or standby mode (hal t or sleep). contr ol register details (s1c17564) 4.6 6.1 p o w er control register t ab le 4. ad dress register name function 0x5121 vd1_ctl v d1 control register controls the regulator oper ation mode . the po wer control re gister (s1c17564) is described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. v d1 control register (vd1_ctl) register name ad dress bit name function setting init. r/w remarks v d1 control register (vd1_ctl) s1c17564 0x5121 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 vd1eco [1:0] regulator oper ation mode select vd1eco[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed a uto-control econom y nor mal d[7:2] reserved d[1:0] vd1eco[1:0]: regulator operation mode select bits sets the operation mode of the embedded re gulator . 6.2 regulator oper ation mode t ab le 4. vd1eco[1:0] operation mode 0x3 reser v ed 0x2 a uto-control mode 0x1 econom y (po w er sa ving) mode 0x0 nor mal mode (def ault: 0x0) f or normal operation (while the ic is operating with a clock other than osc1), set vd1eco[1:0] to 0x0 (def ault). setting vd1eco[1:0] to 0x1 places the re gulator into economy mode. the economy mode can reduce current consumption, note, ho we v er , that the re gulator may become unstable du e to changes of load that cannot be responded. the re gulator should be set to economy mode before the slp instruction is e x ecut- ed. setting vd1eco[1:0] to 0x2 places the re gulator into auto-control mode. in this mode, the hardw are automatically performs switching between normal mode and economy mode according to changes of load. the re gulator enters economy mode when both iosc and osc3 are stopped or when the ic en- ters sleep mode, or enters normal mode otherwise. while the ic is operating with a high-speed clock (other than osc1), the re gulator should not be set to economy mode, as the re gulator output v oltage may become unstable. ev en if the ic is operating with osc1, set the re gulator to normal mode when dri ving a hea vy load such as a lamp or b uzzer . 4 po wer suppl y s1c17554/564 t echnical m anual seiko epson corporation 4-3 precautions on p o wer suppl y 4.7 p o wer -on sequence in order to operate the de vice normally , supply po wer in the follo wing sequence: po wer -on: l v dd hv dd (i/o), a v dd (a/d) apply the input signal or l v dd , hv dd (i/o), a v dd (a/d) apply the input signal (see notes in po wer -of f sequence belo w .) note: when the hv dd po w er is tur ned on from off status , stab le inter nal circuit statuses cannot be guar- a nteed due to noise in the po w er line . theref ore , the circuit statuses m ust be initializ ed (reset) after the po w er is tur ned on. p o wer -off sequence shut of f the po wer supply in the follo wing sequence: po wer -of f: t urn of f the input signal hv dd (i/o), a v dd (a/d) l v dd or t urn of f the input signal hv dd (i/o), a v dd (a/d), l v dd (see notes belo w .) notes: ? applying only l v dd with other po w er v oltage tur n ed off puts the hv dd system circuits into un- stab le status and unstab le current flo ws in the i/o cells . be sure to a v oid applying only l v dd f or a dur ation of one second or more . ? be sure to a v oid applying hv dd or a v dd f or a dur ation of one second or more when the l v dd po w er is off , as a breakdo wn ma y occur in the de vice or the char acter istics ma y be deg r aded due to flo w-through current of the hv d d or a v dd . latc h-up the cmos de vice may be in the latch-up condition. this is the phenomenon caused by conduction of the para- sitic pnpn junction (th yristor) contained in the cmos ic, resulting in a lar ge current between hv dd and v ss and leading to breakage. latch-up occurs when the v oltage applied to the input / output e xceeds the rated v alue and a lar ge current flo ws into the internal element, o r when the v oltage at the hv dd pin e xceeds the rated v alue and the internal element is in the breakdo wn condition. in the latter case, e v en if the application of a v oltage e xceeding the rated v alue is instantaneous, the current remains high between hv dd and v ss once the de vice is in the latch-up condition. as this may result in heat generation or smoking, the follo wing points must be tak en into co nsideration: (1) the v oltage le v el at the input/output must not e xceed the range specif ied in the electrical characteristics. in other w ords, it must be belo w the po wer -supply v oltage and abo v e v ss . the po wer -on timing should also be tak en into consideration. (2) abnormal noise must not be applied to the de vice. (3) the potential at the unused input should be f ix ed at hv dd , a v dd , or v ss . (4) no out puts should be shorted. 5 initial reset s1c17554/564 t echnical m anual seiko epson corporation 5-1 initial reset 5 initial reset sour ces 5.1 the s1c17554/564 has three initial reset sources that initialize the internal circuits. (1) #reset pin (e xternal initial reset) (2) k e y-entry reset using the p0 ports (p00Cp03 pins) (softw are selectable e xternal initial reset) (3) w atchdog timer (softw are selectable internal initial reset) figure 5.1.1 sho ws the conf iguration of the initial reset circuit. p0 ports #reset key-entry reset signal reset input signal internal reset signal (to core and peripheral modules) wdt reset signal p00 p01 p02 p03 watchdog timer 1.1 configur ation of initial reset circuit figure 5. the cpu and peripheral circuits are initialized by the acti v e signal from an initial reset source. when the reset sig- nal is ne g ated, the cpu starts reset handling. the reset handling reads the reset v ector (reset handler start address) from the be ginning of the v ector table and starts e x ecuting the program (initial routine) be ginning with the re ad ad- dress. #reset pin 5.1.1 b y s e t t i n g t h e # r e s e t p i n t o l o w l e v e l , t h e s1c17554/564 e n t e r s i n i t i a l r e s e t s t a t e . i n o r d e r t o i n i t i a l i z e t h e s1c17554/564 for sure, the #reset pin must be held at lo w for more than the prescribed time (see a c character - istics in the electrical characteristics chapter) after the po wer supply v oltage is supplied. initial reset state is canceled when the #reset pin at lo w le v el is set to high le v el and the cpu starts e x ecuting the reset interrupt handler . the #reset pin is equipped with a pull-up resistor . p0 p or t k e y-entr y reset 5.1.2 entering lo w le v el simultaneously to the ports (p00Cp03) selected with softw are triggers an initial reset. f or details of the k e y-entry reset function, see the i/o ports (p) chapter . note: the p0 por t k e y-entr y reset function can not be used f or po w er-on reset as it m ust be enab led with softw are . resetting b y the w atc hdog timer 5.1.3 the s1c17554/564 has a b uilt-in w atchdog timer to detect runa w ay of the cpu. the w atchdog timer o v erflo ws if it is not reset with softw are (due to cpu runa w ay) in four -second c ycles. the o v erflo w signal can generate either nmi or reset. write 1 to the wdtmd/wdt_st re gister to generate reset (nm i occurs when wdtmd = 0). f or details of the w atchdog timer , see the w atchdog t imer (wdt) chapter . notes: ? when using the reset function of the w atchdog timer , prog r am the w atchdog timer so that it will be reset within f our-second cycles to a v oid occurrence of an unnecessar y reset. ? the reset function of the w atchdog timer cannot be used f or po w er-on reset as it m ust be en- ab led with softw are . 5 initial reset 5-2 seiko epson corporation s1c17554/564 t echnical m anual initial reset sequence 5.2 ev en if the #reset pin input ne g ates the reset signal after po wer is turned on, the cpu cannot boot up until the oscillation stabilization w aiting time (*) , system clock internal supply start time (8 c ycles), and flash reset cancella- tion time (16 c ycles) ha v e elapsed. figure 5.2.1 sho ws the operating sequence follo wing cancellation of initial reset. the cpu starts operati ng in synchronization with the osc3 or iosc (s1c17564 internal oscillator) clock (*) after reset state is canceled. note: the oscillation stabilization time descr ibed in this section does not include oscillation star t time . theref ore the time inter v al until the cpu star ts e x ecuting instr uctions after po w er is tur ned on or sleep mode is canceled ma y be longer than that indicated in the figure belo w . boot vector oscillation stabilization waiting time (*) system clock internal supply start time (8 cycles) flash reset canceling time (16 cycles) booting osc3/iosc clock (*) system clock #reset internal reset internal data request internal data address internal reset canceled reset canceled 2.1 oper ation sequence f ollo wing cancellation of initial reset figure 5. * booting cloc k and oscillation stabilization w aiting time s1c17554: boots up with the osc3 clock. the oscillation stabilization w aiting time is conf igured to 1,024 c y- cles (osc3 clock). s1c17564: boots up with the iosc clock. the oscillation stabilization w aiting time is conf igured to 64 c ycles (iosc clock). initial settings aft er an initial reset 5.3 the cpu internal re gisters are initialized as follo ws at initial reset. r0Cr7: 0x0 psr: 0x0 (interrupt le v el = 0, interrupt disabled) sp: 0x0 pc: reset v ector stored at the be ginning of the v ector table is loaded by the reset handling. the internal ram and display memory should be initialized with softw are as the y are not initialized at initial reset. the internal peripheral m odules are initialized to the def ault v alues (e xcept some undef ined re gisters). change the settings with softw are if necessary . f or the def ault v alues set at initial reset, see the list of i/o re gisters in appendix or descriptions for each peripheral module. 6 interr upt contr oller (itc) s1c17554/564 t echnical m anual seiko epson corporation 6-1 interrupt contr oller (itc) 6 itc module over vie w 6.1 the interrupt controller (itc) honors interrupt requests from the peripheral modules and outputs the interrupt re- quest, interrupt le v el and v ector number signals to the s1c17 core according to the priority and interrupt le v els. the features of the itc module are listed belo w . ? supports 23 maskable interrupt systems (for 26 interrupt sources list ed belo w). 1. p00Cp03 input interrupt (4 types) 2. p10Cp17 input interrupt (8 types) 3. p20Cp27 input interrupt (8 types) 4. p30Cp37 input interrupt (8 types) 5. p40Cp45 input interrupt (6 types) 6. p50Cp55 input interrupt (6 types) * cannot be used in the s1c17554 wcsp-48 package. 7. stopw atch timer interrupt (3 types) 8. clock timer interrupt (4 types) 9. 16-bit pwm timer ch.0 interrupt (6 types) 10. 16-bit pwm timer ch.1 interrupt (6 types) 11. 16-bit pwm timer ch.2 interrupt (6 types) 12. 16-bit pwm timer ch.3 interrupt (6 types) 13. fine mode 16-bit timer ch.0 & ch.1 interrupt (2 types) 14. 16-bit timer ch.0 interrupt (1 type) 15. 16-bit timer ch.1 interrupt (1 type) 16. 16-bit timer ch.2 interrupt (1 type) 17. usi ch.0 & ch.1 interrupt (6 types) * cannot be used in the s1c17554. 18. u ar t ch.0 interrupt (4 types) 19. u ar t ch.1 interrupt (4 types) 20. ir remote controller interrupt (3 types) 21. spi ch.0 interrupt (2 types) 22. spi ch.1 interrupt (2 types) 23. spi ch.2 interrupt (2 types) 24. i 2 c master interrupt (2 types) 25. i 2 c sla v e interrupt (3 types) 26. a/d con v erter interrupt (2 types) ? supports eight interrupt le v els to prioritize the interrupt sources. the itc enables the interrupt le v el (priority) for determining the processing sequence when multiple interrupts oc- cur simultaneously to be set for each interrupt system separately . each interrupt system includes the number of interrupt causes indicated in parentheses abo v e. settings to enable or disable interrupt for dif ferent causes are set by the respecti v e peripheral module re gisters. f or specif ic information on interrupt cause s and their control, refer to the peripheral module e xplanations. figure 6.1.1 sho ws the structure of the interrupt system. 6 interr upt contr oller (itc) 6-2 seiko epson corporation s1c17554/564 t echnical m anual s1c17 core interrupt controller watchdog timer interr upt request interr upt le ve l v ector number deb ug signal reset signal interr upt request nmi interrupt level interrupt control vector number interrupt level vector number interr upt request ? ? ? ? ? ? ? ? peripheral module interrupt enable cause of interr upt 1 interrupt enable cause of interr upt n ? ? ? ? interrupt flag interrupt flag peripheral module interrupt enable cause of interr upt 1 interrupt enable cause of interr upt n ? ? ? ? interrupt flag interrupt flag 1.1 interr upt system figure 6. v ector t ab le 6.2 the v ector table contains the v ectors to the interrupt handler routines (handler routine start address) that will be read by the s1c17 core to e x ecute the handler when an interrupt occurs. t able 6.2.1 sho ws the v ector table of the s1c17554/564. 2.1 v ector t ab le t ab le 6. v ector no. s o f t w a r e i n t e r r u p t n o . v ector ad dress har d ware interrupt name cause of har d ware interrupt priority 0 (0x00) ttbr + 0x00 reset ? lo w input to the #reset pin ? w atchdog timer o v er?o w 2 1 1 (0x01) ttbr + 0x04 address misaligned interr upt memor y access instr uction 2 C (0xfffc00) deb ugging interr upt brk instr uction, etc. 3 2 (0x02) ttbr + 0x08 nmi w atchdog timer o v er?o w 2 4 3 (0x03) ttbr + 0x0c reser v ed f or c compiler C C 4 (0x04) ttbr + 0x10 p0 por t interr upt p00Cp03 por t inputs high 1 5 (0x05) ttbr + 0x14 p1 por t interr upt p10Cp17 por t inputs l 6 (0x06) ttbr + 0x18 stopw atch timer interr upt ? 100 hz timer signal ? 10 hz timer signal ? 1 hz timer signal 7 (0x07) ttbr + 0x1c cloc k timer interr upt ? 32 hz timer signal ? 8 hz timer signal ? 2 hz timer signal ? 1 hz timer signal 8 (0x08) ttbr + 0x20 16-bit pwm timer ch.2 interr upt ? compare a/b ? capture a/b ? capture a/b o v erwr ite 9 (0x09) ttbr + 0x24 p4 por t interr upt p40Cp45 por t inputs 10 (0x0a) ttbr + 0x28 spi ch.2 interr upt ? t r ansmit b uff er empty ? receiv e b uff er full 11 (0x0b) ttbr + 0x2c 16-bit pwm timer ch.0 interr upt ? compare a/b ? capture a/b ? capture a/b o v erwr ite 12 (0x0c) ttbr + 0x30 fine mode 16-bit timer ch.0 and ch.1 interr upt ? ch.0 under?o w ? ch.1 under?o w usi ch.0 and ch.1 interr upt ? ch.0 tr ansmit b uff er empty ? ch.0 receiv e b uff er full ? ch.0 receiv e error ? ch.1 tr ansmit b uff er empty ? ch.1 receiv e b uff er full ? ch.1 receiv e error 13 (0x0d) ttbr + 0x34 16-bit timer ch.0 interr upt timer under?o w 6 interr upt contr oller (itc) s1c17554/564 t echnical m anual seiko epson corporation 6-3 v ector no. s o f t w a r e i n t e r r u p t n o . v ector ad dress har d ware interrupt name cause of har d ware interrupt priority 14 (0x0e) ttbr + 0x38 16-bit timer ch.1 interr upt timer under?o w 15 (0x0f) ttbr + 0x3c 16-bit timer ch.2 interr upt timer under?o w 16-bit pwm timer ch.3 interr upt ? compare a/b ? capture a/b ? capture a/b o v erwr ite 16 (0x10) ttbr + 0x40 u ar t ch.0 interr upt ? t r ansmit b uff er empty ? end of tr ansmission ? receiv e b uff er full ? receiv e error 17 (0x11) ttbr + 0x44 u ar t ch.1 interr upt ? t r ansmit b uff er empty ? end of tr ansmission ? receiv e b uff er full ? receiv e error 18 (0x12) ttbr + 0x48 spi ch.0 interr upt ? t r ansmit b uff er empty ? receiv e b uff er full 19 (0x13) ttbr + 0x4c i 2 c master interr upt ? t r ansmit b uff er empty ? receiv e b uff er full 20 (0x14) ttbr + 0x50 ir remote controller interr upt ? data length counter under?o w ? input r i sing edge detected ? input f alling edge detected spi ch.1 interr upt ? t r ansmit b uff er empty ? receiv e b uff er full 21 (0x15) ttbr + 0x54 16-bit pwm timer ch.1 interr upt ? compare a/b ? capture a/b ? capture a/b o v erwr ite 22 (0x16) ttbr + 0x58 a/d con v er ter interr upt ? con v ersion completion ? con v ersion result o v erwr ite 23 (0x17) ttbr + 0x5c p5 por t interr upt p50Cp55 por t inputs 24 (0x18) ttbr + 0x60 p2 por t interr upt p20 Cp27 por t inputs 25 (0x19) ttbr + 0x64 p3 por t interr upt p30Cp37 por t inputs 26 (0x1a) ttbr + 0x68 i 2 c sla v e interr upt ? t r ansmit b uff er empty ? receiv e b uff er full ? bus status 27 (0x1b) ttbr + 0x6c reser v ed C : : : : 31 (0x1f) ttbr + 0x7c reser v ed C lo w *1 *1 when the same interr upt le v el is set *2 either reset or nmi can be selected as the w atchdog timer interr upt with softw are . v ector numbers 4 to 26 are assigned to the maskable interrupts supported by the s1c17554/564. interrupts that share an interrupt vector interrupt v ector numbers 12, 15, and 20 are shared with tw o dif ferent interrupt modules. interrupt v ector 12: fine mode 16-bit timer ch.0/ch.1 and usi ch.0/ch.1 interrupt v ector 15: 16-bit timer ch.2 and 16-bit pwm timer ch.3 interrupt v ector 20: ir remote controller and spi ch.1 the interrupt signals f rom the tw o modules are input to the itc through an or g ate. when using the tw o inter - rupts, check if which interrupt has occurred by reading the interrupt flags in both modules. the tw o modules cannot be set to dif ferent interrupt le v el, as the y use the same interrupt v ector . v ector tab le base ad dress the s1c17554/564 allo ws the base (starting) address of the v ector table to be set using the misc_ ttbrl and misc_ttbrh re gisters. ttbr described in t able 6.2.1 means the v alue set to these re gisters. after an ini- tial reset, the misc_ttbrl and misc_ttbrh re gisters are set to 0x8000. therefore, e v en when the v ector table location is changed, it is necessary that at least the reset v ector be written to the abo v e address. bits 7 to 0 in the misc_ttbrl re gister are f ix ed at 0, so the v ector tabl e starting address al w ays be gins with a 256-byte boundary address. 6 interr upt contr oller (itc) 6-4 seiko epson corporation s1c17554/564 t echnical m anual vector table address low/high registers (misc_ttbrl, misc_ttbrh) register name ad dress bit name function setting init. r/w remarks vector table address low register (misc_ttbrl) 0x5328 (16 bits) d15C8 ttbr[15:8] v ector tab le base address a[15:8] 0x0C0xff 0x80 r/w d7C0 ttbr[7:0] v ector tab le base address a[7:0] (fix ed at 0) 0x0 0x0 r vector table address high register (misc_ttbrh) 0x532a (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 ttbr[23:16] v ector tab le base address a[23:16] 0x0C0xff 0x0 r/w note: t h e m i s c _ t t b r l a n d m i s c _ t t b r h r e g i s t e r s a r e w r i t e - p r o t e c t e d . b e f o r e t h e s e r e g i s t e r s c a n be re wr itten, wr ite protection m ust be remo v ed b y wr iting data 0x96 to the misc_pr o t register . n o t e t h a t s i n c e u n n e c e s s a r y r e w r i t e s t o t h e m i s c _ t t b r l a n d m i s c _ t t b r h r e g i s t e r s c o u l d l e a d to err atic system ope r ation, the misc_pr o t register should be set to other than 0x96 unless the v ector t ab le base registers m ust be re wr itten. contr ol of maskab le interrupts 6.3 interrupt contr ol bits in p eripheral modules 6.3.1 the peripheral module that generates interrupts includes an interrupt enable bit and an interrupt flag for each inter - rupt cause. the interrupt flag is set to 1 when the cause of interrupt occu rs. by setting the interrupt enable bit to 1 (interrupt enabled), the flag state will be sent to the itc as an interrupt request signal, generating an interrupt re- quest to the s1c17 core. the corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are not desired. in this case, although the interrupt flag is set to 1 if the interrupt cause occurs, the interrup t request signal sent to the itc will not be asserted. f or specif ic information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respecti v e pe- ripheral module descriptions. note: t o pre v ent recurrence of the interr upt due to the same cause of interr upt, alw a ys reset the inter- r upt flag in the per ipher al module bef ore enab ling the interr upt, resetting the psr, or e x ecuti ng the reti instr uction. itc interrupt request pr ocessing 6.3.2 on recei ving an interrupt signal from a peripheral module, the itc sends the interrupt request, interrupt le v el, and v ector number signals to the s1c17 core. v ector numbers are determined by the itc internal hardw are for each interrupt cause, as sho wn in t able 6.2.1. the interrupt le v el is a v alue used by the s1c17 core to compare with the il bits (psr). this interrupt le v el is used in the s1c17 core to disable subsequently occurring interrupts with the same or lo wer le v el. (see section 6.3.3.) the def ault itc settings are le v el 0 for all maskable interrupts. interrupt requests are not accepted by the s1c17 core if the le v el is 0. t h e i t c i n c l u d e s c o n t r o l b i t s f o r s e l e c t i n g t h e i n t e r r u p t l e v e l , a n d t h e l e v e l c a n b e s e t t o b e t w e e n 0 ( l o w ) a n d 7 ( h i g h ) interrupt le v els for each interrupt type. if interrupt requests are input to the itc simultaneously from tw o or more peripheral modules, the itc outputs the interrupt request with the highest priority to the s1c17 core in accordance with the follo wing conditions. 1. the interrupt with the highest interrupt le v el tak es precedence. 2. if multiple interrupt requests are input with the s ame interrupt le v el, the interrupt with the lo west v ector number tak es precedence. the other interrupts occurring at the same time are held until all interrupts with higher priority le v els ha v e been ac- cepted by the s1c17 core. if an interrupt cause with higher priority occurs while the itc is outputting an interrupt request signal to the s1c17 core (before being accepted by the s1c17 core), the itc alters the v ector number and interrupt le v el signals to the setting information on the more recent interrupt. the pre viously occurring interrupt is held. the held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral module is reset with softw are. 6 interr upt contr oller (itc) s1c17554/564 t echnical m anual seiko epson corporation 6-5 3.2.1 interr upt le v el setting bits t ab le 6. har d ware interrupt interrupt le vel setting bits register ad dress p0 por t interr upt il v0[2:0] (d[2:0]/itc_l v0 register) 0x4306 p1 por t interr upt il v1[2:0] (d[10:8]/itc_l v0 register) 0x4306 stopw atch timer interr upt il v2[2:0] (d[2:0]/itc_l v1 register) 0x4308 cloc k timer interr upt il v3[2:0] (d[10:8]/itc_l v1 register) 0x4308 16-bit pwm timer ch.2 interr upt il v4[2:0] (d[2:0]/itc_l v2 register) 0x430a p4 por t interr u pt il v5[2:0] (d[10:8]/itc_l v2 register) 0x430a spi ch.2 interr upt il v6[2:0] (d[2:0]/itc_l v3 register) 0x430c 16-bit pwm timer ch.0 interr upt il v7[2:0] (d[10:8]/itc_l v3 register) 0x430c fine mode 16-bit timer ch.0 & ch.1 interr upt / usi ch.0 & ch.1 interr upt il v8[2:0] (d[2:0]/itc_l v4 register) 0x430e 16-bit timer ch.0 interr upt il v9[2:0] (d[10:8]/itc_l v4 register) 0x430e 16-bit timer ch.1 interr upt il v10[2:0] (d[2:0]/itc_l v5 register) 0x4310 16-bit timer ch.2 interr upt / 16-bit pwm timer ch.3 interr upt il v11[2:0] (d[10:8]/itc_l v5 register) 0x4310 u ar t ch.0 interr upt il v12[2:0] (d[2:0]/itc_l v6 register) 0x4312 u ar t ch.1 interr upt il v13[2:0] (d[10:8]/itc_l v6 register) 0x4312 spi ch.0 interr upt il v14[2:0] (d[2:0]/itc_l v7 register) 0x4314 i 2 c master interr upt il v15[2:0] (d[10:8]/itc_l v7 register) 0x4314 ir remote con troller interr upt / spi ch.1 interr upt il v16[2:0] (d[2:0]/itc_l v8 register) 0x4316 16-bit pwm timer ch.1 interr upt il v17[2:0] (d[10:8]/itc_l v8 register) 0x4316 a/d con v er ter interr upt il v18[2:0] (d[2:0]/itc_l v9 register) 0x4318 p5 por t interr upt il v19[2:0] (d[10:8]/itc_l v9 register) 0x4318 p2 por t interr upt il v20[2:0] (d[2:0]/itc_l v10 register) 0x431a p3 por t interr upt il v21[2:0] (d[10:8]/itc_l v10 register) 0x431a i 2 c sla v e interr upt il v22[2:0] (d[2:0]/itc_l v11 register) 0x431c interrupt pr ocessing b y the s1c17 core 6.3.3 a maskable interrupt to the s1c17 core occurs when all of the follo wing conditions are met: ? the interrupt is enabled by the interrupt control bit inside the peripheral module. ? the ie (interrupt enable) bit of the psr (processor status re gister) in the s1c17 core has been set to 1. ? t he cause of interrupt that has occurred has a higher interrupt le v el than the v alue set in the il f ield of the psr. ? no other cause of interrupt ha ving higher priority , such as nmi, has occurred. i f a n i n t e r r u p t c a u s e t h a t h a s b e e n e n a b l e d i n t h e p e r i p h e r a l m o d u l e o c c u r s , t h e c o r r e s p o n d i n g i n t e r r u p t f l a g i s s e t t o 1 , and this state is maintained until it is reset by the program. this means that t he interrupt cause is not cleared e v en if the conditions listed abo v e are not met when the interrupt cause occurs. an interrupt occurs if the abo v e conditions are met. if multiple maskable interrupt causes occurs simultaneously , the interrupt cause with the highest interrupt le v el and lo west v ector number becomes the subject of the interrupt request to the s1c17 core. interrupts with lo wer le v els a re held until the abo v e conditions are subsequently met. t h e s1c17 c o r e s a m p l e s i n t e r r u p t r e q u e s t s f o r e a c h c y c l e . o n a c c e p t i n g a n i n t e r r u p t r e q u e s t , t h e s1c17 c o r e switches to interrupt processing immediately after e x ecution of the current instruction has been completed. interrupt processing in v olv es the follo wing steps: (1) the psr and current program counter (pc) v alues are sa v ed to the stack. (2) the psr ie bit is reset to 0 (disabling subsequent maskable interrupts). (3) the psr il bits are set to the recei v ed interrupt le v el. (the nmi does not af fect the il bits.) (4) the v ector for the interrupt occurred is loaded to the pc to e x ecute the interrupt handler routine. when an interrupt is accepted, (2) pre v ents subsequent maskable interrupts. setting the ie bit to 1 in the interrupt handler r outine allo ws handling of multiple interrupts. in this case, since il is changed by (3), only an interrupt with a higher le v el than that of the currently processed interrupt will be accepted. ending interrupt handler routines using the reti instruction returns the psr to the state before the interrupt has occurred. the program resumes processing follo wing the instruction being e x ecuted at the time the interrupt oc- curred. 6 interr upt contr oller (itc) 6-6 seiko epson corporation s1c17554/564 t echnical m anual nmi 6.4 in the s1c17554/564, the w atchdog timer can generate a non-maskable interrupt (nmi). the v ector number for nmi is 2, with the v ector address set to the v ector table's starting address + 8 bytes. this interrupt tak es precedence o v er other interrupts and is unconditionally accepted by the s1c17 core. f or detailed information on generating nmi, see the w atchdog t imer (wdt) chapter . software interrupts 6.5 the s1c17 core pro vides the int imm5 and intl imm5,imm3 instructions allo wing the softw are to gener - ate an y interrupts. the operand imm5 specif ies a v ector number (0C31) in the v ector table. in addition to this, the intl instruction has the operand imm3 to specify the interrupt le v el (0C7) to be set to the il f ield in the psr. the processor performs the same interrupt processing as that of the hardw are interrupt. hal t and sleep mode cancellation 6.6 hal t and sleep modes are cleared by the follo wing signals, which start the cpu. ? interrupt request signal sent to the cpu from the itc ? nmi signal output by the w atchdog timer ? deb ug interrupt signal ? reset signal notes: ? halt or slp instr uction. ? f or more information, see po wer sa ving by clock control in the appendix chapter . f or the oscillator circuit and sys tem clock statuses after hal t or sleep mode is canceled, see the clock generator (clg) chapter . contr ol register details 6.7 7.1 list of itc registers t ab le 6. ad dress register name function 0x4306 itc_l v0 interr upt le v el setup register 0 sets the p0 and p1 interr upt le v els . 0x4308 itc_l v1 interr upt le v el setup register 1 sets the swt and ct interr upt le v els . 0x430a itc_l v2 interr upt le v el setup register 2 sets the t16a ch.2 and p4 interr upt le v els . 0x430c itc_l v3 interr upt le v el setup register 3 sets the spi ch.2 and t16a ch.0 interr upt le v els . 0x430e itc_l v4 interr upt le v e l setup register 4 sets the t16f ch.0 & ch.1/usi ch.0 & ch.1 and t16 ch.0 interr upt le v els . 0x4310 itc_l v5 interr upt le v el setup register 5 sets the t16 ch.1 and t16 ch.2/t16a ch.3 interr upt le v els . 0x4312 itc_l v6 interr upt le v el setup register 6 sets the u ar t ch.0 and ch.1 interr upt le v els . 0x4314 itc_l v7 interr upt le v el setup register 7 sets the spi ch.0 and i2cm interr upt le v els . 0x4316 itc_l v8 interr upt le v el setup register 8 sets the remc/spi ch.1 and t16a ch.1 interr upt le v els . 0x4318 itc_l v9 interr upt le v el setup register 9 sets the adc10 and p5 interr upt le v els . 0x431a itc_l v10 interr upt le v el setup register 10 sets the p2 and p3 interr upt le v els . 0x431c itc_l v11 interr upt le v el setup register 11 sets the i2cs interr upt le v el. the itc re gisters are described in detail belo w . these are 16-bit re gisters. note: when d ata is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. 6 interr upt contr oller (itc) s1c17554/564 t echnical m anual seiko epson corporation 6-7 interrupt level setup register x (itc_lvx) register name ad dress bit name function setting init. r/w remarks interrupt level setup register x (itc_lv x ) 0x4306 | 0x431c (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 i lv n[2:0] intn (1, 3, ... 21) interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 i lv n[2:0] intn (0, 2, ... 22) interr upt le v el 0 to 7 0x0 r/w d[15:11], d[7:3] reserved d[10:8], d[2:0] ilv n [2:0]: intn interrupt level bits (n = 0C22) sets the interrupt le v el (0 to 7) of each interrupt. (def ault: 0x0) the s1c17 core does not accept interrupts with a le v el set lo wer than the psr il v alue. the itc uses the interrupt le v el when mult iple interrupt requests occur simultaneously . i f m u l t i p l e i n t e r r u p t r e q u e s t s e n a b l e d b y t h e i n t e r r u p t e n a b l e b i t o c c u r s i m u l t a n e o u s l y , t h e i t c s e n d s t h e interrupt request with the highest le v el set by the itc_l vx re gisters (0x4306 to 0x431c) to the s1c17 core. if multiple interrupt requests with the same interrupt le v el occur simultaneously , the interrupt with the lo west v ector number is processe d f irst. the other interrupts are held until all interrupts of higher priority ha v e been accepted by the s1c17 core. if an interrupt requests of higher priority occurs while the itc outputs an interrupt request signal to the s1c17 core (before acceptance by the s1c17 core), the itc alters the v ector number and interrupt le v el signals to the setting details of the most recent interrupt. the immedia tely preceding interrupt is held. 7.2 interr upt le v el bits t ab le 6. register bit interrupt itc_l v0(0x4306) il v0[2:0] (d[2:0]) p0 por t interr upt il v1[2:0] (d[10:8]) p1 por t interr upt itc_l v1(0x4308) il v2[2:0] (d[2:0]) stopw atch timer interr upt il v3[2:0] (d[10:8]) cloc k timer interr upt itc_l v2(0x430a) il v4[2:0] (d[2:0]) 16-bit pwm timer ch.2 interr upt il v5[2:0] (d[10:8]) p4 por t interr upt itc_l v3(0x430c) il v6[2:0] (d[2:0]) spi ch.2 interr upt il v7[2:0] (d[10:8]) 16-bit pwm timer ch.0 inte rr upt itc_l v4(0x430e) il v8[2:0] (d[2:0]) fine mode 16-bit timer ch.0 & ch.1 interr upt / usi ch.0 & ch.1 interr upt il v9[2:0] (d[10:8]) 16-bit timer ch.0 interr upt itc_l v5(0x4310) il v10[2:0] (d[2:0]) 16-bit timer ch.1 interr upt il v11[2:0] (d[10:8]) 16-bit timer ch.2 interr upt / 16-bit pwm timer ch.3 interr upt itc_l v6(0x4312) il v12[2:0] (d[2:0]) u ar t ch.0 interr upt il v13[2:0] (d[10:8]) u ar t ch.1 interr upt itc_l v7(0x 4314) il v14[2:0] (d[2:0]) spi ch.0 interr upt il v15[2:0] (d[10:8]) i 2 c master interr upt itc_l v8(0x4316) il v16[2:0] (d[2:0]) ir remote controller interr upt / spi ch.1 interr upt il v17[2:0] (d[10:8]) 16-bit pwm timer ch.1 interr upt itc_l v9(0x4318) il v18[2:0] (d[2:0]) a/d con v er ter interr upt il v19[2:0] (d[10:8]) p5 por t interr upt itc_l v10(0x431a) il v20[2:0] (d[2:0]) p2 por t interr upt il v21[2:0] (d[10:8]) p3 por t interr up t itc_l v11(0x431c) il v22[2:0] (d[2:0]) i 2 c sla v e interr upt (il v23[2:0] (d[10:8])) reser v ed 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-1 clock generator (clg) 7 note: t h e d e s c r i p t i o n s i n t h i s c h a p t e r r e g a r d i n g i o s c a r e a p p l i e d t o t h e s1c17564 o n l y . t h e i o s c cloc k cannot be used in the s1c15554. clg module over vie w 7.1 the clock generator (clg) controls the internal oscillators and the system clocks to be supplied to the s1c17 core, on-chip peripheral modules, and e xternal de vices. the features of the clg module are listed belo w . ? genera tes the operating clocks with the b uilt-in oscillators. - iosc oscillator circuit: 2/4/8/12 mhz mhz (typ.)* - osc3 oscillator circuit: 24 mhz (max.) crystal or ceramic oscillator circuit, or an e xternal clock input - osc1 oscillator circuit: 32.768 khz (typ.) crystal oscillator circuit or an e xternal clock input ? switches the system clock. the system clock source can be selected from iosc*, osc3, and osc1 via softw are. ? generates the cpu core clock (cclk) and controls the clock supply to the core block. the cclk frequenc y can be selected from system clock 1/1, 1/2, 1/4, and 1/8. ? controls the clock supply to the peripheral modules. ? t urns the clocks on and of f according to the cpu operating status (r un, hal t , or sleep). ? supports quick-restart processing from sleep mode. t urns iosc on fo rcibly and switches the system clock to iosc when sleep mode is canceled. * ? controls tw o clock outputs to e xternal de vices. * s1c17564 only figure 7.1.1 sho ws the clock system and clg module conf iguration. cclk osc3 osc1 iosc fouta output circuit osc3 oscillator (24 mhz) iosc oscillator (2/4/8/12 mhz) osc1 oscillator (32.768 khz) clock gear (1/1C1/8) osc controller gate s1c17 core ct, swt, wdt osc3 osc4 system clock s1c17564 only fouta foutb output circuit foutb osc1 osc2 sleep, wakeup halt clg embedded memory, bus, ct/swt/wdt registers 256 hz gate itc, t16, t16f, spi, usi, i2cm, i2cs, uart, p, misc, vd1, adc, remc pclk t16a, uart iosc divider osc3 divider osc1 divider 1.1 clg module configur ation figure 7. t o reduce current consumption, control the clock in conjunction with processing and use hal t and sleep modes. f or more information on reducing current consumption, see po wer sa ving in the appendix chapter . 7 clock genera t or (clg) 7-2 seiko epson corporation s1c17554/564 t echnical m anual clg input/output pins 7.2 t able 7.2.1 lists the input/output pins for the clg module. 2.1 list of clg pins t ab le 7. pin name i/o qty function osc1 i 1 osc1 oscillator input pin connect a cr ystal resonator (32.768 khz) and a gate capacitor . or input an e xter nal cloc k used as the osc1 cloc k. osc2 o 1 osc1 oscillator output pin connect a cr ystal resonator (32.768 khz). osc3 i 1 osc3 oscillator input pin connect a cr ystal or cer amic resonator (max. 24 mhz), a f eedbac k resistor , and a gate capacitor . or input an e xter nal cloc k used as the osc3 cloc k. osc4 o 1 osc3 oscillator output pin connect a cr ystal or cer amic resonator (max. 24 mhz), a f eedbac k resistor , and a dr ain capacitor . fout a o 1 fout a cloc k output pin outputs a divided iosc/osc3 cloc k or the osc1 cloc k. foutb o 1 foutb cloc k output pin outputs a divided iosc/osc3 cloc k or the osc1 cloc k. the clg output pins (fout a, foutb) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as the clg output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . oscillator s 7.3 t h e s 1 c 1 7 5 5 4 c l g m o d u l e c o n t a i n s t w o i n t e r n a l o s c i l l a t o r c i r c u i t s ( o s c 3 , a n d o s c 1 ) . t h e s 1 c 1 7 5 6 4 c l g m o d - ule contains three internal oscillat or circuits (iosc, osc3, and osc1). the osc3 and iosc oscillators generate the main clock for high-speed operation of the s1c17 core and peripheral circuits. the osc1 oscillator generates a sub-clock for timers and lo w-po wer operations. the osc3 clock is selected as the system clock in the s1c17554 or the iosc clock is selected in the s1c17564 after an initial reset. oscillator on/of f switching an d system clock selection (from iosc, osc3 and osc1) are controlled with softw are. 3.1 oscillator configur ation t ab le 7. model iosc oscillator osc3 oscillator osc1 oscillator default system c loc k s1c17554 una v ailab le a v ailab le (def ault: on) a v ailab le (def ault: off) osc3 s1c17564 a v ailab le (def ault: on) a v ailab le (def ault: off) a v ailab le (def ault: off) iosc osc3 oscillator 7.3.1 the osc3 oscillator is a high-precision, high-speed oscillator circuit that uses either a crystal resonator or a ceramic resonator . figure 7.3.1.1 sho ws the osc 3 oscillator conf iguration. a crystal resonator (x tal3) or a ceramic resonator (ceramic) and a feedback resistor (r f3 ) should be connected between the osc3 and osc4 pins. additionally , tw o capacitors (c g3 and c d3 ) should be connected between the osc3/osc4 pins and v ss . t o use an e xternal clock, lea v e the osc4 pin open and input an l v dd -le v el clock (with a 50% duty c ycle) to the osc3 pin. f or the ef f ecti v e frequenc y range, oscillation characteristics, and e xternal clock input characteristics, see the elec- trical characteristics chapter . 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-3 v ss osc4 osc3 osc4 osc3 r f3 c d3 c g3 sleep status x'tal3 or ceramic f osc3 osc3en oscillation stabilization wait circuit osc3wt[1:0] osc3wce sleep status f osc3 osc3en oscillation stabilization wait circuit osc3wt[1:0] osc3wce n.c. v ss lv dd external clock (1) crystal/ceramic oscillator circuit (2) external clock input 3.1.1 osc3 oscillator circuit figure 7. osc3 oscillation on/off the osc3 oscillator circuit starts oscillating when osc3en/clg_ctl re gister is set to 1 and stops oscillating when it is set to 0. the osc3 oscillator circuit also stops oscillating in sleep mode. after an initial reset, osc3en is initialized as follo ws: 3.1.1 osc3 oscillator initial status t ab le 7. model osc3en initial v alue osc3 oscillator initial status s1c17554 1 on s1c17564 0 off stabilization wait time at star t of osc3 oscillation t h e o s c 3 o s c i l l a t o r c i r c u i t i n c l u d e s a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t t o p r e v e n t m a l f u n c t i o n s d u e t o u n s t a - ble clock operations at the start of osc3 oscillatione.g., when the osc3 oscillator is turned on with softw are. fig ure 7.3.1.2 sho ws the relat ion shi p b etween the osci llat ion star t tim e and the osci ll atio n stab ili zatio n w ait time. oscillation enab le bit (osc3en/ioscen/osc1en) oscillation wave fo rm digitiz ed oscillation wave fo rm oscillator output cloc k (f osc3 /f iosc /f osc1 ) system supply w ait time oscillation star t time oscillation stabilization w ait time 3.1.2 oscillation star t time and oscillation stabilization w ait time figure 7. the osc3 clock is not supplied to the system until the time set for this circuit has elapsed. use osc3wt[1:0]/ clg_ctl re gister to select one of four oscillation stabilization w ait times. 7 clock genera t or (clg) 7-4 seiko epson corporation s1c17554/564 t echnical m anual 3.1.2 osc3 oscillation stabilization w ait time settings t ab le 7. osc3wt[1:0] oscillation stabilization wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles (def ault: 0x0) this is set to 1,024 c ycles (osc3 clock) after an initial reset. when the system clock is switched to osc3 immediately after the osc3 oscillator circuit is turned on, the osc3 clock is supplied to the system after the osc3 clock system supply w ait time indicated belo w (at a maxi- mum) h as elapsed. f or the oscillation start time, see the electrical characteristics chapter . osc3 cloc k system supply w ait time osc3 oscillation star t time (max.) + osc3 oscillation sta- bilization w ait time note: o s c i l l a t i o n s t a b i l i t y w i l l v a r y , d e p e n d i n g o n t h e r e s o n a t o r a n d o t h e r e x t e r n a l c o m p o n e n t s . c a r e f u l l y consider the osc3 oscillation stabilization w ait time bef ore reducing the time . t h e o s c3 o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t c a n b e e n a b l e d o r d i s a b l e d u s i n g o s c3w c e / c l g _ n f e n re gister . after an initial reset, the osc3 oscillation stabilization w ait circuit is enabled ( osc3wce = 1) and it controls the clock supply to the system. when a stabilized e xternal clock is input to the osc3 pin, setting osc3wce to 0 enables the system to start operating without a stabilization w ait time. osc1 oscillator 7.3.2 the osc1 oscillator is a high-precision, lo w-speed oscillator circuit that uses a 32.768 khz crystal resonator . the osc1 clock is generally used as the timer operation clock (for the clock timer , stopw atch timer , w atchdog tim- er , and 16-bit pwm timer). it can be used as the system clock instead of the osc3 or iosc clock to reduce po wer consumption when no high-speed processing is r equired. figure 7.3.2.1 sho ws the osc1 oscillator conf iguration. osc1wce osc1wce v ss osc2 osc1 osc2 osc1 r f1 c d1 c g1 sleep status x'tal1 f osc1 osc1en oscillation stabilization wait circuit sleep status f osc1 osc1en oscillation stabilization wait circuit n.c. v ss lv dd external clock (1) crystal oscillator circuit (2) external clock input 3.2.1 osc1 oscillator circuit figure 7. a crystal resonator (x tal1) and a feedback resistor (r f1 ) should be connected between the osc1 and osc2 pins. additionally , tw o capacitors (c g1 and c d1 ) should be connected between the osc1/osc2 pins and v ss . t o use an e xternal clock, lea v e the osc2 pin open and input an l v dd -le v el clock (with a 50% duty c ycle) to the osc1 pin. f or oscillation characteristics and e xternal clock input characteristics, see the electrical characteristics chapter . 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-5 osc1 oscillation on/off the osc1 oscillator stops oscillating when osc1en/clg_ctl re gister is set to 0 and starts oscillating when set to 1. the osc1 oscillator circuit stops oscillating in sleep mode. after an initial reset, osc1en is set to 0, and the osc1 oscillator circuit is halted. stabilization wait time at star t of osc1 oscillation the osc1 oscillator includes an oscillation stabilization w ait circuit (f ix ed at 256 c ycles) to pre v ent malfunc- tions caused by unstable clock operations at the start of osc1 oscillatione.g., when the osc1 oscillator is turned on with softw are. when the system clock is switched to osc1 immediately after the osc1 oscillator circuit is turned on, the osc1 clock is supplied to the system after the osc1 clock system supply w ait time indicated belo w (at a max imum) has elapsed. f or the oscillation start time, see the electrical characteristics chapter . osc1 cloc k system supply w ait time osc1 oscillation star t time (max.) + osc1 oscillation stabilization w ait time (256 cycles) t h e o s c1 o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t c a n b e e n a b l e d o r d i s a b l e d u s i n g o s c1w c e / c l g _ n f e n re gister . after an initial reset, the osc1 oscillation stabilization w ait ci rcuit is enabled ( osc1wce = 1) and it controls the clock supply to the system. when a stabilized e xternal clock is input to the osc1 pin, setting osc1wce to 0 enables the system to start operating without a stabilization w ait time. iosc oscillator (s1c17564) 7.3.3 the iosc oscillator initiates high-speed oscillation without e xternal components. it initiates oscillation when po w- er is turned on. the s1c17 core and peripheral circuits operates with this oscillation clock after an initial reset. f iosc clock generator ioscen oscillation stabilization wait circuit ioscwt[1:0] 3.3.1 iosc oscillator circuit figure 7. iosc oscillation frequenc y the iosc oscillation frequenc y can be selected from four types sho wn belo w using ioscsel[1:0]/clg_iosc re gister . 3.3.1 iosc oscillation f requency setting t ab le 7. ioscsel[1:0] iosc oscillation frequenc y (typ.) 0x3 2 mhz 0x2 4 mhz 0x1 12 mhz 0x0 8 mhz (def ault: 0x1) iosc oscillation on/off the iosc oscillator stops oscillating when ioscen/clg_ctl re gister is set to 0 and starts oscillating when set to 1. the iosc oscillator stops oscillating in sleep mode. after an initial reset, ioscen is set to 1, and the iosc oscillator goes on. since the iosc clock is used as the s ystem clock, the s1c17 core starts operating using the iosc clock. when sleep mode is canceled, the iosc oscillator circuit is turned on and is used as the system clock source re g ardless of the system clock conf igured before the chip entered sleep mode. stabilization wait time at star t of iosc oscillation t h e i o s c o s c i l l a t o r c i r c u i t i n c l u d e s a n o s c i l l a t i o n s t a b i l i z a t i o n w a i t c i r c u i t t o p r e v e n t m a l f u n c t i o n s d u e t o unstable clock operations at the start of iosc oscillatione.g., when the iosc oscillator is turned on with s o f t w a r e . t h e i o s c c l o c k i s n o t s u p p l i e d t o t h e s y s t e m u n t i l t h e t i m e s e t f o r t h i s c i r c u i t h a s e l a p s e d . u s e ioscwt[1:0]/clg_ctl re gister to select one of four oscillation stabilization w ait times. 7 clock genera t or (clg) 7-6 seiko epson corporation s1c17554/564 t echnical m anual 3.3.2 iosc oscillation stabilization w ait time settings t ab le 7. ioscwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 64 c ycles (iosc clock) after an initial reset. this means the cpu can start operating when the cpu operation start time at initial reset indicated belo w (at a maximum) has elapsed after the reset state is can- celed. f or the oscillation start time, see the electrical character istics chapter . cpu oper ation star t time at initial reset iosc oscillation star t time (max.) + iosc oscillation stabilization w ait time (64 cycles) when the system clock is switched to iosc immediately after turning the iosc oscillator on, the iosc clock is supplied to the system after the iosc clock system supply w ait time indicated belo w (at a maximum) has elapsed. if the po wer supply v oltage l v dd has stabilized suf f iciently , ioscwt[1:0] can be set to 0x3 to reduce the oscillation stabilization w ait time. iosc cloc k system supply w ait time iosc oscillation star t time (max.) + iosc oscillation stabilization w ait time system cloc k switc hing 7.4 the f igure belo w sho ws the system clock selector . f iosc f osc3 f osc1 s1c17564 clksrc[1:0] system clock 4.1 system cloc k selector figure 7. the s1c17554 has tw o system clock sources (osc3 and osc1) and the s1c17564 has three system clock sources (iosc, osc3, and osc1). the system clock can be switched using clksrc[1:0]/clg_src re gister . after an initial reset, the s1c17554 starts operating using osc3 as the system clock and the s1c17564 starts operating us- ing iosc. when no high-speed processing is r equired, switch the system clock to osc1 and stop the high-speed oscillator circuit to reduce current consumption. 4.1 system cloc k selection t ab le 7. clksrc[1:0] system c loc k sour ce s1c17554 s1c17564 0x3 reser v ed 0x2 osc3 (def ault) osc3 0x1 osc1 osc1 0x0 reser v ed iosc (def ault) the follo wing sho ws system clock switching procedures: switc hing the system c loc k to osc3 fr om iosc or osc1 1. set the osc3 oscillation stabilization w ait time if necessary . (osc3wt[1:0]) 2. disable the osc3 oscillation stabilization w ait circuit when a stabilized e xternal clock is input to the osc3 pin. (osc3wce = 0) 3. t urn the osc3 oscillator on if it is of f. (osc3en = 1) 4. select the osc3 clock as the system clock. (clksrc[1:0] = 0x2) 5. t urn the iosc or osc1 oscillator of f if peripheral modules and fout a/b output circuits ha v e not used the iosc or osc1 clock. 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-7 switc hing the system c loc k to osc1 fr om iosc or osc3 1. disable the osc1 oscillation stabilization w ait circuit when a stabilized e xternal clock is input to the osc1 pin. (osc1wce = 0) 2. t urn the osc1 oscillator on. (osc1en = 1) 3. select the osc1 clock as the system clock. (clksrc[1:0] = 0x1) 4. t urn the iosc or osc3 oscillator of f if peripheral modules and fout a/b output circuits ha v e not used the iosc or osc3 clock. switc hing the system c loc k to iosc fr om osc3 or osc1 (s1c17564) 1. set the iosc oscillation stabilization w ait time if necessary . (ioscwt[1:0]) 2. t urn the iosc oscillator on if it is of f. (ioscen = 1) 3. select the iosc clock as the system clock. (clksrc[1:0] = 0x0) 4. t urn the osc3 or osc1 oscillator of f if peripheral modules and fout a/b output circuits ha v e not used the osc3 or o sc1 clock. notes: ? t h e o s c i l l a t o r t o b e u s e d a s t h e s y s t e m c l o c k s o u r c e m u s t b e o p e r a t e d b e f o r e s w i t c h i n g the system cloc k. otherwise , the clg will not s witch the system cloc k source , e v en if clk- src[1:0] is wr itten to , and the clksrc[1:0] v alue will remain unchanged. the tab les belo w list the combinations of cloc k oper ating status and register settings enab ling system cloc k selection. 4.2 system clo c k switching conditions (s1c17554) t ab le 7. osc3en osc1en system c loc k 1 1 osc3 or osc1 4.3 system cloc k switching conditions (s1c17564) t ab le 7. ioscen osc3en osc1en system c loc k 1 1 1 iosc , osc3, or osc1 1 0 1 iosc or osc1 0 1 1 osc3 or osc1 ? the oscillator circuit selected as the system cloc k source cannot be tur ned off . ? contin uous wr ite/read access to clksrc[1:0] is prohibited. at least one instr uction unrelated to clksrc[1:0] access m ust be inser ted betw een the wr ite and read instr uctions . ? when sleep mode is canceled in the s1c17564, the iosc os cillator circuit is tur ned on (io- scen = 1) and is used as the system cloc k source (clksrc[1:0] = 0x0) regardless of the system cloc k configured bef ore the chip entered sleep mode . canceling hal t mode does not change the cloc k status configured bef ore the chip entered hal t mode . cpu core cloc k (cclk) contr ol 7.5 the clg module includes a clock gear to slo w do wn the system clock to send to the s1c 17 core. t o reduce cur - rent consumption, operate the s1c17 core with the slo west possible clock speed. the halt instruction can be e x- ecuted to stop the clock supply from the clg to the s1c17 core for po wer sa vings. f iosc f osc3 f osc1 cclk clock gear (1/1C1/8) gate s1c17 core gear selection system clock halt s1c17564 5.1 cclk supply system figure 7. 7 clock genera t or (clg) 7-8 seiko epson corporation s1c17554/564 t echnical m anual cloc k g ear settings cclkgr[1:0]/clg_cclk re gister is used to select the gear ratio to reduce system clock speeds. 5.1 cclk gear ratio selection t ab le 7. cclkgr[1:0] gear ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k suppl y contr ol t h e c c l k c l o c k s u p p l y i s s t o p p e d b y e x e c u t i n g t h e halt i n s t r u c t i o n . s i n c e t h i s d o e s n o t s t o p t h e s y s t e m clock, peripheral modules will continue to operate. hal t mode is cleared by resetting, nmi, or other interrupts. the cclk supply resumes when hal t mode is cleared. ex ecuting the slp instruction suspends system clock suppl y to the clg, thereby halting the cclk supply as well. clearing sleep mode with an e xternal interrupt restarts the system clock supply and the cclk supply . p eripheral module cloc k (pclk) contr ol 7.6 the clg module also controls the clock supply to peripheral modules. the system clock is used unmodif ied for the peripheral module clock (pclk). internal peripheral modules ? uart ch.0C1 ? fine mode 16-bit timer ch.0C1 ? 16-bit timer ch.0C2 ? spi ch.0C2 ? usi ch.0C1 (s1c17564) ? i 2 c master ? i 2 c slave ? power generator (s1c17564) ? p port & port mux ? misc registers ? ir remote controller ? a/d converter gate on/off control pclk system clock f iosc f osc3 f osc1 s1c17564 6.1 p er ipher al module cloc k control circuit figure 7. cloc k suppl y contr ol pclk supply is controlled by pcken[1:0]/clg_pclk re gister . 6.1 pclk control t ab le 7. pcken[1:0] pclk suppl y 0x3 enab led (on) 0x2 setting prohibited 0x1 setting prohibited 0x0 disab led (off) (def ault: 0x3) the def ault setting is 0x3, which enables the clock supply . stop the clock supply to reduce current consumption unless all peripheral modules (modules listed belo w) within the internal peripheral circuit area need to be run- ning. note: do not set pcken[1:0]/clg_pclk register to 0x2 or 0x1, sin ce doing so will stop the oper ation of cer tain per ipher al modules . 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-9 6.2 p er ipher al modules and oper ating cloc ks t ab le 7. p eripheral modules operating c loc k remarks u ar t ch.0 and 1 pclk the pclk supply cannot be disab led if one or more per ipher al modules in these list m ust be oper ated. the pclk supply can be disab led if all the per iph- er al circuits in these list can be stopped. fine mode 16-bit timer ch.0 and 1 16-bit timer ch.0 to 2 spi ch.0 to 2 usi ch.0 and 1 (s1c17564) i 2 c master i 2 c sla v e p o w er gener ator (s1c17564) p por t & p or t mux misc registers ir remote controller a/d con v er ter cloc k timer divided osc1 cloc k t h e o s c1 o s c i l l a t o r c i r c u i t c a n n o t b e d i s a b l e d i f o n e o r m o r e p e r i p h e r a l m o d u l e s i n t h e s e l i s t m u s t be oper ated. the pclk supply can be disab led. stopw atch timer w atchdog timer 16-bit pwm timer ch.0 to 3 cloc k selected b y softw are (divided iosc/osc3/osc1 cloc k) the oscillator circuit used as the cloc k source can- not be d isab led (see section 7.7 or each per ipher al module chapter). the pclk supply can be disab led. fout a/foutb outputs cloc k external output (fout a, foutb) 7.7 a di vided iosc/osc3 clock or the osc1 clock can be output to e xternal de vices. i/o port (fouta pin) divider (1/1C1/4) osc3 clock fouta output circuit on/off control clock source selection on/off control clock source selection fouta division ratio selection foutb division ratio selection divider (1/1C1/4) iosc clock osc1 clock i/o port (foutb pin) foutb output circuit s1c17564 7.1 cloc k output circuit figure 7. there are tw o output systems a v ailable: fout a and foutb. the fout a and foutb output circuits ha v e the same functions. output pin setting the fout a and foutb output pins are shared with i/o ports. the pin is conf igured for the i/o port by de- f ault, so the pin function should be changed using the port function select bit before the clock output can be used. see the i/o ports (p) chapter for the fout a/foutb pins and selecting pin functions. cloc k sour ce selection the clock source can be selected from iosc (s1c17564), osc3, and osc1 using fout asrc[1:0]/clg_ fout a re gister or foutbsrc[1:0]/clg_foutb re gister . 7.1 cloc k source selection t ab le 7. fout asrc[1:0]/ foutbsrc[1:0] cloc k sour ce s1c17554 s1c17564 0x3 reser v ed 0x2 osc3 osc3 0x1 osc1 osc1 0x0 reser v ed iosc (def ault: 0x0) 7 clock genera t or (clg) 7-10 seiko epson corporation s1c17554/564 t echnical m anual cloc k frequenc y selection three dif ferent clock output frequencies can be selected when osc3 or iosc is used as the clock source. se- lect the di vision ratio for the source clock using fout ad[1:0]/clg_fout a re gister or foutbd[1:0]/clg_ foutb re gister . 7.2 iosc/osc3 division ratio selection t ab le 7. fout ad[1:0]/foutbd[1:0] division ratio 0x3 reser v ed 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k output contr ol the clock output is controlled using fout ae/clg_fout a re gister or foutbe/clg_foutb re gister . set- ting fout ae/foutbe to 1 outputs the fout a/foutb clock from the fout a/foutb pin. setting it to 0 disables output. foutae (foutbe) fouta (foutb) output 00 1 7.2 fout a/foutb output figure 7. note: s i n c e t h e f o u t a / f o u t b s i g n a l i s n o t s y n c h r o n i z e d w i t h f o u t a e / f o u t b e w r i t i n g , s w i t c h i n g output on or off will gener ate cer tain hazards . contr ol register details 7.8 8.1 list of clg registers t ab le 7. ad dress register name function 0x5060 clg_src cloc k source select register selects the cloc k source . 0x5061 clg_ctl oscillation control register controls oscillation. 0x5062 clg_nfen noise filter enab le register t ur ns oscillation stabilization w ait circuit/noise filter on/off . 0x5064 clg_fout a fout a control register controls fout a cloc k output. 0x5065 clg_foutb foutb control register controls foutb cloc k output. 0x506e c lg_iosc iosc control register configures iosc oscillation frequency . 0x5080 clg_pclk pclk control register controls the pclk supply . 0x5081 clg_cclk cclk control register configures the cclk division r atio . the clg module re gisters are described in detail belo w . these are 8-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. clock source select register (clg_src) register name ad dress bit name function setting init. r/w remarks clock source select register (clg_src) s1c17554 0x5060 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x2 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed clock source select register (clg_src) s1c17564 0x5060 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc d[7:2] reserved 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-11 d[1:0] clksrc[1:0]: system clock source select bits selects the system clock source. 8.2 system cloc k selection t ab le 7. clksrc[1:0] system c loc k sour ce s1c17554 s1c17564 0x3 reser v ed 0x2 osc3 (def ault) osc3 0x1 osc1 osc1 0x0 reser v ed iosc (def ault) select iosc or osc3 for normal (high-speed) operations. if no high-speed clock is required, osc1 can be set as the system clock and iosc and osc3 stopped to reduce current consumption. notes: ? t h e o s c i l l a t o r t o b e u s e d a s t h e s y s t e m c l o c k s o u r c e m u s t b e o p e r a t e d b e f o r e s w i t c h i n g the syste m cloc k. otherwise , the clg will not s witch the system cloc k source , e v en if clk- src[1:0] is wr itten to , and the clksrc[1:0] v alue will remain unchanged. the tab les belo w list the combinations of cloc k oper ating status and register settings en- ab ling system cloc k selection. 8.3 system cloc k switching conditions (s1c17554) t ab le 7. osc3en osc1en system c loc k 1 1 osc3 or osc1 8.4 system cloc k switching conditions (s1c17564) t ab le 7. ioscen osc3en osc1en system c loc k 1 1 1 iosc , osc3, or osc1 1 0 1 iosc or osc1 0 1 1 osc3 or osc1 ? the oscillator circuit selected as the system cloc k source cannot be tur ned off . ? contin uous wr ite/read access to clksrc[1:0] is prohibited. at least one instr uction unre- lated to clksrc[1:0] access m ust be inser ted betw een the wr ite and read instr uctions . ? when sleep mode is canceled in the s1c17564, the iosc o scillator circuit is tur ned on (ioscen = 1) and is used as the system cloc k source (clksrc[1:0] = 0x0) regardless of the system cloc k configured bef ore the chip entered sleep mode . canceling hal t mode does not change the cloc k status configured bef ore the chip entered hal t mode . oscillation control register (clg_ctl) register name ad dress bit name function setting init. r/w remarks oscillation control register (clg_ctl) s1c17554 0x5061 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 osc3wt[1:0] osc3 w ait cycle select osc3wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3C2 C reser v ed C C C 0 when being read. d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3en osc3 enab le 1 enab le 0 disab le 1 r/w oscillation control register (clg_ctl) s1c17564 0x5061 (8 bits) d7C6 ioscwt[1:0] iosc w ait cycle select ioscwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d5C4 osc3wt[1:0] osc3 w ait cycle select osc3wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3 C reser v ed C C C 0 when being read. d2 ioscen iosc enab le 1 enab le 0 disab le 1 r/w d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3en osc3 enab le 1 enab le 0 disab le 0 r/w 7 clock genera t or (clg) 7-12 seiko epson corporation s1c17554/564 t echnical m anual d[7:6] reserved (s1c17554) ioscwt[1:0]: iosc wait cycle select bits (s1c17564) an oscillation stabilization w ait time is set to pre v ent malfunctions due to unstable clock operations at the start of iosc oscillation. the iosc clock is not supplied to the system immediately after iosc oscillation starts until the time set here has elapsed. 8.5 iosc oscillation stabilization w ait time settings t ab le 7. ioscwt[1:0] oscillation stabilization wait time 0x3 8 cycles 0x2 16 cycles 0x1 32 cycles 0x0 64 cycles (def ault: 0x0) this is set to 64 c ycles (iosc clock) after an initial reset. this means the cpu can start operating when the cpu operation start time at initial reset indicated belo w (at a maximum) has elapsed after the reset state is canceled. cpu oper ation star t time at initial reset iosc oscillation star t time (max.) + iosc oscilla- tion stabilization w ait time (64 cycles) when the system clock is switched to iosc immediately after turning the iosc oscillator on, the iosc c l o c k i s s u p p l i e d t o t h e s y s t e m a f t e r t h e i o s c c l o c k s y s t e m s u p p l y w a i t t i m e i n d i c a t e d b e l o w ( a t a maximum) has elapsed. if the po wer supply v oltage l v dd has stabilized suf f iciently , ioscwt[1:0] can be set to 0x3 to reduce th e oscillation stabilization w ait time. iosc cloc k system supply w ait time iosc oscillation star t time (max.) + iosc oscillation stabilization w ait time d[5:4] osc3wt[1:0]: osc3 wait cycle select bits an oscillation stabilization w ait time is set to pre v ent malfunctions due to unstable clock operation at the start of osc3 oscillation. the osc3 clock is not supplied to the system immediately after osc3 oscillation startse.g., when the osc3 oscillator is turned on with softw areuntil the time set here has elapsed. 8.6 osc3 oscillation stabilization w ait time settings t ab le 7. osc3wt[1:0] oscillation stabilization wait time 0x3 128 cycles 0x2 256 cycles 0x1 512 cycles 0x0 1024 cycles (def ault: 0x0) this is set to 1,024 c ycles (osc3 clock) after an initial reset. when the system clock is switched to osc3 immediately after the osc3 oscillator circuit is turned on, the osc3 clock is supplied to the system after the osc3 clock system supply w ait time indicated belo w (at a maximum) ha s elapsed. osc3 clock system supply wait time osc3 oscillation start time (max.) + osc3 oscilla- tion stabilization w ait time note: oscillation stability will vary, depending on the resonator and other external components. carefully consider the osc3 oscillation stabilization wait time before reducing the time. the osc3 oscillation stabilization w ait circuit is enabled only when osc3wce/clg_nfen re gister is set to 1 (def ault). d3 reserved 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-13 d2 reserved (s1c17554) ioscen: iosc enable bit (s1c17564) enables or disables iosc oscillator operations. 1 (r/w): enabled (on) (def ault) 0 (r/w): disabled (of f) note: the iosc oscillator cannot be stopped if the iosc clock is being used as the system cloc k. d1 osc1en: osc1 enable bit enables or disables osc1 oscillator operations. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) when the system clock is switched to osc1 immediately after the osc1 oscillator circuit is turned on, the osc1 clock is supplied to the system after the osc1 clock system su pply w ait time indicated belo w (at a maximum) has elapsed. osc1 cloc k system supply w ait time osc1 oscillation star t time (max.) + osc1 oscilla- tion stabilization w ait time (256 cycles) note: the osc1 oscillator cannot be stopped if the osc1 clock is being used as the system clock. d0 osc3en: osc3 enable bit enables or disables osc3 oscillator operations. 1 (r/w): enabled (on) (def ault in s1c17554) 0 (r/w): disabled (of f) (def ault in s1c17564) note: the osc3 oscillator cannot be stopped if the osc3 clock is being used as the system cloc k. noise filter enable register (clg_nfen) register name ad dress bit name function setting init. r/w remarks noise filter enable register (clg_nfen) 0x5062 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 osc1wce osc1 w ait cycle enab le 1 enab le 0 disab le 1 r/w d4 osc3wce osc3 w ait cycle enab le 1 enab le 0 disab le 1 r/w d3C0 C reser v ed C C C 0 when being read. d[7:6] reserved d5 osc1wce: osc1 wait cycle enable bit enables or disables the osc1 oscillation stabilization w ait circuit. 1 (r/w): enabled (def ault) 0 (r/w): disabled when using the internal osc1 oscillator circuit, enable the osc1 oscillation stabilization w ait circuit (osc1wce = 1). when the osc1 oscillator circuit is turned on, the osc1 clock is supplied to the sys- tem after 256 c ycles of oscillation stabilization w ait time has elapsed. w h e n a s t a b i l i z e d e x t e r n a l c l o c k i s i n p u t t o t h e o s c 1 p i n , s e t t i n g o s c 1 w c e t o 0 e n a b l e s t h e s y s t e m t o start operating without a stabilization w ait time. d4 osc3wce: osc3 wait cycle enable bit enables or disables the osc3 oscillation stabilization w ait circuit. 1 (r/w): enable d (def ault) 0 (r/w): disabled when using the internal osc3 oscillator circuit, enable the osc3 oscillation stabilization w ait circuit (osc3wce = 1). when the osc3 oscillator circuit is turned on, the osc3 clock is supplied to the sys- tem after the oscillation stabilization w ait time set using osc3wt[1:0]/clg_ctl re gister has elapsed. w h e n a s t a b i l i z e d e x t e r n a l c l o c k i s i n p u t t o t h e o s c 3 p i n , s e t t i n g o s c 3 w c e t o 0 e n a b l e s t h e s y s t e m t o start operating without a stabilization w ait time. d[3:0] reserved 7 clock genera t or (clg) 7-14 seiko epson corporation s1c17554/564 t echnical m anual fouta control register (clg_fouta) register name ad dress bit name function setting init. r/w remarks fouta control register (clg_fouta ) s1c17554 0x5064 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutad [1:0] fout a cloc k division r atio select fout ad[1:0] division r atio 0x0 r/w when the cloc k source is osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w fouta control register (clg_fouta ) s1c17564 0x5064 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutad [1:0] fout a cloc k division r atio select fout ad[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w d[7:6] reserved d[5:4] foutad[1:0]: fouta clock division ratio select bits selects the clock di vision ratio to set the fo ut a clock frequenc y when osc3 or iosc is used as the clock source. 8.7 osc3/iosc division ratio selection t ab le 7. fout ad[1:0] division ratio 0x3 reser v ed 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) when osc1 is used as the clock source, fout ad[1:0] is inef fecti v e and the osc1 clock is output without frequenc y di vision. d[3:2] foutasrc[1:0]: fouta clock source select bits selects the fout a clock source. 8.8 fout a cloc k source selection t ab le 7. fout asrc[1:0] cloc k sour ce s1c17554 s1c17564 0x3 reser v ed 0x2 osc3 osc3 0x1 osc1 osc1 0x0 reser v ed iosc (def ault: 0x0) d1 reserved d0 foutae: fouta output enable bit enables or disables fout a clock e xternal output. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) setting fout ae to 1 outputs the fout a clock from the fout a pin. setting it to 0 stops the output. 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-15 foutb control register (clg_foutb) register name ad dress bit name function setting init. r/w remarks foutb control register (clg_foutb ) s1c17554 0x5065 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutbd [1:0] foutb cloc k division r atio select foutbd[1:0] division r atio 0x0 r/w when the cloc k source is osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w foutb control register (clg_foutb ) s1c17564 0x5065 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutbd [1:0] foutb cloc k division r atio select foutbd[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w d[7:6] reserved d[5:4] foutbd[1:0]: foutb clock division ratio select bits selects the clock di vision ratio to set the fo utb clock frequenc y when osc3 or iosc is used as the clock source. 8.9 osc3/iosc division ratio selection t ab le 7. foutbd[1:0] division ratio 0x3 reser v ed 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) when osc1 is used as the clock source, foutbd[1:0] is inef fecti v e and the osc1 clock is output without frequenc y di vision. d[3:2] foutbsrc[1:0]: foutb clock source select bits selects the foutb clock source. 8.10 foutb cloc k source selection t ab le 7. foutbsrc[1:0] cloc k sour ce s1c17554 s1c17564 0x3 reser v ed 0x2 osc3 osc3 0x1 osc1 osc1 0x0 reser v ed iosc (def ault: 0x0) d1 reserved d0 foutbe: foutb output enable bit enables or disables foutb clock e xternal output. 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) setting foutbe to 1 outputs the foutb clock from the foutb pin. setting it to 0 stops the output. 7 clock genera t or (clg) 7-16 seiko epson corporation s1c17554/564 t echnical m anual iosc control register (clg_iosc) register name ad dress bit name function setting init. r/w remarks iosc control register (clg_iosc ) s1c17564 0x506e (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 ioscsel [1:0] iosc frequency select ioscsel[1:0] f requency 0x1 r/w 0x3 0x2 0x1 0x0 2 mhz 4 mhz 12 mhz 8 mhz d[7:2] reserved d[1:0] reserved (s1c17554) ioscsel[1:0]: iosc frequency select bits (s1c17564) selects the iosc oscillation frequenc y . 8.11 iosc oscillation f requency setting t ab le 7. ioscsel[1:0] iosc oscillation frequenc y (typ.) 0x3 2 mhz 0x2 4 mhz 0x1 12 mhz 0x0 8 mhz (def ault: 0x1) pclk control register (clg_pclk) register name ad dress bit name function setting init. r/w remarks pclk control register (clg_pclk ) 0x5080 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 pcken[1:0] pclk enab le pcken[1:0] pclk supply 0x3 r/w 0x3 0x2 0x1 0x0 enab le not allo w ed not allo w ed disab le d[7:2] reserved d[1:0] pcken[1:0]: pclk enable bits enables or disables clock (pclk) supply to the internal peripheral modules. 8.12 pclk control t ab le 7. pcken[1:0] pclk suppl y 0x3 enab led (on) 0x2 setting prohibited 0x1 setting prohibited 0x0 disab led (off) (def ault: 0x3) the pcken[1:0] def ault setting is 0x3, which enables clock supply . p er ipher al modules that use pclk ? u ar t ch.0 and 1 ? fine mode 16-bit timer ch.0 and 1 ? 16-bit timer ch.0 to 2 ? spi ch.0 to 2 ? usi ch.0 and 1 (s1c17564) ? i 2 c master ? i 2 c sla v e ? po wer generator (s1c17564) ? p port & port mux ? misc re gisters ? ir remote controller ? a/d con v erter the pclk supply cannot be disabled if one or more peripheral modules in these list must be oper - ated. the pclk supply can be disabled if all the peripheral circuits in these list can be stopped. 7 clock genera t or (clg) s1c17554/564 t echnical m anual seiko epson corporation 7-17 stop the pclk supply to reduce current consumption if all the peripheral modules listed abo v e are not required. p er ipher al modules/functions that do not use pclk ? clock timer ? stopw atch timer ? w atchdog timer ? 16-bit pwm timer ch.0 to 3 ? fout a/foutb outputs these peripheral modules/functions can operate e v en if pclk is stopped. note: do not set pcken[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain per iph- er al modules . cclk control register (clg_cclk) register name ad dress bit name function setting init. r/w remarks cclk control register (clg_cclk ) 0x5081 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 cclkgr[1:0] cclk cloc k gear r atio select cclkgr[1:0] gear r atio 0x0 r/w 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d[7:2] reserved d[1:0] cclkgr[1:0]: cclk clock gear ratio select bits selects the gear ratio for reducing system clock speed and sets the cclk clock speed for operating the s1c17 core. t o reduce current consumption, operate the s1c17 core using the slo west possible clock speed. 8.13 cclk gear ratio selection t ab le 7. cclkgr[1:0] gear ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-1 i/o p orts (p) 8 p module over vie w 8.1 the p ports are general-purpose digital inputs/outputs that allo w softw are to control the input/output direction, pull- up resistor , and input interf ace le v el. each port can generate interrupts caused by a transition of the input signal. these ports are shared with internal peripheral module inputs/outputs, and the pin functions can be switched by set- ting the re gisters. the follo wing sho ws the features of the p module: ? s1c17564, s1c17554 (tqfp package) maximum 40 i/o ports (p0[3:0], p1[7:0], p2[7:0], p3[7:0], p4[5:0], p5[5:0]) are a v ailable. s1c17554 (wcsp package) maximum 34 i/o ports (p0[3:0], p1[7:0], p2[7:0], p3[7:0], p4[5:0]) are a v ailable. * the number of ports for general-purpose use depends on the peripheral functions used. ? each port has a pu ll-up resistor that can be enabled with softw are. ? each port can generate input interrupts at the signal edge selected with softw are. ? each port includes a chattering f ilter . ? can generate an initial reset by entering lo w le v el simultaneously to the p0 ports selected with softw are. ? all port pro vide a port function select bit to conf igure the pin function (for gpio or peripheral functions). figure 8.1.1 sho ws the i/o port conf iguration. peripheral output peripheral i/o control pxpuy pxoeny pxouty pxymux pull-up enable output enable output data function selection hv dd v ss internal data bus pxy peripheral module input pxieny pxcf1[2:0]/pxcf2[2:0] chattering filter input enable 1.1 i/o p or t configur ation figure 8. notes: ? the pclk cloc k m ust be supplied from the cloc k gener ator to access the i/o por t. the pclk cloc k is also needed to oper ate the chatter ing filters . ? the xy in the register and bit names ref ers to the por t n umber (pxy, x = 0 to 5, y = 0 to 7). example: pxiny/px_in register p00: p0in0/p0_in register p17: p1in7/p1_in register 8 i/o por ts (p) 8-2 seiko epson corporation s1c17554/564 t echnical m anual input/output pin function selection (p or t mux) 8.2 the i/o port pins share peripheral module input/output pins. each pin can be conf igured for use as an i/o port or for a peripheral module function via the corresponding port function-select bits. pins not used for peripheral mod- ules can be used as general-purpose i/o ports. 2.1 input/output pin function selection t ab le 8. pin function 1 pxymux[1:0] = 0x0 pin function 2 pxymux[1:0] = 0x1 pin function 3 pxymux[1:0] = 0x2 pin function 4 pxymux[1:0] = 0x3 p or t function select bits p00 ain0 (adc10) C C p00mux[1:0]/p00_03pmux register p01 ain1 (adc10) C C p01mux[1:0]/p00_03pmux register p02 ain2 (adc10) us_ssi0 (usi)* C p02mux[1:0]/p00_03pmux register p03 ain3 (adc10) us_ssi1 (usi)* C p03mux[1:0]/p00_03pmux register p10 sdi0 (spi) C C p10mux[1:0]/p10_13p mux register p11 sdo0 (spi) C C p11mux[1:0]/p10_13pmux register p12 spiclk0 (spi) C C p12mux[1:0]/p10_13pmux register p13 #spiss0 (spi) t out5/cap5 (t16a) C p13mux[1:0]/p10_13pmux register p14 sin1 (u ar t) sdi1 (spi) C p14mux[1:0]/p14_17pmux register p15 sout1 (u ar t) sdo1 (spi) C p15mux[1:0]/p14_17pmux register p16 sclk1 (u ar t) spiclk1 (spi) C p16mux[1:0]/p14_17pmux register p17 scl0 (i2cm) C C p17mux[1:0]/p14_17pmux register p20 t out2 /cap2 (t16a) C C p20mux[1:0]/p20_23pmux register p21 t out3/cap3 (t16a) C C p21mux[1:0]/p20_23pmux register p22/excl1 (t16a) foutb (clg) C C p22mux[1:0]/p20_23pmux register p23/excl2 (t16a) sdi2 (spi) C C p23mux[1:0]/p20_23pmux register p24/excl3 (t16a) sdo2 (spi) C C p24mux[1:0]/p24_27pmux register p25 #bfr (i2cs) #spiss2 (spi) C p25mux[1:0]/p24_27pmux register p26 sd a1 (i2cs) C C p26mux[1:0]/p24_27pmux register p27 scl1 (i2cs) C C p2 7mux[1:0]/p24_27pmux register p30 t out0/cap0 (t16a) C C p30mux[1:0]/p30_33pmux register p31 #bfr (i2cs) #adtrg (adc10) C p31mux[1:0]/p30_33pmux register p32 t out4/cap4 (t16a) fout a (clg) C p32mux[1:0]/p30_33pmux register p33 remi (remc) spiclk2 (spi) C p33mux[1:0]/p30_33pmux register p34 remo (remc) #spiss1 (spi) C p34mux[1:0]/p34_37pmux register dclk (dbg) p35 C C p35mux[1:0]/p34_37pmux register dsio (dbg) p36 C C p36mux[1:0]/p34_ 37pmux register dst2 (dbg) p37 C C p37mux[1:0]/p34_37pmux register p40 sin0 (u ar t) t out6/cap6 (t16a) C p40mux[1:0]/p40_43pmux register p41 sout0 (u ar t) t out7/cap7 (t16a) C p41mux[1:0]/p40_43pmux register p42 sclk0 (u ar t) t out1/cap1 (t16a) C p42mux[1:0]/p40_43pmux register p43 sd a1 (i2cs) remi (remc) C p43mux[1:0]/p40_33pmux register p44 scl1 (i2cs) remo (remc) C p44mux[1:0]/p44_45pmux register p45/excl0 (t16a) sd a0 (i2cm) C C p45mu x[1:0]/p44_45pmux register p50 us_sdi0 (usi)* C C p50mux[1:0]/p50_53pmux register p51 us_sdo0 (usi)* C C p51mux[1:0]/p50_53pmux register p52 us_sck0 (usi)* C C p52mux[1:0]/p50_53pmux register p53 us_sdi1 (usi)* C C p53mux[1:0]/p50_53pmux register p54 us_sdo1 (usi)* C C p54mux[1:0]/p54_55pmux register p55 us_sck1 (usi)* C C p55mux[1:0]/p54_55pmux register * a v ailab le only in s1c17564 at initial reset, each i/o port pin (pxy) is in itialized for the def ault function (pin function 1 in t able 8.2.1). pins p22, p23, p24, and p45 can also be used as 16-bit pwm timer e xternal clock input pins by setting them to in- put mode. ho we v er , general-purpose input port function is also ef fecti v e in this case. f or information on functions other than the i/o ports, see the descriptions of the peripheral modules indicated in parentheses. the sections belo w describe port functions with the pins set as general-purpose i/o ports. 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-3 data input/output 8.3 data input/output contr ol t h e i / o p o r t s a l l o w s e l e c t i o n o f t h e d a t a i n p u t / o u t p u t d i r e c t i o n f o r e a c h b i t u s i n g p x o e n y / p x _ o e n r e g i s t e r a n d pxieny/px_ien re gister . pxoeny enables and disables data output, while pxieny enables and disables data input. 3.1 data input/output status t ab le 8. pxoeny output contr ol pxieny input contr ol pxpuy pull-up contr ol p or t status 0 1 0 functions as an input por t (pull-up off). the por t pin (e xter nal input signal) v alue can be read out from pxiny (input data). output is disab led. 0 1 1 functions as an input por t (pull-up on). (def ault) the por t pin (e xter nal input signal) v alue can be read out from pxiny (input data). output is disab led. 1 0 1 or 0 functions as an out put por t (pull-up off). input is disab led. the v alue read from pxiny (input data) is 0. 1 1 1 or 0 functions as an output por t (pull-up off). input is also enab led. the por t pin v alue (output v alue) can be read out from pxiny (input data). 0 0 0 the pin is placed into high-impedance status (pull-up off). output and input are both disab led. the v alue read from pxiny (input data) is 0. 0 0 1 the pin is placed into high-impedance status (pull-up on). output and input are both disab led. the v alue read from pxiny (input data) is 0. the input/output direction of ports with a peripheral module function selected is controlled by the peripheral module. pxoeny and pxieny settings are ignored. data input t o input the port pin status and read out the v alue, enable input by setting pxieny to 1 (def ault). t o input an e x ternal signal, pxoeny should also be set to 0 (def ault). the i/o port is placed into high-imped- ance status and it functions as an input port (input mode). the port is pulled up if pull-up is enabled by pxpuy/ px_pu re gister . in input mode, the input pin status can be read out directly from pxiny/px_in re gister . the v alue read will be 1 when the input pin is at high (hv dd ) le v el and 0 when it is at lo w (v ss ) le v el. the port pin status is al w ays input when pxieny is 1, e v en if output is enabled (pxoeny = 1) (output mode). in this case, the v alue actually output from the port can be read out from pxiny. when pxieny is set to 0, input is disabled, and 0 will be read out from pxiny. data output t o output data from the port pin, enable output by setting pxoeny to 1 (set to output mode). the i/o p ort then functions as an output port, and the v alue set in the pxouty/px_out re gister is output from the port pin. the port pin outputs high (hv dd ) le v el when pxouty is set to 1 and lo w (v ss ) le v el when set to 0. note that the port will not be pulled up in output mode, e v en if pull-up is enabled by pxpuy. writing to pxouty is possible without af fecting pin status, e v en in input mode. pull-up contr o l 8.4 the i/o port contains a pull-up resistor that can be enabled or disabled indi vidually for each bit using pxpuy/px_ pu re gister . setting pxpuy to 1 (def ault) enables the pull-up resistor and pulls up the port pin in input mode. it will not be pulled up if set to 0. the pxpuy setting is ignored and not pulled up in output mode, re g ardless of ho w the pxieny is set. i/o ports that are not used sho uld be set with pull-up enabled. this pull-up setting is also enabled for ports for which the peripheral module function has been selected. 8 i/o por ts (p) 8-4 seiko epson corporation s1c17554/564 t echnical m anual a delay will occur in the w a v eform rising edge depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from lo w le v el to high le v el through the internal pull-up resistor . an ap- propriate w ait time must be set for the i/o port loading. the w ait time set should be a v alue not less than that calcu- lated from the follo wing equation. w ait time = r in (c in + load capacitance on board) 1.6 [s] r in : pull-up resistance maximum v alue, c in : pin capacitance maximum v alue p0Cp3 p or t chattering filter function 8.5 the i/o ports include a chattering f ilter circuit for k e y entry that can be disabled or enabled with a check time spec- if ied indi vidually for the four px[3:0] and px[7:4] ports using pxcf1[2:0]/px_cha t re gister and pxcf2[2:0]/px_ cha t re gist er , respecti v ely . 5.1 chatter ing filter function settings t ab le 8. pxcf1[2:0]/pxcf2[2:0] chec k time * 0x7 16384/f pclk (8 ms) 0x6 8192/f pclk (4 ms) 0x5 4096/f pclk (2 ms) 0x4 2048/f pclk (1 ms) 0x3 1024/f pclk (512 s) 0x2 512/f pclk (256 s) 0x1 256/f pclk (128 s) 0x0 no chec k time (off) (def ault: 0x0, * when pclk = 2 mhz) notes: ? t h e c h a t t e r i n g f i l t e r c h e c k t i m e r e f e r s t o t h e m a x i m u m p u l s e w i d t h t h a t c a n b e f i l t e r e d . gener ating an input interr upt requires a minim um input time of th e chec k time and a maxim um input time of twice the chec k time . ? the px por t interr upt m ust be disab led bef ore setting the px_cha t register . setting the regis- ter while the interr upt is enab led ma y gener ate inadv er tent px por t interr upt. also the chatter- ing filter circuit requires a maxim um of twice the chec k time f or stabilizing the oper ation status . bef ore enab ling the interr upt, mak e sure that the stabilization time has elapsed. p or t input interrupt 8.6 the i/o ports include input interrupt functions. select which of the 40 ports are to be used for interrupts based on requirements. y ou can also select whether inter - rupts are generated for either the rising edge or f alling edge of the input signals. figure 8.6.1 sho ws the port input interrupt circuit conf iguration. px port interrupt request (to itc) (px = p0 to p5) chattering filter interrupt flag interrupt enable interrupt edge selection px0 pxcf1[2:0] pxedge0 pxif0 pxie0 px7 pxcf2[2:0] pxedge7 pxif7 pxie7 ? ? ? 6.1 p or t input interr upt circuit configur ation figure 8. 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-5 interrupt por t selection select the port generating an interrupt using pxiey/px_imsk re gister . setting pxiey to 1 enables interrupt generation by the corresponding port. setting to 0 (def ault) disables inter - rupt generation. interrupt edg e selection p o r t i n p u t i n t e r r u p t s c a n b e g e n e r a t e d a t e i t h e r t h e r i s i n g e d g e o r f a l l i n g e d g e o f t h e i n p u t s i g n a l . s e l e c t t h e e d g e used to generate interrupts using pxedgey/px_edge re gister . setting pxedgey to 1 generates port input interrupts at the input signal f alling edge. setting it to 0 (def ault) generates interrupts at the rising edge. interrupt fla gs the itc is able to accept six interrupt requests from the p0Cp5 ports, and the p port module contains interrupt flags pxify/px_iflg re gister corresponding to the indi vidual 40 ports to enable indi vidual c ontrol of the 40 pxy port interrupts. pxify is set to 1 at the specif ied edge (rising or f alling edge) of the input signal. if the cor - responding pxiey has been set to 1, an interrupt request signal is also output to the itc at the same time. an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. pxify is reset by writing 1. f or specif ic information on interrupt pro cessing, see the interrupt controller (itc) chapter . notes: ? the p por t module interr upt flag pxify m ust be reset in the interr upt handler routine after a por t interr upt has occurred to pre v ent recurr ing interr upts . ? t o pre v ent gener ating unnecessar y interr upts , reset the rele v ant pxify bef ore enab ling inter- r upts f or the required por t using pxiey. p0 p or t k e y-entr y reset 8.7 entering lo w le v el sim ultaneously to the ports (p00Cp03) selected with softw are triggers an initial reset. the ports used for the reset function can be selected with the p0krst[1:0]/p0_krst re gister . 7.1 configur ation of p0 p or t k e y-entr y reset t ab le 8. p0krst[1:0] p or t used f or resetting 0x3 p00, p01, p02, p03 0x2 p00, p01, p02 0x1 p00, p01 0x0 not used (def ault: 0x0) f or e xample, if p0krst[1:0] is set to 0x3, an initial reset will tak e place when the four ports p00Cp03 are set to lo w le v el at the same time. note: the p0 po r t k e y-entr y rese t funct ion cannot be use d f or po w er-on reset as i t m ust be enab led wit h softw are . contr ol register details 8.8 8.1 list of i/o p or t control registers t ab le 8. ad dress register name function 0x5200 p0_in p0 p or t input data register p0 por t input data 0x5201 p0_out p0 p or t output data register p0 por t output data 0x5202 p0_oen p0 p or t output enab le register enab les p0 por t outputs . 0x5203 p0_pu p0 p or t pull-up control register controls the p0 por t pull-up resistor . 0x5205 p0_imsk p0 p or t interr upt mask register enab les p0 por t interr upts . 0x5206 p0_edge p0 p or t interr upt edge sel ect register selects the signal edge f or gener ating p0 por t interr upts . 0x5207 p0_iflg p0 p or t interr upt flag register indicates/resets the p0 por t interr upt occurrence status . 0x5208 p0_cha t p0 p or t chatter ing filter control register controls the p0 por t chatter ing filter . 0x5209 p0_krst p0 p or t k e y-entr y reset configur ation register configures the p0 por t k e y-entr y reset function. 8 i/o por ts (p) 8-6 seiko epson corporation s1c17554/564 t echnical m anual ad dress register name function 0x520a p0_ien p0 p or t input enab le register enab les p0 por t inputs . 0x5210 p1_in p1 p or t input data register p1 por t input data 0x5211 p1_out p1 p or t output data register p1 por t output data 0x5212 p1_oen p1 p or t output enab le register enab les p1 por t outputs . 0x5213 p1_pu p1 p or t pull-up control register controls the p1 por t pull-up resistor . 0x5215 p1_imsk p1 p or t interr upt mask register en ab les p1 por t interr upts . 0x5216 p1_edge p1 p or t interr upt edge select register selects the signal edge f or gener ating p1 por t interr upts . 0x5217 p1_iflg p1 p or t interr upt flag register indicates/resets the p1 por t interr upt occurrence status . 0x5218 p1_cha t p1 p or t chatter ing filter control register controls the p1 por t chatter ing filter . 0x521a p1_ien p1 p or t input enab le register enab les p1 por t inputs . 0x5220 p 2_in p2 p or t input data register p2 por t input data 0x5221 p2_out p2 p or t output data register p2 por t output data 0x5222 p2_oen p2 output enab le register enab les p2 por t outputs . 0x5223 p2_pu p2 p or t pull-up control register controls the p2 por t pull-up resistor . 0x5225 p2_imsk p2 p or t interr upt mask register enab les p2 por t interr upts . 0x5226 p2_edge p2 p or t interr upt edge select register selects the signal edge f or gener ating p2 por t interr upts . 0x5227 p2_iflg p2 p or t interr upt flag register indicates/resets the p2 por t interr upt occurrence status . 0x5228 p2_cha t p2 p or t chatter ing filter control register controls the p2 por t chatter ing filter . 0x522a p2_ien p2 p or t input enab le register enab les p2 por t inputs . 0x5230 p3_in p3 p or t input data register p3 por t input data 0x5231 p3_out p3 p or t output data register p3 por t output data 0x5232 p3_oen p3 p or t output enab le register enab les p3 por t outputs . 0x5233 p3_pu p3 p or t pull-up control register controls the p3 por t pull-up resistor . 0x5235 p3_imsk p3 p or t interr upt mask register enab les p3 por t interr upts . 0x5236 p3_edge p3 p or t interr upt edge select register selects the signal edge f or gener ating p3 por t interr upts . 0x5237 p3_iflg p3 p or t interr upt flag register indicates/resets the p3 p or t interr upt occurrence status . 0x5238 p3_cha t p3 p or t chatter ing filter control register controls the p3 por t chatter ing filter . 0x523a p3_ien p3 p or t input enab le register enab les p3 por t inputs . 0x5240 p4_in p4 p or t input data register p4 por t input data 0x5241 p4_out p4 p or t output data register p4 por t output data 0x5242 p4_oen p4 p or t output enab le register enab les p4 por t outputs . 0x5243 p4_pu p4 p or t pull-up co ntrol register controls the p4 por t pull-up resistor . 0x5245 p4_imsk p4 p or t interr upt mask register enab les p4 por t interr upts . 0x5246 p4_edge p4 p or t interr upt edge select register selects the signal edge f or gener ating p4 por t interr upts . 0x5247 p4_iflg p4 p or t interr upt flag register indicates/resets the p4 por t interr upt occurrence status . 0x5248 p4_cha t p4 p or t chatter ing filter control register controls the p4 por t chatter ing filter . 0x524a p4_ien p4 p or t input enab le register enab les p4 por t inputs . 0x5250 p5_in p5 p or t input data register p5 por t input data 0x5251 p5_out p5 p or t output data register p5 por t output data 0x5252 p5_oen p5 p or t output enab le register enab les p5 por t outputs . 0x5253 p5_pu p5 p or t pull-up control register controls the p5 por t pull-up resistor . 0x5255 p5_imsk p5 p or t interr upt mask register ena b les p5 por t interr upts . 0x5256 p5_edge p5 p or t interr upt edge select register selects the signal edge f or gener ating p5 por t interr upts . 0x5257 p5_iflg p5 p or t interr upt flag register indicates/resets the p5 por t interr upt occurrence status . 0x5258 p5_cha t p5 p or t chatter ing filter control register controls the p5 por t chatter ing filter . 0x525a p5_ien p5 p or t input enab le register enab les p5 por t inputs . 0x52a0 p0 0_03pmux p0[3:0] p or t function select register selects the p0[3:0] por t functions . 0x52a2 p10_13pmux p1[3:0] p or t function select register selects the p1[3:0] por t functions . 0x52a3 p14_17pmux p1[7:4] p or t function select register selects the p1[7:4] por t functions . 0x52a4 p20_23pmux p2[3:0] p or t function select register selects the p2[3:0] por t functions . 0x52a5 p24_27pmux p2[7:4] p or t function select register sel ects the p2[7:4] por t functions . 0x52a6 p30_33pmux p3[3:0] p or t function select register selects the p3[3:0] por t functions . 0x52a7 p34_37pmux p3[7:4] p or t function select register selects the p3[7:4] por t functions . 0x52a8 p40_43pmux p4[3:0] p or t function select register selects the p4[3:0] por t functions . 0x52a9 p44_45pmux p4[5:4] p or t function select register selects the p4[5:4] por t functions . 0x52aa p50_53pmux p5[3:0] p or t function select register selects the p5[3:0] por t functions . 0x52ab p54_55pmux p5[5:4] p or t function select register selects the p5[5:4] por t functions . the i/o port re gisters are described in detail belo w . these are 8-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-7 px port input data registers (px_in) register name ad dress bit name function setting init. r/w remarks px port input data register (px_in) 0x5200 0x5210 0x5220 0x5230 0x5240 0x5250 (8 bits) d7C0 pxin[7:0] px[7:0] por t input data 1 1 (h) 0 0 (l) r note: p0in[3:0] only are a v ailab le f or the p0 por ts . pxin[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px in[7:0]: px [7:0] port input data bits the port pin status can be read out. (def ault: e xternal input status) 1 (r): high le v el 0 (r): lo w le v el pxiny corresponds directly to the pxy pin. the pin v oltage le v el can be read out when input is enabled (pxieny = 1) (e v en if output is also enabled (pxoeny = 1)). the v alue read out will be 1 when the pin v oltage is high and 0 when lo w . the v alue read out is 0 when input is disabled (pxieny = 0). writing operations to the read-only pxiny is disabled. px port output data registers (px_out) register name ad dress bit name function setting init. r/w remarks px port output data register (px_out) 0x5201 0x5211 0x5221 0x5231 0x5241 0x5251 (8 bits) d7C0 pxout[7:0] px[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w note: p0out[3:0] only are a v ailab le f or the p0 por ts . pxout[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px out[7:0]: px [7:0] port output data bits sets the data to be output from the port pin. 1 (r/w): high le v el 0 (r/w): lo w le v el (def ault) pxouty corresponds directly to the pxy pins. the data written will be output unch anged from the port pins when output is enabled (pxoeny = 1). the port pin will be high when the data bit is set to 1 and lo w when set to 0. port data can also be written when output is disabled (pxoeny = 0) (the pin status is unaf fected). px port output enable registers (px_oen) register name ad dress bit name function setting init. r/w remarks px port output enable register (px_oen) 0x5202 0x5212 0x5222 0x5232 0x5242 0x5252 (8 bits) d7C0 pxoen[7:0] px[7:0] por t output enab le 1 enab le 0 disab le 0 r/w note: p0oen[3:0] only are a v ailab le f or the p0 por ts . pxoen[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. 8 i/o por ts (p) 8-8 seiko epson corporation s1c17554/564 t echnical m anual d[7:0] px oen[7:0]: px [7:0] port output enable bits enables or disables port outputs. 1 (r/w): enabled 0 (r/w): disabled (def ault) pxoeny is the output enable bit that corresponds directly to pxy port. setting to 1 enables output and the data set in pxouty is output from the port pin. output is disabled when pxoeny is set to 0, and the port pin is set into high-impedance status. the peripheral module determines whether output is enabled or dis abled when the port is used for a peripheral module function. refer to t able 8.3.1 for more information on input/output status for ports, including settings other than for the pxoen re gister . px port pull-up control registers (px_pu) register name ad dress bit name function setting init. r/w remarks px port pull-up control register (px_pu) 0x5203 0x5213 0x5223 0x5233 0x5243 0x5253 (8 bits) d7C0 pxpu[7:0] px[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w note: p0p u [3:0] o n l y a r e a v a i l a b l e f o r t h e p0 p o r t s . p x p u [5:0] o n l y a r e a v a i l a b l e f o r t h e p4 a n d p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px pu[7:0]: px [7:0] port pull-up enable bits enables or disables the pull-up resistor included in each port. 1 (r/w): enabled (def ault) 0 (r/w): disabled pxpuy is the pull-up control bit that corresponds direct ly to the pxy port. setting to 1 enables the pull- up resistor and the port pin will be pulled up when output is disabled (pxoeny = 0). when pxpuy is set to 0, the pin will not be pulled up. when output is enabled (pxoeny = 1), the pxpuy setting is ignored, and the pin is not pulled up. i/o ports that are not used should be set with pull-up enabled. this pull-up setting is also enabled for ports for which the peripheral module input function is selected. px port interrupt mask registers (px_imsk) register name ad dress bit name function setting init. r/w remarks px port interrupt mask register (px_imsk) 0x5205 0x5215 0x5225 0x5235 0x5245 0x5255 (8 bits) d7C0 pxie[7:0] px[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w note: p0ie[3:0] only are a v ailab le f or the p0 por ts . pxie[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px ie[7:0]: px [7:0] port interrupt enable bits enables or disables each port interrupt. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting pxiey to 1 enables the corresponding pxy port input int errupt, while setting to 0 disables the in- terrupt. status changes for the input pins with interrupt disabled do not af fect interrupt occurrence. 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-9 px port interrupt edge select registers (px_edge) register name ad dress bit name function setting init. r/w remarks px port interrupt edge select register (px_edge) 0x5206 0x5216 0x5226 0x5236 0x5246 0x5256 (8 bits) d7C0 pxedge[7:0] px[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w note: p0edge[3:0] only are a v ailab le f or the p0 por ts . pxedge[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px edge[7:0]: px [7:0] port interrupt edge select bits selects the input signal edge for generating each port interrupt. 1 (r/w): f alling edge 0 (r/w): rising edge (def ault) port interrupts are generated at the input signal f alling edge when pxedgey is set to 1 and at the rising edge when set to 0. px port interrupt flag registers (px_iflg) register name ad dress bit name function setting init. r/w remarks px port interrupt flag register (px_iflg) 0x5207 0x5217 0x5227 0x5237 0x5247 0x5257 (8 bits) d7C0 pxif[7:0] px[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. note: p0if[3:0] only are a v ailab le f or the p0 por ts . pxif[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px if[7:0]: px [7:0] port interrupt flag bits these are interrupt flags indicating the interrupt cause occurrence status. 1 (r): interrupt cause occurre d 0 (r): no interrupt cause occurred (def ault) 1 (w): reset flag 0 (w): ignored pxify is the interrupt flag that corresponds directly to the pxy port and is set to 1 at the specif ied edge (rising or f alling edge) of the input signal. when the corresponding pxiey/px_imsk re gister has been set to 1, a port interrupt request signal is also output to the itc at the same time. an interrupt is gener - ated if the itc and s1c17 core interrupt conditions are satisf ied. pxify is reset by writing 1. notes: ? the p por t module interr upt flag pxify m ust be reset in the interr upt handler routine after a por t interr upt has occurred to pre v ent recurr ing interr upts . ? t o pre v ent gener ating unnecessar y interr upts , reset the rele v ant pxify bef ore enab ling in- terr upts f or the required por t using pxiey/px_imsk regist er . 8 i/o por ts (p) 8-10 seiko epson corporation s1c17554/564 t echnical m anual px port chattering filter control registers (px _chat) register name ad dress bit name function setting init. r/w remarks px port chattering filter control register (px _chat) 0x5208 0x5218 0x5228 0x5238 0x5248 0x5258 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 pxcf2[2:0] px[7:4] chatter ing filter time select pxcf2[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none d3 C reser v ed C C C 0 when being read. d2C0 pxcf1[2:0] px[3:0] chatter ing filter time select pxcf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pcl k 512/f pclk 256/f pclk none note: p0cf1[2:0] only are a v ailab le f or the p0 por ts . other bits are reser v ed and alw a ys read as 0. d7 reserved d[6:4] px cf2[2:0]: px [7:4] chattering filter time select bits conf igures the chattering f ilter circuit for the px[7:4] ports. d3 reserved d[2:0] px cf1[2:0]: px [3:0] chattering filter time select bits conf igures the chattering f ilter circuit for the px[3:0] ports. t h e i / o p o r t s i n c l u d e a c h a t t e r i n g f i l t e r c i r c u i t f o r k e y e n t r y t h a t c a n b e d i s a b l e d o r e n a b l e d w i t h a c h e c k t i m e s p e c i f i e d i n d i v i d u a l l y f o r t h e f o u r p x [3:0] a n d p x [7:4] p o r t s u s i n g p x c f1[2:0] a n d pxcf2[2:0], respecti v ely . 8.2 chatter ing filter function settings t ab le 8. pxcf1[2:0]/pxcf2[2:0] chec k time * 0x7 16384/f pclk (8 ms) 0x6 8192/f pclk (4 ms) 0x5 4096/f pclk (2 ms) 0x4 2048/f pclk (1 ms) 0x3 1024/f pclk (512 s) 0x2 512/f pclk (256 s) 0x1 256/f pclk (128 s) 0x0 no chec k time (off) (def ault: 0x0, * when pclk = 2 mhz) notes: ? the chatter ing filter chec k time ref ers to the maxim um pulse width that can be filtered. gen- er ating an input interr upt requires a minim um input time of t he chec k time and a maxim um input time of twice the chec k time . ? the px por t interr upt m ust be disab led bef ore setting the px_cha t register . setting the reg- i s t e r w h i l e t h e i n t e r r u p t i s e n a b l e d m a y g e n e r a t e i n a d v e r t e n t p x i n t e r r u p t . a l s o t h e c h a t t e r i n g filter circuit requires a maxim um of twice the chec k time f or stabilizing the oper ation status . bef ore enab ling the interr upt, mak e sure that the stabilization time has elapsed. p0 port key-entry reset configuration register (p0_krst) register name ad dress bit name function setting init. r/w remarks p0 port key- entry reset configuration register (p0_krst) 0x5209 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 p0krst[1:0] p0 por t k e y-entr y reset configur ation p0krst[1:0] configur ation 0x0 r/w 0x3 0x2 0x1 0x0 p0[3:0] p0[2:0] p0[1:0] disab le 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-11 d[7:2] reserved d[1:0] p0krst[1:0]: p0 port key-entry reset configuration bits selects the port combination used for p0 port k e y-entry reset. 8.3 p0 p or t k e y-entr y reset settings t ab le 8. p0krst[1:0] p or ts used f or resetting 0x3 p00, p01, p02, p03 0x2 p00, p01, p02 0x1 p00, p01 0x0 not used (def ault: 0x0) the k e y-entry reset function performs an initial reset by inputting lo w le v el simultaneously to the ports selected here. f or e xample, if p0krst[1:0] is set to 0x3, an initial reset is performed when the four ports p00 to p03 are simultaneously set to lo w le v el. set p0krst[1:0] to 0x0 when t his reset function is not used. note: the p0 por t k e y-entr y reset function is disab led at initial reset and cannot be used f or po w er- on reset. px port input enable registers (px_ien) register name ad dress bit name function setting init. r/w remarks px port input enable register (px_ien) 0x520a 0x521a 0x522a 0x523a 0x524a (8 bits) d7C0 pxien[7:0] px[7:0] por t input enab le 1 enab le 0 disab le 1 (0xff) r/w note: p0ien[3:0] only are a v ailab le f or the p0 por ts . pxien[5:0] only are a v ailab le f or the p4 and p5 por ts . other bits are reser v ed and alw a ys read as 0. d[7:0] px ien[7:0]: px [7:0] port input enable bits enables or disables port inputs. 1 (r/w): enable (def ault) 0 (r/w): disable pxieny is the input enable bit that corresponds directly to the pxy port. setting to 1 ena bles input and the corresponding port pin input or output signal le v el can be read out from the px_in re gister . setting to 0 disables input. refer to t able 8.3.1 for more information on port input/output status, including settings other than for the px_ien re gister . p0[3:0] port function select register (p00_03pmux) register name ad dress bit name function setting init. r/w remarks p0[3:0] port function select register (p00_03pmux) 0x52a0 (8 bits) d7C6 p03mux[1:0] p03 por t function select p03mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed us_ssi1* ain3 p03 d5C4 p02mux[1:0] p02 por t function select p02mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed us_ssi0* ain2 p02 d3C2 p01mux[1:0] p01 por t function select p01mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed ain1 p01 d1C0 p00mux[1:0] p00 por t function select p00mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed ain0 p00 8 i/o por ts (p) 8-12 seiko epson corporation s1c17554/564 t echnical m anual the p00 to p03 port pins are shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p03mux[1:0]: p03 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): usi_ssi1 (s1c17564 usi ch.1) 0x1 (r/w): ain3 (adc10) 0x0 (r/w): p03 port (def ault) d[5:4] p02mux[1:0]: p02 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): usi_ssi0 (s1c17564 usi ch.0) 0x1 (r/w): ain2 (adc10) 0x0 (r/w): p02 port (def ault) d[3:2] p01mux[1:0]: p01 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 ( r/w): ain1 (adc10) 0x0 (r/w): p01 port (def ault) d[1:0] p00mux[1:0]: p00 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): ain0 (adc10) 0x0 (r/w): p00 port (def ault) p1[3:0] port function select register (p10_13pmux) register name ad dress bit name function setting init. r/w remarks p1[3:0] port function select register (p10_13pmux) 0x52a2 (8 bits) d7C6 p13mux[1:0] p13 por t function select p13mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out5/cap5 #spiss0 p13 d5C4 p12mux[1:0] p12 por t function select p12mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed spiclk0 p12 d3C2 p11mux[1:0] p11 por t function select p11mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdo0 p11 d1C0 p10mux[1:0] p10 por t function select p10mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdi0 p10 the p10 to p13 port pin s are shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p13mux[1:0]: p13 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): t out5 (t16a ch.2 comparator mode) or cap5 (t16a ch.2 capture mode) 0x1 (r/w): #spiss0 (spi ch.0) 0x0 (r/w): p13 port (def ault) d[5:4] p12mux[1:0]: p12 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): spiclk0 (spi ch.0) 0x0 (r/w): p12 port (def ault) 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-13 d[3:2] p11mux[1:0]: p11 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sdo0 (spi ch.0) 0x0 (r/w): p11 port (def ault) d[1:0] p10mux[1:0]: p10 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sdi0 (spi ch.0) 0x0 (r/w): p10 port (def ault) p1[7:4] port function select register (p14_17pmux) register name ad dress bit name function setting init. r/w remarks p1[7:4] port function select register (p14_17pmux) 0x52a3 (8 bits) d7C6 p17mux[1:0] p17 por t function select p17mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed scl0 p17 d5C4 p16mux[1:0] p16 por t function select p16mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk1 sclk1 p16 d3C2 p15mux[1:0] p15 por t function select p15mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdo1 sout1 p15 d1C0 p14mux[1:0] p14 por t function select p14mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdi1 sin1 p14 the p14 to p17 port pins are shared wi th the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p17mux[1:0]: p17 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): scl0 (i2cm) 0x0 (r/w): p17 port (def ault) d[5:4] p16mux[1:0]: p16 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): spiclk1 (spi ch.1) 0x1 (r/w): sclk1 (u ar t ch.1) 0x0 (r/w): p16 port (def ault) d[3:2] p15mux[1:0]: p15 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): sdo1 (spi ch.1) 0x1 (r/w): sout1 (u ar t ch.1) 0x0 (r/w): p15 port (def ault) d[1:0] p14mux[1:0]: p14 port function select bits 0x 3 (r/w): reserv ed 0x2 (r/w): sdi1 (spi ch.1) 0x1 (r/w): sin1 (u ar t ch.1) 0x0 (r/w): p14 port (def ault) 8 i/o por ts (p) 8-14 seiko epson corporation s1c17554/564 t echnical m anual p2[3:0] port function select register (p20_23pmux) register name ad dress bit name function setting init. r/w remarks p2[3:0] port function select register (p20_23pmux) 0x52a4 (8 bits) d7C6 p23mux[1:0] p23 por t function select p23mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdi2 p23/excl2 d5C4 p22mux[1:0] p22 por t function select p22mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed foutb p22/excl1 d3C2 p21mux[1:0] p21 por t function select p21mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out3/cap3 p21 d1C0 p20mux[1:0] p20 por t function select p20mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out2/cap2 p20 the p2 0 to p23 port pins are shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p23mux[1:0]: p23 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sdi2 (spi ch.2) 0x0 (r/w): p23 port and excl2 (t16a ch.2) (def ault) t o use the p23 pin for excl2 input, p2oen3/p2_oen re gister must be set to 0 and p2ien3/p2_ien re gister must be set to 1. d[5:4] p22mux[1:0]: p22 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): foutb (clg) 0x0 (r/w): p22 port and excl1 (t16a ch.1) (def ault) t o use the p22 pin for excl1 input, p2oen2/p2_oen re gister must be set to 0 and p2ien2/p2_ien re gister must be set to 1. d[3:2] p21mux[1:0]: p21 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): t out3 (t16a ch.1 comparator mode) or cap3 (t16a ch.1 capture mode) 0x0 (r/w): p21 port (def ault) d[1:0] p20mux[1:0]: p20 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): t ou t2 (t16a ch.1 comparator mode) or cap2 (t16a ch.1 capture mode) 0x0 (r/w): p20 port (def ault) 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-15 p2[7:4] port function select register (p24_27pmux) register name ad dress bit name function setting init. r/w remarks p2[7:4] port function select register (p24_27pmux) 0x52a5 (8 bits) d7C6 p27mux[1:0] p27 por t function select p27mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed scl1 p27 d5C4 p26mux[1:0] p26 por t function select p26mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sd a1 p26 d3C2 p25mux[1:0] p25 por t function select p25mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss2 #bfr p25 d1C0 p24mux[1:0] p24 por t function select p24mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdo2 p24/excl3 the p24 to p27 port pins a re shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p27mux[1:0]: p27 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): scl1 (i2s) 0x0 (r/w): p27 port (def ault) d[5:4] p26mux[1:0]: p26 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sd a1 (i2s) 0x0 (r/w): p26 port (def ault) d[3:2] p25mux[1:0]: p25 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): #spiss2 (spi ch.2) 0x1 (r/w):#bfr (i2s) 0x0 (r/w): p25 port (def ault) d[1:0] p24mux[1:0]: p24 port function select bits 0x3 (r/w): re serv ed 0x2 (r/w): reserv ed 0x1 (r/w): sdo2 (spi ch.2) 0x0 (r/w): p24 port and excl3 (t16a ch.3) (def ault) t o use the p24 pin for excl3 input, p2oen4/p2_oen re gister must be set to 0 and p2ien4/p2_ien re gister must be set to 1. 8 i/o por ts (p) 8-16 seiko epson corporation s1c17554/564 t echnical m anual p3[3:0] port function select register (p30_33pmux) register name ad dress bit name function setting init. r/w remarks p3[3:0] port function select register (p30_33pmux) 0x52a6 (8 bits) d7C6 p33mux[1:0] p33 por t function select p33mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk2 remi p33 d5C4 p32mux[1:0] p32 por t function select p32mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed fout a t out4/cap4 p32 d3C2 p31mux[1:0] p31 por t function select p31mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #adtrg #bfr p31 d1C0 p30mux[1:0] p30 por t function select p30mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out0/cap0 p30 the p30 to p33 port pins are shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p33mux[1:0]: p33 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): spiclk2 (spi ch.2) 0x1 (r/w): remi (remc) 0x0 (r/w): p33 port (def ault) d[5:4] p32mux[1:0]: p32 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): fout a (clg) 0x1 (r/w): t out4 (t16a ch.2 comparator mode) or cap4 (t16a ch.2 capture mode) 0x0 (r/w): p32 port (def ault) d[3:2] p31mux[1:0]: p31 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): #adtrg (adc10 ) 0x1 (r/w): #bfr (i2cs) 0x0 (r/w): p31 port (def ault) d[1:0] p30mux[1:0]: p30 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): t out0 (t16a ch.0 comparator mode) or cap0 (t16a ch.0 capture mode) 0x0 (r/w): p30 port (def ault) 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-17 p3[7:4] port function select register (p34_37pmux) register name ad dress bit name function setting init. r/w remarks p3[7:4] port function select register (p34_37pmux) 0x52a7 (8 bits) d7C6 p37mux[1:0] p37 por t function select p37mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p37 dst2 d5C4 p36mux[1:0] p36 por t function select p36mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p36 dsio d3C2 p35mux[1:0] p35 por t function select p35mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p35 dclk d1C0 p34mux[1:0] p34 por t function select p34mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss1 remo p34 the p34 to p37 port pins are sha red with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p37mux[1:0]: p37 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): p37 port 0x0 (r/w): dst2 (dbg) (def ault) d[5:4] p36mux[1:0]: p36 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): p36 port 0x0 (r/w): dsio (dbg) (def ault) d[3:2] p35mux[1:0]: p35 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): p35 port 0x0 (r/w): dclk (dbg) (def ault) d[1:0] p34mux[1:0]: p34 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w ): #spiss1 (spi ch.1) 0x1 (r/w): remo (remc) 0x0 (r/w): p34 port (def ault) 8 i/o por ts (p) 8-18 seiko epson corporation s1c17554/564 t echnical m anual p4[3:0] port function select register (p40_43pmux) register name ad dress bit name function setting init. r/w remarks p4[3:0] port function select register (p40_43pmux) 0x52a8 (8 bits) d7C6 p43mux[1:0] p43 por t function select p43mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed remi sd a1 p43 d5C4 p42mux[1:0] p42 por t function select p42mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out1/cap1 sclk0 p42 d3C2 p41mux[1:0] p41 por t function select p41mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out7/cap7 sout0 p41 d1C0 p40mux[1:0] p40 por t function select p40mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out6/cap6 sin0 p40 the p40 to p43 port pins ar e shared with the peripheral module pins. this re gister is used to select ho w the pins are used. d[7:6] p43mux[1:0]: p43 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): remi (remc) 0x1 (r/w): sd a1 (i2cs) 0x0 (r/w): p43 port (def ault) d[5:4] p42mux[1:0]: p42 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): t out1 (t16a ch.0 comparator mode) or cap1 (t16a ch.0 capture mode) 0x1 (r/w): sclk0 (u ar t ch.0) 0x0 (r/w): p42 port (def ault) d[3:2] p41mux[1:0]: p41 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): t out7 (t16a ch.3 comparator mode) or cap7 (t16a ch.3 capture mode) 0x1 (r/w): sout0 (u ar t ch.0) 0x0 (r/w): p41 port (def ault) d[1:0] p40mux[1:0]: p40 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): t out7 (t16a ch.3 comparator mode) or cap7 (t16a ch.3 capture mode) 0x1 (r/w): sin0 (u ar t ch.0) 0x0 (r/w): p40 port (def ault) p4[5:4] port function select register (p44_45pmux) register name ad dress bit name function setting init. r/w remarks p4[5:4] port function select register (p44_45pmux) 0x52a9 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C2 p45mux[1:0] p45 por t function select p45mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sd a0 p45/excl0 d1C0 p44mux[1:0] p44 por t function select p44mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed remo scl1 p44 the p44 and p45 port pins are shared with the peripheral module pins. this re gister is used to select ho w the pins are used. 8 i/o por ts (p) s1c17554/564 t echnical m anual seiko epson corporation 8-19 d[7:4] reserved d[3:2] p45mux[1:0]: p45 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): sd a0 (i2cm) 0x0 (r/w): p45 port and excl0 (t16a ch.0) (def ault) t o use the p45 pin for excl0 input, p4oen5/p4_oen re gister must be set to 0 and p4ien5/p4_ien re gister must be set to 1. d[1:0] p44mux[1:0]: p44 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): remo (remc) 0x1 (r/w): scl1 (i2cs) 0x0 (r/w): p44 port (def ault) p5[3:0] port function select register (p50_53pmux) register name ad dress bit name function setting init. r/w remarks p5[3:0] port function select register (p50_53pmux) 0x52aa (8 bits) d7C6 p53mux[1:0] p53 por t function select p53mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdi1* p53 d5C4 p52mux[1:0] p52 por t function select p52mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sck0* p52 d3C2 p51mux[1:0] p51 por t function select p51mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdo0* p51 d1C0 p50mux[1:0] p50 por t function select p50mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdi0* p50 note: this register can only be used in the s1c17564. t h e p 5 0 t o p 5 3 p o r t p i n s o f t h e s 1 c 1 7 5 6 4 a r e s h a r e d w i t h t h e p e r i p h e r a l m o d u l e p i n s . t h i s r e g i s t e r i s u s e d t o s e l e c t ho w the pins are used. d[7:6] p53mux[1:0]: p53 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sdi1 (s1c17564 usi ch.1) 0x0 (r/w): p53 port (def ault) d[5:4] p52mux[1:0]: p52 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sck0 (s1c17564 usi ch.0) 0x0 (r/w): p52 port (def ault) d[3:2] p51mux[1:0]: p51 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sdo0 (s1c17564 usi ch.0) 0x0 (r/w): p51 port (def ault) 8 i/o por ts (p) 8-20 seiko epson corporation s1c17554/564 t echnical m anual d[1:0] p50mux[1:0]: p50 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sdi0 (s1c17564 usi ch.0) 0x0 (r/w): p50 port (def ault) p5[5:4] port function select register (p54_55pmux) register name ad dress bit name function setting init. r/w remarks p5[5:4] port function select register (p54_55pmux) 0x52ab (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C2 p55mux[1:0] p55 por t function select p55mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sck1* p55 d1C0 p54mux[1:0] p54 por t function select p54mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdo1* p54 note: this register can only be used in the s1c17564. the p54 and p55 port pins of the s1c17564 are shared with the peripheral module pins. this re gister is used to se- lect ho w the pins are used. d[7:4] reserved d[3:2] p55mux[1:0]: p55 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sck1 (s1c17564 usi ch.1) 0x0 (r/w): p55 port (def ault) d[1:0] p54mux[1:0]: p54 port function select bits 0x3 (r/w): reserv ed 0x2 (r/w): reserv ed 0x1 (r/w): us_sdo1 (s1c17564 usi ch.1) 0x0 (r/w): p54 port (def ault) 9 16-bit timers (t16) s1c17554/564 t echnical m anual seiko epson corporation 9-1 16-bit t imers (t16) 9 t16 module over vie w 9.1 the s1c17554/564 includes three-channel 16-bit timer module (t16). the features of the t16 module are listed belo w . ? 16-bit presettable do wn counter with a 16-bit reload data re gister for setting the preset v alue ? generates the spi, i 2 c master operating clocks and a/d con v ersion trigger signal from the counter underflo w signals. ? generates underflo w int errupt signals to the interrupt controller (itc). ? an y desired time interv als and serial transfer rates can be programmed by selecting an appropriate count clock and preset v alue. figure 9.1.1 sho ws the t16 conf iguration. reload data register t16_trx prun df[3:0] underflow run/stop control internal data bus count clock select interrupt request clock outputs to itc to a/d converter (from ch.0) to spi (from ch.1) to i 2 c master (from ch.2) pclk preser timer reset down counter t16_tcx control circuit count mode select trmd 16-bit timer ch.x divider (1/1C1/16k) clg 1.1 t16 configur ation (1 channel) figure 9. each channel of the t16 module consists of a 16-bit presettable do wn counter and a 16-bit reload data re gister holding the preset v alue. the timer counts do wn from the initial v alue set in the reload data re gister and outputs an underflo w signal when the counter underflo ws. the underflo w signal is used to generate an interrupt and an internal serial inter f ace clock or an a/d con v erter trigger signal. the underflo w c ycle can be programmed by selecting the count clock and reload data, enabling the application program to obtain time interv als and serial transfer rates as required. note: all three t16 channels ha v e the same functions e xcept f or the control register addresses . the de- scr iption in this chapter applies to all channels . the x in the registe r name ref ers to the channel n umber (0 to 2). example: t16_ctlx register ch.0: t16_ctl0 register ch.1: t16_ctl1 register ch.2: t16_ctl2 register 9 16-bit timers (t16) 9-2 seiko epson corporation s1c17554/564 t echnical m anual count cloc k 9.2 the count clock is generated by di viding the pclk clock into 1/1 to 1/16k. the di vision ratio can be selected from the 15 types sho wn belo w using df[3:0]/t16_clkx re gister . 2.1 pclk division ratio selection t ab le 9. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) notes: ? the cloc k gener ator (clg) m ust be configured to supply pclk to the per ipher al modules be- f ore r unning the timer . ? mak e sure the counter is halted bef ore setting the count cloc k. f or detailed information on the clg control, see the clock generator (clg) chapter . count mode 9.3 t h e t16 m o d u l e f e a t u r e s t w o c o u n t m o d e s : r e p e a t m o d e a n d o n e - s h o t m o d e . t h e s e m o d e s a r e s e l e c t e d u s i n g trmd/t16_ctlx re gister . repeat mode (trmd = 0, default) setting trmd to 0 sets t16 to repeat mode. in this mode, once the count starts, the timer continues running until stopped by the application program. when the counter underflo w s, the timer presets the reload data re gister v alue into the counter and continues the count. thus, the timer periodically outputs an underflo w pulse. t16 should be set to this mode to generate periodic in- terrupts or a/d con v ersion triggers at desired interv als or to generate a serial transfer clock. one-shot mode (trmd = 1) setting trmd to 1 sets t16 to one-shot mode. in this mode, the timer stop s automatically as soon as the counter underflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the reload data re gister v alue to the counter , then stops after an underflo w has occurred. t16 should be set to this mode to set a specif ic w ait time. reload data register and underflo w cyc le 9.4 the reload data re gister t16_trx is used to set the ini tial v alue for the do wn counter . the initial counter v alue set in the reload data re gister is preset to the do wn counter if the timer is reset or the coun- ter underflo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue). this means that the reload v alue and the input clock frequenc y determine the time elapsed from the point at which the timer starts unti l the underflo w occurs (or between underflo ws). the time determined is used to obtain the specif ied w ait time, the interv als between periodic interrupts or a/d con v ersion triggers, and the programmable serial interf ace transfer clock. 9 16-bit timers (t16) s1c17554/564 t echnical m anual seiko epson corporation 9-3 one-shot mode counter repeat mode counter 0 1 n-1 n n preset by resetting the timer preset by resetting the timer preset automatically underflow preset automatically (n = reload data) 0 1 n-1 n n underflow timer starts timer starts preset automatically 0 1 n-1 n underflow 4.1 preset timing figure 9. the underflo w c ycle can be calculated as follo ws: tr + 1 ct_clk underflo w interv al = [s] underflo w c ycle = [hz] ct_clk tr + 1 ct_clk: count clock frequenc y [hz] tr: reload data (0C65535) timer reset 9.5 the timer is reset by writing 1 to preser/t16_ctlx re gister . the reload data is preset and the counter is initial- ized. timer r un/st op contr ol 9.6 mak e the follo wing set tings before starting the timer . (1) select the count clock. see section 9.2. (2) set the count mode (one-shot or repeat). see section 9.3. (3) calculate the initial counter v alue and set it to the reload data re gister . see section 9.4. (4) reset the timer to preset the counter to the initial v alue. see section 9.5. (5) when using timer interrupts, set the interrupt le v el and enable interrupts for the rele v ant timer channel. see section 9.8. t o start the timer , write 1 to pr un/t16_ctlx re gister . t h e t i m e r s t a r t s c o u n t i n g d o w n f r o m t h e i n i t i a l v a l u e o r f r o m t h e c u r r e n t c o u n t e r v a l u e i f n o i n i t i a l v a l u e w a s p r e s e t . when the counter underflo ws, the timer outputs an underflo w pulse and presets the counter to the initial v alue. an interrupt request is sent simultaneously to the interrupt controller (i tc). in one-shot mode, the timer stops counting. in repeat mode, the timer continues counting from the reloaded initial v alue. write 0 to pr un to stop the timer via the application program. the counter stops counting and retains the current counter v alue until either the timer is reset or restarted. t o restart the count from the initial v alue, the timer should be reset before writing 1 to pr un. 9 16-bit timers (t16) 9-4 seiko epson corporation s1c17554/564 t echnical m anual count clock preser write prun counter interrupt request 0 1 n-1 n n count clock preser write prun counter interrupt request 0 1 n-1 n n 0 1 n-1 n n-1 one-shot mode repeat mode reset by hardware set by software set by software reset by software 6.1 count oper ation figure 9. t16 output signals 9.7 the t16 module outputs underflo w pulses when the counter underflo ws. these pulses are used for timer interrupt requests. these pulses are also used to generate the serial transfer clock for the internal serial interf ace or the a/d con v ersion trigger signal. the clock generated is sent to the internal peripheral module, as sho wn belo w . t16 ch.0 outpu t clock a/d con v erter t16 ch.1 output clock spi t16 ch.2 output clock i 2 c master use the follo wing equations to calculate the reload data re gister v alue for obtaining the desired transfer rate or a/d con v ersion interv al: ct_clk spi tr = - 1 bps 2 ct_clk i 2 c master tr = - 1 bps 4 ct_clk adi a/d con v er ter tr = - 1 2 ct_clk: count clock frequenc y (hz) tr: reload data (0C65535) bps: t ra nsfer rate (bits/s) adi: a/d con v ersion interv al (s) t16 interrupts 9.8 each channel of the t16 module outputs an interrupt request to the interrupt controller (itc) when the counter un- derflo ws. underflo w interrupt when the counter underflo ws, the interrupt flag t16if/t16_intx re gister , which is pro vided for each channel in the t16 module, is set to 1. at the same time, an interrupt request is sent to the itc if t16ie/t16_intx re g- ister has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt condi- tions are satisf ied. 9 16-bit timers (t16) s1c17554/564 t echnical m anual seiko epson corporation 9-5 if t16ie is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. f or specif ic information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? the t16 module interr upt flag t16if m ust be reset in the interr upt handler routine after a t16 interr upt has occurred to pre v ent recurr ing interr upts . ? reset t16if bef ore enab ling t16 interr upts with t16ie to pre v ent occurrence of unw anted in- terr upt. t16if is reset b y wr iting 1. contr ol register details 9.9 9.1 list of t16 registers t ab le 9. ad dress register name function 0x4220 t16_clk0 t16 ch.0 count cloc k select register selects a count cloc k. 0x4222 t16_tr0 t16 ch.0 reload data register sets reload data. 0x4224 t16_tc0 t16 ch.0 counter data register counter data 0x4226 t16_ctl0 t16 ch.0 control register sets the timer mode and star ts/stops the timer . 0x4228 t16_int0 t16 ch.0 interr upt control register controls the interr upt. 0x4240 t16_clk1 t16 ch.1 count cloc k select register selects a count cloc k. 0x4242 t16_tr1 t16 ch.1 reload data register sets reload data. 0x4244 t16_tc1 t16 ch.1 counter data register counter data 0x4246 t16_ctl1 t16 ch.1 control register sets the timer mode and star ts/stops the timer . 0x4248 t16_int1 t16 ch.1 interr upt control register controls the interr upt. 0x4260 t16_clk2 t16 ch.2 count cloc k select register selects a count cloc k. 0x4262 t16_tr 2 t16 ch.2 reload data register sets reload data. 0x4264 t16_tc2 t16 ch.2 counter data register counter data 0x4266 t16_ctl2 t16 ch.2 control register sets the timer mode and star ts/stops the timer . 0x4268 t16_int2 t16 ch.2 interr upt control register controls the interr upt. the t16 re gisters are described in detail belo w . these are 16-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m u st alw a ys be wr itten as 0 and not 1. t16 ch.x count clock select registers (t16_clkx) register name ad dress bit name function setting init. r/w remarks t16 ch.x count clock select register (t16_clkx) 0x4220 0x4240 0x4260 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d[15:4] reserved 9 16-bit timers (t16) 9-6 seiko epson corporation s1c17554/564 t echnical m anual d[3:0] df[3:0]: count clock division ratio select bits selects a pclk di vision ratio to generate the count clock. 9.2 pclk division ratio selection t ab le 9. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) note: mak e sure the counter is halted bef ore setting the count cloc k. t16 ch.x reload data registers (t16_trx) register name ad dress bit name function setting init. r/w remarks t16 ch.x reload data register (t16_trx) 0x4222 0x4242 0x4262 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w d[15:0] tr[15:0]: reload data bits sets the counter initial v alue. (def ault: 0x0) the reload data set in this re gister is preset to the counter when the timer is reset or the counter under - flo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue). this means that the reload v alue and the input clock frequenc y dete rmine the time elapsed from the point at which the timer starts until the underflo w occurs (or between underflo ws). the time determined is used to obtain the desired w ait time, the interv als between periodic interrupts or a/d con v ersion trigger , and the programmable serial interf ace transfer clock. t16 ch.x counter data registers (t16_tcx) register name ad dress bit name function setting init. r/w remarks t16 ch.x counter data register (t16_tcx) 0x4224 0x4244 0x4264 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r d[15:0] tc[15:0]: counter data bits the counter data can be read out. (def ault: 0xf f f f) this re gister is read-only and cannot be written to. t16 ch.x control registers (t16_ctlx) register name ad dress bit name function setting init. r/w remarks t16 ch.x control register (t16_ctlx) 0x4226 0x4246 0x4266 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w d[15:5] reserved (do not write 1.) d4 trmd: count mode select bit selects the count mode. 1 (r/w): one-shot mode 0 (r/w): repeat mode (def ault) 9 16-bit timers (t16) s1c17554/564 t echnical m anual seiko epson corporation 9-7 setting trmd to 0 sets the timer to repeat mode. in this mode, once the count starts, the timer contin- ues to run until stopped by the application program. when the counter underflo ws, the timer presets the counter to the reload data re gister v alue and continues the count. thus, the timer periodically outputs an underflo w pulse. set the timer to this mode to generate periodic interrupts or a/d co n v ersion triggers at desired interv als or to generate a serial transfer clock. setting trmd to 1 sets the timer to one-shot mode. in this mode, the 16-bit timer stops automatically as soon as the counter underflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the counter to the reload data re gister v alue, then stops when an underflo w occurs. s et the timer to this mode to set a specif ic w ait time. d[3:2] reserved d1 preser: timer reset bit resets the timer . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit presets the counter to the reload data v alue. d0 prun: timer run/stop control bit controls the timer r un/st op . 1 (r/w): run 0 (r/w): stop (def ault) the timer starts counting when pr un is written as 1 and stops when written as 0. when the timer is stopped, the counter data i s retained until reset or until the ne xt r un state. t16 ch.x interrupt control registers (t16_intx) register name ad dress bit name function setting init. r/w remarks t16 ch.x inter - rupt control register (t16_intx) 0x4228 0x4248 0x4268 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16ie t16 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16if t16 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d[15:9] reserved d8 t16ie: t16 interrupt enable bit enables or disables interrupts caused by counter underflo ws for each channel. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting t16ie to 1 enables t16 interrupt requests to the itc; setting to 0 disables interrupts. d[7:1] reserved d0 t16if: t16 interrupt flag bit indicates whether the cause of counter underflo w interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored t16if is the t16 module interrupt flag that is set to 1 when the counter underflo ws. t16if is reset by writing 1 . 10 fine mode 16-bit timers (t16f) s1c17554/564 t echnical m anual seiko epson corporation 10-1 fine mode 16-bit t imers (t16f) 10 t16f module over vie w 10.1 the s1c17554/564 includes tw o-channel f ine mode 16-bit timer module (t16f). the features of the t16f module are listed belo w . ? 16-bit presettable do wn counter with a 16-bit reload data re gister for setting the preset v alue ? generates the usi operating clock from the counter underflo w signals. (s1c17564) ? generates underflo w interrupt signa ls to the interrupt controller (itc). ? an y desired time interv als and serial transfer rates can be programmed by selecting an appropriate count clock and preset v alue. ? fine mode is pro vided to minimize transfer rate errors. figure 10.1.1 sho ws the t16f conf iguration. reload data register t16f_trx prun df[3:0] underflow run/stop control internal data bus count clock select interrupt request clock outputs s1c17564 to usi ch.0 (from ch.0) to usi ch.1 (from ch.1) to itc preser timer reset down counter t16f_tcx control circuit count mode select trmd fine mode setting tfmd[3:0] fine mode 16-bit timer ch.x pclk divider (1/1C1/16k) clg 1.1 t16f configur ation (1 channel) figure 10. each channel of the t16f module consists of a 16-bit presettable do wn counter and a 16-bit reload data re gister holding the preset v alue. the timer counts do wn from the initial v alue set in the reload data re gister and outputs an underflo w signal when the counter underflo ws. the underflo w signal is used to generate an interrupt and an internal serial in terf ace clock. the underflo w c ycle can be programmed by selecting the count clock and reload data, en- abling the application program to obtain time interv als and serial transfer rates as required. note: both t16f channels ha v e the same functions e xcept f or the control register addresses . the de- scr iption in this chapter applies to both channels . the x in the register name ref ers to the channel n umbe r (0 or 1). example: t16f_ctlx register ch.0: t16f_ctl0 register ch.1: t16f_ctl1 register 10 fine mode 16-bit timers (t16f) 10-2 seiko epson corporation s1c17554/564 t echnical m anual count cloc k 10.2 the count clock is generated by di viding the pclk clock into 1/1 to 1/16k. the di vision ratio can be selected from the 15 types sho wn belo w using df[3:0]/t16f_clkx re gister . 2.1 pclk division ratio selection t ab le 10. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) notes: ? the cloc k gener ator (clg) m ust be configured to supply pclk to the per ipher al modules be- f ore r unning the timer . ? mak e sure the counter is halted bef ore setting the count cloc k. f or detailed information on the clg control, see the clock generator (clg) chapter . count mode 10.3 t h e t16f m o d u l e f e a t u r e s t w o c o u n t m o d e s : r e p e a t m o d e a n d o n e - s h o t m o d e . t h e s e m o d e s a r e s e l e c t e d u s i n g trmd/t16f_ctlx re gister . repeat mode (trmd = 0, default) setting trmd to 0 sets t16f to repeat mode. in this mode, once the count starts, the timer continues running until stopped by the application program. when the counter under flo ws, the timer presets the reload data re gister v alue into the counter and continues the count. thus, the timer periodically outputs an underflo w pulse. t16f should be set to this mode to generate periodic interrupts or to generate a serial transfer clock. one-shot mode (trmd = 1) setting trmd to 1 sets t16f to one-shot mode. in this mode, the timer stops automatically as soon as the counter unde rflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the reload data re gister v alue to the counter , then stops after an underflo w has occurred. t16f should be set to this mode to set a specif ic w ait time. reload data register and underflo w cyc le 10.4 the reload data re gister t16f_trx is used to set the initial v alue for the do wn counter . the init ial counter v alue set in the reload data re gister is preset to the do wn counter if the timer is reset or the coun- ter underflo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue). this means that the reload v alue and the input clock frequenc y determine the time elapsed from the point at which the timer starts until the underflo w occurs (or between under flo ws). the time determined is used to obtain the specif ied w ait time, the interv als between periodic interrupts, and the programmable serial interf ace transfer clock. 10 fine mode 16-bit timers (t16f) s1c17554/564 t echnical m anual seiko epson corporation 10-3 one-shot mode counter repeat mode counter 0 1 n-1 n n preset by resetting the timer preset by resetting the timer preset automatically underflow preset automatically (n = reload data) 0 1 n-1 n n underflow timer starts timer starts preset automatically 0 1 n-1 n underflow 4.1 preset timing figure 10. the underflo w c ycle can be calculated as follo ws: tr + 1 ct_clk underflo w interv al = [s] underflo w c ycle = [hz] ct_clk tr + 1 ct_clk: count clock frequenc y [hz] tr: reload data (0C65535) timer reset 10.5 the timer is reset by writing 1 to preser/t16f_ctlx re gister . the reload data is preset and the counter is initial- ized. timer r un/st op contr ol 10.6 mak e the follo wing settings before starting the timer . (1) select the count clock. see section 10.2. (2) set the count mode (one-shot or repeat). see section 10.3. (3) calculate the initial counter v alue and set it to the reload data re gister . see section 10.4. (4) reset the timer to preset the counter to the initial v alue. see section 10.5. (5) when using timer interrupts, set the interrupt le v el and enable interrupts for the rele v ant timer channel. see section 10.9. t o start the timer , write 1 to pr un/t16f_ctlx re gister . t h e t i m e r s t a r t s c o u n t i n g d o w n f r o m t h e i n i t i a l v a l u e o r f r o m t h e c u r r e n t c o u n t e r v a l u e i f n o i n i t i a l v a l u e w a s p r e s e t . when the counter underflo ws, the timer outputs an underflo w pulse and presets the counter to the initial v alue. an interrupt request is sent simultaneously to the interrupt con troller (itc). in one-shot mode, the timer stops counting. in repeat mode, the timer continues counting from the reloaded initial v alue. write 0 to pr un to stop the timer via the application program. the counter stops counting and retains the current counter v alue until either the timer is reset or restarted. t o restart the count from the initial v alue, the timer should be reset before writing 1 to p r un. 10 fine mode 16-bit timers (t16f) 10-4 seiko epson corporation s1c17554/564 t echnical m anual count clock preser write prun counter interrupt request 0 1 n-1 n n count clock preser write prun counter interrupt request 0 1 n-1 n n 0 1 n-1 n n-1 one-shot mode repeat mode reset by hardware set by software set by software reset by software 6.1 count oper ation figure 10. t16f output signals 10.7 the t16f module outputs underflo w pulses when the counter underflo ws. these pulses are used for timer interrupt requests. in the s1c17564, these pulses are also used to generate a usi clock. the clock generated is sent to the internal pe- ripheral module, as sho wn belo w . t16f ch.0 output clock usi ch.0 t16f ch.1 output clock usi ch.1 underflow signal timer output (to usi) interrupt request to the itc 7.1 t16f output cloc k figure 10. fine mode 10.8 fine mode pro vides a function that minimizes transfer rate errors. t16f can output a programmable clock signal for use as the usi serial transfer clock. the timer output clock can be set to the required frequenc y by selecting the appropriate count clock and reload data. note that errors may oc- cur , depending on the transfer rate. fine mode e xtends the output clock c ycle by delaying the underflo w pulse from the counter . this delay can be specif ied with the tfmd[3:0]/t16f_ctlx re gister . tfmd[3:0] specif ies the delay pattern to be inserted into a 16 underflo w period. inserting one delay e xtends the output clock c ycle by one count clock c ycle. this setting delays the interrupt timing in the same w ay . 10 fine mode 16-bit timers (t16f) s1c17554/564 t echnical m anual seiko epson corporation 10-5 8.1 dela y p atter ns specified b y tfmd[3:0] t ab le 10. tfmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle . count clock underflow signal (not corrected) underflow signal (corrected) output clock (not corrected) output clock (corrected) delayed 15 16 15 16 1 1 8.1 dela y cycle inser tion in fine mode figure 10. at initial reset, tfmd[3:0] is set to 0x0, pre v enting insertion of delay c ycles. t16f interrupts 10.9 each channel of the t16f module outputs an interrupt request to the interrupt controller (itc) when the counter underflo ws. underflo w interrupt when the counter underflo ws, the interrupt flag t16fif/t16f_intx re gister , which is pro vided for each chan- nel in the t16f module, is set to 1. at the same time, an interrupt request is sent to the itc if t16fie/t16f_ intx re gister has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core inter - rupt conditions are satisf ied. if t16fie is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. f or specif ic information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? the t16f module interr upt flag t16fif m ust be reset in the interr upt handler routine after a t16f interr upt has occurred to pre v ent recurr ing interr upts . ? reset t16fif bef ore enab ling t16f interr upts with t16fie to pre v ent occurrence of unw anted interr upt. t16fif is reset b y wr iting 1. 10 fine mode 16-bit timers (t16f) 10-6 seiko epson corporation s1c17554/564 t echnical m anual contr ol register details 10.10 10.1 list of t16f registers t ab le 10. ad dress register name function 0x4200 t16f_clk0 t16f ch.0 count cloc k select register selects a count cloc k. 0x4202 t16f_tr0 t16f ch.0 reload data register sets reload data. 0x4204 t16f_tc0 t16f ch.0 counter data register counter data 0x4206 t16f_ctl0 t16f ch.0 control register sets the timer mode and star ts/stops the timer . 0x4208 t16f_int0 t16f ch.0 interr upt control register controls the interr upt. 0x4280 t16f_clk1 t16 f ch.1 count cloc k select register selects a count cloc k. 0x4282 t16f_tr1 t16f ch.1 reload data register sets reload data. 0x4284 t16f_tc1 t16f ch.1 counter data register counter data 0x4286 t16f_ctl1 t16f ch.1 control register sets the timer mode and star ts/stops the timer . 0x4288 t16f_int1 t16f ch.1 interr upt control register controls the interr upt. the t16f re gisters are described in detail belo w . these are 16-b it re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. t16f ch.x count clock select registers (t16f_clkx) register name ad dress bit name function setting init. r/w remarks t16f ch.x count clock select register (t16f_clkx) 0x4200 0x4280 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d[15:4] reserved d[3:0] df[3:0]: count clock division ratio select bits selects a pclk di vision ratio to generate the count clock. 10.2 pclk division ratio selection t ab le 10. df[3:0] division ratio df[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) note: mak e sure the counter is halted bef ore setting the count cloc k. t16f ch.x reload data registers (t16f_trx) register name ad dress bit name function setting init. r/w remarks t16f ch.x reload data register (t16f_trx) 0x4202 0x4282 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w 10 fine mode 16-bit timers (t16f) s1c17554/564 t echnical m anual seiko epson corporation 10-7 d[15:0] tr[15:0]: reload data bits sets the counter initial v alue. (def ault: 0x0) the reload data set in this re gister is preset to the counter when the timer is reset or the counter under - flo ws. if the timer is started after resetting, it counts do wn from the reload v alue (initial v alue). this means that the reload v alue and the input clock frequenc y determine the time elapsed from the point at which the timer starts until the u nderflo w occurs (or between underflo ws). the time determined is used to obtain the desired w ait time, the interv als between periodic interrupts, and the programmable serial interf ace transfer clock. t16f ch.x counter data registers (t16f_tcx) register name ad dress bit name function setting init. r/w remarks t16f ch.x counter data register (t16f_tcx) 0x4204 0x4284 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r d[15:0] tc[15:0]: counter data bits the counter data can be read out. (def ault: 0xf f f f) this re gister is read-only and cannot be written to. t16f ch.x control registers (t16f_ctlx) register name ad dress bit name function setting init. r/w remarks t16f ch.x control register (t16f_ctlx) 0x4206 0x4286 (16 bits) d15C12 C reser v ed C C C 0 when being read. d11C8 tfmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. d7C5 C reser v ed C C C 0 when being read. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w d[15:12] reserved d[11:8] tfmd[3:0]: fine mode setup bits corrects the transfer rate error . (def ault: 0x0) tfmd[3:0] specif ies the delay pattern to be inserted into a 16 underflo w period. inserting one delay e xtends the output clock c ycle by one count clock c ycle. this setting delays the interrupt timing in the same w ay . 10.3 dela y p atter ns specified b y tfmd[3:0] t ab le 10. tfmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle . 10 fine mode 16-bit timers (t16f) 10-8 seiko epson corporation s1c17554/564 t echnical m anual count clock underflow signal (not corrected) underflow signal (corrected) output clock (not corrected) output clock (corrected) delayed 15 16 15 16 1 1 10.1 dela y cycle inser tion in fine mode figure 10. d[7:5] reserved d4 trmd: count mode select bit selects the count mode. 1 (r/w): one-shot mode 0 (r/w): repeat mode (def ault) setting trmd to 0 sets the timer to repeat mode. in this mode, once the count starts, the timer contin- ues to run until stopped by the application program. when the counter underflo ws, the timer presets the counter to the reload data re gister v alue and continues the co unt. thus, the timer periodically outputs an underflo w pulse. set the timer to this mode to generate periodic interrupts or to generate a serial trans- fer clock. setting trmd to 1 sets the timer to one-shot mode. in this mode, the f ine mode 16-bit timer stops au- tomatically as soon as the counter underflo ws. this means only one interrupt can be generated after the timer starts. note that the timer presets the counter to the reload data re gister v alue, then stops when an underflo w occurs. set the timer to this mode to set a specif ic w ait time. d[3:2] reserved d1 preser: timer reset bit resets the timer . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit presets the counter to the reload data v alue. d0 prun: timer run/stop control bit controls the timer r un/st op . 1 (r/w): run 0 (r/w): stop (def ault) the timer starts counting when p r un is written as 1 and stops when written as 0. when the timer is stopped, the counter data is retained until reset or until the ne xt r un state. t16f ch.x interrupt control registers (t16f_intx) register name ad dress bit name function setting init. r/w remarks t16f ch.x inter - rupt control register (t16f_intx) 0x4208 0x4288 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16fie t16f interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16fif t16f interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d[15:9] reserved d8 t16fie: t16f interrupt enable bit enables or disables interrupts caused by counter underflo ws for each channel. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting t16fie t o 1 enables t16f interrupt requests to the itc; setting to 0 disables interrupts. 10 fine mode 16-bit timers (t16f) s1c17554/564 t echnical m anual seiko epson corporation 10-9 d[7:1] reserved d0 t16fif: t16f interrupt flag bit indicates whether the cause of counter underflo w interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored t16fif is the t16f module interrupt flag that is set to 1 when the counter underflo ws. t16fif is reset by writing 1. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-1 16-bit pwm t imers (t16a) 11 t16a module over vie w 11.1 the s1c17554/564 includes a 16-bit pwm timer (t16a) module that consists of four channels of counter blocks and comparator/capture blocks. this timer can be used as an interv al timer , pwm w a v eform generator , e xternal e v ent counter and a count capture unit to measure e xternal e v ent periods. the features of t16a are listed belo w . ? f our channels of 16-bit up counter blocks ? f our channels of comparator/capture blocks to which a counter block to be connected is selectable. ? allo ws selection of a count clock asynchronously with the cpu clock. ? supports e v ent counter function using an e xternal clock. ? the comparator compares the counter v alue with tw o specif ied comparison v alues to generate interrupts and a pwm w a v eform. ? the capture unit captu res counter v alues using tw o e xternal trigger signals and generates interrupts. figure 11.1.1 sho ws the t16a conf iguration. a data register t16a_cca0 tout0 tout1 cap0 cap1 interrupt request b data register t16a_ccb0 interrupt control tout control comparator/ capture controller a data buffer (t16a_cca0) b data buffer (t16a_ccb0) counter block ch.0 comparator/capture block ch.0 counter block ch.1 comparator/capture block ch.1 counter t16a_tc0 count control iosc osc1 excl0 divider (1/1C1/16384) osc3 divider (1/1C1/16384) tout6/7 cap6/7 interrupt request tout4/5 cap4/5 interrupt request tout2/3 cap2/3 interrupt request excl1 excl2 excl3 divider (1/1C1/256) gate clock controller ch.0 clock controller ch.1 16-bit pwm timer counter block ch.2 comparator/capture block ch.2 clock controller ch.2 counter block ch.3 comparator/capture block ch.3 clock controller ch.3 s1c17564 1.1 t16a configur ation figure 11. cloc k contr oller t16a i n c l u d e s f o u r c h a n n e l s o f c l o c k c o n t r o l l e r s t h a t g e n e r a t e t h e c o u n t c l o c k f o r t h e c o u n t e r s . t h e c l o c k source and di vision ratio can be selected with softw are. counter b loc k the counter block includes a 16-bit up-counter that operates with an iosc (s1c17564 only), osc3, or osc1 di vision clock, or the e xternal count clock input from outside the ic. the t16a module allo ws softw are to run and stop the counter of each channel, and to reset the counter v alue (cleared to 0) as well as selection of the count clock. the counter can also be reset by the compare b signal output from the comparator/capture block. 11 16-bit pwm timers (t16a) 11-2 seiko epson corporation s1c17554/564 t echnical m anual comparator/capture b loc k the comparator/capture block includes tw o systems (units a and b) of comparators that compare between the counter v alue and the specif ied comparison v alue and capture circuits that capture the counter v alue by an e x- ternal trigger signal. note, ho we v er , that the comparator and capture functions cannot be used at the same time in each system. one of the tw o functions must b e selected by the softw are switch. when using the comparator function, set the v alue(s) to be compared with the counter v alue to the compare a and/or compare b re gisters. when the counter reaches the v alue set in the compare a or compare b re gister , the comparator asserts the compare a or compare b signal. these signals can generate interrupts. also the signals control the c ycle time and duty rati o of the timer output signal allo wing the timer to output a pwm or other w a v eform. in addition to these functions, the compare b signal is used to reset the counter . comparison data can be read or written directly from/to the compare a and compare b re gisters. the compare b uf fers are separately pro vided to load data to the compare a and compare b re gisters automatically by the compare b signal. so ftw are can select which of the compare re gister and b uf fer the comparison v alues are writ- ten to. when the capture function is enabled, the compare a and compare b re gisters are used as the capture a and capture b re gisters, respecti v ely . the capture a and capture b circuits can input a trigger signal indi vidually , and the counter v alue is loaded to the respecti v e capture re gister at the selected edge of the trigger signal. the capturing operation can generate an interrupt, this mak e it possible to read the captured data in the interrupt handler routine. also an o v erwrite interrupt can be generated for the error handling when the counter v alue is captured before reading the pre vious captured data. combination of counter b loc k c hannel and comparator/capture b loc k c hannel generally , a counte r block is connected to the comparator/capture block with the same channel number . the c o u n t e r b l o c k a n d t h e c o m p a r a t o r / c a p t u r e b l o c k i n d i f f e r e n t c h a n n e l s c a n a l s o b e c o n n e c t e d . t h i s a l l o w s a counter to use tw o or more comparator/capture blocks for e xpanding the comparison/capturing function from tw o systems to maximum eight systems (details are described later). note: each channel of the t16a module has the same functions e xcept f or the control register address- es . the descr iption in this section applies to all channels of the t16a module otherwise a channel n umber is specified. the x in the register name ref ers to the channel n umber (0 to 3). example: t16a_ctlx register ch.0: t16a_ctl0 register ch.1: t16a_ctl1 register ch.2: t16a_ctl2 register ch.3: t16a_ctl3 register t16a input/outpu t pins 11.2 t able 11.2.1 lists the input/output pins for the t16a module. 2.1 list of t16a pins t ab le 11. pin name i/o qty function excl0 (f or ch.0) excl1 (f or ch.1) excl2 (f or ch.2) excl3 (f or ch.3) i 4 exter nal cloc k input pins inputs an e xter nal cloc k f or the e v ent counter function. cap0, cap1 (f or ch.0) cap2, cap3 (f or ch.1) cap4, cap5 (f or ch.2) cap6, cap7 (f or ch.3) i 8 counter-capture tr igger signal input pins (eff ectiv e in capture mode) the specified edge (f alling edge , r ising edge , or both) of the signal input to the cap0/2/4/6 pin captures the counter data into the capture a reg- ister . the cap1/3/5/7 pin input signal captures the counter data into the capture b register . t out0, t out1 (f or ch.0) t out2, t out3 (f or ch.1) t out4, t out5 (f or ch.2) t out6, t out7 (f or ch.3) o 8 timer gener ating signal output pins (eff ectiv e in compar ator mode) each channel has tw o output pins and the signals gener ated in diff erent cond itions can be output. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-3 the t16a input/output pins (exclx, capx, t outx) are shared with i/o ports and are initially set as general pur - pose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as t16a input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . count cloc k 11.3 the clock controller includes a clock source selector , di viders, and a g ate circuit for controlling the count clock. the count clock can be controlled in each channel indi vidually . osc1 clock external clock (excl0) osc3 clock clksrc[1:0] multimd clkdiv[3:0] counter ch.0 clken divider (1/1C1/16k) divider (1/1C1/256) clock controller ch.0 external clock (excl1) counter ch.1 iosc clock divider (1/1C1/16k) clock controller ch.1 external clock (excl2) counter ch.2 clock controller ch.2 external clock (excl3) counter ch.3 clock controller ch.3 s1c17564 3.1 cloc k controller figure 11. cloc k sour ce selection t h e c l o c k s o u r c e c a n b e s e l e c t e d f r o m i o s c ( s 1 c 1 7 5 6 4 ) , o s c 3 , o s c 1 , o r e x t e r n a l c l o c k u s i n g c l k s r c [ 1 : 0 ] / t16a_clkx re gister . 3.1 cloc k source selection t ab le 11. clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (exclx) 0x2 osc3 0x1 osc1 0x0 iosc (s1c17564) (def ault: 0x0) when e xternal clock is selected, the timer can be used as an e v ent counter or for measuring pulse widths by inputting an e xternal clock or pulses. the table belo w lists the e xternal clock input pins. it is not necessary to switch their pin functions from general-purpose i/o port. ho we v er , do not set the i/o port to output mode. 3.2 exter nal cloc k input pins t ab le 11. channel external c loc k input pin t16a ch.0 excl0 t16a ch.1 excl1 t16a ch.2 excl2 t16a ch.3 excl3 11 16-bit pwm timers (t16a) 11-4 seiko epson corporation s1c17554/564 t echnical m anual internal c loc k division ratio selection when an internal clock (iosc, osc3, or osc1) is selected, use clkdiv[3:0]/t16a_clkx re gister to select the di vision ratio. 3.3 inter nal cloc k division ratio selection t ab le 11. clkdiv[3:0] division ratio cloc k sour ce = iosc or osc3 cloc k sour ce = osc1 0xf reser v ed 0x e 1/16384 reser v ed 0xd 1/8192 reser v ed 0xc 1/4096 reser v ed 0xb 1/2048 reser v ed 0xa 1/1024 reser v ed 0x9 1/512 reser v ed 0x8 1/256 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) cloc k enab le clock supply to the counter is controlled using clken/t16a_clkx re gister . the clken def ault setting is 0, which disables the clo ck supply . setting clken to 1 sends the clock generated as abo v e to the counter . if t16a is not required, disable the clock supply to reduce current consumption. multi-comparator/capture mode the t16a module allo ws a counter channel to be connected to multiple comparator/capture channels (multi- comparator/capture mode). in this case, all channels must be clock ed with the ch.0 clock. use mul timd/ t16 a_clk0 re gister to supply the ch.0 clock to all channels. when using t16a in multi-comparator/capture mode, set mul timd to 1. when connecting the counter and comparator/capture block in the same channel (normal channel mode), set mul timd to 0 (def ault). note: mak e sure the t16a count is stopped bef ore setting the count cloc k. t16a operating modes 11.4 the t16a module pro vides some operating modes to su pport v arious usages. this section describes the functions of each operating mode and ho w to enter the mode. comparator mode and capture mode 11.4.1 the t16a_ccax and t16a_ccbx re gisters that are embedded in the comparator/capture block can be set to com- p a r a t o r m o d e o r c a p t u r e m o d e , i n d i v i d u a l l y . t h e t16a _ c c a x r e g i s t e r m o d e i s s e l e c t e d u s i n g c c a m d / t16a _ ccctlx re gister and the t16a_ccbx re gister mo de is selected using ccbmd/t16a_ccctlx re gister . comparator mode (ccamd/ccbmd = 0, default) the comparator mode compares the counter v alue and the comparison v alue set via softw are. it generates an interrupt and toggles the timer output signal le v el when the v alues are matched. the t16a_ccax and t16a_ ccbx re gisters function as the compare a and compare b re gisters that are used for loading compare v alues in this mode. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-5 when the counter reaches the v alue set in the compare a re gister during counting, the comparator asserts the compare a signal. at the same time the compare a interrupt flag is set and the interrupt signal of the timer channel is output to the itc if the interrupt has been enabled. when the counter reaches the v alue set in the compare b re gister , the comparator asserts the compare b signal. at the same time the compare b interrupt flag is set and the interrupt signal of the timer channel is output to the itc if the interrupt is enabled. furthermore, the counter is reset to 0. the compare a period (time from start of counting to occurrence of a compare a interrupt) and the compare b period (time from start of counting to occurrence of a compare b interrupt) can be calculated as follo ws: co mpare a period = (cca + 1) / ct_clk [second] compare b period = (ccb + 1) / ct_clk [second] cca: compare a re gister v alue set (0 to 65535) ccb: compare b re gister v alue set (0 to 65535) ct_clk: count clock frequenc y [hz] the compare a and compare b signals are also used to generate a timer output w a v eform (t out). see section 11.6, t imer output control, for more information. t o generate pwm w a v eform, the t16a_ccax and t16a_ccbx re gisters must be both placed into comparator mode. compare b uff er s comparison data can be read or written directly from/to the compare re gisters. comparison data for sys- tem a or b can also be written to the compare b uf fer so that it will be loaded to the compare a or compare b re gister when the compare b signal is generated. the cb ufen/t16a_ctlx re gister is u sed to select whether comparison data is written to the compare re gister or b uf fer . setting cb ufen to 0 (def ault) selects the compare re gisters. setting it to 1 selects the compare b uf fers. al- though the t16a_ccax and t16a_ccbx re gisters are used to read/write compare data e v en if cb ufen is set to 1, compare b uf fers will be accessed. capture mode (ccamd/ccbmd = 1) the capture mode captures the coun ter v alue when an e xternal e v ent such as a k e y entry occurs (at the specif ied edge of the e xternal input signal). in this mode, the t16a_ccax and/or t16a_ccbx re gisters function as the capture a and/or capture b re gisters. the table belo w lists the input pins of the e xternal trigger signals used for capturing counter v alues. the pin function of the corresponding ports must be switched for trigger input in adv ance. see the i/o ports (p) chap- ter for switching the pin function. 4.1.1 list of counter capture t r igger signal input pins t ab le 11. channel t rig g er input pins capture a capture b t16a ch.0 cap0 cap1 t16a ch.1 cap2 cap3 t16a ch.2 cap4 cap5 t16a ch.3 cap6 cap7 the trigger edge of the signal can be selected using the cap a trg[1:0]/t16a_ccctlx re gister for capture a and capbtrg[1:0]/t16a_ccctlx re gister for capture b. 4.1.2 capture t r igger edge selection t ab le 11. cap a trg[1:0]/ capbtrg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) when a specif ied trigger edge is input during counting, the current counter v alue is loaded to the capture re gis- ter . at the same time the capture a or capture b interrupt flag is set and the interrupt signal of the timer channel is output to the itc if the interrupt has been enabled. 11 16-bit pwm timers (t16a) 11-6 seiko epson corporation s1c17554/564 t echnical m anual this interrupt can be used to read the captured data from the t16a_ccax or t16a_ccbx re gister . f or e xam- ple, e xternal e v ent c ycles and pulse widths can be measured from the dif ference between tw o captured counter v alues read. if the captured data is o v erwritten by the ne xt trigger when the capture a or capture b interrupt flag has already been set, the o v erwrite interrupt flag will be set. this i nterrupt can be used to e x ecute an o v erwrite error han- dling. t o a v oid occurrence of unnecessary o v erwrite interrupt, the capture a or capture b interrupt flag must be reset after the captured data has been read from the t16a_ccax or t16a_ccbx re gister . notes: ? the correct captured data ma y not be obtained if the captured data is read at the same time the ne xt v alue is being captured. read the capture register twice to chec k if the read data is correct as necessar y . ? t o capture counter data proper ly , both the high and lo w per iod of the capx tr igger signal m ust be longer than the source cloc k cycle time . the setting of cap a trg[1:0] or capbtrg[1:0] is inef fecti v e in comparator mode. no counter capturing op- eration will be performed e v en if a trigger edge is specif ied. the capture mode cannot ge nerate/output the t out signal as no compare signal is generated. repeat mode and one-shot mode 11.4.2 each counter features tw o count modes: repeat mode and one-shot mode. the count mode is selected using trmd /t16a_ctlx re gister . repeat mode (trmd = 0, default) setting trmd to 0 sets the corresponding counter to repeat mode. in this mode, once the count starts, the counter continues running until s topped by the application program. the counter continues the count e v en if the counter returns to 0 due to a counter o v erflo w . the counter should be set to this mode to generate periodic interrupts at desired interv als or to generate a timer output w a v eform. one-shot mode (trmd = 1) setting trmd to 1 sets the corresponding counter to one-shot mode. in this mode, the counter stops automatically as s oon as the compare b signal is generated. the counter should be set to this mode to set a specif ic w ait time or for pulse width measurement. normal channel mode and multi-comparator/capture mode 11.4.3 one channel of the t16a module basically consists of a counter block and a comparator/capture block. the t16a module also allo ws the application to use e xpanded comparator/capture function by connect ing tw o or more com- parator/capture blocks to one counter block. t o support this e xpansion, tw o operating modes are pro vided: normal channel mode and multi-comparator/capture mode. this operating mode can be selected using mul timd/t16_ clk0 re gister . normal c hannel mode (mul timd = 0, default) set the t16a module to this mode when using it as four channels of dif ferent timers by connecting a counter block with the comparator/capture block of the same channel. in this mode, the counters can use dif ferent count clocks. each timer channel pro vides ccabcnt[1:0]/t16a_ctlx re gister to select a counter channel to be connected to the comparator/capture block. 4.3.1 counter selection t ab le 11. ccabcnt[1:0] counter c hannel 0x3 ch.3 (counter 3) 0x2 ch.2 (counter 2) 0x1 ch.1 (counter 1) 0x0 ch.0 (counter 0) (def ault: 0x0) when using the t16a module in normal channel mode, be sure to connect the counter block to the comparator/ capture block in the same channel. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-7 counter block ch.1 comparator/capture block ch.1 clock controller ch.1 counter block ch.0 comparator/capture block ch.0 clock controller ch.0 counter block ch.2 comparator/capture block ch.2 clock controller ch.2 counter block ch.3 comparator/capture block ch.3 clock controller ch.3 t16a iosc* osc3 osc1 excl1 iosc* osc3 osc1 excl0 iosc* osc3 osc1 excl2 iosc* osc3 osc1 excl3 * available only in s1c17564 tout6/7 cap6/7 interrupt request tout4/5 cap4/5 interrupt request tout2/3 cap2/3 interrupt request tout0/1 cap0/1 interrupt request 4.3.1 timer configur ation in nor mal channel mode (tw o compar ator/capture b loc ks f our channels) figure 11. note: do not connect a counter b loc k to a compar ator/capture b loc k in a diff erent channel in nor mal channel mode (mul timd = 0), as nor mal oper ation cannot be guar anteed. multi-comparator/capture mode (mul timd = 1) in order to set three or more comparison v alues for one counter or to capture the contents of one counter using three or more trigger signals, tw o or more comparator/capture blocks can be connected to one counter . multi- comparator/capture mode is pro vided for this purpose. in this mode, an y counter block can be combined with the comparator/capture blocks using ccabcnt[1:0] described abo v e. note, ho we v er , that the count clock is f ix ed at one type for counter ch.0, re g ardless of the counter to be used. the clock settings for ch.1 to ch.3 are inef fecti v e. counter block ch.1 comparator/capture block ch.1 clock controller ch.1 counter block ch.0 comparator/capture block ch.0 clock controller ch.0 counter block ch.2 comparator/capture block ch.2 clock controller ch.2 counter block ch.3 comparator/capture block ch.3 clock controller ch.3 tout6/7 cap6/7 interrupt request tout4/5 cap4/5 interrupt request tout2/3 cap2/3 interrupt request tout0/1 cap0/1 interrupt request t16a iosc* osc3 osc1 excl1 iosc* osc3 osc1 excl0 iosc* osc3 osc1 excl2 iosc* osc3 osc1 excl3 * available only in s1c17564 (1) configur ation example 1 (f our compar ator/capture b loc ks tw o channels) counter block ch.1 comparator/capture block ch.1 clock controller ch.1 counter block ch.0 comparator/capture block ch.0 clock controller ch.0 t16a counter block ch.2 comparator/capture block ch.2 clock controller ch.2 counter block ch.3 comparator/capture block ch.3 clock controller ch.3 tout6/7 cap6/7 interrupt request tout4/5 cap4/5 interrupt request tout2/3 cap2/3 interrupt request tout0/1 cap0/1 interrupt request iosc* osc3 osc1 excl1 iosc* osc3 osc1 excl0 iosc* osc3 osc1 excl2 iosc* osc3 osc1 excl3 * available only in s1c17564 (2) configur ation example 2 (eight compar ator/capture b loc ks one channel) 4.3.2 timer configur ation example in multi-compar ator/capture mode figure 11. 11 16-bit pwm timers (t16a) 11-8 seiko epson corporation s1c17554/564 t echnical m anual counter contr ol 11.5 counter reset 11.5.1 the counter can be reset to 0 by writing 1 to preset/t16a_ctlx re gister . normally , the counter should be reset by writing 1 to this bit before starting the count. the counter is reset by the hardw are if the counter reaches the compare b re gister v alue after the count starts. counter r un/st op contr ol 11.5.2 mak e the follo wing settings before starting the coun t operation. (1) switch the input/output pin functions to be used for t16a. refer to the i/o port (p) chapter . (2) select operating modes. see section 11.4. (3) select the clock source. see section 11.3. (4) conf igure the timer outputs (t out). see section 11.6. (5) if using interrupts, set the interrupt le v el and enable the t16a interrupts. see section 11.7. (6) reset the counter to 0. see section 11. 5.1. (7) set comparison data (in comparator mode). see section 11.4.1. each timer channel pro vides pr un/t16a_ctlx re gister to control the counter operation. th e cou nt er st art s cou nt in g whe n 1 is wri tt en to pr un. wri ti ng 0 to pr un di sab les clo ck in pu t and st op s th e count. this control does not af fect the counter data. the counter data is retained e v en when the count is halted, allo wing resumption of th e count from that data. if pr un and preset are written as 1 simultaneously , the counter starts counting after reset. reading counter v alues 11.5.3 the counter v alue can be read from t16a tc[15:0]/t16a_tcx re gister e v en if the counter is running. ho we v er , the counter v alue should be read at once using a 16-bit transfer instruction. if data is read twice using an 8-bit transfer instruction, the correct v alue may not be obtained due to occurrence of count up between readings. timing char ts 11.5.4 comparator mode prun preset t16a_ccax t16a_ccbx count clock t16a_tcx reset compare a interrupt reset and compare b interrupt compare a interrupt reset and compare b interrupt 0x2 01 2 3 4 5 0 1 2 3 4 5 0 1 0x5 5.4.1 oper ation timing in compar ator mode figure 11. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-9 capture mode prun preset cap(a) cap(b) count clock t16a_tcx t16a_ccax t16a_ccbx 2 01 2 3 4 5 6 7 8 9 10 11 12 13 5 10 (when capatrg[1:0] = 0x1, capbtrg[1:0] = 0x3) reset capture a interrupt capture b interrupt capture b interrupt (and capture b overwrite interrupt if capbif = 1) 5.4.2 oper ation timing in capture mode figure 11. timer output contr ol 11.6 the timer that has been set in comparator mode can generate t out signals using the compare a and compare b signals and can output it to e xternal de vices. each timer channel pro vides tw o t out outputs, thus the t16a mod- ule can output up to eight t out signals. figure 11.6.1 sho ws the t out output circuit (one timer channel). tout a output control compare a signal compare b signal toutamd[1:0] toutainv tout0(2/4/6) tout b output control compare a signal compare b signal toutbmd[1:0] toutbinv tout1(3/5/7) comparator/capture block ch.0 (1/2/3) 6.1 t out output circuit figure 11. each timer channel includes tw o t out output circuits and their signal generation and output can be controlled in- di vidually . although the output circuit and re gister names use letters a and b to distinguish tw o systems, it does not mean that the y correspond to compare a and b signals. t out output pins t able 11.6.1 lists correspondence between the t out pins and the timer channels. the pin function of the cor - responding ports must be switched for t out output in adv ance. see the i/o ports (p) chapter for switching the pin function. 6.1 list of t out output pins t ab le 11. channel t out output pin system a system b t16a ch.0 t out0 t out1 t16a ch.1 t out2 t out3 t16a ch.2 t out4 t out5 t16a ch.3 t out6 t out7 11 16-bit pwm timers (t16a) 11-10 seiko epson corporation s1c17554/564 t echnical m anual t out g eneration mode t out amd[1:0]/t16a_ccctlx re gister (for system a) or t outbmd[1:0]/t16a_ccctlx re gister (for sys- tem b) is used to set ho w the t out signal is changed by the compare a and compare b signals. 6.2 t out gener ation mode t ab le 11. t out amd[1:0]/ t outbmd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0) t out amd[1:0] and t outbmd[1:0] are also used to turn the t out outputs on and of f. t out signal polarity selection b y d e f a u l t , a n a c t i v e h i g h o u t p u t s i g n a l i s g e n e r a t e d . t h i s l o g i c c a n b e i n v e r t e d u s i n g t o u t a i n v / t16a _ c c c t l x r e g i s t e r ( f o r s y s t e m a ) o r t o u t b i n v / t16a _ c c c t l x r e g i s t e r ( f o r s y s t e m b ) . w r i t i n g 1 t o t out ainv/t outbinv sets the timer to generate an acti v e lo w t out signal. resetting the counter sets the t out signal to the inacti v e le v el. figure 11.6.2 illustrates the t out output w a v eform. count clock preset prun counter value compare a signal compare b signal tout(a) output (toutamd[1:0] = 0x0, toutainv = 0) (toutamd[1:0] = 0x0, toutainv = 1) (toutamd[1:0] = 0x1, toutainv = 0) (toutamd[1:0] = 0x1, toutainv = 1) (toutamd[1:0] = 0x2, toutainv = 0) (toutamd[1:0] = 0x2, toutainv = 1) (toutamd[1:0] = 0x3, toutainv = 0) (toutamd[1:0] = 0x3, toutainv = 1) 1 2 3 4 5 0 0 1 2 3 4 5 0 1 2 3 4 5 0 1 (when t16a_ccax = 3, t16a_ccbx = 5) 6.2 t out output w a v ef or m figure 11. t16a interrupts 11.7 the t16a module can generate the follo wing six kinds of interrupts: ? compare a interrupt (in comparator mode) ? compare b interrupt (in comparator mode) ? capture a interrupt (in capture mode) ? capture b interrupt (in capture mode) ? capture a o v erwrite interrupt (in capture mode) ? capture b o v erwrite interrupt (in capture mode) each timer chann el outputs a single interrupt signal shared by the abo v e interrupt causes to the interrupt controller (itc). read the interrupt flags in the t16a module to identify the interrupt cause that has been occurred. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-11 interrupts in comparator mode compare a interrupt this interrupt request is generated when the counter matches the compare a re gister v alue during counting in comparator mode. it sets the interrupt flag caif/t16a_iflgx re gister in the t16a module to 1. t o use this interrupt, set caie/t16a_ienx re gister to 1. if caie is set to 0 (def ault), interrupt requests for this cause is not sent to the itc. compare b interrupt this interrupt request is generated when the counter matches the compare b re gister v alue during counting in comparator mode. it sets the interrupt flag cbif/t16a_iflgx re gister in the t16a module to 1. t o use this interrupt, set cbie/t16a_ienx re gister to 1. if cbie is set to 0 (def ault), interrupt requests for this cause is not sent to the itc. interrupts in capture mode captu re a interrupt this interrupt request is generated when the counter v alue is captured in the capture a re gister by an e xter - nal trigger during counting in capture mode. it sets the interrupt flag cap aif/t16a_iflgx re gister in the t16a module to 1. t o use this interrupt, set cap aie/t16a_ienx re gister to 1. if cap aie is set to 0 (def ault), interrupt re- quests for this cause is not sent to the itc. c apture b interrupt this interrupt request is generated when the counter v alue is captured in the capture b re gister by an e xter - nal trigger during counting in capture mode. it sets the interrupt flag capbif/t16a_iflgx re gister in the t16a module to 1. t o use this interrupt, set capbie/t16a_ienx re gister to 1. if capbie is set to 0 (def ault), interrupt re- quests for this cause is not sent to the it c. capture a o verwrite interrupt this interrupt request is generated if the capture a re gister is o v erwritten by a ne w e xternal trigger when the capture a interrupt flag cap aif has been set (a counter v alue has already been loaded to the capture a re gister). it sets the interrupt flag cap a o wif/t16a_iflgx re gister in the t16a module to 1. t o u s e t h i s i n t e r r u p t , s e t c a p a o w i e / t16a _ i e n x r e g i s t e r t o 1. i f c a p a o w i e i s s e t t o 0 ( d e f a u l t ) , interrupt requests for this cause is not sent to the itc. cap a o wif will be set if the capture a re gister is o v erwritten when cap aif has been set re g ardless of whether the capture a re gister has been read or not. therefore, be sure to reset cap aif immediately after the capture a re gister is read. capture b o verwrite interrupt this interrupt request is generated i f the capture b re gister is o v erwritten by a ne w e xternal trigger when the capture b interrupt flag capbif has been set (a counter v alue has already been loaded to the capture b re gister). it sets the interrupt flag capbo wif/t16a_iflgx re gister in the t16a module to 1. t o u s e t h i s i n t e r r u p t , s e t c a p b o w i e / t16a _ i e n x r e g i s t e r t o 1. i f c a p b o w i e i s s e t t o 0 ( d e f a u l t ) , interrupt requests for this cause is not sent to the itc. capbo wif will be set if the capture b re gister is o v erwritten when capbif has been set re g ardless of whether the capture b re gister has been read or not. therefore, be sure to reset capbif immediately after the capture b re gister is read. if the interrupt flag is set to 1 when the interrupt has been enabled, the t16a module outputs an interrupt request to the itc. an interru pt is generated if the itc and s1c17 core interrupt conditions are satisf ied. f or more information on interrupt control re gisters and the operation when an interrupt occurs, see the interrupt controller (itc) chapter . 11 16-bit pwm timers (t16a) 11-12 seiko epson corporation s1c17554/564 t echnical m anual notes: ? reset the interr upt flag bef ore enab ling interr upts with the interr upt enab le bit to pre v ent oc- currence of unw anted interr upt. the interr upt flag is reset b y wr iting 1. ? after an interr upt occurs , the interr upt flag in the t16a module m ust be reset in the interr upt handler routine . contr ol register details 11.8 8.1 list of t16a registers t ab le 11. ad dress register name function 0x5068 t16a_clk0 t16a cloc k control register ch.0 controls the t16a ch.0 cloc k. 0x5069 t16a_clk1 t16a cloc k control register ch.1 controls the t16a ch.1 cloc k. 0x506a t16a_clk2 t16a cloc k control register ch.2 controls the t16a ch.2 cloc k. 0x506b t16a_clk3 t16a cloc k control register ch.3 controls the t16a ch.3 cloc k. 0x5400 t16a_ctl0 t16a counter ch.0 control register controls the counte r . 0x5402 t16a_tc0 t16a counter ch.0 data register counter data 0x5404 t16a_ccctl0 t16a compar ator/capture ch.0 control register controls the compar ator/capture b loc k and t out . 0x5406 t16a_cca0 t16a compare/capture ch.0 a data register compare a/capture a data 0x5408 t16a_ccb0 t16a compare/capture ch.0 b data register compare b/capture b data 0x540a t16a_ien0 t16a compare/capture ch.0 interr upt enab le register enab l es/disab les interr upts . 0x540c t16a_iflg0 t16a compare/capture ch.0 interr upt flag register displa ys/sets interr upt occurrence status . 0x5420 t16a_ctl1 t16a counter ch.1 control register controls the counter . 0x5422 t16a_tc1 t16a counter ch.1 data register counter data 0x5424 t16a_ccctl1 t16a compar ator/capture ch.1 control register controls the compar ator/capture b loc k and t out . 0x5426 t16a_cca1 t16a compare/captu re ch.1 a data register compare a/capture a data 0x5428 t16a_ccb1 t16a compare/capture ch.1 b data register compare b/capture b data 0x542a t16a_ien1 t16a compare/capture ch.1 interr upt enab le register enab les/disab les interr upts . 0x542c t16a_iflg1 t16a compare/capture ch.1 interr upt flag register displa ys/sets interr upt occurrence status . 0x5440 t16a_ctl2 t16a counter ch.2 control register controls the counter . 0x 5442 t16a_tc2 t16a counter ch.2 data register counter data 0x5444 t16a_ccctl2 t16a compar ator/capture ch.2 control register controls the compar ator/capture b loc k and t out . 0x5446 t16a_cca2 t16a compare/capture ch.2 a data register compare a/capture a data 0x5448 t16a_ccb2 t16a compare/capture ch.2 b data register compare b/capture b data 0x544a t16a_ien2 t16a compare/capture ch.2 interr upt enab le register enab les/d isab les interr upts . 0x544c t16a_iflg2 t16a compare/capture ch.2 interr upt flag register displa ys/sets interr upt occurrence status . 0x5460 t16a_ctl3 t16a counter ch.3 control register controls the counter . 0x5462 t16a_tc3 t16a counter ch.3 data register counter data 0x5464 t16a_ccctl3 t16a compar ator/capture ch.3 control register controls the compar ator/capture b loc k and t out . 0x5466 t16a_cca3 t16a compare/capture c h.3 a data register compare a/capture a data 0x5468 t16a_ccb3 t16a compare/capture ch.3 b data register compare b/capture b data 0x546a t16a_ien3 t16a compare/capture ch.3 interr upt enab le register enab les/disab les interr upts . 0x546c t16a_iflg3 t16a compare/capture ch.3 interr upt flag register displa ys/sets interr upt occurrence status . the t16a re gisters are described in detail belo w . note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-13 t16a clock control register ch. x (t16a_clkx) register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.x (t16a_clkx) 0x5068 0x5069 0x506a 0x506b (8 bits) d7C4 clkdiv [3:0] cloc k division r atio select clkdiv[3:0] division r atio 0x0 r/w osc3 or iosc osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C C 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 multimd multi-compar ator/capture mode select 1 multi 0 nor mal 0 r/w t16a_clk0 C reser v ed C C C t16a_clk1C3 0 when being read. d0 clken count cloc k enab le 1 enab le 0 disab le 0 r/w d[7:4] clkdiv[3:0]: clock division ratio select bits selects the di vision ratio for generating the count clock when an internal clock (iosc, osc3, or osc1) is used. 8.2 inter nal cloc k division ratio selection t ab le 11. clkdiv[3:0] division ratio cloc k sour ce = iosc or osc3 cloc k sour ce = osc1 0xf reser v ed 0x e 1/16384 reser v ed 0xd 1/8192 reser v ed 0xc 1/4096 reser v ed 0xb 1/2048 reser v ed 0xa 1/1024 reser v ed 0x9 1/512 reser v ed 0x8 1/256 0x7 1/128 0x6 1/64 0x5 1/32 0x4 1/16 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] clksrc[1:0]: clock source select bits selects the count clock source. 8.3 cloc k source selection t ab le 11. clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (exclx) 0x2 osc3 0x1 osc1 0x0 iosc (s1c17564) (def ault: 0x0) when using an e xternal clock as the count clock, supply the clock to the exclx pin. 11 16-bit pwm timers (t16a) 11-14 seiko epson corporation s1c17554/564 t echnical m anual d1 multimd: multi-comparator/capture mode select bit (t16a_clk0 register) sets the t16a module to multi-comparator/capture mode. 1 (r/w): multi-comparator/capture mode 0 (r/w): normal channel mode (def ault) in multi-comparator/capture mode, the clock for ch.0 conf igured in the t16a_clk0 re gister is sup- plied to all timer channels. in normal channel mode, dif ferent clock conf igured for each channel indi- vidually is supplied to the respecti v e counter . d1 reserved (t16a_clk1C3 registers) d0 clken: count clock enable bit enables or disa bles the count clock supply to the counter . 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the clken def ault setting is 0, which disables the clock supply . setting clken to 1 sends the clock selected as abo v e to the counter . if timer operation is not required, disable the clock supply to reduce current consumption. t16a counter ch.x control registers (t16a_ctlx) register name ad dress bit name function setting init. r/w remarks t16a counter ch.x control register (t16a_ctlx) 0x5400 0x5420 0x5440 0x5460 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 ccabcnt [1:0] counter select ccabcnt[1:0] counter ch. 0x0 r/w 0x3 0x2 0x1 0x0 ch.3 ch.2 ch.1 ch.0 d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w d[15:6] reserved d[5:4] ccabcnt[1:0]: counter select bits selects a counter to be connected to the comparator/capture block of each channel in mul ti-comparator/ capture mode (mul timd/t16a_clk0 re gister = 1). 8.4 counter selection t ab le 11. ccabcnt[1:0] counter c hannel 0x3 ch.3 (counter 3) 0x2 ch.2 (counter 2) 0x1 ch.1 (counter 1) 0x0 ch.0 (counter 0) (def ault: 0x0) when using the t16a module in normal channel mode (t16amul timd = 0), be sure to connect the counter of the same channel to each comparator/capture block. d3 cbufen: compare buffer enable bit enables or disables writing to the compare b uf fer . 1 (r/w): enabled 0 (r/w): disabled (def ault) when cb ufen is set to 1, com pare data is written via the compare data b uf fer . the b uf fer contents are loaded into the compare a and compare b re gisters when the compare b signal is generated. when cb ufen is set to 0, compare data is written directly to the compare a and compare b re gisters. note: make sure the counter is halted (prun = 0) before setting cbufen. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-15 d2 trmd: count mode select bit selects the count mode. 1 (r/w): one-shot mode 0 (r/w): repeat mode (def ault) setting trmd to 0 sets the counter to repeat mode. in this mode, once the count starts, the counter con- tinues counting until stopped by the application program. setting trmd to 1 sets the counter to one-shot mode. in this mode, the counter stops counting auto- matically as soon as the compare b signal is generated. d1 preset: counter reset bit r esets the counter . 1 (w): reset 0 (w): ignored 0 (r): normally 0 when read out (def ault) writing 1 to this bit resets the counter to 0. d0 prun: counter run/stop control bit starts/stops the count. 1 (w): run 0 (w): stop 1 (r): counting 0 (r): stopped (def ault) the counter starts counting when pr un is written as 1 and stops when written as 0. the counter data is retained e v en if the counter is stopped. t16a counter ch.x data registers (t16a_tcx) register name ad dress bit name function setting init. r/w remarks t16a counter ch.x data register (t16a_tcx) 0x5402 0x5422 0x5442 0x5462 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r d[15:0] t16atc[15:0]: counter data bits counter data can be read out. (def ault: 0x0) the counter v alue can be read out e v en if the counter is running. ho we v er , the counter v alue should be read at once using a 16-bit transfer instruction. if data is read twice using an 8-bit transfer instruction, the correct v alue may not be obtained due to occurrence o f count up between readings. 11 16-bit pwm timers (t16a) 11-16 seiko epson corporation s1c17554/564 t echnical m anual t16a comparator/capture ch.x control registers (t16a_ccctlx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x control register (t16a_ccctlx) 0x5404 0x5424 0x5444 0x5464 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w d[15:14] capbtrg[1:0]: capture b trigger select bits selects the trigger edge(s) of the e xternal signal (cap1/3/5/7) at which the counter v alue is captured in the capture b re gister . 8.5 capture b t r igger edge selection t ab le 11. capbtrg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) capbtrg[1:0] are control bits for capture mode and are inef fecti v e in comparator mode. d[13:12] toutbmd[1:0]: tout b mode select bits conf igures ho w the t out b signal w a v eform (t out1/3/5/7 output) is changed by the compare a and compare b signals. these bits are also used to turn the t out b output on and of f. 8.6 t out b gener a tion mode t ab le 11. t outbmd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0) t outbmd[1:0] are control bits for comparator mode and are inef fecti v e in capture mode. d[11:10] reserved d9 toutbinv: tout b invert bit selects the t out b signal (t out1/3/5/7 output) polarity . 1 (r/w): in v erted (acti v e lo w) 0 (r/w): normal (acti v e high) (def ault) writing 1 to t outbinv generates an acti v e lo w sign al (of f le v el = high) for the t out b output. when t outbinv is 0, an acti v e high signal (of f le v el = lo w) is generated. t outbinv is a control bit for comparator mode and is inef fecti v e in capture mode. 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-17 d8 ccbmd: t16a_ccb register mode select bit selects the t16a_ccbx re gister function (comparator mode or capture mode). 1 (r/w): capture mode 0 (r/w): comparator mode (def ault) writing 1 to ccbmd conf igures the t16a_ccbx re gister as the capture b re gister (capture mode) to which the counter data will be loaded by the e xternal trigger signal. when ccbmd is 0, the t16a_ ccbx re gister functions as the compare b re gister (comparator mode) for writing a comparison v alue to generate the compare b signal. d[7:6] capatrg[1:0]: capture a trigger select bits selects the trigger edge(s) of the e xternal signal (cap0/2/4/6) at which the counter v alue is captured in the capture a re gister . 8.7 capture a t r igger edge selection t ab le 11. cap a trg[1:0] t rig g er edg e 0x3 f alling edge and r ising edge 0x2 f alling edge 0x1 rising edge 0x0 not tr iggered (def ault: 0x0) cap a trg[1:0] are control bits for capture mode and are inef fecti v e in comparator mode. d[5:4] toutamd[1:0]: tout a mode select bits conf igures ho w the t out a signal w a v eform (t out0/2/4/6 output) is changed by the compare a and compare b signals. these bits are also used to turn the t out a output on and of f. 8.8 t out a gener a tion mode t ab le 11. t out amd[1:0] when compare a occur s when compare b occur s 0x3 no change t oggle 0x2 t oggle no change 0x1 rise f all 0x0 disab le output (def ault: 0x0) t out amd[1:0] are control bits for comparator mode and are inef fecti v e in capture mode. d[3:2] reserved d1 toutainv: tout a invert bit selects the t out a signal (t out0/2/4/6 output) polarity . 1 (r/w): in v erted (acti v e lo w) 0 (r/w): normal (acti v e high) (def ault) writing 1 to t out ainv generates an acti v e lo w sign al (of f le v el = high) for the t out a output. when t out ainv is 0, an acti v e high signal (of f le v el = lo w) is generated. t out ainv is a control bit for comparator mode and is inef fecti v e in capture mode. d0 ccamd: t16a_cca register mode select bit selects the t16a_ccax re gister function (comparator mode or capture mode). 1 (r/w): capture mode 0 (r/w): comparator mode (def ault) writing 1 to ccamd conf igures the t16a_ccax re gister as the captu re a re gister (capture mode) to which the counter data will be loaded by the e xternal trigger signal. when ccamd is 0, the t16a_ ccax re gister functions as the compare a re gister (comparator mode) for writing a comparison v alue to generate the compare a signal. 11 16-bit pwm timers (t16a) 11-18 seiko epson corporation s1c17554/564 t echnical m anual t16a comparator/capture ch.x a data registers (t16a_ccax) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x a data register (t16a_ccax) 0x5406 0x5426 0x5446 0x5466 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w d[15:0] cca[15:0]: compare/capture a data bits in compar ator mode (ccamd/ t16a_ccctlx register = 0) sets a compare a data, which will be compared with the counter v alue, through this re gister . when cb ufen/t16a_ctlx re gister is set to 0, compare a data will be set to the compare a re gister after a lapse of tw o t16a count clock c ycles from the time when i t is written to this re gister . when cb ufen is set to 1, the data written to this re gister is loaded to the compare a b uf fer . the b uf fer contents are loaded into the compare a re gister when the compare b signal is generated. the compare a re gister is al w ays directly accessed when being read re g ardless of the cb ufen setting. the data set is compared with the counter data. when the counter reaches th e comparison v alue set, the compare a signal is asserted and a cause of compare a interrupt occurs. furthermore, the t out output w a v eform changes when t out amd[1:0]/t16a_ccctlx re gister or t outbmd[1:0]/t16a_ ccctlx re gister is set to 0x2 or 0x1. these processes do not af fect the counter data and the count up operation. in capture mode (ccamd = 1) w h e n t h e c o u n t e r v a l u e i s c a p t u r e d a t t h e e x t e r n a l t r i g g e r s i g n a l ( c a p0/2/4/6) e d g e s e l e c t e d u s i n g cap a trg[1:0]/t16a_ccctlx re gister , the captured v alue is loaded to this re gister . at the same time a capture a interrupt can be generated, thus the captured counter v alue can be read out in the interrupt handler . t16a comparator/capture ch.x b data registers (t16a_ccbx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x b data register (t16a_ccbx) 0x5408 0x5428 0x5448 0x5468 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w d[15:0] ccb[15:0]: compare/capture b data bits in compar ator mode (ccbmd/ t16a_ccctlx register = 0) sets a compare b data, which will be compared with the counter v alue, through this re gister . when cb ufen/t16a_ctlx re gister is set to 0, compare b data will be set to the compare b re gister after a lapse of tw o t16a count clock c ycles from the time when i t is written to this re gister . when cb ufen is set to 1, the data written to this re gister is loaded to the compare b b uf fer . the b uf fer contents are loaded into the compare b re gister when the compare b signal is generated. the compare b re gister is al w ays directly accessed when being read re g ardless of the cb ufen setting. the data set is compared with the counter data. when the counter reaches th e comparison v alue set, the compare b signal is asserted and a cause of compare b interrupt occurs. the counter is reset to 0. furthermore, the t out output w a v eform changes when t out amd[1:0]/t16a_ccctlx re gister or t outbmd[1:0]/t16a_ccctlx re gister is set to 0x3 or 0x1. in capture mode (ccbmd = 1) w h e n t h e c o u n t e r v a l u e i s c a p t u r e d a t t h e e x t e r n a l t r i g g e r s i g n a l ( c a p1/3/5/7) e d g e s e l e c t e d u s i n g ca pbtrg[1:0]/t16a_ccctlx re gister , the captured v alue is loaded to this re gister . at the same time a capture b interrupt can be generated, thus the captured counter v alue can be read out in the interrupt handler . note: when wr iting data to the t16a_ccax or t16a_ccbx register successiv ely , data should be wr it- ten at inter v als of one or more t16a count cloc k cycles . 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-19 t16a comparator/capture ch.x interrupt enable registers (t16a_ienx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x interrupt enable register (t16a_ienx) 0x540a 0x542a 0x544a 0x546a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w d[15:6] reserved d5 capbowie: capture b overwrite interrupt enable bit enables or disables capture b o v erwrite interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting capbo wie to 1 enables capture b o v erwrite interrupt requests to the itc. setting it to 0 dis- ables interrupts. d4 capaowie: capture a overwrite interrupt enable bit enables or disables capture a o v erwrite interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cap a o wie to 1 enables capture a o v erwrite interrupt requests to the itc. setting it to 0 dis- ables interrupts. d3 capbie: capture b interrupt enable bit enables or disables capture b interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting capbie to 1 enables capture b interrupt requests to the itc. setting it to 0 disables interrupts. d2 capaie: capture a interrupt enable bit enables or disables capture a interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cap aie to 1 enables capture a interrupt requests to the itc. setting it to 0 disables interrupts. d1 cbie: compare b interrupt enable bit enables or disables compare b interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting cbie to 1 enables compare b interrupt requests to the itc. setting it to 0 disables interrupts. d0 caie: compare a interrupt enable bit enables or disables compare a interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting c aie to 1 enables compare a interrupt requests to the itc. setting it to 0 disables interrupts. 11 16-bit pwm timers (t16a) 11-20 seiko epson corporation s1c17554/564 t echnical m anual t16a comparator/capture ch.x interrupt flag registers (t16a_iflgx) register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.x interrupt flag register (t16a_iflgx) 0x540c 0x542c 0x544c 0x546c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w d[15:6] reserved d5 capbowif: capture b overwrite interrupt flag bit indicates whether the cause of capture b o v erwrite int errupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored c a p b o w i f i s a t 1 6 a i n t e r r u p t f l a g t h a t i s set to 1 when the capture b re gister is o v erwritten. capbo wif is reset by writing 1. d4 capaowif: capture a overwrite interrupt flag bit indicates whether the cause of capture a o v erwrite interrupt has occurred or not. 1 (r): cause of interrupt has occu rred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored c a p a o w i f i s a t 1 6 a i n t e r r u p t f l a g t h a t i s set to 1 when the capture a re gister is o v erwritten. cap a o wif is reset by writing 1. d3 capbif: capture b interrupt flag bit indicates whether the cause of capture b interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored capbif is a t16a interrupt flag that is set to 1 when the counter v alue is captured in the capture b re g- ister . capbif is reset by writing 1. d2 capaif: capture a interrupt flag bit indicates whether the cause of capture a interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored cap aif is a t16a interrupt flag that is set to 1 when the counter v alue is captured in the capture a re g- ister . cap aif is reset by writing 1. d1 cbif: compare b interrupt flag bit indicates whether the cause of compare b interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored 11 16-bit pwm timers (t16a) s1c17554/564 t echnical m anual seiko epson corporation 11-21 cbif is a t16a interrupt flag that is set to 1 when the counter reaches the v alue set in the compare b re gister . cbif is reset by writing 1. d0 caif: compare a interrupt flag bit indicates whether the cause of compare a interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored caif is a t16a interrupt flag that is set to 1 when the co unter reaches the v alue set in the compare a re gister . caif is reset by writing 1. 12 clock timer (ct) s1c17554/564 t echnical m anual seiko epson corporation 12-1 clock t imer (ct) 12 ct module over vie w 12.1 the s1c17554/564 includes a clock timer module (ct) that uses the osc1 oscillator as its clock source. this timer can be used for generating c yclic interrupts to implement a softw are clock function. the features of the ct module are listed belo w . ? 8-bit binary counter (128 hz to 1 hz) ? 32 hz, 8 hz, 2 hz, and 1 hz interrupts can be generated. figure 12.1.1 sho ws the ct conf iguration. 256 hz internal data bus clock timer interrupt request to itc 128 hz 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz count control circuit interrupt control circuit run/stop control interrupt enable ctrun ctie32 ctie8 ctie2 ctie1 timer reset ctrst ct_cnt d0 d1 d2 d3 d4 d5 d6 d7 clock timer clg osc1 oscillator/divider 1.1 ct configur ation figure 12. the ct module consists of an 8-bit binary counter that uses the 256 hz signal di vided from the osc1 clock as the input clock and allo ws data for each bit (128 hz to 1 hz) to be read out by softw are. the clock timer can also gen- erate interrupts using the 32 hz, 8 hz, 2 hz, and 1 hz signals. this clock timer is normally used for v arious timing functions, such as a clo ck. operation cloc k 12.2 the ct module uses the 256 hz clock output by the clg module as the operation clock. the clg module gener - ates this operation clock by di viding the osc1 clock into 1/128, resulting in a frequenc y of 256 hz when the osc1 clock frequenc y is 32.768 khz. the frequenc y described in this chapter will v ary accordingly for other osc1 clock frequencies. the clg module does not includ e a 256 hz clock output control bit. the 256 hz clock is normally supplied to the clock timer when the osc1 oscillation is on. f or detailed information on osc1 oscillator control, see the clock generator (clg) chapter . note: the osc1 oscillator m ust be tur ned on bef ore the ct module can oper ate . timer reset 12.3 reset the timer by writing 1 to ctrst/ct_ctl re gister . this clears the counter to 0. apart from this operation, the counter is also cleared by an initial reset. timer r un/st op contr ol 12.4 mak e the follo wing settings before starting ct . (1) if using interrupts, set the interrupt le v el and enable interrupts for the clock timer . see section 12.5. (2) reset the timer . see section 12.3. the clock timer includes ctr un/ct_ctl re gister for run/stop control. 12 clock timer (ct) 12-2 seiko epson corporation s1c17554/564 t echnical m anual the clock timer starts operating when 1 is written to ctr un. writing 0 to ctr un disables clock input and stops the operation. this control does not af fect the counter (ct_cnt re gister) data. the counter data is retained e v en when the count is halted, allo wing resumption of the count from that data. if 1 is written to both ctr un and ctrst simultaneously , the clock timer starts counting after resettin g. a cause of interrupt occurs during counting at the 32 hz, 8 hz, 2 hz, and 1 hz signal f alling edges. if interrupts are enabled, an interrupt request is sent to the interrupt controller (itc). 256 hz 128 hz 64 hz 32 hz 16 hz 8 hz 4 hz 2 hz 1 hz 32 hz interrupt 8 hz interrupt 2 hz interrupt 1 hz interrupt osc1/128 ctcnt0 ctcnt1 ctcnt2 ctcnt3 ctcnt4 ctcnt5 ctcnt6 ctcnt7 4.1 cloc k timer timing char t figure 12. notes: ? the cloc k timer s witches to run/stop status synchroniz ed with the 256 hz signal f alling edge after data is wr itten to ctr un. when 0 is wr itten to ctr un, the timer stops after counting an additional +1. 1 is retained f or ctr un reading until the timer actually stops . figure 12.4.2 sho ws the run/stop control timing char t. ctrun(wr) ct_cnt register 0x57 0x58 0x59 0x5a 0x5b 0x5c ctrun(rd) 256 hz 4.2 run/stop control timing char t figure 12. ? ex ecuting the slp instr uction while the timer is r unning (ctr un = 1) will destabiliz e the timer o p e r a t i o n d u r i n g r e s t a r t i n g f r o m s l e e p s t a t u s . w h e n s w i t c h i n g t o s l e e p s t a t u s , s t o p t h e timer (ctr un = 0) bef ore e x ecuting the slp instr uction. ct interrupts 12.5 the ct module includes functions for generating the follo wing four kinds of interrupts: 32 hz, 8 hz, 2 hz, and 1 hz interrupts the ct module outputs a single interrupt signal shared by the abo v e four interrupt causes to the interrupt controller (itc). the interrupt flag in the ct module should be read to identify the cause of interrupt that occurred. 32 hz, 8 hz, 2 hz, and 1 hz interrupts t h e 3 2 h z , 8 h z , 2 h z , a n d 1 h z s i g n a l f a l l i n g e d g e s s e t t h e c o r r e s p o n d i n g i n t e r r u p t f l a g i n t h e c t m o d u l e t o 1 . at the same time, an interrupt request is sent to the itc if the corresponding interrupt enable bit has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. if the interrupt enable bit is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. 12 clock timer (ct) s1c17554/564 t echnical m anual seiko epson corporation 12-3 5.1 ct interr upt flags and interr upt enab le bits t ab le 12. cause of interrupt interrupt fla g interrupt enab le bit 32 hz interr upt ctif32/ct_iflg register ctie32/ct_imsk register 8 hz interr upt ctif8/ct_iflg register ctie8/ct_imsk register 2 hz interr upt ctif2/ct_iflg register ctie2/ct_imsk register 1 hz interr upt ctif1/ct_iflg register ctie1/ct_imsk register f or specif ic information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? the ct m odule interr upt flag m ust be reset in the interr upt handler routine after a ct interr upt has occurred to pre v ent recurr ing interr upts . ? reset the interr upt flag bef ore enab ling ct interr upts with the interr upt enab le bit to pre v ent occurrence of unw anted interr upt. the interr upt flag is reset b y wr iting 1. contr ol register details 12.6 6.1 list of ct registers t ab le 12. ad dress register name function 0x5000 ct_ctl cloc k timer control register resets and star ts/stops the timer . 0x5001 ct_cnt cloc k timer counter register counter data 0x5002 ct_imsk cloc k timer interr upt mask register enab les/disab les interr upt. 0x5003 ct_iflg cloc k timer interr upt flag register indicates/resets interr upt occurrence status . the ct re gisters are described in detail belo w . these are 8-bit re gisters. note: w hen data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. clock timer control register (ct_ctl) register name ad dress bit name function setting init. r/w remarks clock timer control register (ct_ctl) 0x5000 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 ctrst cloc k timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 ctrun cloc k timer r un/stop control 1 run 0 stop 0 r/w d[7:5] reserved d4 ctrst: clock timer reset bit resets the clock timer . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit resets the counter to 0x0. when reset in run state, the clock timer restarts immedi- ately after resetting. the reset data 0x0 is retained when in stop state. d[3:1] reserved d0 ctrun: clock timer run/stop control bit controls the clock timer run/stop. 1 (r/w): run 0 (r/w): stop (def ault) the clock timer starts counting when ctr un is written as 1 and stops when written as 0. the counter data is retained at stop state until a reset or the ne xt run state. clock timer counter register (ct_cnt) register name ad dress bit name function setting init. r/w remarks clock timer counter register (ct_cnt) 0x5001 (8 bits) d7C0 ctcnt[7:0] cloc k timer counter v alue 0x0 to 0xff 0x0 r 12 clock timer (ct) 12-4 seiko epson corporation s1c17554/564 t echnical m anual d[7:0] ctcnt[7:0]: clock timer counter value bits the counter data can be read out. (def ault: 0x0) this re gister is read-only and cannot be written to. the bits correspond to v arious frequencies, as follo ws: d7: 1 hz, d6: 2 hz, d5: 4 hz, d4: 8 hz, d3: 16 hz, d2: 32 hz, d1: 64 hz, d0: 128 hz note: the correct counter v alue ma y not be read out (reading is unstab le) if the register is read while counting is underw a y . read the counter register twice in succession and treat the v alue as v alid if the v alues read are identical. clock timer interrupt mask register (ct_imsk) register name ad dress bit name function setting init. r/w remarks clock timer interrupt mask register (ct_imsk) 0x5002 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctie32 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 ctie8 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 ctie2 2 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 ctie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w this re gister enables or disables interrupt requests indi vidually for the 32 hz, 8 hz, 2 hz, and 1 hz signals. setting ctie* to 1 enables ct interrupts for the corresponding freque nc y signal f alling edge, while setting to 0 disables interrupts. d[7:4] reserved d3 ctie32: 32 hz interrupt enable bit enables or disables 32 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d2 ctie8: 8 hz interrupt enable bit enables or disables 8 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d1 ctie2: 2 hz interrupt enable bit enables or disables 2 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d0 ctie1: 1 hz interrupt enable bit enables or disables 1 h z interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) clock timer interrupt flag register (ct_iflg) register name ad dress bit name function setting init. r/w remarks clock timer interrupt flag register (ct_iflg) 0x5003 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctif32 32 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d2 ctif8 8 hz interr upt flag 0 r/w d1 ctif2 2 hz interr upt flag 0 r/w d0 ctif1 1 hz interr upt flag 0 r/w this re gister indicates the occurrence state of interrupt causes due to 32 hz, 8 hz, 2 hz, and 1 hz signals. if a ct interrupt occurs, identify the interrupt cause (freq uenc y) by reading the interrupt flag in this re gister . ctif* is a ct module interrupt flag that is set to 1 at the f alling edge of the corresponding 32 hz, 8 hz, 2 hz, or 1 hz interrupt. ctif* is reset by writing 1. d[7:4] reserved 12 clock timer (ct) s1c17554/564 t echnical m anual seiko epson corporation 12-5 d3 ctif32: 32 hz interrupt flag bit indicates whether the cause of 32 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d2 ctif8: 8 hz interrupt flag bit indicates whether the cause of 8 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d1 ctif2: 2 hz interrupt flag bit indicat es whether the cause of 2 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d0 ctif1: 1 hz interrupt flag bit indicates whether the cause of 1 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored 13 st opw a tch timer (swt) s1c17554/564 t echnical m anual seiko epson corporation 13-1 stopwatch t imer (swt) 13 swt module over vie w 13.1 the s1c17554/564 includes a 1/100-second stopw atch timer module (swt) that uses the osc1 oscillator as its clock source. this timer can be used to implement a softw are stopw atch function. the features of the swt module are listed belo w . ? t w o 4-bit bcd counters (approximately 1/100 and 1/10-second counters) ? approximately 100 hz, approximately 10 hz, and 1 hz interrupts can be generated. figure 13.1.1 sho ws the swt conf iguration. 256 hz internal data bus interrupt request to itc feedback divider 1/100 s 4-bit bcd counter 1/10 s 4-bit bcd counter count control circuit interrupt control circuit run/stop control interrupt enable swtrun sie100 sie10 sie1 reset swtrst stopwatch timer clg osc1 oscillator/divider approx. 100 hz approx. 10 hz 1 hz 1.1 swt configur ation figure 13. the swt module consists of tw o 4-bit bcd counters (1/100 and 1/10 second) that use the 256 hz signal di vided from the osc1 clock as the input clock and allo ws count data to be read out by softw are. the swt module can also generate interrupts using the 100 hz (approximately 100 hz), 10 hz (approximately 10 hz), and 1 hz signals. operation cloc k 13.2 t h e s w t m o d u l e u s e s t h e 256 h z c l o c k o u t p u t b y t h e c l g m o d u l e a s t h e o p e r a t i o n c l o c k . t h e c l g m o d u l e generates this operation clock by di viding the osc1 clock into 1/128, resulting in a frequenc y of 256 hz when the osc1 clock frequenc y is 32.768 khz. the frequenc y described in this chapter will v ary accordingly for other osc1 clock frequencies. the clg module does not include a 256 hz clock output control bit. the 2 56 hz clock is normally supplied to the swt module when the osc1 oscillation is on. f or detailed information on osc1 oscillator control, see the clock generator (clg) chapter . note: the osc1 oscillator m ust be tur ned on bef ore the swt module can oper ate . bcd counter s 13.3 the swt module consists of 1/100-second and 1/10-second 4-bit bcd counters. t h e 1/100- s e c o n d a n d 1/10- s e c o n d c o u n t e r v a l u e s c a n b e r e a d f r o m b c d100[3:0] / s w t _ b c n t r e g i s t e r a n d bcd10[3:0]/swt_bcnt re gister , respecti v ely . count-up p attern a feedback di vider is used to generate 100 hz, 10 hz, and 1 hz signals from the 256 hz clock. the counter count-up pattern v aries as sho wn in figure 13.3.1. 13 st opw a tch timer (swt) 13-2 seiko epson corporation s1c17554/564 t echnical m anual 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 1/100-second counter count-up pattern 1 256 hz approximate 100 hz (feedback divider output) 1/100-second counter approximate 10 hz (1/100-second counter output) approximate 10 hz (1/100-second counter output) 1/10-second counter 1 hz (1/10-second counter output) 25 256 1/100-second counter count-up pattern 2 s 26 256 6 + 25 256 4 = 1 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s 25 256 s 25 256 s 26 256 s 26 256 s s 26 256 3 256 3 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1/10-second counter count-up pattern 3.1 swt count-up p atter ns figure 13. the feedback di vider generates an approximate 100 hz signal at 2/256-second and 3/256-second interv als from the 256 hz signal supplied from the clg module. t h e 1/100- s e c o n d c o u n t e r c o u n t s t h e a p p r o x i m a t e 100 h z s i g n a l o u t p u t b y t h e f e e d b a c k d i v i d e r a n d g e n e r - a t e s a n a p p r o x i m a t e 10 h z s i g n a l a t 25/256- s e c o n d a n d 26/256- s e c o n d i n t e r v a l s . c o u n t - u p w i l l b e p s e u d o 1 /100-second counting at 2/256-second and 3/256-second interv als. the 1/10-second counter counts the approximate 10 hz signal generated by the 1/100-second counter at a ra- tio of 4:6, and generates a 1 hz signal. count-up will be pseudo 1/10-second counting at 25/256-second and 26/256-second interv als. timer reset 13.4 reset the swt module by writing 1 to swtrst/swt_ctl re gister . this clears the cou nter to 0. apart from this operation, the counter is also cleared by initial reset. timer r un/st op contr ol 13.5 mak e the follo wing settings before starting swt . (1) if using interrupts, set the interrupt le v el and enable interrupts for the swt module. see section 13.6. (2) reset the timer . see section 13.4. t h e swt module i n c l u d e s s w t r u n / s w t _ c t l r e g i s t e r f o r r u n / s t o p c o n t r o l . the timer starts operating when 1 is written to swtr un. writing 0 to swtr un disables clock input and stops the operation. this control does not af fect the counter (swt_bcnt re gister) data. the counter data is retained e v en when the count is halted, allo wing resumption of the count from that data. if 1 is written to both swtr un and swtrst simultaneously , the timer starts counting after resetting. a cause of interrupt occurs d uring counting at the 100 hz (approximate 100 hz), 10 hz (approximate 10 hz), and 1 hz signal f alling edges. if interrupts are enabled, an interrupt request is sent to the interrupt controller (itc). 13 st opw a tch timer (swt) s1c17554/564 t echnical m anual seiko epson corporation 13-3 bcd100[0] bcd100[1] bcd100[2] bcd100[3] 100 hz interrupt 10 hz interrupt 1/100-second counter bcd data bcd10[0] bcd10[1] bcd10[2] bcd10[3] 1 hz interrupt 1/10-second counter bcd data 123456789012345678901234 0 5.1 swt timing char t figure 13. notes: ? the timer s witches to run/stop status synchroniz ed with the 256 hz signal f alling edge after data is wr itten to swtr un. when 0 is wr itten to swtr un, the timer stops after counting an additional +1. 1 is retained f or swtr un reading until the timer actually stops . figure 13.5.2 sho ws the run/stop control timing char t. swtrun(wr) swt_bcnt register 27 28 29 30 31 32 swtrun(rd) 256 hz 5.2 run/stop control timing char t figure 13. ? ex ecuting the slp instr uction while the timer is r unning (swtr un = 1) will destabiliz e the timer oper ation dur ing restar ting from sleep status . when s witching to sleep status , stop the timer (swtr un = 0) bef ore e x ecuting the slp instr uction. swt interrupts 13.6 the swt module includes functions for generating the follo wing three kinds of interrupts: 100 hz, 10 hz, and 1 hz interrupts the swt module outputs a single interrupt signal shared by the abo v e three interrupt causes to the interrupt control- ler (itc). the interrupt flag in the swt module should be read to identify the cause of interrupt that occurred. 100 hz, 10 hz, 1 hz interrupts the 100 hz (approximate 100 hz), 10 hz (approximate 10 hz), and 1 hz signal f alling edges set the corre- sponding interrupt flag in the swt module to 1. at the same time, an interrupt request is sent to the itc if the corresponding interrupt enable bit has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. if the interrupt enable bit is set to 0 (interrupt disabled, def ault), no interrupt request will be sent to the itc. 6.1 swt interr upt flags and interr upt enab le bits t ab le 13. cause of interrupt interrupt fla g interrupt enab le bit 100 hz interr upt sif100/swt_iflg register sie100/swt_imsk register 10 hz interr upt sif10/swt_iflg register sie10/swt_imsk register 1 hz interr upt sif1/swt_iflg register sie1/swt_imsk register f or specif ic information on interrupt processing, see the interrupt controller (itc) chapter . 13 st opw a tch timer (swt) 13-4 seiko epson corporation s1c17554/564 t echnical m anual notes: ? the swt module interr upt flag m ust be reset in the interr upt handler routine after a stopw atch timer interr upt has occurred to pre v ent recurr ing interr upts . ? reset the interr upt flag bef ore enab ling swt interr upts with the interr upt enab le bit to pre v ent occurrence of unw anted interr upt. the interr upt flag is reset b y wr iting 1. contr ol register details 13.7 7.1 list of swt registers t ab le 13 . ad dress register name function 0x5020 swt_ctl stopw atch timer control register resets and star ts/stops the timer . 0x5021 swt_bcnt stopw atch timer bcd counter register bcd counter data 0x5022 swt_imsk stopw atch timer interr upt mask register enab les/disab les interr upt. 0x5023 swt_iflg stopw atch timer interr upt flag register indicates/resets interr upt occurrence status . the swt re gisters are described in detail belo w . these are 8-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. stopwatch timer control register (swt_ctl) register name ad dress bit name function setting init. r/w remarks stopwatch timer control register (swt_ctl) 0x5020 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 swtrst stopw atch timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 swtrun stopw atch timer r un/stop control 1 run 0 stop 0 r/w d[7:5] reserved d4 swtrst: stopwatch timer reset bit resets the swt module. 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) writing 1 to this bit resets the counter to 0x0. when reset in run state, the timer restarts immediately after resetting. the reset data 0x0 is retained when in stop state. d[3:1] reserved d0 swtrun: stopwatch timer run/stop control bit controls the timer run/stop. 1 (r/w): run 0 (r/w): stop (def ault) the timer starts counting when swtr un is written as 1 and stops when written as 0. the counter data is retained at stop state until a reset or the ne xt run state. stopwatch timer bcd counter register (swt_bcnt) register name ad dress bit name function setting init. r/w remarks stopwatch timer bcd counter register (swt_bcnt) 0x5021 (8 bits) d7C4 bcd10[3:0] 1/10 sec. bcd counter v alue 0 to 9 0 r d3C0 bcd100[3:0] 1/100 sec. bcd counter v alue 0 to 9 0 r d[7:4] bcd10[3:0]: 1/10 sec. bcd counter value bits the 1/10-second counter bcd data can be read out. (def ault: 0) this re gister is read-only and cannot be written to. d[3:0] bcd100[3:0]: 1/100 sec. bcd counter value bits the 1/100-second counter bcd data can be read out. (def ault: 0) this re gister is read-only and cannot be written to. 13 st opw a tch timer (swt) s1c17554/564 t echnical m anual seiko epson corporation 13-5 note: the correct counter v alue ma y not be read out (reading is unstab le) if the register is read while counting is underw a y . read the counter register twice in succession and treat the v alue as v alid if the v alues read are identical. stopwatch timer interrupt mask register (swt_imsk) register name ad dress bit name function setting init. r/w remarks stopwatch timer interrupt mask register (swt_imsk) 0x5022 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 sie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 sie10 10 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 sie100 100 hz interr upt enab le 1 enab le 0 disab le 0 r/w this re gister enables or disables interrupt requests indi vidually for the 100 hz, 10 hz, and 1 hz signals. setting sie* to 1 enables swt interrupts for the corresponding frequenc y signal f alling edge, while setting to 0 d isables interrupts. d[7:3] reserved d2 sie1: 1 hz interrupt enable bit enables or disables 1 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d1 sie10: 10 hz interrupt enable bit enables or disables 10 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d0 sie100: 100 hz interrupt enable bit enables or disables 100 hz interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) stopwatch timer interrupt flag register (swt_iflg) register name ad dress bit name function setting init. r/w remarks stopwatch timer interrupt flag register (swt_iflg) 0x5023 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 sif1 1 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d1 sif10 10 hz interr upt flag 0 r/w d0 sif100 100 hz interr upt flag 0 r/w this re gister indicates the occurrence state of interrupt causes due to 100 hz, 10 hz, and 1 hz signals. if an swt interrupt occurs, identify the interrupt cause (frequenc y) by reading the inte rrupt flag in this re gister . sif* is an swt module interrupt flag that is set to 1 at the f alling edge of the corresponding 100 hz, 10 hz, or 1 hz interrupt. sif* is reset by writing 1. d[7:3] reserved d2 sif1: 1 hz interrupt flag bit indicates whether the cause of 1 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored d1 sif10: 10 hz interrupt flag bit indicates whether the cause of 10 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored 13 st opw a tch timer (swt) 13-6 seiko epson corporation s1c17554/564 t echnical m anual d0 sif100: 100 hz interrupt flag bit indicates whether the cause of 100 hz interrupt has occurred or not. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored 14 w a tchdog timer (wdt) s1c17554/564 t echnical m anual seiko epson corporation 14-1 w atchdog t imer (wdt) 14 wdt module over vie w 14.1 the s1c17554/564 includes a w atchdog timer module (wdt) that uses the osc1 oscillator as its clock source. this timer is used to detect cpu runa w ay . the features of wdt are listed belo w . ? 10-bit up counter ? either reset or nmi can be generated if the counter o v erflo ws. figure 14.1.1 sho ws the wdt conf iguration. 256 hz nmi reset 10-bit counter interrupt control circuit run/stop control nmi/reset mode select wdtrun[3:0] wdtmd watchdog timer reset wdtrst watchdog timer clg osc1 oscillator/divider 1.1 wdt configur ation figure 14. the wdt module generates an nmi or reset (selectable via softw are) to the cpu if not reset within 131,072/f osc1 seconds (4 seconds when f osc1 = 32.768 khz). reset wdt via softw are within this c ycle to pre v ent nmi/resets, which in turn enables runa w ay detection for pro- grams that do not pass through the handler routine. operation cloc k 14.2 t h e w d t m o d u l e u s e s t h e 256 h z c l o c k o u t p u t b y t h e c l g m o d u l e a s t h e o p e r a t i o n c l o c k . t h e c l g m o d u l e generates this operation clock by di viding the osc1 clock into 1/128, resulting in a frequenc y of 256 hz when the osc1 clock frequenc y is 32.768 khz. the frequenc y described in this chapter will v ary accordingly for other osc1 clock frequencies. the clg module does not include a 256 hz clock output control bit. the 256 hz clo ck is normally supplied to the wdt module when the osc1 oscillation is on. f or detailed information on osc1 oscillator control, see the clock generator (clg) chapter . wdt contr ol 14.3 nmi/reset mode selection 14.3.1 wdtmd/wdt_st re gister is used to select whether an nmi signal or a reset signal is output when wdt has not been reset within the nmi/reset generation c ycle. t o generate an nmi, set wdtm d to 0 (def ault). set to 1 to generate a reset. wdt run/stop contr ol 14.3.2 wdt starts counting when a v alue other than 0b1010 is written to wdtr un[3:0]/wdt_ctl re gister and stops when 0b1010 is written. at initial reset, wdtr un[3:0] is set to 0b1010 to stop wdt . since an nmi or reset may be generated immediately after running depending on the counter v alue, wdt should also be reset concurrently (bef ore running wdt), as e xplained in the follo wing section. 14 w a tchdog timer (wdt) 14-2 seiko epson corporation s1c17554/564 t echnical m anual wdt reset 14.3.3 t o reset wdt , write 1 to wdtrst/wdt_ctl re gister . a location should be pro vided for periodically processing the routine for resetting wdt before an nmi or reset is generated when using wdt . process this routine within 131,072/f osc1 second (4 seconds when f osc1 = 32.768 khz) c ycle. after resetting, wdt starts counting with a ne w nmi/reset generation c ycle. if wdt is not reset within t he nmi/reset generation c ycle for an y reason, the cpu is switched to interrupt pro- cessing by nmi or reset, the interrupt v ector is read out, and the interrupt handler routine is e x ecuted. the reset and nmi v ector addresses are ttbr + 0x0 and ttbr + 0x08. if the counter o v erflo ws and generates an nmi without wdt being reset, wdtst/wdt_st re gister is set to 1. this bit is pro vided to conf irm that wd t w as the source of the nmi. the wdtst set to 1 is cleared to 0 by reset- ting wdt . operations in hal t and sleep modes 14.3.4 hal t mode t h e wdt m o d u l e o p e r a t e s i n h a l t m o d e , a s t h e c l o c k i s s u p p l i e d . h a l t m o d e i s t h e r e f o r e c l e a r e d b y a n n m i o r r e s e t i f i t c o n t i n u e s f o r m o r e t h a n t h e n m i / r e s e t g e n e r a t i o n c y c l e . t o d i s a b l e wdt w h i l e i n h a l t m o d e , s t o p wdt b y w r i t i n g 0 b 1 0 1 0 t o w d t r u n [ 3 : 0 ] / w d t _ c t l r e g i s t e r b e f o r e e x e c u t i n g t h e halt i n s t r u c t i o n . r e s e t wdt b e f o r e r e s u m i n g o p e r a t i o n s a f t e r h a l t m o d e i s c l e a r e d . sleep mode t h e c l o c k s u p p l i e d f r o m t h e c l g m o d u l e i s s t o p p e d i n s l e e p m o d e , w h i c h a l s o s t o p s wdt . t o p r e v e n t g e n e r a t i o n o f a n u n n e c e s s a r y n m i o r r e s e t a f t e r c l e a r i n g s l e e p m o d e , r e s e t wdt b e f o r e e x e c u t i n g t h e slp i n s t r u c t i o n . wdt s h o u l d a l s o b e s t o p p e d a s r e q u i r e d u s i n g w d t r u n [ 3 : 0 ] . contr ol registe r details 14.4 t ab le 14.4.1 list of wdt registers ad dress register name function 0x5040 wdt_ctl w atchdog timer control register resets and star ts/stops the timer . 0x5041 wdt_st w atchdog timer status register sets the timer mode and indicates nmi status . the wdt re gisters are described in detail belo w . these are 8-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. watchdog timer control register (wdt_ctl) register name ad dress bit name function setting init. r/w remarks watchdog timer control register (wdt_ctl) 0x5040 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 wdtrst w atchdog timer reset 1 reset 0 ignored 0 w d3C0 wdtrun[3:0] w atchdog timer r un/stop control o t h e r t h a n 1 0 1 0 run 1010 stop 1010 r/w d[7:5] reserved d4 wdtrst: watchdog timer reset bit resets wdt . 1 (w): reset 0 (w): ignored 0 (r): al w ays 0 when read (def ault) note: to use wdt, it must be reset by writing 1 to this bit within the nmi/reset generation cycle (4 seconds when f osc1 = 32.768 khz). this resets the up-counter to 0 and starts counting with a new nmi/reset generation cycle. 14 w a tchdog timer (wdt) s1c17554/564 t echnical m anual seiko epson corporation 14-3 d[3:0] wdtrun[3:0]: watchdog timer run/stop control bits controls wdt run/stop. v alues other than 0b1010 (r/w): run 0b1010 (r/w): stop (def ault) note: wdt must also be reset to prevent generation of an unnecessary nmi or reset before start - ing wdt. watchdog timer status register (wdt_st) register name ad dress bit name function setting init. r/w remarks watchdog timer status register (wdt_st) 0x5041 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 wdtmd nmi/reset mode select 1 reset 0 nmi 0 r/w d0 wdtst nmi status 1 n m i o c c u r r e d 0 n o t o c c u r r e d 0 r d[7:2] reserved d1 wdtmd: nmi/reset mode select bit selects nmi or reset generation on counter o v erflo w . 1 (r/w): reset 0 (r/w): nmi (def ault) setting this bit to 1 outputs a reset signal when the counter o v erflo ws. setting to 0 outputs an nmi sig- nal. d0 wdtst: nmi status bit indicates a counter o v erflo w and nmi occurrence. 1 (r): nmi occurred (counter o v erflo w) 0 (r): nmi not occurred (def ault) this bit conf irms that wdt w as the source of the nmi. the wdtst set to 1 is cleared to 0 by resetting wdt . this is also set by a counter o v erflo w if reset output is selected, b ut is cleared by initial reset and cannot be conf irmed. 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-1 u ar t 15 u ar t module over vie w 15.1 the s1c17554/564 includes a u ar t module with tw o asynchronous communication channels. it includes a 2-byte recei v e data b uf fer and 1-byte transmit data b uf fer allo wing successi v e data transfer . the u ar t module also in- cludes an rzi modulator/demodulator circuit that enables ird a 1.0-compatible infrared communications simply by adding basic e xternal circuits. the fo llo wing sho ws the main features of the u ar t : ? t ransfer rate: 150 to 960 kbps (150 to 115,200 bps in ird a mode) ? t ransfer clock: internal clock (baud rate generator output) or an e xternal clock (sclk input) can be selected. ? character length: 7 or 8 bits (lsb f irst) ? p arity mode: ev en, odd, or no parity ? stop bit: 1 or 2 bits ? start bit: 1 bit f ix ed ? supports full-duple x communications. ? includes a 2-byte recei v e data b uf fer and a 1-byte transmit data b uf fer . ? includes a baud rate generator with f ine adjustment function. ? includes an rzi modulator/demodulator circuit to support ird a 1.0-compatible infrared communications. ? can detect parity error , framing error , and o v errun error during recei ving. ? can generate recei v e b uf fer full, transmit b uf fer empty , end of transmission and recei v e er ror interrupts. figure 15.1.1 sho ws the u ar t conf iguration. shift register receive data buffer (2 bytes) ch.0: sin0 ch.1: sin1 internal bus itc uart ch.x bus i/f and control registers ch.0: sclk0 ch.1: sclk1 shift register transmit data buffer (1 byte) clock/transfer control ch.0: sout0 ch.1: sout1 rzi demodulator rzi modulator interrupt control sclk baud rate generator figure 15.1.1 u ar t configur ation note: t w o channels in the u ar t module ha v e the same functions e xcept f or control register addresses . f or this reason, the descr iption in this chapter applies to both u ar t channels . the x in the regis- ter name indicates the channel n umber (0 or 1). example: u ar t_ctlx register ch.0: u ar t_ctl0 register ch.1: u ar t_ctl1 register 15 u ar t 15-2 seiko epson corporation s1c17554/564 t echnical m anual u ar t input/output pins 15.2 t able 15.2.1 lists the u ar t input/output pins. 2.1 list of u ar t pins t ab le 15. pin name i/o qty function sin0 (ch.0) sin1 (ch.1) i 2 u ar t ch.x data input pin inputs ser ial data sent from an e xter nal ser ial de vice . sout0 (ch.0) sout1 (ch.1) o 2 u ar t ch.x data output pin outputs ser ial data sent to an e xter nal ser ial de vice . sclk0 (ch.0) sclk1 (ch.1) i 2 u ar t ch.x cloc k input pin inputs the tr ansf er cloc k when an e xter nal cloc k is used. the u ar t input/output pins (sinx, soutx, sclkx) are shared wit h i/o ports and are initially set as general pur - pose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as u ar t input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . baud rate generator 15.3 the u ar t module includes a baud rate generator to generate the transfer (sampling) c lock. it consists of an 8-bit programmable timer with f ine mode. the timer counts do wn from the initial v alue set via softw are and outputs an underflo w signal when the counter underflo ws. the underflo w signal is used to generate the transfer clock. the un- derflo w c ycle can be programmed by selecting the clock source and initial data, enabling the application program to obtain serial transfer rates as required. fine mode pro vides a function that minimizes transfer rate errors. s1c17564 baud rate register uart_brx underflow fine mode setting clock enable ct_clk division ratio selection clock source selection down counter control circuit fmd[3:0] clken clkdiv[1:0] clksrc[1:0] baud rate generator for uart ch. x osc1 clock external clock (sclkx) osc3 clock divider (1/1C1/8) iosc clock divider (1/1C1/8) serial transfer clock sclk sclk16 1/16 3.1 baud rate gener ator figure 15. cloc k sour ce settings t h e c l o c k s o u r c e c a n b e s e l e c t e d f r o m i o s c ( s 1 c 1 7 5 6 4 ) , o s c 3 , o s c 1 , o r e x t e r n a l c l o c k u s i n g c l k s r c [ 1 : 0 ] / u ar t_clkx re gister . 3.1 cloc k source selection t ab le 15. clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (sclkx) 0x2 osc3 0x1 osc1 0x0 iosc (s1c17564) (def ault: 0x0) note: when inputting the e xter nal cloc k via the sclkx pin, the cloc k duty r atio m ust be 50%. when iosc or osc3 is selected as the clock source, use clkdiv[1:0]/u ar t_clkx re gister to select the di- vision ratio. 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-3 3.2 iosc/osc3 division ratio selection t ab le 15. clkdiv[1:0] division ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) c l o c k s u p p l y t o t h e c o u n t e r i s c o n t r o l l e d u s i n g c l k en / u a r t _ c l k x r e g i s t e r . t h e c l k en d e f a u l t s e t t i n g i s 0 , which disables the clock supply . setting clken to 1 sends the clock selected to the counter . initial counter v alue setting br[7:0]/u ar t_brx re gister is used to set the initial v alue for the do wn counter . the initial counter v alue i s preset to the do wn counter if the counter underflo ws. this means that the initial counter v alue and the count clock frequenc y determine the time elapsed between underflo ws. underflow signal/ baud rate generator output (sclk16) baud rate generator output (sclk) 123 81 6 3.2 counter underflo w and cloc k gener ated figure 15. use the follo wing equations to calculate the initial counter v alue for obtaining the desired transfer rate. ct_clk bps = {(br + 1) 16 + fmd} ct_clk br = ( - fmd - 16 ) 16 bps ct_clk: count clock frequenc y (hz) br: br[7:0] setting (0 to 255) bps: t ransfer rate (bit/s) fmd: fmd[3:0] (f ine mode) setting (0 to 15) note: t h e u a r t t r a n s f e r r a t e i s c a p p e d a t 960 k b p s (115,200 b p s i n i r d a m o d e ) . d o n o t s e t f a s t e r tr ansf er r ates . fine mode fine mode pro vides a function that minimizes transfer rate errors. the baud rate generator output clock can be set to the required frequenc y by selecting the appropriate clock source and initial counter data. note that errors may occur , depending on the transfer rate. fine mode e xtends the output clock c ycle by del aying the underflo w pulse from the counter . this delay can be specif ied with the fmd[3:0]/u ar t_fmdx re gister . fmd[3:0] speci- f ies the delay pattern to be inserted into a 16 underflo w period. inserting one delay e xtends the output clock c ycle by one count clock c ycle. 3.3 dela y p atter ns specified b y fmd[3:0] t ab le 15. fmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle . 15 u ar t 15-4 seiko epson corporation s1c17554/564 t echnical m anual count clock underflow signal (not corrected) underflow signal (corrected) sclk (not corrected) sclk (corrected) delayed 15 16 15 16 1 1 3.3 dela y cycle inser tion in fine mode figure 15. at initial reset, fmd[3:0] is set to 0x0, pre v enting insertion of delay c ycles. note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore setting the baud r ate gen- er ator . t ransf er data settings 15.4 set the follo wing conditions to conf igure the transfer data format. ? data length: 7 or 8 bits ? start bit: fix ed at 1 bit ? stop bit: 1 or 2 bi ts ? p arity bit: ev en, odd, or no parity note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore changing tr ansf er data f or mat settings . data length the data length is selected by chln/u ar t_modx re gister . setting chln to 0 (def ault) conf igures the data length to 7 bits. setting chln to 1 conf igures it to 8 bits. stop bit the stop bit length is selected by stpb/u ar t_modx re gister . setting stpb to 0 (def ault) conf igures the stop bit length to 1 bit. setting stpb to 1 conf igures it to 2 bits. p arity bit whether the parity function is enabled or disabled is selected by pren/u ar t_modx re gister . setting pren to 0 (def ault) disables the parity function. in this case, no parity bit is added to the transfer data and the data is not check ed for parity when recei v ed. setting pren to 1 enables the parity function. in this case, a parity bit is added to the transfer data and the data is check ed for parity when recei v ed. when the parity function is enabled, the parity mode is selected by pmd/u ar t_modx re gister . setting pmd to 0 (def ault) adds a parity bit and checks for e v en parity . setting pmd to 1 adds a parity bit and checks for odd parity . sampling clock (sclk) chln = 0, pren = 0, stpb = 0 chln = 0, pren = 1, stpb = 0 chln = 0, pren = 0, stpb = 1 chln = 0, pren = 1, stpb = 1 chln = 1, pren = 0, stpb = 0 chln = 1, pren = 1, stpb = 0 chln = 1, pren = 0, stpb = 1 chln = 1, pren = 1, stpb = 1 s1 d0 d1 d2 d3 d4 d5 d6 s2 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s1 d0 d1 d2 d3 d4 d5 d6 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s3 s1: start bit, s2 & s3: stop bit, p: parity bit figure 15.4.1 t r ansf er data f or mat 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-5 data t ransf er contr ol 15.5 mak e the follo wing settings before starting data transfers. (1) select the input clock. (see section 15.3.) (2) program the baud rate generator to output the transfer clock. (see section 15.3.) (3) set the transfer data format. (see section 15.4.) (4) t o use the ird a interf ace, set ird a mode. (see section 15.8.) (5) set interrupt conditions to use u ar t interrupts. (see sectio n 15.7.) note: mak e sure the u ar t is halted (rxen/u ar t_ctlx register = 0) bef ore changing the abo v e set- tings . enab ling data transf er s s e t r x e n / u a r t _ c t l x r e g i s t e r t o 1 t o e n a b l e d a t a t r a n s f e r s . t h i s p u t s t h e t r a n s m i t t e r / r e c e i v e r c i r c u i t i n r e a d y - to-transmit/recei v e status. note: do not set rxen to 0 while the u ar t is sending or receiving data. data transmission contr ol t o start data transmission, write the transmit data to txd[7:0]/u ar t_txdx re gister . the data is written to the transmit data b uf fer , and the transmitter circuit starts sending data. the b uf fer data is sent to the transmit shift re gister , and the start bit is output from the soutx pin. the data in the shift re gister is then output from the lsb. the transfer data bit is shifted in sync with the sampling clock rising edge and output in s equence via the soutx pin. f ollo wing output of msb, the parity bit (if parity is en- abled) and the stop bit are output. the transmitter circuit includes three status flags: tdbe/u ar t_stx re gister , trbs/u ar t_stx re gister , and tred/u ar t_stx re gister . the tdbe flag indicates the transmit data b uf fer status. this flag switches to 0 when the application program writes data to the transmit data b uf fer a nd re v erts to 1 when the b uf fer data is sent to the transmit shift re gister . an interrupt can be generated when this flag is set to 1 (see section 15.7). subsequent data is sent after con- f irming that the transmit data b uf fer is empty either by using this interrupt or by reading the tdbe flag. the transmit data b uf fer size is 1 byte, b ut a shift re gister is pro vided separately to allo w data to be written while the pre vious data is being sent. al w ays conf irm that the transmit data b uf fer is empty before writing transmit data. writing data while the tdbe flag is 0 will o v erwrite earlier transmit data inside the transmit data b uf fer . the trbs flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and r e v erts to 0 once the data is sent. read this flag to check whether the transmitter circuit is operating or at standby . the tred switches to 1 when the trbs flag re v erts to 0 from 1, indicating that transmit operation has com- pleted. an interrupt can be generated when this flag is set to 1 (see section 15.7). use this interrupt for trans- mission end processing. the tred flag is reset to 0 by writin g 1. s1: start bit, s2: stop bit, p: parity bit, wr: data write to transmit data buffer sampling clock (sclk) soutx tdbe trbs tred interrupt s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d7 p s2 s1 d0 d1 d7 p wr wr wr s2 transmit buffer empty interrupt request end of transmission interrupt request 5.1 data t r ansmission timing char t figure 15. 15 u ar t 15-6 seiko epson corporation s1c17554/564 t echnical m anual data reception contr ol the recei v er circuit is acti v ated by setting rxen to 1, enabling data to be recei v ed from an e xternal serial de- vice. when the e xternal serial de vice sends a start bit, the recei v er circuit detects its lo w le v el and starts sampling the follo wing data bits. the data bits are sampled at the sampling clock rising edge, and the lead bit is loaded into the recei v e shift re gister as lsb. once the msb has been recei v ed into the shift re gister , the recei v ed data is loaded into the recei v e data b uf fer . if parity checking is enabled, the recei v er circuit checks the recei v ed data at the same time by checking the parity bit recei v ed immediately after the msb. the recei v e data b uf fer , a 2-byte fifo, recei v es data until full. recei v ed data in the b uf fer can be read from rxd[7:0]/ u ar t_rxdx re gister . the oldest data is read out f irst and data is cleared by reading. the recei v er circuit includes tw o b uf fer status flags: rdr y/u ar t_stx re gister and rd2b/u ar t_stx re gis- ter . the rdr y flag indicates that the recei v e data b uf fer still contains data. the rd2b flag indicates that the re- cei v e data b uf fer is full. (1) rdr y = 0, rd2b = 0 the recei v e data b uf fer contents need not be rea d, since no data has been recei v ed. (2) rdr y = 1, rd2b = 0 one 8-bit data has been recei v ed. read the recei v e data b uf fer contents once. this clears the data inside the b uf fer and resets the rdr y flag. the b uf fer re v erts to state (1) abo v e. if the recei v e data b uf fer contents are read twice, the second data read will be in v alid. (3) rdr y = 1, rd2b = 1 t w o 8- b i t d a t a h a v e b e e n r e c e i v e d . r e a d t h e r e c e i v e d a t a b u f f e r c o n t e n t s t w i c e . t h e r e c e i v e d a t a b u f f e r outputs the oldest data f irst, clearing the b uf fer data read out and resetting the rd2b flag. the b uf fer then re v erts to the state in (2) abo v e. the second read outputs the most recent recei v ed data, after which the b uf- fer re v erts to the state in (1) abo v e. ev en when the recei v e data b uf fer is full, the shift re gister can recei v e one more 8 -bit data. an o v errun error will occur if additional data is sent from the e xternal serial de vice in this status, and the ne w data will o v er - write the shift re gister data. the contents of the recei v e data b uf fer must be read out before an o v errun error occurs. f or detailed information on o v errun errors, refer to section 15.6. the v olume of data recei v ed can be check ed by reading these flags. the u ar t allo ws recei v e b uf fer full interrupts to be generated once data has been recei v ed in the recei v e data b uf fer . these interrupts can be used to read the recei v e data b uf fer . by def ault, a recei v e b uf fer full interrupt occurs when the recei v e data b uf fer recei v es one 8-bit data (status (2) abo v e). this can be changed by setting rbfi/u ar t_ctlx re gister to 1 so that an interrupt occurs when the rec ei v e data b uf fer recei v es tw o 8-bit data. three error flags are also pro vided in addition to the flags pre viously mentioned. see section 15.6 for detailed information on flags and recei v e errors. 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-7 receive buffer full interrupt request (rbfi = 0) overrun error interrupt request sampling clock (sclk) sinx receive data buffer rdry rd2b rxd[7:0] interrupt data 1 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 s1 d0 p s2 data 2 data 3 data 4 data 5 data 6 rd rd data 3, 4 data 2 data 1 C data 2, 3 data 3 data 3 data 2 data 1 s1: start bit, s2: stop bit, p: parity bit, rd: data read from rxd[7:0] 5.2 data receiving timing char t figure 15. disab ling data transf er s after a data transfer is completed (both transmission and reception), write 0 to rxen to disable data transfers. note: setting rxen to 0 empties the tr ansmit data b uff er , clear ing an y remaining data. the data being tr ansf erred cannot be guar anteed if rxen is set to 0 while data is being sent or receiv ed. mak e sure that the tdbe flag i s 1 and the trbs and rdr y flags are both 0 bef ore disab ling data tr ansf er . receive err or s 15.6 three dif ferent recei v e errors may be detected while recei ving data. since recei v e errors are interrupt causes, the y can be processed by generating interrupts. f or more information on u ar t interrupt control, see section 15.7. p arity err or if pren/u ar t_modx re gister has been set to 1 (parity enabled), data r ecei v ed is check ed for parity . data recei v ed in the shift re gister is check ed for parity when sent to the recei v e data b uf fer . the matching is check ed ag ainst the pmd/u ar t_modx re gister setting (odd or e v en parity). if the result is a non-match, a parity error is issued, and the parity error flag per/u ar t_stx re gister is set to 1. ev en if this error occurs, the data recei v ed is sent to the recei v e data b uf fer , and the recei ving operation continues. ho we v er , the recei v ed data cannot be guaranteed if a parity error occurs. the per flag is reset to 0 by writing 1. framing err or a framing error occurs if the stop bit is recei v ed as 0 and the u ar t determines loss of sync. if the stop bit is set to tw o bits, only the f irst bit is check ed. the framing error flag fer/u ar t_stx re gister is set to 1 i f this error occurs. the recei v ed data is still trans- ferred to the recei v e data b uf fer if this error occurs and the recei ving operation continues, b ut the data cannot be g u a r a n t e e d , e v e n i f n o f r a m i n g e r r o r o c c u r s f o r s u b s e q u e n t d a t a r e c e i v i n g . t h e f e r f l a g i s r e s e t t o 0 b y w r i t i n g 1 . overrun err or ev en if the recei v e data b uf fer is full (tw o 8-bit data already recei v ed), the third data can be rec ei v ed in the shift re gister . ho we v er , if the recei v e data b uf fer is not emptied (by reading out data recei v ed) by the time this data has been recei v ed, the third data recei v ed in the shift re gister will not be sent to the b uf fer . the fourth data sent in this status will o v erwrite the third data in the shift re gister and generate an o v errun error . if an o v errun error occurs, the o v errun error flag oer/u ar t_stx re gister is set to 1. the recei ving operation continues e v en if this error occurs. the oer flag is reset to 0 by writing 1. 15 u ar t 15-8 seiko epson corporation s1c17554/564 t echnical m anual u ar t interrupts 15.7 the u ar t includes a function for generating the follo wing four dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? end of transmission interrupt ? recei v e b uf fer full interrupt ? recei v e error interrupt each u ar t channel outputs one interrupt signal shared by the four abo v e interrupt causes to the interrupt control- ler (itc). inspect the status flag and error flag to determine the interrupt cause occurred. t ransmit b uff er empty interrupt t o use this interrupt, set tien/u ar t_ctlx re gister to 1. if tien is set to 1 while tdbe/u ar t_stx re gister is 1 (transmit data b uf fer empty) or if tdbe is set to 1 (when the transmit data b uf fer becomes empty by load- ing the transmit data written to it to the shift re gister) while tien is 1, an interrupt request is sent to the itc. an interrupt occurs if other interrupt conditions are met. if tien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. y ou can inspect the tdbe flag in the u ar t interrupt handler routine to determine whether the u ar t interrupt is attrib utable to a transmit b uf fer empty . if tdbe is 1, the ne xt transmit data can be written to the transmit data b uf fer by the int errupt handler routine. end of transmission interrupt t o use this interrupt, set teien/u ar t_ctlx re gister to 1. if teien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when the trbs flag is reset to 0, the u ar t sets tred/u ar t_stx re gister to 1, indicating that the transmit operation has completed. if end of transmission interrupts are enabled (teien = 1), an i nterrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the tred flag in the u ar t interrupt h a n d l e r r o u t i n e t o d e t e r m i n e w h e t h e r t h e u a r t i n t e r r u p t i s a t t r i b u t a b l e t o a n e n d o f t r a n s m i s s i o n . i f t r e d i s 1 , the transmission processing can be terminated. receive b uff er full interrupt t o use this interrupt, set rien/u ar t_ctlx re gist er to 1. if rien is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if the specif ied v olume of recei v ed data is loaded into the recei v e data b uf fer when a recei v e b uf fer full interrupt is enabled (rien = 1), the u ar t outputs an interrupt request to the itc. if rbfi/u ar t_ctlx re gister is 0, an interrupt request is output as soon as one recei v ed data is loaded into the recei v e data b uf fer (when rdr y/ u ar t_stx re gister is set to 1). if rbfi is 1, an interrupt request is output as soon as tw o recei v ed data are loaded into the recei v e data b uf fer (when rd2b/u ar t_stx re gister is set to 1). an interrupt occurs if other interrupt conditions are met. y ou can inspect the rdr y and rd2b flags in the u ar t interrupt handler routine to determine whether the u ar t interrup t is attrib utable to a recei v e b uf fer full. if rdr y or rd2b is 1, the recei v ed data can be read from the recei v e data b uf fer by the interrupt handler rou- tine. receive err or interrupt t o u s e t h i s i n t e r r u p t , s e t r e i e n / u a r t _ c t l x r e g i s t e r t o 1 . i f r e i e n i s s e t t o 0 ( d e f a u l t ) , i n t e r r u p t r e q u e s t s f o r this cause will not be sent to the itc. the u ar t sets an error flag, per, fer, or oer/u ar t_stx re gister to 1 if a parity error , framing error , or o v errun error is detected when recei ving data. if recei v e error interrupts are enabled (reien = 1), an interrupt request is sent simultaneously to the itc. if other interrupt conditions are satisf ied, an interrupt occurs. y ou can inspect the per, fer, and oer flags in the u ar t interrupt handler routine to determine whether the u ar t interrupt w as caused by a recei v e error . if an y of the error flags has the v alue 1, the interrupt handler routine will proceed with error reco v ery . f or more information on interrupt processing, see the interrupt controller (itc) chapter . 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-9 ird a interface 15.8 t h i s u a r t m o d u l e i n c l u d e s a n r z i m o d u l a t o r / d e m o d u l a t o r c i r c u i t e n a b l i n g i m p l e m e n t a t i o n o f i r d a 1 . 0 - c o m p a t i b l e infrared communication function simply by adding basic e xternal circuits. the transmit data output from the u ar t transmit shift re gister is input to the modulator circuit and output from the soutx pin after the lo w pulse has been modulated to a 3 sclk16 c ycle. sclk16 modulator input (shift register output) modulator output (soutx) 12 38 91 01 11 6 3 sclk16 modulator input (shift register output) modulator output (soutx) s1 d0 d1 d2 d3 d4 d5 d6 d7 ps 2s 3 (s1: start bit, s2 & s3: stop bits, p: parity bit) 8.1 t r ansmission signal w a v ef or m figure 15. the recei v ed ird a signal is input to the demodulator circuit and the lo w pulse width is con v erted to 16 sclk16 c y c l e s b e f o r e e n t r y t o t h e r e c e i v e s h i f t r e g i s t e r . t h e d e m o d u l a t o r c i r c u i t u s e s t h e p u l s e d e t e c t i o n c l o c k s e l e c t e d separately from the transfer clock to detect lo w pulses input (when minimum pulse width = 1.41 s/115,200 bps). (s1: start bit, s2 & s3: stop bits, p: parity bit) sclk16 demodulator input (sinx) demodulator output (shift register input) 1 234 16 16 sclk16 2 sclk16 or more demodulator input (sinx) demodulator output (shift register input) s1 d0 d1 d2 d3 d4 d5 d6 d7 ps 2s 3 8.2 receiv e signal w a v ef or m figure 15. ird a enab le t o use the ird a interf ace function, set irmd/u ar t_expx re gister to 1. this enables the rzi modulator/de- modulator circuit. note: this setting m ust be perf or med bef ore setting other u ar t conditions . serial data transf er contr ol data transfer control in ird a mode is identical to that for normal interf aces. f or detailed information on data format settings and data transfer and interrupt control methods, refer to the preceding sections. contr ol register details 15.9 9.1 list of u ar t registers t ab le 15. ad dress register name function 0x4100 u ar t_st0 u ar t ch.0 status register indicates tr ansf er , b uff er and error statuses . 0x4101 u ar t_txd0 u ar t ch.0 t r ansmit data register t r ansmit data 0x4102 u ar t_rxd0 u ar t ch.0 receiv e data register receiv e data 0x4103 u ar t_mod0 u ar t ch.0 mode register sets tr ansf er data f or mat. 15 u ar t 15-10 seiko epson corporation s1c17554/564 t echnical m anual ad dress register name function 0x4104 u ar t_ctl0 u ar t ch.0 control register controls data tr ansf er . 0x4105 u ar t_exp0 u ar t ch.0 expansion register sets ird a mode . 0x4106 u ar t_br0 u ar t ch.0 baud rate register sets baud r ate . 0x4107 u ar t_fmd0 u ar t ch.0 fine mode register sets fine mode . 0x4120 u ar t_st1 u ar t ch.1 status register indicates tr ansf er , b uff er and error statuses . 0x4121 u ar t_txd1 u ar t ch.1 t r ansmit data register t r a nsmit data 0x4122 u ar t_rxd1 u ar t ch.1 receiv e data register receiv e data 0x4123 u ar t_mod1 u ar t ch.1 mode register sets tr ansf er data f or mat. 0x4124 u ar t_ctl1 u ar t ch.1 control register controls data tr ansf er . 0x4125 u ar t_exp1 u ar t ch.1 expansion register sets ird a mode . 0x4126 u ar t_br1 u ar t ch.1 baud rate register sets baud r ate . 0x4127 u ar t_fmd1 u ar t ch.1 fine mode register sets fine mode . 0x506c u ar t_clk0 u ar t ch.0 cloc k control register selects the baud r ate gener ator cloc k. 0x506d u ar t_clk1 u ar t ch.1 cloc k control register selects the baud r ate gener ator cloc k. the u ar t re gisters are described in detail belo w . these are 8-bit re gisters. notes: ? w h e n d a t a i s w r i t t e n t o t h e r e g i s t e r s , t h e r e s e r v e d b i t s m u s t a l w a y s b e w r i t t e n a s 0 a n d n o t 1 . ? the f ollo wing u ar t bits should be set with tr ansf ers disab led (rxen = 0). - all u ar t_modx register bits (stpb , pmd , pren, chln) - rbfi bit in the u ar t_ctlx register - all u ar t_expx register bits (irmd) - all u ar t_brx register bits (br[7:0]) - all u ar t_fmdx register bits (fmd[3:0]) - all u ar t_clkx register bits (clkdiv[1:0], clksrc[1:0], clken) uart ch. x status registers (uart_stx) register name ad dress bit name function setting init. r/w remarks uart ch. x status register (uart_st x) 0x4100 0x4120 (8 bits) d7 tred end of tr ansmission flag 1 completed 0 n o t c o m p l e t e d 0 r/w reset b y wr iting 1. d6 fer f r aming error flag 1 error 0 nor mal 0 r/w d5 per p ar ity error flag 1 error 0 nor mal 0 r/w d4 oer ov err un error flag 1 error 0 nor mal 0 r/w d3 rd2b second b yte receiv e flag 1 ready 0 empty 0 r d2 trbs t r ansmit b usy flag 1 busy 0 idle 0 r shift register status d1 rdry receiv e data ready flag 1 ready 0 empty 0 r d0 tdbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r d7 tred: end of transmission flag bit indicat es whether the transmit operation has completed or not. 1 (r): completed 0 (r): not completed (def ault) 1 (w): reset to 0 0 (w): ignored tred is set to 1 when the trbs flag is reset to 0 (when transmission has completed). tred is reset by writing 1. d6 fer: framing error flag bit indicates whether a framing error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored fer is set t o 1 when a framing error occurs. framing errors occur when data is recei v ed with the stop bit set to 0. fer is reset by writing 1. 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-11 d5 per: parity error flag bit indicates whether a parity error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored per is set to 1 when a parity error occurs. p arity checking is enabled only when pren/ u ar t_modx re gister is set to 1 and is performed when recei v ed data is transferred from the shift re gister to the re- cei v e data b uf fer . per is reset by writing 1. d4 oer: overrun error flag bit indicates whe ther an o v errun error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored oer is set to 1 when an o v errun error occurs. ov errun errors occur when data is recei v ed in the shift re gister when the recei v e data b uf fer is already full and additional data is sent. the recei v e data b uf fer is not o v erwritten e v en if this error occurs. the shift re gister is o v erwritten as soon as the error occurs. oer is reset by writing 1. d3 rd2b: second byte receive flag bit indicates that the recei v e data b uf fer contains tw o recei v ed data. 1 (r): second byte can be read 0 (r): second byte not recei v ed (def ault) rd2b is set to 1 when the second byte of data is loaded into the recei v e data b uf fer and is reset to 0 when the f irst data is read from the recei v e data b uf fer . d2 trbs: transmit busy flag bit indicates the transmit shift re gister status. 1 (r): operating 0 (r): standby (def ault) trbs is set to 1 when transmit data is loaded from the transmit data b uf fer into the shift re gister and is reset to 0 when the data transfer is completed. inspect trbs to determine whether the transmit circuit is operating or at standby . d1 rdry: receive data ready flag bit indicates that the recei v e data b uf fer contains v alid recei v ed data. 1 (r): data can be read 0 (r): b uf fer empty (def ault) rdr y is set to 1 when recei v ed data is loaded into the recei v e data b uf fer and is reset to 0 when all data has been read from the recei v e data b uf fer . d0 tdbe: transmit data buffer empty flag bit indicates the transmit data b uf fer status. 1 (r): buf fer empty (def ault) 0 (r): data e xists tdbe is reset to 0 when transmit data is written to the transmit data b uf fer and is set to 1 when the data is transferred to the shift re gister . 15 u ar t 15-12 seiko epson corporation s1c17554/564 t echnical m anual uart ch. x transmit data registers (uart_txdx) register name ad dress bit name function setting init. r/w remarks uart ch. x transmit data register (uart_txd x) 0x4101 0x4121 (8 bits) d7C0 txd[7:0] t r ansmit data txd7(6) = msb txd0 = lsb 0x0 to 0xff (0x7f) 0x0 r/w d[7:0] txd[7:0]: transmit data write transmit data to be set in the transmit data b uf fer . (def ault: 0x0) the u ar t starts transmitting when data is written to this re gister . data written to txd[7:0] is retained until sent to the transmit data b uf fer . t ransmitting data from within the transmit data b uf fer generates a cause of transmit b uf fer empt y interrupt. txd7 (msb) is in v alid in 7-bit mode. serial con v erted data is output from the soutx pin be ginning with the lsb, in which the bits set to 1 are output as high le v el and bits set to 0 as lo w le v el signals. this re gister can also be read. uart ch. x receive data registers (uart_rxdx) register name ad dress bit name function setting init. r/w remarks uart ch. x receive data register (uart_rxd x) 0x4102 0x4122 (8 bits) d7C0 rxd[7:0] receiv e data in the receiv e data b uff er rxd7(6) = msb rxd0 = lsb 0x0 to 0xff (0x7f) 0x0 r o l d e r d a t a i n t h e b u f - f er is read out first. d[7:0] rxd[7:0]: receive data data in the recei v e data b uf fer is read out in sequence, starting with the oldest. recei v ed data is placed in the recei v e data b uf fer . the recei v e data b uf fer is a 2-byte fifo that allo ws proper data reception until it f ills, e v en if data is not r ead out. if the b uf fer is full and the shift re gister also contains recei v ed data, an o v errun error will occur , unless the data is read out before reception of the subsequent data starts. t h e r e c e i v e c i r c u i t i n c l u d e s t w o r e c e i v e b u f f e r s t a t u s f l a g s : r d r y / u a r t _ s t x r e g i s t e r a n d r d2b / u ar t_stx re gister . the rdr y flag indicates the presence of v alid recei v ed data in the recei v e data b uf fer , while the r d2b flag indicates the presence of tw o recei v ed data in the recei v e data b uf fer . a recei v e b uf fer full interrupt occurs when the recei v ed data in the recei v e data b uf fer reaches the num- ber specif ied by rbfi/u ar t_ctlx re gister . 0 is loaded into rxd7 in 7-bit mode. serial data input via the sinx pin is con v erted to parallel, with the initial bit as lsb, the high le v el bit as 1, and the lo w le v el bi t as 0. this data is then loaded into the recei v e data b uf fer . this re gister is read-only . (def ault: 0x0) uart ch. x mode registers (uart_modx) register name ad dress bit name function setting init. r/w remarks uart ch. x mode register (uart_mod x) 0x4103 0x4123 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 chln char acter length select 1 8 bits 0 7 bits 0 r/w d3 pren p ar ity enab le 1 with par ity 0 no par ity 0 r/w d2 pmd p ar ity mode select 1 odd 0 ev en 0 r/w d1 stpb stop bit select 1 2 bits 0 1 bit 0 r/w d0 C reser v ed C C C 0 when being read. d[7:5] reserved d4 chln: character length select bit selects the serial transfer data length. 1 (r/w): 8 bits 0 (r/w): 7 bits (def ault) d3 pren: parity enable bit enables the parity function. 1 (r/w): w ith parity 0 (r/w): no parity (def au lt) 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-13 pren is used to select whether recei v ed data parity checking is performed and whether a parity bit is added to transmit data. setting pren to 1 parity-checks the recei v ed data. a parity bit is automatically added to the transmit data. if pren is set to 0, no parity bit is check ed or added. d2 pmd: parity mode select bit selects the parity mode. 1 (r/w): odd parity 0 (r/w): ev en parity (def ault) writing 1 to pmd selects odd pa rity; writing 0 to it selects e v en parity . p arity checking and parity bit addition are enabled only when pren is set to 1. the pmd setting is disabled if pren is 0. d1 stpb: stop bit select bit selects the stop bit length. 1 (r/w): 2 bits 0 (r/w): 1 bit (def ault) writing 1 to stpb selects 2 stop bits; writing 0 to it selects 1 bit. the start bit is f ix ed at 1 bit. d0 reserved uart ch. x control registers (uart_ctlx) register name ad dress bit name function setting init. r/w remarks uart ch. x control register (uart_ctl x) 0x4104 0x4124 (8 bits) d7 teien end of tr ansmission int. enab le 1 enab le 0 disab le 0 r/w d6 reien receiv e error int. enab le 1 enab le 0 disab le 0 r/w d5 rien receiv e b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 tien t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 rbfi r e c e i v e b u f f e r f u l l i n t . c o n d i t i o n s e t u p 1 2 b ytes 0 1 b yte 0 r/w d0 rxen u ar t enab le 1 enab le 0 disab le 0 r/w d7 teien: end of transmission interrupt enable bit enables interrupt requests to the itc when t ransmit operation has completed. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to terminate transmit processing using interrupts. d6 reien: receive error interrupt enable bit enables interrupt requests to the itc when a recei v e error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process recei v e errors using interrupts. d5 rien: receive buffer full interrupt enable bit enables interrupt requests to the itc caused when the recei v ed data quantity in the recei v e data b uf fer reaches the quantity specif ied in rbfi. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to read recei v ed data using interrupts. d4 tien: transmit buffer empty interrupt enable bit enables interrupt requests to the itc caused when transmission data in the transmit data b uf fer is sent to the shift re gister (i.e. when data transmission be gins). 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to write data to the transmit data b uf fer using interrupts. d[3:2] reserved 15 u ar t 15-14 seiko epson corporation s1c17554/564 t echnical m anual d1 rbfi: receive buffer full interrupt condition setup bit sets the quantity of data in the recei v e data b uf fer to generate a recei v e b uf fer full interrupt. 1 (r/w): 2 bytes 0 (r/w): 1 byte (def ault) if recei v e b uf fer full interrupts are enabled (rien = 1), the u ar t outputs an interrupt request to the itc when the quantity of recei v ed data specif ied by rbfi is loaded into the recei v e data b uf fer . if rbfi is 0, an interrupt request is output as soon as o ne recei v ed data is loaded into the recei v e data b uf fer (when rdr y/u ar t_stx re gister is set to 1). if rbfi is 1, an interrupt request is output as soon a s t w o r e c e i v e d d a t a a r e l o a d e d i n t o t h e r e c e i v e d a t a b u f f e r ( w h e n r d 2 b / u a r t _ s t x r e g i s t e r i s s e t t o 1 ) . d0 rxen: uart enable bit enables data transfer by the u ar t . 1 (r/w): enabled 0 (r/w): disabled (def ault) set rxen to 1 before starting u ar t transfers. setting rxen to 0 disables data transfers. the data being transferred cannot be guaranteed if rxen is set to 0 while data is being sent or recei v ed. before setting rxen to 0, check the data transfer sta- t u s w i t h s o f t w a r e i n c o n s i d e r a t i o n o f t h e c o m m u n i c a t i o n p r o c e d u r e . t h e d a t a t r a n s m i t s t a t u s c a n b e check ed using the trbs flag. the transfer conditions must be set while rxen is 0. disabling transfers by writing 0 to rxen also clears transmit data b uf fers. uart ch. x expansion registers (uart_expx) register name ad dress bit name function setting init. r/w remarks uart ch. x expansion register (uart_exp x) 0x4105 0x4125 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 irmd ird a mode select 1 on 0 off 0 r/w d[7:1] reserved d0 irmd: irda mode select bit switches the ird a interf ace function on and of f. 1 (r/w): on 0 (r/w): of f (def ault) set irmd to 1 to use the ird a interf ace. when irmd is set to 0, this module functions as a normal u ar t , with no ird a functions. uart ch. x baud rate registers (uart_brx) register name ad dress bit name function setting init. r/w remarks uart ch. x baud rate register (uart_br x) 0x4106 0x4126 (8 bits) d7C0 br[7:0] baud r ate setting 0x0 to 0xff 0x0 r/w d[7:0] br[7:0]: baud rate setting bits sets the initial counter v alue of the baud rate generator . (def ault: 0x0) the counter in the baud rate generator repeats counting from the v alue set in this re gister to occurrence of counter underflo w to generate the transfer (sampling) clock. use the follo wing equations to calculate the initial counter v alue for obtaining the desired tran sfer rate. ct_clk bps = {(br + 1) 16 + fmd} ct_clk br = ( - fmd - 16 ) 16 bps 15 u ar t s1c17554/564 t echnical m anual seiko epson corporation 15-15 ct_clk: count clock frequenc y (hz) br: br[7:0] setting (0 to 255) bps: t ransfer rate (bit/s) fmd: fmd[3:0] (f ine mode) setting (0 to 15) uart ch. x fine mode registers (uart_fmdx) register name ad dress bit name function setting init. r/w remarks uart ch. x fine mode register (uart_fmd x) 0x4107 0x4127 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 fmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. d[7:4] reserved d[3:0] fmd[3:0]: fine mode setup bits corrects the transfer rate error . (def ault: 0x0) fmd[3:0] specif ies the delay pattern to be inserted into a 16 underflo w period of the baud rate genera- tor output clock. inserting one delay e xtends the output clock c ycle by one count clock c ycl e. 9.2 dela y p atter ns specified b y fmd[3:0] t ab le 15. fmd[3:0] underflo w n umber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0x0 C C C C C C C C C C C C C C C C 0x1 C C C C C C C C C C C C C C C d 0x2 C C C C C C C d C C C C C C C d 0x3 C C C C C C C d C C C d C C C d 0x4 C C C d C C C d C C C d C C C d 0x5 C C C d C C C d C C C d C d C d 0x6 C C C d C d C d C C C d C d C d 0x7 C C C d C d C d C d C d C d C d 0x8 C d C d C d C d C d C d C d C d 0x9 C d C d C d C d C d C d C d d d 0xa C d C d C d d d C d C d C d d d 0xb C d C d C d d d C d d d C d d d 0xc C d d d C d d d C d d d C d d d 0xd C d d d C d d d C d d d d d d d 0x e C d d d d d d d C d d d d d d d 0xf C d d d d d d d d d d d d d d d d: indicates the inser tion of a dela y cycle . count clock underflow signal (not corrected) underflow signal (corrected) sclk (not corrected) sclk (corrected) delayed 15 16 15 16 1 1 9.1 dela y cycle inser tion in fine mode figure 15. 15 u ar t 15-16 seiko epson corporation s1c17554/564 t echnical m anual uart ch. x clock control registers (uart_clkx) register name ad dress bit name function setting init. r/w remarks uart ch. x clock control register (uart_clk x) 0x506c 0x506d (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 clkdiv [1:0] cloc k division r atio select clkdiv[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C 0 when being read. d0 clken count cloc k enab le 1 enab le 0 disab le 0 r/w d[7:6] reserved d[5:4] clkdiv[1:0]: clock division ratio select bits s e l e c t s t h e d i v i s i o n r a t i o f o r g e n e r a t i n g t h e c o u n t c l o c k o f t h e b a u d r a t e g e n e r a t o r w h e n i o s c (s1c17564) or osc3 is used as the clock source. 9.3 iosc/osc3 division ratio selection t ab le 15. clkdiv[1:0] division ratio 0x3 1/8 0x2 1/4 0x1 1/2 0x0 1/1 (def ault: 0x0) d[3:2] clksrc[1:0]: clock source select bits selects the count clock source for the baud rate generator . 9.4 cloc k source selection t ab le 15. clksrc[1:0] cloc k sour ce 0x3 exter nal cloc k (exclx) 0x2 osc3 0x1 osc1 0x0 iosc (s1c17564) (def ault: 0x0) d1 reserved d0 clken: count clock enable bit enables or disables the count clock supply to the counter of the baud rate generator . 1 (r/w): enabled (on) 0 (r/w): disabled (of f) (def ault) the clken def ault setting is 0, which disables the clock supply . setting clken to 1 sends the clock selected to the counter . 16 spi s1c17554/564 t echnical m anual seiko epson corporation 16-1 spi 16 spi module over vie w 16.1 the s1c17554/564 includes a synchronized serial interf ace module (spi) with three communication channels. the follo wing sho ws the main features of the spi: ? supports both master and sla v e modes. ? data length: 8 bits f ix ed ? supports both msb f irst and lsb f irst modes. ? contains one-byte recei v e data b uf fer and one-byte transmit data b uf fer . ? supports full-duple x comm unications. ? data transfer timing (clock phase and polarity v ariations) is selectable from among 4 types. ? can generate recei v e b uf fer full and transmit b uf fer empty interrupts. figure 16.1.1 sho ws the spi module conf iguration. shift register receive data buffer (1 byte) sdix pclk internal bus itc spi ch.x bus i/f and control registers spiclkx #spissx shift register transmit data buffer (1 byte) clock/transfer control sdox t16 ch.1 output clock interrupt control 1/4 1.1 spi module configur ation (1 channel) figure 16. note: three channels in the spi module ha v e the same functions e xcept f or control register addresses . f or this reason, the descr iption in this chapter applies to all spi channels . the x in the register name indicates the channel n umber (0 to 2). example: spi_ctlx register ch.0: spi_ctl0 register ch.1: spi_ctl1 register ch.2: spi_ctl2 register spi input/output pins 16.2 t able 16.2.1 lists the spi pins. 2.1 list of spi pins t ab le 16. pin name i/o qty function sdi0 (ch.0) sdi1 (ch.1) sdi2 (ch.2) i 3 spi ch.x data input pin inputs ser ial data from spi b us . sdo0 (ch.0) sdo1 (ch.1) sdo2 (ch.2) o 3 spi ch.x data output pin outputs ser ial data to spi b us . 16 spi 16-2 seiko epson corporation s1c17554/564 t echnical m anual pin name i/o qty function spiclk0 (ch.0) spiclk1 (ch.1) spiclk2 (ch.2) i/o 3 spi ch.x e xter nal cloc k input/output pin outputs spi cloc k when spi is in master mode . inputs e xter nal cloc k when spi is used in sla v e mode . #spiss0 (ch.0) #spiss1 (ch.1) #spiss2 (ch.2) i 3 spi ch.x sla v e select signal (activ e lo w) input pin spi (sla v e mode) is selected as a sla v e de vice b y lo w input to this pin. note: use an i/o (p) por t to o utput the sla v e select signal when the spi module is configured to master mode . the spi input/output pins (sdix, sdox, spiclkx, #spissx) are shared with i/o ports and are initially set as gen- eral purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as spi input/output pins. f or detailed information on pin function swi tching, see the i/o ports (p) chapter . spi cloc k 16.3 the master mode spi uses the 16-bit timer (t16) ch.1 output clock or a pclk/4 clock to generate the spi clock. this clock is output from the spiclkx pin to the sla v e de vice while also dri ving the shift re gister . use mclk/spi_ctlx re gister to select whether the t16 ch.1 output clock or pclk/4 clock is used. setting mclk to 1 selects the t16 ch.1 output clock; setting to 0 selects the pclk/4 clock. using the t16 ch.1 output clock enables programmable transfer rates. f or more information on t16 control, see the 16-bit t imers (t16) chapter . pclk 16-bit timer ch.1 output clock or pclk/4 spi clock (spiclkx output) 3.1 master mode spi cloc k figure 16. i n s l a v e m o d e , t h e s p i c l o c k i s i n p u t v i a t h e s p i c l k x p i n . s i n c e t h e i n t e r n a l c i r c u i t o p e r a t e s i n s y n c w i t h t h e pclk clock, the input clock is dif ferentiated and used to sync with the pclk clock. data t ransf er condition settings 16.4 t h e s p i m o d u l e c a n b e s e t t o m a s t e r o r s l a v e m o d e s . t h e s p i c l o c k p o l a r i t y / p h a s e a n d b i t d i r e c t i o n ( m s b f i r s t / l s b f irst) can also b e set via the spi_ctlx re gister . the data length is f ix ed at 8 bits. note: mak e sure the spi module is halted (spen/spi_ctlx register = 0) bef ore master/sla v e mode se- lection and cloc k condition settings . master/sla ve mode selection mssl/spi_ctlx re gister is used to set the spi module to master mode or sla v e mode. setting mssl to 1 sets master mode; setting it to 0 (def ault) sets sla v e mode. in master mode, data is transferred using the internal clock. in sla v e mode, data is transferred by inputting the master de vice clock. spi c loc k polarity and phase settings the spi clock polarity is selected by cpol/spi_ctlx re gister . setting cpol to 1 treats the spi clock as ac- ti v e lo w; setting it to 0 (def ault) treats it as acti v e high. the spi clock phase is selected by cpha/spi_ctlx re gister . as sho wn b elo w , these control bits set transfer timing. 16 spi s1c17554/564 t echnical m anual seiko epson corporation 16-3 spiclkx (cpol = 1, cpha = 1) spiclkx (cpol = 1, cpha = 0) spiclkx (cpol = 0, cpha = 1) spiclkx (cpol = 0, cpha = 0) sdix/sdox fetching received data into shift register d7 (msb) d0 (lsb) 4.1 cloc k and data t r ansf er timing figure 16. msb fir st/lsb fir st settings use mlsb/spi_ctlx re gister to select whether the data msb or lsb is input/output f irst. msb f irst is selected when mlsb is 0 (def ault); lsb f irst is selected when mlsb is 1. data t ransf er contr ol 16.5 mak e the follo wing settings before starting data transfers. (1) select the spi clock source. (see section 16.3.) (2) select mast er mode or sla v e mode. (see section 16.4.) (3) set clock conditions. (see section 16.4.) (4) set the interrupt conditions to use spi interrupts. (see section 16.6.) note: mak e sure the spi is halted (spen/spi_ctlx register = 0) bef ore setting the abo v e conditions . enab ling data transf er s set spen/spi_ctlx re gister to 1 to enable spi operations. this enables spi transfers and clock input/output. note: do not set spen to 0 when the spi module is tr ansf err ing data. data transmission contr ol t o start data transmission, write the transmit data to sptdb[7:0]/spi_txdx re gister . the data is written to the transmit data b uf fer , and the spi module starts sending data. the b uf fer data is sent to the transmit shift re gister . in master mode, the module starts clock output from the spiclkx pin. in sla v e mode, the m odule a w aits clock input from the spiclkx pin. the data in the shift re gister is shifted in sequence a t t h e c l o c k r i s i n g o r f a l l i n g e d g e , a s d e t e r m i n e d b y c p h a / s p i _ c t l x r e g i s t e r a n d c p o l / s p i _ c t l x r e g i s t e r ( s e e figure 16.4.1) and sent from the sdox pin. the spi module includes tw o status flags for transfer control: sptbe/spi_stx re gister and spbsy/spi_stx re gister . the sptbe flag indicates the tran smit data b uf fer status. this flag switches to 0 when the application program writes data to the spi_txdx re gister (transmit data b uf fer) and re v erts to 1 when the b uf fer data is sent to the transmit shift re gister . an interrupt can be generated when this flag is set to 1 (see section 16.6). subsequent data is sent after conf irming that the transmit data b uf fer is empty either by using this interr upt or by inspecting the sptbe flag. the transmit data b uf fer size is 1 byte, b ut a shift re gister is pro vided separately to allo w data to be written while the pre vious data is being sent. al w ays conf irm that the transmit data b uf fer is empty before writing transmit data. writing data while the sptbe flag is 0 will o v erwrite earlier transmit data inside the transmit data b uf fer . in master mode, th e spbsy flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and re v erts to 0 once the data is sent. read this flag to check whether the spi module is operating or at standby . in sla v e mode, spbsy flag indicates the spi sla v e selection signal (#spissx pin) status. the flag is set to 1 when the spi module is selected as a sla v e module and is set to 0 when the module is not selected. 16 spi 16-4 seiko epson corporation s1c17554/564 t echnical m anual pclk spen spi cloc k (master mode) spi_txdx register shift register spiclkx pin (cpol = 0, cpha = 1) spiclkx pin (cpol = 0, cpha = 0) sdox pin spbsy sptbe interr upt a d7 b d7 a d6 wr ite wr ite tr ansmit b uff er empty data a data b a d0 5.1 data t r ansmission timing char t (msb first) figure 16. data reception contr ol in master mode, write dummy data to sptdb[7:0]/spi_txdx re gister . writing to the spi_txdx re gister cre- ates the trigger for reception as well as transmission start. writing actual transmit data enables simultaneous transmission and reception. this starts the spi clock output from the spiclkx pin. in sla v e mode, the mod ule w aits until the clock is input from the spiclkx pin. there is no need to write to the spi_txdx re gister if no transmission is required. the recei ving operation is started by the clock input from the master de vice. if data is transmitted simultaneously , write transmit data to the spi_txdx re gister before the clock is input. the data is recei v ed in sequence in the shift re gister at the rising or f alling edge of the clock determined by cpha/spi_ctlx re gister and cpol/spi_ctlx re gister . (see figure 16.4.1.) the recei v ed data is loaded into the recei v e data b uf fer once the 8 bits of data are recei v ed in the shift re gister . t h e r e c e i v e d d a t a i n t h e b u f f e r c a n b e r e a d f r o m s p r d b [ 7 : 0 ] / s p i _ r x d x r e g i s t e r . the spi module includes sprbf/spi_stx re gister for reception control. the sprbf flag indica tes the recei v e data b uf fer status. this flag is set to 1 when the data recei v ed in the shift re gister is loaded into the recei v e data b uf fer , indicating that the recei v ed data can be read out. it re v erts to 0 when the b uf fer data is read out from the spi_rxdx re gister . an interrupt can be generated as soon as the flag is set to 1 (see section 16.6). the recei v ed data should be read out either by using this interrupt or by inspecting the sprbf flag to conf irm that the recei v e data b uf fer contains v alid recei v ed data. the recei v e data b uf fer is 1 byte in size, b ut a shift re gister is also pro vided, enabling recei v ed data to be retained in the b uf fer e v en while the subsequent data is being recei v ed. note that the recei v e data b uf fer should be read out before recei ving the subsequent data is complete. if recei ving the subsequent data is complete before the recei v e data b uf fer contents are read out, the ne wly recei v ed data will o v erwrite the pre vious recei v ed data in the b uf fer . in master mode, the spbsy flag indicating the shift re gister status can be used in the same w ay while transfer - ring data. 16 spi s1c17554/564 t echnical m anual seiko epson corporation 16-5 pclk spen spi cloc k (master mode) spi_txdx register spiclkx pin (cpol = 0, cpha = 1) spiclkx pin (cpol = 0, cpha = 0) sdix pin shift register spi_rxdx register spbsy sprbf interr upt data a data b a d7 b d7 a d6 a d0 b d0 wr ite wr ite read dumm y dumm y b d6 5.2 data receiving timing char t (msb first) figure 16. disab ling data transf er s after a data transfer is completed (both transmission and reception), write 0 to spen to disable data transfers. conf irm that the sptbe flag is 1 and the sprbf flag is 0 before disabling data transfer . setting spen to 0 empties the transmit and recei v e data b uf fers, clearing an y remaining data. the data being transferre d cannot be guaranteed if spen is set to 0 while data is being sent or recei v ed. spi interrupts 16.6 each channel of the spi module includes a function for generating the follo wing tw o dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? recei v e b uf fer full interrupt t h e s p i c h a n n e l o u t p u t s o n e i n t e r r u p t s i g n a l s h a r e d b y t h e t w o a b o v e i n t e r r u p t c a u s e s t o t h e i n t e r r u p t c o n t r o l l e r ( i t c ) . i nspect the status flag to determine the interrupt cause occurred. t ransmit b uff er empty interrupt t o use this interrupt, set sptie/spi_ctlx re gister to 1. if sptie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when transmit data written to the transmit data b uf fer is transferred to the shift re gister , the spi module sets sptbe/spi_stx re gister to 1, indicatin g that the transmit data b uf fer is empty . if transmit b uf fer empty inter - rupts are enabled (sptie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the sptbe flag in the spi interrupt handler routine to determine whether the spi interrupt is attrib utable to a transmit b uf fer empty . if sptbe is 0, the ne xt transm it data can be written to the transmit data b uf fer by the interrupt handler routine. receive b uff er full interrupt t o use this interrupt, set sprie/spi_ctlx re gister to 1. if sprie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when data recei v ed in the shift re gister is loaded into the recei v e data b uf fer , the spi module sets sprbf/spi_ stx re gister to 1, indi cating that the recei v e data b uf fer contains readable recei v ed data. if recei v e b uf fer full interrupts are enabled (sprie = 1), an interrupt request is output to the itc at the same time. an interrupt occurs if other interrupt conditions are met. y ou can inspect the sprbf flag in the spi interrupt handler routine to determine whether the spi interrupt is attrib utable to a recei v e b uf fer full. if s prbf is 1, the recei v ed data can be read from the recei v e data b uf fer by the interrupt handler routine. f or more information on interrupt processing, see the interrupt controller (itc) chapter . 16 spi 16-6 seiko epson corporation s1c17554/564 t echnical m anual contr ol register details 16.7 7.1 list of spi registers t ab le 16. ad dress register name function 0x4320 spi_st0 spi ch.0 status register indicates tr ansf er and b uff er statuses . 0x4322 spi_txd0 spi ch.0 t r ansmit data register t r ansmit data 0x4324 spi_rxd0 spi ch.0 receiv e data register receiv e data 0x4326 spi_ctl0 spi ch.0 control register sets the spi mode and enab les data tr ansf er . 0x4380 spi_st1 spi ch.1 status register indicates tr ansf er and b uff er statuses . 0x4382 spi_txd1 spi ch.1 t r ansmit data register t r ansmit data 0x4384 spi_rxd1 spi ch.1 receiv e data register receiv e data 0x4386 spi_ctl1 spi ch.1 control register sets the spi mode and enab les data tr ansf er . 0x43a0 spi_st2 spi ch.2 status register indicates tr ansf er and b uff er statuses . 0x43a2 spi_txd2 spi ch.2 t r ansmit data register t r ansmit data 0x43a4 spi_rxd2 spi ch.2 receiv e data register receiv e data 0x43a6 spi_ctl2 spi ch.2 control regis ter sets the spi mode and enab les data tr ansf er . the spi re gisters are described in detail belo w . these are 16-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. spi ch.x status registers (spi_stx) register name ad dress bit name function setting init. r/w remarks spi ch.x status register (spi_stx) 0x4320 0x4380 0x43a0 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r d[15:3] reserved d2 spbsy: transfer busy flag bit (master mode)/ss signal low flag bit (slave mode) master mode indicates the spi transfer status. 1 (r): operating 0 (r): standby (def ault) spbsy is set to 1 when the spi starts data transfer in master mode and is maintained at 1 while transfer is underw ay . it is cleared to 0 once the transfer is complete. sla v e mode indicates the sla v e selection (#spissx) signal status. 1 (r): lo w le v el (this spi is selected) 0 (r): high le v el (this spi is not selected) (def ault) spbsy is set to 1 when the master de vice asserts the #spissx signal to select this spi module (sla v e d e v i c e ) . i t i s r e t u r n e d t o 0 w h e n t h e m a s t e r d e v i c e c l e a r s t h e s p i m o d u l e s e l e c t i o n b y n e ga t i n g t h e #spissx signal. d1 sprbf: receive data buffer full flag bit indicates the recei v e data b uf fer status. 1 (r): data full 0 (r): no data (def ault) sprbf is set to 1 when data recei v ed in the shift re gister is sent to the recei v e data b uf fer (when recei v- ing is completed), indicating that the data can be read. it re v erts to 0 once the b uf fer data is read from the spi_rxdx re gister . 16 spi s1c17554/564 t echnical m anual seiko epson corporation 16-7 d0 sptbe: transmit data buffer empty flag bit indicates the transmit data b uf fer status. 1 (r): empty (def ault) 0 (r): data e xists sptbe is set to 0 when transmit data is written to the spi_txdx re gister (transmit data b uf fer), and is set to 1 when the data is transferred to the shift re gister (when transmission starts). t ransmission data must be written to the spi_txdx re gister when this bit is 1. spi ch.x transmit data registers (spi_txdx) register name ad dress bit name function setting init. r/w remarks spi ch.x transmit data register (spi_txdx) 0x4322 0x4382 0x43a2 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w d[15:8] reserved d[7:0] sptdb[7:0]: spi transmit data buffer bits sets transmit data to be written to the transmit data b uf fer . (def ault: 0x0) in master mode, transmission is started by writing data to this re gister . in sla v e mode, the contents of this re gister are sent to the shift re gister and transmission be gins when the clock is inp ut from the mas- ter . sptbe/spi_stx re gister is set to 1 (empty) as soon as data written to this re gister has been transferred to the shift re gister . a transmit b uf fer empty interrupt is generated at the same time. the subsequent transmit data can then be written, e v en while data is being transmitted. serial con v erted data is output from the sdox pin, with the bit set to 1 as high le v el and the bit set to 0 as lo w le v el. spi ch.x receive data registers (spi_rxdx) register name ad dress bit name function setting init. r/w remarks spi ch.x receive data register (spi_rxdx) 0x4324 0x4384 0x43a4 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r d[15:8] reserved d[7:0] sprdb[7:0]: spi receive data buffer bits contains the recei v ed data. (def ault: 0x0) sprbf/spi_stx re gister is set to 1 (data full) as soon as data is recei v ed and the shift re gister data has been transferred to the recei v e data b uf fer . a recei v e b uf fer full interrupt is generated at the same time. data can then be read until subsequent data is recei v ed. if recei ving the subsequent data is completed before the re gister has been read out, the ne w recei v ed data o v erwrites the contents. serial data input from the sdix pin is con v erted to parallel, with the high le v el bit set to 1 and the lo w le v el bit set to 0. the data is the loaded into this re gister . this re gister is read-only . spi ch.x control registers (spi_ctlx) register name ad dress bit name function setting init. r/w remarks spi ch.x con- trol register (spi_ctlx) 0x4326 0x4386 0x43a6 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t16 ch.1 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar it y select 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w 16 spi 16-8 seiko epson corporation s1c17554/564 t echnical m anual note: do not access to the spi_ctlx register while spbsy/spi_stx register is set to 1 or sprbf/ spi_stx register is set to 1 (while data is being tr ansmitted/receiv ed). d[15:10] reserved d9 mclk: spi clock source select bit selects the spi clock source. 1 (r/w): 16-bit timer ch.1 0 (r/w): pclk/4 (def ault) d8 mlsb: lsb/msb first mode select bit selects whether data is transferred with msb f irst or lsb f irst. 1 (r/w): lsb f irst 0 (r/w): msb f irst (def ault) d[7:6] reserved d5 sprie: receive data buffer full interrupt enable bit enables or disables spi recei v e da ta b uf fer full interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting sprie to 1 enables the output of spi interrupt requests to the itc due to a recei v e data b uf fer full. these interrupt requests are generated when the data recei v ed in the shift re gister is transferred to the recei v e data b uf fer (when reception is completed). spi interrupts are not generated by recei v e data b uf fer full if sprie is set to 0. d4 sptie: transmit data buffer empty interrupt enable bit enables or disables spi transmit data b uf fer empty interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting sptie to 1 enables the output of spi interrupt requests to the itc due to a transmit data b uf fer empty . these interrupt requests are generated when the data written to the transmit data b uf fer is trans- ferred to the shift re gister (when transmission starts). sp i interrupts are not generated by transmit data b uf fer empty if sptie is set to 0. d3 cpha: clock phase select bit selects the spi clock phase. (def ault: 0) set the data transfer timing together with cpol. (see figure 16.7.1.) d2 cpol: clock polarity select bit selects the spi clock polarity . 1 (r/w): acti v e lo w 0 (r/w): acti v e high (def ault) set the data transfer timing together with cpha. (see figure 16.7.1.) spiclkx (cpol = 1, cpha = 1) spiclkx (cpol = 1, cpha = 0) spiclkx (cpol = 0, cpha = 1) spiclkx (cpol = 0, cpha = 0) sdix/sdox fetching received data into shift register d7 (msb) d0 (lsb) 7.1 cloc k and data t r ansf er timing figure 16. 16 spi s1c17554/564 t echnical m anual seiko epson corporation 16-9 d1 mssl: master/slave mode select bit sets the spi module to master or sla v e mode. 1 (r/w): master mode 0 (r/w): sla v e mode (def ault) setting mssl to 1 selects master mode; setting it to 0 selects sla v e mode. master mode performs data transfer with the internal clock. in sla v e mode, data is transferred by inputting the clock from the master de vice. d0 spen: spi enable bit enables or disables spi module operation. 1 (r/w): enabled 0 (r/w): disabled (def aul t) setting spen to 1 starts the spi module operation, enabling data transfer . setting spen to 0 stops the spi module operation. note: the spen bit should be set to 0 bef ore setting the cpha, cpol, and mssl bits . 17 i 2 c master (i2cm) s1c17554/564 t echnical m anual seiko epson corporation 17-1 i 17 2 c master (i2cm) i2cm module over vie w 17.1 t h e s1c17554/564 i n c l u d e s a n i 2 c m a s t e r ( i2c m ) m o d u l e t h a t s u p p o r t s t w o - w i r e c o m m u n i c a t i o n s . t h e i2c m module operates as an i 2 c b us master de vice and can communicate with i 2 c-compliant sla v e de vices. the follo wing sho ws the main features of i2cm: ? operates as an i 2 c b us master de vice (as single master only). ? supports standard (100 kbps) and f ast (400 kbps) modes. ? supports 8-bit data length only (msb f irst). ? 7-bit addressing mode (10-bit addressing is possible by softw are control.) ? includes one-byte recei v e data b uf fer and one-byte transmit data b uf fer . ? can generate start, repeated start, and stop conditions. ? supports half-duple x communications. ? supports clock stretch function. ? includes a noise f ilter function to help impro v e the reliab ility of data transfers. ? can generate transmit b uf fer empty and recei v e b uf fer full interrupts. figure 17.1.1 sho ws the i2cm conf iguration. shift register sda0 sda scl scl0 i 2 c master clock (from t16 ch.2) internal bus itc i 2 c master bus i/f and control registers shift register clock/transfer control noise filter interrupt control 1.1 i2cm module configur ation figure 17. i2cm input/output pins 17.2 t able 17.2.1 lists the i2cm pins. 2.1 list of i2cm pins t ab le 17. pin name i/o qty function sd a0 i/o 1 i2cm data input/output pin (see note belo w) inputs ser ial data from the i 2 c b us . also outputs ser ial data to the i 2 c b us . scl0 i/o 1 i2cm cloc k input/output pin (see note belo w) inputs scl line status . also outputs a ser ial cloc k. note: the pins go to high impedance status when the por t function is s witched. the i2cm input/output pins (sd a0, scl0) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as i2cm input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . 17 i 2 c master (i2cm) 17-2 seiko epson corporation s1c17554/564 t echnical m anual sync hr onization cloc k 17.3 the i2cm module uses the internal clock (i2cm clock) output by the 16-bit timer (t16) ch.2 as the synchroniza- tion clock. this clock is output from the scl0 pin to the sla v e de vice while also dri ving the shift re gister . the clock should be programmed to output a signal matching the transfer rate from t16 ch.2. f or more information on t16 control, see the 16-bit t imers ( t16) chapter . the i2cm module does not function as a sla v e de vice. the scl0 input pin is used to check the i 2 c b us scl signal status. it is not used for synchronization clock input. settings bef ore data t ransf er 17.4 the i2cm module includes an optional noise f ilter function that can be selected via the application program. noise filter function t h e i2c m m o d u l e i n c l u d e s a f u n c t i o n f o r f i l t e r i n g n o i s e f r o m t h e s d a0 a n d s c l0 p i n i n p u t s i g n a l s . t h i s function is enabled by setting nserm/i2cm_ctl re gister to 1. note that using this function requires setting the i2cm clock (t16 ch.2 output clock) frequenc y to 1/6 or less of pclk. data t ransf er contr ol 17.5 mak e the follo wing settings before starting data transfers. (1) conf igure t16 ch.2 to output the i2cm clock. (see the t16 module chapter .) ( 2) select the option function. (see section 17.4.) (3) set the interrupt conditions to use i2cm interrupts. (see section 17.6.) note: m a k e s u r e t h e i 2 c m m o d u l e i s h a l t e d ( i 2 c m e n / i 2 c m _ e n r e g i s t e r = 0 ) b e f o r e c h a n g i n g t h e a b o v e settings . enab ling data transf er s set i2cmen/i2cm_en re gister to 1 to enable i2cm operations. this enables i2cm transfers and clock input/ output. note: do not set i2cmen to 0 when the i2cm module is tr ansf err ing data. star ting data transf er t o start data transfers, the i 2 c master (this module) must generate a start condition. the sla v e address is then sent to establish communications. (1) gener ating star t condition the start condition applies when the scl line is maintained at high and the sd a line is pulled do wn to lo w . sda0 (output) scl0 (output) start condition 5.1 star t condition figure 17. the start condition is generated by setting str t/i2cm_ctl re gister to 1. str t is automatically reset to 0 once the start condition is generated. the i 2 c b us is b usy from this point on. (2) sla v e address tr ansmission once the start condition has been generated, the i 2 c master (this module) sends a bit indicating the sla v e address and transfer direction for communicat ions. i 2 c sla v e addresses are either 7-bit or 10-bit. this module uses an 8-bit transfer data re gister to send the sla v e address and transfer direction bit, enabling single transfers in 7-bit address mode. in 10-bit mode, data is sent twice under softw are control. figure 17.5.2 sho ws the conf iguration of the address data. 17 i 2 c master (i2cm) s1c17554/564 t echnical m anual seiko epson corporation 17-3 slave address 7-bit address transfer direction 0: master slave (transmission) 1: slave master (reception) a6 a5 d7 d6 a4 d5 a3 d4 a2 d3 a1 d2 a0 d1 dir d0 8 low order slave address bits a7 a6 d7 d6 a5 d5 a4 d4 a3 d3 a2 d2 a1 d1 a0 d0 2 high order slave address bits 10-bit address transfer direction 0: master slave (transmission) 1: slave master (reception) 1 first transmit data second transmit data 1 d7 d6 1 d5 1 d4 0 d3 a9 d2 a8 d1 dir d0 5.2 t r ansmit data specifying sla v e address and t r ansf er direction figure 17. the transfer direction bit indicates the data transfer direction after the sla v e address has been sent. this is set to 0 when sending data from the master to the sla v e and to 1 when recei ving data from the sla v e. t o send a sla v e address, set the address with the transfer direction bit to r tdt[7:0]/i2cm_d a t re gister . at th e same time, set txe/i2cm_d a t re gister transmitting the address to 1. after the sla v e address has been output, data can be sent and recei v ed as man y times as required. data must be sent or recei v ed according to the transfer direction set together with the sla v e address. data transmission contr ol the procedure for transmitting data is described belo w . data transmission is performed by the same proce dure as for sla v e address transmission. t o send byte data, set the transmit data to r tdt[7:0] and set txe to 1 to transmit 1 byte. when txe is set to 1, the i2cm module be gins data transmission in sync with the clock. if the pre vious data is currently being transmitted, data transmission starts after this has been completed. the i2cm module f irst transfers the data written to the shift re gister , then starts outputting the clock from the scl0 pin. txe is reset to 0 at this point and a cause of interrupt occurs, enabling the subsequent transmission data and txe to be set. the data bits in the shift re gister are shifted in sequence at the clock f alling edge and output via the sd a0 pin with the msb leading. the i2cm module outputs 9 clocks with each data transmission. in the 9th clock c ycle, the i2cm module sets the sd a line into high impedance to recei v e an a ck or n ak sent from the sla v e de vice. the sla v e de vice returns a ck (0) to the master if the data is recei v ed. if the data is not recei v ed, the sd a line is not pulled do wn, which the i2cm module interprets to mean a n ak (1) (transmission f ailed). sda0 (output) sda0 (input) scl0 (output) start condition 12 89 d7 d6 d0 ack nak 5.3 a ck and nak figure 17. the i2cm module includes tw o status bits for transmission control: tb usy/i2cm_ctl re gister and r t a ck/ i2cm_d a t re gister . t h e t b u s y f l a g i n d i c a t e s t h e d a t a t r a n s m i s s i o n s t a t u s . t h i s f l a g b e c o m e s 1 w h e n t r a n s m i s s i o n s t a r t s ( i n c l u d i n g s l a v e a d d r e s s t r a n s m i s s i o n ) a n d r e v e r t s t o 0 o n c e d a t a t r a n s m i s s i o n e n d s . i n s p e c t t h e f l a g t o c h e c k w h e t h e r t h e i 2 c m m o d u l e i s c u r r e n t l y t r a n s m i t t i n g o r a t s t a n d b y . the r t a ck bit indicates whether or not the sla v e de vice returned an a ck for the pre vious transmission. r t - a ck is 0 if an a ck w as returned and 1 if a ck w as not returned. 17 i 2 c master (i2cm) 17-4 seiko epson corporation s1c17554/564 t echnical m anual data reception contr ol the procedure for recei ving data is described belo w . when recei ving data, the sla v e address must be sent with the transfer direction bit set to 1. t o recei v e data, set rxe/i2cm_d a t re gister to 1 for recei ving 1 byte. when txe/i2cm_d a t re gister is set to 1 for sending the sla v e address, rxe can also be set to 1 at the same time. if both txe and rxe are set to 1, txe tak es pr iority . when rxe is set to 1, allo wing recei ving to start, the i2cm module starts outputting the clock from the scl0 pin with the sd a line at high impedance. the data is loaded to the shift re gister in sequence at the clock rising edge, with the msb leading. rxe is reset to 0 when d6 is loaded. the recei v ed data is loaded to r tdt[7:0] once the 8-bit data has been recei v ed in the shift re gister . t h e i2c m m o d u l e i n c l u d e s t w o s t a t u s b i t s f o r r e c e i v e c o n t r o l : r b r d y / i2c m _ d a t r e g i s t e r a n d r b u s y / i2cm_ctl re gister . t h e r b r d y f l a g i n d i c a t e s t h e r e c e i v e d d a t a s t a t u s . t h i s f l a g b e c o m e s 1 w h e n t h e d a t a r e c e i v e d i n t h e s h i f t r e g i s - t e r i s l o a d e d t o r t d t [ 7 : 0 ] a n d r e v e r t s t o 0 w h e n t h e r e c e i v e d d a t a i s r e a d o u t f r o m r t d t [ 7 : 0 ] . i n t e r r u p t s c a n a l s o b e g e n e r a t e d o n c e t h e f l a g v a l u e b e c o m e s 1 . t h e r b u s y f l a g i n d i c a t e s t h e r e c e i v i n g o p e r a t i o n s t a t u s . t h i s f l a g i s 1 w h e n r e c e i v i n g s t a r t s a n d r e v e r t s t o 0 w h e n t h e d a t a i s r e c e i v e d . i n s p e c t t h e f l a g t o d e t e r m i n e w h e t h e r t h e i 2 c m m o d u l e i s c u r r e n t l y r e c e i v i n g o r i n s t a n d b y . the i2cm module outputs 9 clocks with each data reception. in the 9th clock c ycle, an a ck or n ak is sent to the sla v e via the sd a0 pin. the bit state sent can be set in r t a ck/i2 cm_d a t re gister . t o send a ck, set r t - a ck to 0. t o send n ak, set r t a ck to 1. end of data transf er s (generating stop condition) t o end data transfers after all data has been transferred, the i 2 c master (this module) must generate a stop con- dition. the stop condition applies when the scl line is maintained at high and the sd a line is pulled up from lo w to high. sda0 (output) scl0 (output) stop condition 5.4 stop condition figure 17. the stop condition is generated by setting stp/i2cm_ctl re gister to 1. when stp is set to 1, the i2cm module pulls up the i 2 c b us sd a line from lo w to high with the scl line maintained at high to generates a stop condition. the i 2 c b us subsequently switches to free state. s t o p c o n d i t i o n g e n e r a t i o n c a n b e r e s e r v e d . t o r e s e r v e t h e s t o p c o n d i t i o n , c h e c k t h a t i 2 c m i s o p e r a t i n g ( t b u s y = 1 or rb usy = 1), and then set stp to 1. the stop condition is generated as soon as data transfer (including a ck transfer) ends. stp is reset to 0 when the stop condition is generated. contin uing data transf er (generating repeated star t condition) t o mak e it possible to continue with a dif ferent data transfer after data transfer completion, the i 2 c master (this module) can generat e a repeated start condition. sda0 (output) scl0 (output) repeated start condition 5.5 repeated star t condition figure 17. 17 i 2 c master (i2cm) s1c17554/564 t echnical m anual seiko epson corporation 17-5 the repeated start condition is generated by setting str t/i2cm_ctl re gister to 1 when the i 2 c b us is b usy . str t is automatically reset to 0 once the repeated start condition is generated. sla v e address transmission is subsequently possible with the i 2 c b us remaining in the b usy state. disab ling data transf er after data transfer has completed (both transmission and reception), write 0 to i2cmen to disable data trans- fers. conf irm that the rb usy and tb usy flags are 0 before disabling data transfers. data being transferred cannot be guaranteed if i2cmen is set to 0 during the transfer . timing c har t pclk t16 ch.2 output scl0 sd a0 str t str t setting star t condition i 2 c b us b usy 5.6 star t condition gener ation figure 17. pclk t16 ch.2 output scl0 sd a0 txe tbusy rt ac k r tdt[7:0] interr upt d[7:0] d[7:0] a6/d7 a5/d6 dir/d0 ac k txe setting tr ansmit data setting a ck receiving tr ansmission end tr ansmission star t 5.7 sla v e address t r ansmission/data t r ansmission figure 17. 17 i 2 c master (i2cm) 17-6 seiko epson corporation s1c17554/564 t echnical m anual pclk t16 ch.2 output scl0 sd a0 rxe rbusy rt ac k r tdt[7:0] rbrd y/ interr upt d[7:0] d7 d6 d0 ac k rxe setting a ck transmitting receiving end receiving star t 5.8 data receiving figure 17. pclk t16 ch.2 output scl0 sd a0 stp stp setting stop condition i 2 c b us free 5.9 stop condition gener ation figure 17. i2cm interrupts 17.6 the i2cm module includes a function for generating the follo wing tw o dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? recei v e b uf fer full interrupt the i2cm module outputs one interrupt signal shared by the tw o abo v e interrupt causes to the interrupt controller (itc). t ransmit b uff er empty interrupt t o use this interru pt, set tinte/i2cm_ictl re gister to 1. if tinte is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if transmit b uf fer empty interrupts are enabled (tinte = 1), an interrupt request is output to the itc as soon as the transmit data set in r tdt[7:0]/i2cm_d a t re gister is transferred to the shift re gister . an interrupt occurs if other interrupt conditions are satis f ied. chec king whether a transmit b uff er empty interrupt has occurred or not a transmit b uf fer empty interrupt has occurred if tb usy/i2cm_ctl re gister is read as 0 in the procedure sho wn belo w . (1) set tinte/i2cm_ictl re gister to 1. (2) write data to r tdt[7:0]/i2cm_d a t re gister . (3) an i2cm interrupt occurs. (4) read tb usy/i2cm_ctl re gister . 17 i 2 c master (i2cm) s1c17554/564 t echnical m anual seiko epson corporation 17-7 clearing the cause of transmit b uff er empty interrupt write data to r tdt[7:0]/i2cm_d a t re gister . notes: ? data will not be sent if txe/i2cm_d a t register is set to 0. ? if r tdt[7:0] contains data receiv ed from the i 2 c b us , it will be o v erwr itten. receive b uff er full interrupt t o use this interrupt, set rinte/i2cm_ictl re gister to 1. if rinte is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if recei v e b uf fer full interrupts are enabled (rinte = 1), an interrupt request is output to the itc as soon as the data recei v ed in the shift re gister is loaded to r tdt[7:0]. an interrupt occurs if other interrupt conditions are met. chec king whether a receive b uff er full interrupt has occurred or not a recei v e b uf fer full interrupt has occurred if rb usy/i2cm_ctl re gis ter is read as 1 in the procedure sho wn belo w . (1) set rinte/i2cm_ictl re gister to 1. (2) an i2cm interrupt occurs. (3) read rb usy/i2cm_ctl re gister . clearing the cause of receive b uff er full interrupt read data from r tdt[7:0]/i2cm_d a t re gister . f or more information on interrupt processing, see the interrupt controller (itc) chapter . contr ol register details 17.7 7.1 list of i2cm registers t ab le 17. ad dress register name function 0x4340 i2cm_en i 2 c master enab le register enab les the i 2 c master module . 0x4342 i2cm_ctl i 2 c master control register controls the i 2 c master oper ation and indicates tr ansf er status . 0x4344 i2cm_d a t i 2 c master data register t r ansmit/receiv e data 0x4346 i2cm_ictl i 2 c master interr upt control register controls the i 2 c master interr upt. the i2cm module re gisters are described in detail bel o w . these are 16-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. i 2 c master enable register (i2cm_en) register name ad dress bit name function setting init. r/w remarks i 2 c master en- able register (i2cm_en) 0x4340 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 i2cmen i 2 c master enab le 1 enab le 0 disab le 0 r/w d[15:1] reserved d0 i2cmen: i 2 c master enable bit enables or disables i2cm module operation. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting i2cmen to 1 starts the i2cm module operation, enabling data transfer . setting i2cmen to 0 stops the i2cm module operation. 17 i 2 c master (i2cm) 17-8 seiko epson corporation s1c17554/564 t echnical m anual i 2 c master control register (i2cm_ctl) register name ad dress bit name function setting init. r/w remarks i 2 c master con- trol register (i2cm_ctl) 0x4342 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 rbusy receiv e b usy flag 1 busy 0 idle 0 r d8 tbusy t r ansmit b usy flag 1 busy 0 idle 0 r d7C5 C reser v ed C C C 0 when being read. d4 nserm noise remo v e on/off 1 on 0 off 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 stp stop control 1 stop 0 ignored 0 r/w d0 strt star t control 1 star t 0 ignored 0 r/w d[15:10] reserved d9 rbusy: receive busy flag bit indicates the i2cm recei ving status. 1 (r): operating 0 (r): standby (def ault) rb usy is set to 1 when the i2cm starts data recei ving and is maintained at 1 while recei ving is under - w ay . it is cleared to 0 once reception is completed. d8 tbusy: transmit busy flag bit indicates the i2cm transmission status. 1 (r): operating 0 (r): standby (def ault) tb usy is set to 1 when the i2cm starts data transmission and is maintained at 1 while transmission is underw ay . it is cleared to 0 once transmission is completed. d[7:5] reserved d4 nserm: noise remove on/off bit t urns the noise f il ter function on or of f. 1 (r/w): on 0 (r/w): of f (def ault) the i2cm module includes a function for f iltering noise from the sd a0 and scl0 pin input signals. t h i s f u n c t i o n i s e n a b l e d b y s e t t i n g n s e r m t o 1 . n o t e t h a t u s i n g t h i s f u n c t i o n r e q u i r e s s e t t i n g t h e i 2 c m clock (t16 ch.2 output clock) frequenc y to 1/6 or less of pclk. d[3:2] reserved d1 stp: stop control bit generates the stop condition. 1 (r/w): stop condition generated 0 (r /w): inef fecti v e (def ault) by setting stp to 1, the i2cm module generates the stop condition by pulling up the i 2 c b us sd a line from lo w to high with the scl line maintaining at high. the i 2 c b us subsequently becomes free. note that the stop condition will be generated only if stp is 1 and txe/i2cm_d a t re gister , rxe/i2cm_ d a t re gister , and str t are set to 0 when data transfer is completed (includ ing a ck transfer). stp is disabled if an y of txe, rxe, or str t is 1. stp is automatically reset to 0 if the stop condition is gen- erated. d0 strt: start control bit generates the start condition. 1 (r/w): start condition generated 0 (r/w): inef fecti v e (def ault) by setting str t to 1, the i2cm module generates the start condition by pulling do wn the i 2 c b us sd a line to lo w with scl line maintaining at high. the repeated start condition can be generated by setting str t to 1 when the i 2 c b us is b usy . str t is automatically reset to 0 once the start condition or repeated start condition is generated. the i 2 c b us subsequently becomes b usy . 17 i 2 c master (i2cm) s1c17554/564 t echnical m anual seiko epson corporation 17-9 i 2 c master data register (i2cm_dat) register name ad dress bit name function setting init. r/w remarks i 2 c master data register (i2cm_dat) 0x4344 (16 bits) d15C12 C reser v ed C C C 0 when being read. d11 rbrdy receiv e b uff er ready flag 1 ready 0 empty 0 r d10 rxe receiv e e x ecution 1 receiv e 0 ignored 0 r/w d9 txe t r ansmit e x ecution 1 t r ansmit 0 ignored 0 r/w d8 rtack receiv e/tr ansmit a ck 1 error 0 a ck 0 r/w d7C0 rtdt[7:0] receiv e/tr ansmit data r tdt7 = msb r tdt0 = lsb 0x0 to 0xff 0x0 r/w d[15:12] reserved d11 rbrdy: receive buffer ready flag bit indicates the recei v e b uf fer status. 1 (r): recei v e data e xists 0 (r): no recei v e data (def ault) the rbrd y flag beco mes 1 when the data recei v ed in the shift re gister is loaded to r tdt[7:0] and re v erts to 0 when the recei v e data is read out from r tdt[7:0]. interrupts can also be generated once the flag v alue becomes 1. d10 rxe: receive execution bit recei v es 1 byte of data. 1 (r/w): data reception start 0 (r/w): inef fecti v e (def ault) setting rxe to 1 and txe to 0 starts recei ving for 1 byte of data. rxe can be set to 1 for subsequent re- ception, e v en if the sla v e address is being sent or data is being recei v ed. rxe is reset to 0 as soon as d6 is loaded to the shift re gister . d9 txe: transmit execution bit t ransmits 1 byte of data. 1 (r/w): data transmission start 0 (r/w): inef fecti v e (def ault) t ransmission is started by setting the transmit data to r tdt[7:0] and writing 1 to txe. txe can be set to 1 for subsequent transmission, e v en if the sla v e address o r data is being sent. txe is reset to 0 as soon as the data set in r tdt[7:0] is transferred to the shift re gister . d8 rtack: receive/transmit ack bit when tr ansmitting data indicates the response bit status. 1 (r/w): error (n ak) 0 (r/w): a ck (def ault) r t a ck becomes 0 when a ck is returned from the sla v e after 1 byte of data is sent, indicating that the sla v e has recei v ed the data correctly . if r t a ck is 1, the sla v e de vice is not operating or the data w as not recei v ed correctly . when receiving data sets the response bit sent to the sla v e. 1 (r/w): error (n ak) 0 (r/w): a ck (def ault) t o return an a ck after data has been recei v ed, r t a ck should be set to 0 before the i2cm module sends the response bit. t o return a n ak, set r t a ck to 1. 17 i 2 c master (i2cm) 17-10 seiko epson corporation s1c17554/564 t echnical m anual d[7:0] rtdt[7:0]: receive/transmit data bits when tr ansmitting data sets the transmit data. (def ault: 0x0) data transmission is started by setting txe to 1. if a sla v e address or data is currently being transmit- ted, transmission be gins once the pre vious transmission is completed. serial con v erted data is output from the sd a0 pin with msb leading and bits set to 0 as lo w le v el. a cause of transmit b uf fer empty interrupt is generated as soon as the data written to this re gister is transferred to the shift re gister , after which the subsequent transmission data can be written. when receiving data the recei v ed data can be read out. (def ault: 0x0) data reception is started by setting rxe to 1. if a sla v e address is currently being transmitted or data is currently being recei v ed, the ne w reception starts once the pre vious data has been transferred. the rbrd y flag is set and a cause of recei v e b uf fer full interrupt generated as soon as reception is com- pleted and the shift re gister data is transferred to this re gister . data can then be read until the subsequent data has been recei v ed. if the subsequent data is recei v ed before this re gister is read out, the contents are o v erwritten by the most recent recei v ed data. serial dat a input from the sd a0 pin with msb lead- ing is con v erted to parallel, with the high le v el bit set to 1 and the lo w le v el bit set to 0, then loaded to this re gister . i 2 c master interrupt control register (i2cm_ictl) register name ad dress bit name function setting init. r/w remarks i 2 c master interrupt control register (i2cm_ictl) 0x4346 (16 bits) d15C2 C reser v ed C C C 0 when being read. d1 rinte receiv e interr upt enab le 1 enab le 0 disab le 0 r/w d0 tinte t r ansmit interr upt enab le 1 enab le 0 disab le 0 r/w d[15:2] reserved d1 rinte: receive interrupt enable bit enables or disables i2cm recei v e b uf fer full interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting rinte to 1 enables the output of i2cm interrupt requests to the itc due to a recei v e data b uf- fer full. these interrupt requests are generat ed when the data recei v ed in the shift re gister is transferred to r tdt[7:0]/i2cm_d a t re gister (when reception is completed). i2cm interrupts are not generated by recei v e data b uf fer full if rinte is set to 0. d0 tinte: transmit interrupt enable bit enables or disables i2cm transmit b uf fer empty interrupts. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting tinte to 1 enables the output of i2cm interrupt requests to the itc due to a transmit b uf fer empty . these interrupt requests are generated when the data written to r tdt[7:0] is transferred to the shift re gister . i2cm interrupts are not generated by transmit b uf fer empty if tinte is set to 0. 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-1 i 18 2 c sla v e (i2cs) i2cs module over vie w 18.1 the s1c17554/564 includes an i 2 c sla v e (i2cs) module that supports tw o-wire communications. the i2cs mod- ule operates as an i 2 c b us sla v e de vice and can communicate with an i 2 c-compliant master de vice. the follo wing sho ws the main features of i2cs: ? operates as an i 2 c b us sla v e de vice. ? supports standard (100 kbps) and f ast (400 kbps) modes. ? supports 8-bit data length only (msb f irst). ? supports 7-bit addressing mode. ? includes one-byte recei v e data b uf fer and one-byte transmit data b uf fer . ? can detect start and stop conditions. ? supports half-duple x communications. ? supports clock stretch function. ? supports forced b us release function. ? includes a noise f ilter function to help impro v e the reliability of data transfers. ? can generate transmit b uf fer empty , recei v e b uf fer full, and b us status interrupts. figure 18.1.1 sho ws the i2cs conf iguration. #bfr shift register sda1 sda scl scl1 internal bus itc i 2 c slave bus i/f and control registers shift register clock/transfer control noise filter interrupt control 1.1 i2cs module configur ation figure 18. note: the i2cs module does not suppor t gener al call address and 10-bit address mode . i2cs input/output pins 18.2 t able 18.2.1 lists the i2cs pins. 2.1 list of i2cs pins t ab le 18. pin name i/o qty function sd a1 i/o 1 i2cs data input/output pin (see note belo w) inputs ser ial data from the i 2 c b us . also outputs ser ial data to the i 2 c b us . scl1 i/o 1 i2cs cloc k input pin (see note belo w) inputs scl line status from the i 2 c b us . #bfr i 1 i 2 c b us free request input pin a lo w pulse input to this pin requests the i2cs to release the i 2 c b us . when the b us free request input has been enab led with softw are , a lo w pulse initializ es the comm unication process of the i2cs module and sets the sd a1 and scl1 pins into high impedance . 18 i 2 c sla ve (i2cs) 18-2 seiko epson corporation s1c17554/564 t echnical m anual note: the pins go to high impedance status when the por t function is s witched. the i2cs input/output pins (sd a1, scl1, #bfr) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as i2cs input/output pins. f or detailed information on pin function switching, see th e i/o ports (p) chap- ter . operation cloc k 18.3 the i2cs module operates with the clock output from the e xternal i 2 c master de vice by inputting it from the scl1 pin. the i2cs module also uses the peripheral module clock (pclk) for its operations. the pclk frequenc y must be set eight-times or higher than the scl1 input clock frequenc y during data transfer . in standby status, use of the asynchronous address detection function allo ws the application to lo wer the pclk clock frequenc y to reduce cur - rent consumption. f or more information, see asynchronous address detection function in section 18.4.3. initializing i2cs 18.4 reset 18.4.1 the i2cs module must be reset to initialize the communication process and to set the i 2 c b us into free status (high impedance). the follo wing sho ws tw o methods f or resetting the module: (1) software reset the i2cs module can be reset using softreset/i2cs_ctl re gister . t o reset the i2cs module, write 1 to softreset to place the i2cs module into reset status, then write 0 to softreset to release it from reset status. it is not necessary to insert a w aiting time between writing 1 and 0. the i2cs module initializes the i 2 c communication process and put the sd a 1 and scl1 pins into high-im- pedance to be ready to detect a start condition. furthermore, the i2cs control bits e xcept for softreset are initialized. perform the softw are reset in the initial setting process before staring communication. (2) bus free request with an input fr om the #bfr pin the i2cs module can accept b us free requests via the #bfr pin. the b us free request support is disabled by d ef ault. t o enable this function, set bfreq_en/i2cs_ctl re gister to 1. when this function is enabled, a lo w pulse (f i v e peripheral module clock (pclk) c ycles or more pulse width is required) input to the #bfr pin sets bfreq/i2cs_st a t re gister to 1. this initializes the i 2 c communication process and puts the sd a1 and scl1 pins into high-impedance. the control re gisters will not be initialized as dis tinct from the softw are reset described abo v e. note: when bfreq is set to 1 (an interr upt can be used f or chec king this status), perf or m a softw are reset and set the registers again. setting sla ve ad dress 18.4.2 i 2 c de vices ha v e a unique sla v e address to identify each de vice. the i2cs module supports 7-bit address (does not support 10-bit address), and the address of this module must be set to sadrs[6:0 ]/i2cs_sadrs re gister . optional functions 18.4.3 the i2cs module has a clock stretch, asynchronous address detection, and noise f ilter optional functions selectable in the application program. cloc k stretc h function after data and a ck are transmitted or recei v ed, the sla v e de vice may issue a w ait request to the master de vice until it is ready to transmit/recei v e by pulling the i 2 c b us scl line do wn to lo w . the i2cs module supports this clock stretch function. 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-3 the master de vice enters a standby state until the w ait request is canceled (the scl line goes high). the clock stretch function in this module is disabled by def ault. when using the clock stretch function, set clkstr_en/ i2cs_ctl re gister to 1 before starting data communication. async hr onous ad dress detection function the i2cs module operation clock (pclk) frequenc y must be set eight-times or high er than the transfer rate during data transfer . ho we v er , the pclk frequenc y can be lo wered to reduce current consumption if no other p r o c e s s i n g i s r e q u i r e d d u r i n g s t a n d b y f o r d a t a t r a n s f e r . t h e a s y n c h r o n o u s a d d r e s s d e t e c t i o n f u n c t i o n i s p r o v i d e d to detect the i 2 c sla v e address sent from the master in this status. the asynchronous address detection function in this module is disabled by def ault. wh en using the asynchro- nous address detection function, set asdet_en/i2cs_ctl re gister to 1. if the sla v e address sent from the master has matched with one that has been set in this i2cs module when the asynchronous address detection function has been enabled, the i2cs module generates a b us status interrupt and returns n ak to the i 2 c master to request for resending the sla v e address. set the pclk frequenc y to eight-times or higher than the transfer rate and reset asdet_en to 0 in the inter - rupt handler routine. data transfer will be able to resume normally after the master retries transmission. after the master generates a stop condition to put the i 2 c b us into free status, the asynchronous address detection function can be enabled ag ain to lo wer the operating speed. notes: ? when the asynchro nous address detection function is enab led, the i 2 c b us signals are input without passing through the noise filter . theref ore , the sla v e address ma y not be detected in a high-noise en vironment. ? when the asynchronous address detection function is enab led, data tr ansf er cannot be per- f or med e v en if the pclk frequency is eight-times or higher than the tr ansf er r ate . be sure to disab le the asynchron ous address detection function dur ing nor mal oper ation. noise filter the i2cs module includes a function to remo v e noise from the sd a1 and scl1 input signals. this function is enabled by setting nf_en/i2cs_ctl re gister to 1. data t ransf er contr ol 18.5 mak e the follo wing settings before starting data transfers. (1) initialize the i2cs module. see section 18.4. (2) set the interrupt conditions to use i 2cs interrupt. see section 18.6. note: mak e sure that the i2cs module is disab led (i2csen/i2cs_ctl register = 0) bef ore setting the conditions abo v e . enab ling data transf er s first, set i2csen/i2cs_ctl re gister to 1 to enable i2cs operation. this mak es the i2cs in ready-to-transmit/ recei v e status in which a start condition can be detected. note: do not set the i2csen bit to 0 while the i2cs module is tr ansm itting/receiving data. star ting data transf er t o start data transmission/reception, set com_mode/i2cs_ctl re gister to 1 to enable data communications. when the sla v e address for this module that has been sent from the master is recei v ed after a start condition is detected, the i2cs module returns an a ck (sd a1 = lo w) and starts operating for data reception or data trans- mission according to the tran sfer direction bit that has been recei v ed with the sla v e address. when com_mode is 0 (def ault), the i2cs module does not send back a response if the master has sent the sla v e address of this module (it is re g arded as that the i2cs module has returned a n ak to the master). 18 i 2 c sla ve (i2cs) 18-4 seiko epson corporation s1c17554/564 t echnical m anual sda1 (input) sda1 (output) scl1 (input) start condition 12 3 4 5 6 7 89 ack nak 7-bit slave address transfer direction 0: master slave (data reception) 1: slave master (data transmission) a6 a5 d7 d6 a4 d5 a3 d4 a2 d3 a1 d2 a0 d1 r/w d0 5.1 receiving sla v e address and data direction bit figure 18. when a start condition is detected, b usy/i2cs_ast a t re gister is set to 1 to indicate that the i 2 c b us is put into b usy status. when the sla v e address of this module is recei v ed, selected/i2cs_ast a t re gister is set to 1 to indicate that this module has been selected as the i 2 c sla v e de vice. both b usy and selected are main- tained at 1 unt il a stop condition is detected. the v alue of the transfer direction bit is set to r/w/i2cs_ast a t re gister , so use r/w to select the transmit- or recei v e-handling. if the sla v e address of this module is detected when the asynchronous address detection function has been en- abled, asdet/i2cs_st a t re gister is set to 1. the i2cs module generates a b us status interrupt and returns n ak to the i 2 c mast er to request for resending the sla v e address. set the pclk frequenc y to eight-times or higher than the transfer rate and disable the asynchronous address detection function in the interrupt handler r o u t i n e . d a t a t r a n s f e r w i l l b e a b l e t o r e s u m e n o r m a l l y a f t e r t h e m a s t e r r e t r i e s t r a n s m i s s i o n . a s d e t c a n b e cleared by writing 1. data transmission the follo wing describes a data transmission procedure. t h e i 2 c s m o d u l e s t a r t s d a t a t r a n s m i s s i o n p r o c e s s w h e n b o t h s e l e c t e d a n d r / w a r e s e t t o 1 . i t s e t s t x e m p / i2cs_ast a t re gister to 1 to issue a request to the application program to write transmit data. write transmit data to sd a t a[7:0]/i2cs_trns re gister . when setting the f irst transmit data after this module has been selected as the sla v e de vice, follo w the precau- tions described belo w . when the clo ck stretch function is disabled (def ault) t ransmit data must be written to sd a t a[7:0] within 1 c ycle of the i 2 c clock (scl1 input clock) after tx- emp has been set to 1. this time is not enough for data preparation, so write transmit data before txemp has been set to 1. if the pre vious transmit data is still stored in sd a t a[7:0], it is o v erwritten with the ne w data to be transferred. therefore, the clear operation (see belo w) using tb uf_clr is unnecessary . when the clock stretch function is enabled the master de vice is placed into w ait status by the clock stretch function, so transmit data can be written after txemp is set. ho we v er , if the pre vious transmit data is still stored in sd a t a[7:0], it will be sent im- mediately after txemp has been set. in order to a v oid this problem, clear the i2 cs_trns re gister using tb uf_clr/i2cs_ctl re gister before this module is selected as the sla v e de vice. the i2cs_trns re gis- ter is cleared by writing 1 to tb uf_clr then writing 0 to it. it is not necessary to clear the i2cs_trns re gister if the f irst transmit data is written before txemp has been set. f or writing transmit data other than the f irst time, use an interrupt that can be generated when tx emp is set to 1. txemp is also set to 1 when the transmit data written to sd a t a[7:0] is loaded to the sift re gister during transmission. txemp is cleared by writing transmit data to sd a t a[7:0]. when the clock stretch function is disabled (def ault) when the clock stretch function has been disabled, data must be written to the i2cs_trns re gister within 7 c ycles of the i 2 c clock (scl1 input clock) fr om txemp being set to 1. 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-5 if data has not been written in this period, the current re gister v alue (pre vious transmit data) will be sent. in this case, txudf/i2cs_st a t re gister is set to 1 to indicate that in v alid data has been sent. an interrupt can be generated when txudf is set to 1, so an error handling should be performed in the interrupt han- dler routine. txudf is cleared by writing 1. when the clock stretch function is enabled when the clock stretch function has been enabled, the i2cs module pulls do wn the scl1 pin to lo w to gen- erate a clock stretch (w ait) status until transmit data is written to the i2cs_trns re gister . t ransmit data bits are output from the sd a1 pin in sync with the scl1 input clock sent from the master . the msb is output f irst. after the eight bits has been output, the master sends back a n a ck or n ak in the ninth clock c ycle. sda1 (output) sda1 (input) scl1 (input) 12 89 d7 d6 d0 ack nak 5.2 a ck and nak figure 18. the a ck bit indicates that the master could recei v e data. it is also a transmit request bit, therefore, the ne xt transmit data must be written in adv ance. recei ving an a ck generates a clock stretch status when the clock stretch function has been enabled, so data can be written after an a ck is recei v ed. a n ak will be returned from the master if the master could not recei v e data or when the master terminates data reception. in this case a clock stretch status is not generated e v en if the clock stretch function has been enabled. read d a_n ak/i2cs_st a t re gister to check if an a ck is returned or if a n ak is returned. d a_n ak is set to 0 when an a ck is returned or set to 1 when a n ak is returned. an interrupt can be generated when d a_n ak is set to 1, so an error or termi nation handling can be performed in the interrupt handler routine. d a_n ak is cleared by writing 1. the sd a line status during data transmission is input in the module and is compare with the output data. the comparison results are set to dms/i2cs_st a t re gister . dms is set to 0 when data is output correctly . if the sd a line status is dif ferent from the output data, dms is set to 1. this may be caus ed by a lo w pull-up resistor v alue or another de vice that is controlling the sd a line. an interrupt can be generated when dms is set to 1, so an error handling can be performed in the interrupt handler routine. dms is cleared by writing 1. note: if the i2cs module has sent bac k a nak as the response to the address sent b y the master when the conditions sho wn belo w are all met, the master m ust w ait f or 33 s or more bef ore it can send another sla v e address (e xcept when the master sends the i2cs sla v e address again). 1. more than one sla v e de vice is connected to the i 2 c b us . 2. the tr ansf er r ate is set to 320 kbps or higher . 3. the asynchronous address detection function is enab led. 4. t h e i2c s m o d u l e i s p l a c e d i n t o t r a n s f e r s t a n d b y s t a t e a n d o s c1 i s u s e d a s t h e o p e r a t i n g cloc k (pclk). data reception the follo wing describes a data recei v e procedure. the i2cs module starts data recei ving process when selected is set to 1 and r/w is set to 0. the recei v ed data bits are input from the sd a1 pin in sync with the scl1 input clock sent from the master . when the eight- bit data (msb f irst) is recei v ed in the shift re gister , the recei v ed data is loaded to rd a t a[7:0]/i2cs_recv re gister . when the recei v ed data is loaded to rd a t a[7:0], rxrd y/i2cs_ast a t re gister is set to 1 to issue a request to the application program to read rd a t a[7:0]. an interrupt can be generated when rxrd y is set to 1, so the recei v ed data should be read in the interrupt handler routine. rxrd y is cleared by reading the recei v ed data. 18 i 2 c sla ve (i2cs) 18-6 seiko epson corporation s1c17554/564 t echnical m anual when the clock stretch function is disabled (def ault) when the clock stretch function has been disabled, data must be read from the i2cs_recv re gister within 7 c ycles of the i 2 c clock (scl1 input clock) from rxrd y being set to 1. when the clock stretch function is enabled when the clock stretch function has been enabled, the i2cs module pulls do wn the scl1 pin to lo w to gen- erate a clock stretch (w ait) status until the recei v ed data is read from the i2cs_recv re gister . if the ne xt data has been recei v ed without reading the recei v ed data, rd a t a[7:0] will be o v erwritten. in this case, rxo vf/i2cs_st a t re gister is set to 1 to indicate that the recei v ed data has been o v erwritten. an inter - rupt can be generated when rxo vf is set to 1, so an error handling should be performed in the interrupt han- dler routine. rxo vf is cleared by writing 1. t o return nak during data reception during data reception (master transmission), the i2cs module sends back an a ck (sd a1 = lo w) e v ery time an 8-bit data has been recei v ed (by def ault setting). the response code can be changed to n ak (sd a1 = hi-z) by setting n ak_ans/i2cs_ctl re gister . an a ck will be sent when n ak_ans is 0 or a n ak will be sent when n a k_ans is set to 1. n ak_ans should be set within 7 c ycles of the i 2 c clock (scl1 input clock) after rxrd y has been set to 1 by recei ving data just prior to one required for returning n ak. scl1 (input) sda1 (input) sda1 (output) rxrdy nak_ans nak_ans setting period receiv e interr upt 67891 d0 d2 d1 d7 d6 d5 d4 d3 d2 d0 d1 ack nak 2 3 4 5 6789 5.3 nak_ans setting and nak response timing figure 18. end of data transf er (detecting stop condition) data transfers will be terminated when the master generates a stop condition. the stop condition is a state in which the sd a line is pulled up from lo w to high with the scl line maintained at high. sda1 (input) scl1 (input) stop condition 5.4 stop condition figure 18. if a stop condition is detected while the i2cs module is selected as the sla v e de vice (selected = 1), the i2cs module sets d a_st op/i2cs_st a t re gister to 1. at the same time, it sets the sd a1 and scl1 pins into high-impedance and initializes the i 2 c communication process to enter standby state that is ready to detect the ne xt start condition. also selected and b usy are reset to 0. an interrupt can be generated when d a_st op is set to 1, so a communication terminating process should be performed in the interrupt handler routine. d a_st op is cleared by writing 1. disab ling data transf er after data transfer has f inished, write 0 to the com_mode/i2cs_ctl re gister to disable data transfer . al w ays mak e sure that b usy and selected are 0 before disabling data transfer . t o deacti v ate the i2cs module, set i2csen/i2cs_ctl re gister to 0. 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-7 timing c har ts pclk scl1 (input) scl1 (output) sd a1 (input) sd a1 (output) r/w busy selected txemp txudf d a_nak d a_st op tr ansmit data shift register sd at a[7:0] interr upt a6 v alid d[7:0] a5 a4 a3 a2 a1 a0 d7 d6 r/w = 1 ac k star t condition sla ve address reception data transmission cloc k stretch tr ansmit interr upt shift 5.5 i2cs timing char t 1 (star t condition data tr ansmission) figure 18. d5 d4 d3 d2 d1 d0 d7 d6 d0 v alid shift shift shift shift shift shift shift shift ac k pclk scl1 (input) scl1 (output) sd a1 (input) sd a1 (output) r/w busy selected txemp txudf d a_nak d a_st op t ransmit data shift register sd at a[7:0] interr upt data transmission data transmission cloc k stretch stop condition bus status interr upt nak d[7:0] tr ansmit interr upt 5.6 i2cs timing char t 2 (data tr ansmission stop condition) figure 18. sift shift shift shift shift shift shift shift d7 pclk scl1 (input) scl1 (output) sd a1 (input) sd a1 (output) r/w busy selected rxrd y rxo vf d a_st op receiv e data sift register rd at a[7:0] interr upt a6 a5 a4 a3 a2 a1 a0 d6 d5 d4 r/w = 0 ac k star t condition sla ve address reception data reception shift shift shift 5.7 i2cs timing char t 3 (star t condition data reception) figure 18. 18 i 2 c sla ve (i2cs) 18-8 seiko epson corporation s1c17554/564 t echnical m anual d[7:0] d[7:0] d5 d4 d3 d2 d1 d0 d7 d6 d0 shift shift shift shift shift shift shift shift shift ac k pclk scl1 (input) scl1 (output) sd a1 (input) sd a1 (output) r/w busy selected rxrd y rxo vf d a_st op receiv e data sift register rd at a[7:0] interr upt data reception data reception cloc k stretch stop condition bus status interr upt nak read receiv e interr upt 5.8 i2cs timing char t 4 (data reception stop condition) figure 18. i2cs interrupts 18.6 the i2cs module includes a function for generating the follo wing three dif ferent types of interrupts. ? t ransmit interrupt ? recei v e interrupt ? bus status interrupt the i2cs module outputs one interrupt signal shared by the three abo v e interrupt causes to the interrupt controller (itc). t ransmit interrupt when the transmit data written to sd a t a[7:0]/i2cs_trns re gister is sent to the shift re gister , txemp/i2cs_ ast a t re gister is set to 1 and an interrupt signal is output to the itc. an interrupt occurs if other interrupt con- ditions are satisf ied. this interrupt can be used to write the ne xt transmit data to sd a t a[7:0]. set txemp_ien/i2cs_ictl re gister to 1 when using this interrupt. if txemp_ien is set to 0 (def ault), inter - rupt requests by this cause will not be sent to the itc. receive interrupt when the recei v ed data is loaded to rd a t a[7:0]/i2cs_recv re gister , rxrd y/i2cs_ast a t re gister is set to 1 and an interrupt signal is output to the itc. an interrupt occurs if other interrupt conditions are satisf ied. this interrupt can be used to read the recei v ed data from rd a t a[7:0]. set rxrd y_ien/i2cs _ictl re gister to 1 when using this interrupt. if rxrd y_ien is set to 0 (def ault), in- terrupt requests by this cause will not be sent to the itc. bus status interrupt t h e i 2 c s m o d u l e p r o v i d e s t h e s t a t u s b i t s l i s t e d b e l o w t o r e p r e s e n t t h e t r a n s m i t / r e c e i v e a n d i 2 c b u s s t a t u s e s ( s e e section 18.5 for details of each function). 1. asdet/i2cs_st a t re gister: this bit is set to 1 when the sla v e address is detected by the asynchronous ad- dress detection function. 2. txudf/i2cs_st a t re gister: this bit is set to 1 when a transmit operation has started before transmit data is written. (when the clock stretch function is disabled) 3. d a_n ak/i2cs_st a t re gister: this bit is set to 1 when a n ak is returned from the master during trans- mission. 4. dms/i2cs_st a t re gister: this bit is set to 1 when the sd a line status is dif ferent from transfer data. dms will also be set to 1 when another sla v e de vice issues a ck to this i 2 c sla v e address (when asdet_ en/i2cs_ctl re gister = 0). 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-9 note: w h e n t h e m a s t e r d e v i c e o f t h e i 2 c b u s , w h i c h h a s m u l t i p l e s l a v e d e v i c e s c o n n e c t e d i n c l u d - ing this ic , star ts comm unication with another sla v e de vice , the i2cs module issues nak in response to the sent sla v e address . on the other hand, the selected sla v e de vice issues a ck. theref ore , dms ma y be set due to a diff erence betw een the output v alue of this ic and the sd a line status . when selected/ i2cs_ast a t register is set to 0, y ou can ig- nore dms without a prob lem e v en if it is set to 1 as there is a diff erence in the response code (a ck/nak) from the selected sla v e de vice . when the i2cs module is placed into asynchronous address detection mode (asdet_en = 1), a dms does not occur as in the condition abo v e . 5. rxo vf/i2cs_st a t re gister: this bit is set to 1 when the ne xt data has been recei v ed before the recei v ed data is read (the recei v ed data is o v erwritten). (when the clock stretch function is disabled) 6. bfreq/i2cs_st a t re gister: this bit is set to 1 when a b us free request is accepted. 7. d a_st op/i2cs_st a t re gister: this bit is set to 1 if a stop condition is detected while this module is se- lected as the sla v e de vice. when one of the bits listed abo v e is set to 1, bst a t/i2cs_st a t re gister is set to 1 and an interrupt signal is output to the itc. an interrupt occurs if other interrupt conditions are satisf ied. this interrupt can be used to perform an error or terminate handling. set bst a t_ien/i2cs_ictl re gister to 1 when using this interrupt. if bst a t_ien is set to 0 (def ault), inter - rupt requests by this cause will not be sent to the itc. f or more information on interru pt processing, see the interrupt controller (itc) chapter . contr ol register details 18.7 7.1 list of i2cs registers t ab le 18. ad dress register name function 0x4360 i2cs_trns i 2 c sla v e t r ansmit data register i 2 c sla v e tr ansmit data 0x4362 i2cs_recv i 2 c sla v e receiv e data register i 2 c sla v e receiv e data 0x4364 i2cs_sadrs i 2 c sla v e address setup register sets the i 2 c sla v e address . 0x4366 i2cs_ctl i 2 c sla v e control register controls the i 2 c sla v e module . 0x4368 i2cs_st a t i 2 c sla v e status register indicates the i 2 c b us status . 0x436a i2cs_ast a t i 2 c sla v e access status register indicates the i 2 c sla v e access status . 0x436c i2cs_ictl i 2 c sla v e interr upt control register controls the i 2 c sla v e interr upt. the i2cs module re gisters are described in detail belo w . these are 16-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. i 2 c slave transmit data register (i2cs_trns) register name ad dress bit name function setting init. r/w remarks i 2 c slave transmit data register (i2cs_trns) 0x4360 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sdata[7:0] i 2 c sla v e tr ansmit data 0C0xff 0x0 r/w d[15:8] reserved d[7:0] sdata[7:0]: i 2 c slave transmit data bits sets a transmit data in this re gister . (def ault: 0x0) the serial-con v erted data is output from the sd a1 pin be ginning with the msb, in which the bits set to 0 are output as lo w-le v el signals. when the data set in this re gister is sent to the shift re gister , a trans- mit interrupt occurs. the ne xt transmi t data can be written to the re gister after that. if the clock stretch function has been disabled, data must be written to this re gister within 7 c ycles of the i 2 c clock (scl1 input clock) after a transmit interrupt has been occurred. ho we v er , when setting the f irst transmit data after this module has been selected as the sla v e de vice, follo w the precautions described belo w . 18 i 2 c sla ve (i2cs) 18-10 seiko epson corporation s1c17554/564 t echnical m anual when the clock stretch function is disabled (def ault) t ransmit data must be written to sd a t a[7:0] within 1 c ycle of the i 2 c clock (scl1 input clock) after txemp has been set to 1. this time is not enough for data preparation, so write transmit data before txemp has been set to 1. if the pre vious transmit data is still stored in sd a t a[7:0], it is o v erwritten with the ne w data to be transferred. t herefore, the clear operation (see belo w) using tb uf_clr is unnecessary . when the clock stretch function is enabled the master de vice is placed into w ait status by the clock stretch function, so transmit data can be written after txemp is set. ho we v er , if the pre vious transmit data is still stored in sd a t a[7:0], it will be sent immediately after txemp has been set. in order to a v oid this problem, clear the i2cs_ t r n s r e g i s t e r u s i n g t b u f _ c l r / i2c s _ c t l r e g i s t e r b e f o r e t h i s m o d u l e i s s e l e c t e d a s t h e s l a v e de vice. the i2cs_trns re gister is cleared by writing 1 to tb uf_clr then writing 0 to it. it is not necessary to clear the i2cs_trns re gister if the f irst transmit data is written before tx- emp has been set. i 2 c slave receive data register (i2cs_recv) register name ad dress bit name function setting init. r/w remarks i 2 c slave receive data register (i2cs_recv) 0x4362 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 rdata[7:0] i 2 c sla v e receiv e data 0C0xff 0x0 r d[15:8] reserved d[7:0] rdata[7:0]: i 2 c slave receive data bits the recei v ed data can be read from this re gister . (def ault: 0x0) the serial data input from the sd a1 pin be ginning with the msb is con v erted into parallel data, with the high-le v el signals changed to 1 and the lo w-le v el signals changed to 0. the resulting data is stored in this re gister . when a recei v e ope ration is completed and the data recei v ed in the shift re gister is loaded to this re gis- ter , rxrd y/i2cs_ast a t re gister is set and a recei v e interrupt occurs. thereafter , the data can be read out. when the clock stretch function has been disabled, data must be read from this re gister within 7 c ycles of the i 2 c clock (scl1 input clock) after rxrd y is set to 1. if the ne xt data has been recei v ed with out reading the recei v ed data, this re gister will be o v erwritten with the ne wly recei v ed data. i 2 c slave address setup register (i2cs_sadrs) register name ad dress bit name function setting init. r/w remarks i 2 c slave address setup register (i2cs_sadrs) 0x4364 (16 bits) d15C7 C reser v ed C C C 0 when being read. d6C0 sadrs[6:0] i 2 c sla v e address 0C0x7f 0x0 r/w d[15:7] reserved d[6:0] sadrs[6:0]: i2cs address bits sets the sla v e address of the i2cs module to this re gister . (def ault: 0x0) i 2 c slave control register (i2cs_ctl) register name ad dress bit name function setting init. r/w remarks i 2 c slave control register (i2cs_ctl) 0x4366 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 tbuf_clr i2cs_trns register clear 1 clear state 0 nor mal 0 r/w d7 i2csen i 2 c sla v e enab le 1 enab le 0 disab le 0 r/w d6 softreset softw are reset 1 reset 0 cancel 0 r/w d5 nak_ans nak ans w er 1 nak 0 a ck 0 r/w d4 bfreq_en bus free request enab le 1 enab le 0 disab le 0 r/w d3 clkstr_en cloc k stretch on/off 1 on 0 off 0 r/w d2 nf_en noise filter on/off 1 on 0 off 0 r/w d1 asdet_en async.address detection on/off 1 on 0 off 0 r/w d0 com_mode i 2 c sla v e comm unication mode 1 activ e 0 standb y 0 r/w 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-11 d[15:9] reserved d8 tbuf_clr: i2cs_trns register clear bit clears the i2cs_trns re gister . 1 (r/w): clear state 0 (r/w): normal state (clear state cancellation) (def ault) when tb uf_clr is set to 1, the i2cs_trns re gister enters clear state. after that writing 0 to tb uf_ clr returns the i2cs_trns re gister to normal state. it is not necessary to insert a w aiting time be- tween writing 1 and 0. if a ne w transmission is started when the i2cs_trns re gister sti ll stores data for the pre vious trans- mission that has already f inished, the data will be sent when txemp/i2cs_ast a t re gister is set. in order to a v oid this problem, clear the i2cs_trns re gister using tb uf_clr before starting transmis- sion (before sla v e selection). the clear operation is not required if transmit data is written to the i2cs_ trns re gister before txemp is set to 1. data can be writt en to the i2cs_trns re gister e v en if it is placed into clear state (tb uf_clr = 1). ho we v er , this writing does not reset txemp to 0. note that txemp is not reset to 0 when tb uf_clr is set back to 0. therefore, data must be written to the i2cs_trns re gister when tb uf_clr = 0. d7 i2csen: i 2 c slave enable bit enables or disables operations of the i2cs module. 1 (r/w): enabled 0 (r/w): disabled (def ault) when i2csen is set to 1, t he i2cs module is acti v ated and data transfer is enabled. when i2csen is set to 0, the i2cs module goes of f. d6 softreset: software reset bit resets the i2cs module. 1 (r/w): reset 0 (r/w): cancel reset state (def ault) t o r e s e t t h e i2c s m o d u l e , w r i t e 1 t o s o f t r e s e t t o p l a c e t h e i2c s m o d u l e i n t o r e s e t s t a t u s , t h e n write 0 to softreset to release it from reset status. it is not necessary to insert a w aiting time be- tween writing 1 and 0. the i2cs module initializes the i 2 c communication process and put the sd a1 and scl1 pins into high-impedance to be ready to detect a start condition. furthermore, the i2cs con- trol bits e xcept for softreset are initialized. perform the softw are reset in the initial setting process before staring communication. d5 nak_ans: nak answer bit specif ies the ackno wledge bit to be sent after data reception. 1 (r/w): n ak 0 ( r/w): a ck (def ault) w h e n a n e i g h t - b i t d a t a i s r e c e i v e d , t h e i 2 c s m o d u l e s e n d s b a c k a n a c k ( s d a 1 = l o w ) o r a n a k ( s d a 1 = hi-z). either a ck or n ak should be specif ied using n ak_ans within 7 c ycles of the i 2 c clock (scl1 input clock) after rxrd y has been set to 1 by recei ving the pre vious data. d4 bfreq_en: bus free request enable bit enables or disables i 2 c b us free requests by inputting a lo w pulse to the #bfr pin. 1 (r/w): enabled 0 (r/ w): disabled (def ault) t o accept i 2 c b us free requests, set bfreq_en to 1. when a b us free request is accepted, bfreq/ i2cs_st a t re gister is set to 1. this initializes the i 2 c communication process and puts the sd a1 and scl1 pins into high-impedance. the control re gisters will not be initialized in this process. when bfreq_en is set to 0, lo w pulse inputs to the #bfr pin are ignored and bfreq is no t set to 1. 18 i 2 c sla ve (i2cs) 18-12 seiko epson corporation s1c17554/564 t echnical m anual d3 clkstr_en: clock stretch on/off bit t urns the clock stretch function on or of f. 1 (r/w): on 0 (r/w): of f (def ault) after data and a ck are transmitted or recei v ed, the sla v e de vice may issue a w ait request to the master de vice until it is ready to transmit/recei v e by pulling the i 2 c b us scl line do wn to lo w . the i2cs mod- ule supports this clock stretch function. the master de vice enters a standby state until the w ait request is can celed (the scl line goes high). when using the clock stretch function, set clkstr_en to 1 before starting data communication. d2 nf_en: noise filter on/off bit t urns the noise f ilter on or of f. 1 (r/w): on 0 (r/w): of f (def ault) the i2cs module contains a function to remo v e noise from the sd a1 and scl1 input signals. this function is enabled by setting nf_en to 1. d1 asdet_en: async. address detection on/off bit t urns the asynchronous address detection function on or of f. 1 ( r/w): on 0 (r/w): of f (def ault) the i2cs module operation clock (pclk) frequenc y must be set eight-times or higher than the transfer rate during data transfer . ho we v er , the pclk frequenc y can be lo wered to reduce current consumption if no other processing is required during standby for data transfer . the asynchronous address detection function is pro vided to detect the i 2 c sla v e address sent from the master in this status. this function is enabled by setting asdet_en to 1. if the sla v e address sent from the master has matched with one that has been set in this i2cs module when the asynchronous address detection function has been enabled, the i2cs module generates a b us status interrupt and returns n ak to the i 2 c master to request for resending the sla v e address. set the pclk frequenc y to eight-times or higher than the transfer rate and reset asdet_en to 0 in the interrupt handler routine. data transfer will be able to resume normally after the master retries transmission. after the master generates a stop condition to put the i 2 c b us into free status, the asynchronous address detection function can be enabled ag ain to lo wer the operating speed. notes: ? when the asynchronous address de tection function is enab led, the i 2 c b us signals are input without passing through the noise filter . theref ore , the sla v e address ma y not be detected in a high-noise en vironment. ? when the asynchronous address detection function is enab led, data tr ansf er cannot be per- f or med e v en if the pclk frequency is eight-times or higher than the tr ansf er r ate . be sure to disab le the asynchronous address det ection function dur ing nor mal oper ation. d0 com_mode: i 2 c slave communication mode bit enables or disables data communication. 1 (r/w): enabled 0 (r/w): disabled (def ault) set com_mode to 1 to enable data communication after setting i2csen to 1 to enable i2cs opera- tion. when com_mode is 0 (def ault), the i2cs module does not send back a response if the master has sent the sla v e address of this module (it is re g arded as that the i2cs module has returned a n ak to the master). 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-13 i 2 c slave status register (i2cs_stat) register name ad dress bit name function setting init. r/w remarks i 2 c slave status register (i2cs_stat) 0x4368 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 bstat bus status tr ansition 1 changed 0 unchanged 0 r d6 C reser v ed C C C 0 when being read. d5 txudf t r ansmit data underflo w 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. rxovf receiv e data o v erflo w d4 bfreq bus free request 1 occurred 0 n o t o c c u r r e d 0 r/w d3 dms output data mismatch 1 error 0 nor mal 0 r/w d2 asdet async. address detection status 1 detected 0 n o t d e t e c t e d 0 r/w d1 da_nak nak receiv e status 1 nak 0 a ck 0 r/w d0 da_stop st op condition detect 1 detected 0 n o t d e t e c t e d 0 r/w d[15:8] reserved d7 bstat: bus status transition bit indicates transition of the b us status. 1 (r): changed 0 (r): unchanged (def ault) w h e n o n e o f t h e t x u d f / r x o v f , b f r e q , d m s , a s d e t , d a _ n a k , a n d d a _ s t o p b i t s i s s e t t o 1, bst a t is also set to 1 and an interrupt signal is output to the itc if the interrupt is enabled with bst a t_ien/i2cs_ictl re gister . this interrupt can be used to perform an error or t erminate handling. b s t a t w i l l b e r e s e t t o 0 w h e n t h e t x u d f / r x o v f , b f r e q , d m s , a s d e t , d a _ n a k , a n d d a _ st op bits are all reset to 0. d6 reserved d5 txudf: transmit data underflow bit (for transmission) rxovf: receive data overflow bit (for reception) indicates the transmit/recei v e data re gister status. 1 (r/w): data underflo w/o v erflo w has been occurred 0 (r/w): data underflo w/o v erflo w has not been occurred (def ault) this bit is ef fecti v e during transmission/reception when the clock stretch function is disabled. i f a data transmission be gins before transmit data is written to the i2cs_trns re gister , it is re g arded as a trans- mit data underflo w and txudf is set to 1. if the ne xt data reception has completed before the recei v ed data is read from the i2cs_recv re gister and the i2cs_recv re gister v alue is o v erwritten with the ne wly recei v ed data, it is re g arded as a data o v erflo w and rxo vf is set to 1. at the same time, an interrupt signal is output to the itc if the interrupt is enabled with bst a t_ien/ i2cs_ictl re gister . this interrupt can be used to perform an error handling. after txudf/rxo vf is set to 1, it is reset to 0 by writing 1. d4 bfreq: bus free request bit indicates the i 2 c b us free request input status. 1 (r/w): request has been issued 0 (r/w): request has not been issued (def ault) if bfreq_en/i2cs_ctl re gister has b een set to 1 (b us free request enabled), a lo w pulse longer than f i v e peripheral module clock (pclk) c ycles input to the #bfr pin sets bfreq to 1 and the b us free request is accepted. when a b us free request is accepted, the i2cs module initializes the i 2 c communi- cation process and puts the sd a1 and scl1 pins into high-impedance. the control re gisters will not be initialized in this process. at t he same time, an interrupt signal is output to the itc if the interrupt is enabled with bst a t_ien/ i2cs_ictl re gister . this interrupt can be used to perform an error handling. after bfreq is set to 1, it is reset to 0 by writing 1. if bfreq_en is set to 0, lo w pulse inputs to the #bfr pin are ignored and bfreq is not set to 1. 18 i 2 c sla ve (i2cs) 18-14 seiko epson corporation s1c17554/564 t echnical m anual d3 dms: output data mismatch bit represents the results of comparison between output data and sd a line status. 1 (r/w): error has been occurred 0 (r/w): error has not been occurred (def ault) the i 2 c b us sd a line status during data transmission is input in the module and is compared with the output data. the comparison results are set to dms. dms is set to 0 when data is output correctly . if the sd a line status is dif ferent from the output data, dms is set to 1. this may be caused by a lo w pull- up resistor v alue or another de vice that is controlling the sd a line. at the same time, an interrupt signal is output to the itc if the interrupt is enabled with bst a t_ien/i2cs_ictl re gister . this interrupt can be used to perform an error handling. after dms is set to 1, it is reset to 0 by writing 1. note: when the master device of the i 2 c bus, which has multiple slave devices connected includ - ing this ic, starts communication with another slave device, the i2cs module of this ic issues nak in response to the sent slave address. on the other hand, the selected slave device is - sues ack. therefore, dms may be set due to a difference between the output value of this ic and the sda line status. when selected/i2cs_astat register is set to 0, you can ignore dms without a problem even if it is set to 1 as there is a difference in the response code (ack/ nak) from the selected slave device. when the i2cs module is placed into asynchronous address detection mode ( a s d e t _ e n = 1 ) , a dms does not occur as in the condition above. d2 asdet: async. address detection status bit indicates the asynchronous address detection status. 1 (r/w): detected 0 (r/w): not detected (def ault) the i2cs module operation clock (pclk) frequenc y must be set eight-times or higher than the transfer rate during data transfer . ho we v er , the pclk frequenc y can be lo wered to reduce current consumption if no other processing is required during standby for data transfer . the asynchronous address detection function is pro vided to detect the i 2 c sla v e address sent from the master in this status. asdet is set to 1 if the sla v e address of the i2cs module is detected when the asynchronous address detection function has been enabled by setting asdet_en/i2cs_ctl re gister . the i2cs module returns a n ak to the i 2 c master to request for resending the sla v e address. at the same time, an interrupt s ignal is output to the itc if the interrupt is enabled with bst a t_ien/i2cs_ ictl re gister . set the pclk frequenc y to eight-times or higher than the transfer rate and reset asdet_ en to 0 in the interrupt handler routine. data transfer will be able to resume normally after the master retries transmission. after asdet is set to 1, it is reset to 0 by writing 1. d1 da_nak: nak receive status bit indicates the ackno wledge bit returned from the master . 1 (r/w): n ak 0 (r/w): a ck (def ault) d a_n ak is set to 0 when an a ck is returned from the master after an eight-bit data has been sent. this indicates that the master could recei v e data. if d a_n ak is 1, it indicates that the master could not recei v e data or the master terminates data reception. at the same time d a_n ak is set to 1, an interrupt signal is output to the itc if the inte rrupt is enabled with bst a t_ien/i2cs_ictl re gister . this inter - rupt can be used to perform an error handling. after d a_n ak is set to 1, it is reset to 0 by writing 1. d0 da_stop: stop condition detect bit indicates that a stop condition is detected. 1 (r/w): detected 0 (r/w): not detected (def ault) i f a s t o p c o n d i t i o n i s d e t e c t e d w h i l e t h e i2c s m o d u l e i s s e l e c t e d a s t h e s l a v e d e v i c e ( s e l e c t e d / i2cs_ast a t re gister = 1), the i2cs module sets d a_st op to 1. at the same time, it puts the sd a1 a n d s c l1 p i n s i n t o h i g h - i m p e d a n c e a n d i n i t i a l i z e s t h e i 2 c c o m m u n i c a t i o n p r o c e s s t o e n t e r s t a n d b y state that is ready to detect the ne xt start condition. 18 i 2 c sla ve (i2cs) s1c17554/564 t echnical m anual seiko epson corporation 18-15 when d a_st op is set to 1, an interrupt signal is output to the itc if the interrupt is enabled with b s t a t _ i e n / i2c s _ i c t l r e g i s t e r . t h i s i n t e r r u p t c a n b e u s e d t o p e r f o r m a t e r m i n a t e h a n d l i n g . a f t e r d a_st op is set to 1, it is reset to 0 by writing 1. i 2 c slave access status register (i2cs_astat) register name ad dress bit name function setting init. r/w remarks i 2 c slave access status register (i2cs_astat) 0x436a (16 bits) d15C5 C reser v ed C C C 0 when being read. d4 rxrdy receiv e data ready 1 ready 0 not ready 0 r d3 txemp t r ansmit data empty 1 empty 0 not empty 0 r d2 busy i 2 c b us status 1 busy 0 f ree 0 r d1 selected i 2 c sla v e select status 1 selected 0 n o t s e l e c t e d 0 r d0 r/w read/wr ite direction 1 output 0 input 0 r d[15:5] reserved d4 rxrdy: receive data ready bit indicates that the recei v ed data is ready to read. 1 (r): recei v ed data ready 0 (r): no recei v ed data (def ault) when the recei v ed data is loaded to th e i2cs_recv re gister , rxrd y is set to 1. at the same time, an interrupt signal is output to the itc if the interrupt is enabled with rxrd y_ien/i2cs_ictl re gister . this interrupt can be used to read the recei v ed data from the i2cs_recv re gister . after rxrd y is set to 1, it is reset to 0 when the i2cs_recv re gister is read. d3 txemp: transmit data empty bit indicates that transmit data can be written. 1 (r): t ransmit data empty (da ta can be written) 0 (r): t ransmit data still stored (data cannot be written) (def ault) when the transmit data written to the i2cs_trns re gister is sent, txemp is set to 1. at the same time, an interrupt signal is output to the itc if the interrupt is enabled with txemp_ien/i2cs_ictl re gister . this interrupt can be used to write the ne xt transmit data to the i2cs_trns re gister . after txemp is set to 1, it is reset to 0 when data is written to the i2cs_trns re gister . d2 busy: i 2 c bus status bit indicates the i 2 c b us status. 1 (r): bus b usy status 0 (r): bus free status (def ault) when the i2cs module detects a start condition or detects that the scl1 or sd a1 signal goes lo w , b usy is set to 1 to indicate that the i 2 c b us enters b usy status. the sla v e select status whether this module is selected as the sla v e de vice o r not does not af fect the b usy status. after b usy is set to 1, it is reset to 0 when a st op condition is detected. d1 selected: i 2 c slave select status bit indicates that this module is selected as the i 2 c sla v e de vice. 1 (r): selected 0 (r): not selected (def ault) when the sla v e address that is set in this module is recei v ed, selected is set to 1 to indicate that this module is selected as the i 2 c sla v e de vice. after selected is set to 1, it is reset to 0 when a stop con- dition is detected. d0 r/w: read/write direction bit represents the transfer direction bit v alue. 1 (r): output (master read operation) 0 (r): input (master write operation) (def ault) the transfer direction bit v alue that has been recei v ed with the sla v e address is set to r/w . use r/w to select the transmit- or recei v e-handling. 18 i 2 c sla ve (i2cs) 18-16 seiko epson corporation s1c17554/564 t echnical m anual i 2 c slave interrupt control register (i2cs_ictl) register name ad dress bit name function setting init. r/w remarks i 2 c slave interrupt control register (i2cs_ictl) 0x436c (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 bstat_ien bus status interr upt enab le 1 enab le 0 disab le 0 r/w d1 rxrdy_ien receiv e interr upt enab le 1 enab le 0 disab le 0 r/w d0 txemp_ien t r ansmit interr upt enab le 1 enab le 0 disab le 0 r/w d[15:3] reserved d2 bstat_ien: bus status interrupt enable bit enables or disables the b us status interrupt. 1 (r/w): enabled 0 (r/w): disabled (def ault) when bst a t_ien is set to 1, i 2 c b us status interrupt requests to the itc are enabled. a b us status in- terrupt req uest occurs when bst a t/i2cs_st a t re gister is set to 1. (see description of bst a t .) when bst a t_ien is set to 0, a b us status interrupt will not be generated. d1 rxrdy_ien: receive interrupt enable bit enables or disables the i2cs recei v e interrupt. 1 (r/w): enabled 0 (r/w): disabled (def ault) when rxrd y_ien is set to 1, i2cs recei v e interrupt requests to the itc are enabled. a recei v e inter - rupt request occurs when the data recei v ed in the shift re gister is loaded to the i2cs_recv re gister (recei v e operation completed). when rxrd y_ien is set to 0, a recei v e interrupt will not be generated. d0 txemp_ien: transmit interrupt enable bit enables or disables the i2cs transmit interrupt. 1 (r/w): enabled 0 (r/w): disabled (def ault) when txemp_ien is set to 1, i2cs transmit interrupt requests to the itc are enabled. a transmit in- terrupt request occurs when the data written to the i2cs_trns re gister is transferred to the shift re gis- ter . when txemp_ien is set to 0, a transmit interrupt will not be generated. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-1 uni v ersal serial interface (usi) 19 [s1c17564] note: the univ ersal ser ial interf ace (usi) is una v ailab le in the s1c17554. usi module over vie w 19.1 the s1c17564 incorporates a tw o-channel uni v ersal serial interf ace (usi) module in which each channel can be conf igured as a u ar t , spi, or i 2 c interf ace unit by the softw are switch. the follo wing sho ws the main features of usi: ? supports four interf ace mod es: u ar t , spi master , i 2 c master , and i 2 c sla v e modes. ? t w o channels can be conf igured to dif ferent interf ace modes. ? contains one-byte recei v e data b uf fer and one-byte transmit data b uf fer . ? supports both msb f irst and lsb f irst modes. ? u ar t mode - character length: 7 or 8 bits - p arity mode: e v en, odd, or no parity - stop bit: 1 or 2 bits - start bit: 1 bit f ix ed - p arity error , framing error , and o v errun error detectable - can generate recei v e b uf fer full, transmit b uf fer empty , and recei v e error interrupts. ? spi master mode - data length: 8 or 9 bits - supports both f ast and normal modes. - data transfer timing (clock phase and polarity v ariations) is selectable from among 4 types. - recei v e data mask function is a v ailable. - can generate recei v e b uf fer full, transmit b uf fer empty , and o v errun er ror interrupts. ? i 2 c master/sla v e mode - 7-bit addressing mode (10-bit addressing is possible by softw are control.) - supports single master conf iguration only (master mode). - supports clock stretch/w ait functions. - can generate start/stop, data transfer , a ck/n ak transfer , and o v errun error interrupts. figure 19.1.1 sho ws the usi conf iguration. shift register receive data buffer (1 byte) us_sdix internal bus itc usi ch.x bus i/f and control registers us_sckx us_ssix shift register transmit data buffer (1 byte) clock/transfer control us_sdox interrupt control transfer clock source ch.0: from t16f ch.0 ch.1: from t16f ch.1 1.1 usi configur ation (one channel) figure 19. note: t w o channels in the usi module ha v e the same functions e xcept f or control register addresses . f or this reason, the descr iption in this chapter applies to all usi channels . the x in the register name indicates the channel n umber (0 or 1). example: usi_gcfgx register ch.0: usi_gcfg0 register ch.1: usi_gcfg1 register 19 universal serial interf a ce (usi) [s1c17564] 19-2 seiko epson corporation s1c17554/564 t echnical m anual usi pins 19.2 t able 19.2.1 lists the usi input/output pins. 2.1 list of usi pins t ab le 19. pin name usi mode signal name i/o function us_sdi0 us_sdi1 u ar t uar t_rx i data input pins inputs ser ial data sent from an e xter nal ser ial de vice . spi master spi_sdi i i 2 c master i2c_sda i/o data input/output pins inputs/outputs ser ial data from/to the i 2 c b us . (*1) i 2 c sla v e i2c_sda i/o us_sdo0 us_sdo1 u ar t uar t_tx o data output pins outputs ser ial data sent to an e xter nal ser ial de vice . spi master spi_sdo o i 2 c master C C not used i 2 c sla v e C C us_sck0 us_sck1 u ar t C C not used spi master spi_sc k o cloc k output pins outputs the spi cloc k. i 2 c master i2c_scl i/o scl input/output pins inputs scl line status from the i 2 c b us . also outputs the i 2 c cloc k. i 2 c sla v e i2c_scl i/o scl input/output pins i n p u t s s c l l i n e s t a t u s f r o m t h e i 2 c b u s . a l s o o u t p u t s a c l o c k s t r e t c h condition. us_ssi0 us_ssi1 u ar t C C not used spi master C C i 2 c master i2c_sda i/o data input/ou tput pins inputs/outputs ser ial data from/to the i 2 c b us . (*1) i 2 c sla v e i2c_sda i/o *1: when usi ch.x is configured to i 2 c master or sla v e mode , either the us_sdix pin or the us_ssix pin can be used as the data input/output pin. note , ho w e v er , that both the us_sdix and us_ssix pins cannot be used as the data input/output pin sim ultaneously . note: use an i/o (p) por t to output the sla v e select signal when usi ch.x is configured to spi master mode . the usi input/output pins (us_sdix, us_sdox, us_sckx, us_ssix) are shared with i/o ports and are initially set as general-purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as usi input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . usi cloc k sour ces 19.3 operating c loc k the usi module uses pclk as the operating clock. therefore, pclk must be supplied from the clg before starting the usi including setting the control re gisters. f or more information on the pclk supply , refer to the clock generator (clg). t ransf er c loc k when the usi is conf igured to a u ar t , spi master (normal mode), or i 2 c master de vice, the source cl ock for transfer is supplied by the f ine mode 16-bit timer (t16f). program the t16f according to the transfer rate and enable supplying the source clock to the usi module. the usi module di vides the source clock to generate the transfer clock (or sampling clock). be a w are that the di vision ratio in the usi depends on the interf ace mode. when the usi is conf igured to an spi master (f ast mode) de vic e, pclk is used as the source clock. when the usi is conf igured to an i 2 c sla v e de vice, the transfer clock is supplied from the e xternal master de- vice. ho we v er , i 2 c sla v e mode uses the t16f output clock to generate the sampling signal. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-3 3.1 usi cloc ks t ab le 19. cloc k interface mode usi ch.0 usi ch.1 oper ating cloc k u ar t pclk pclk spi master pclk pclk i 2 c master pclk pclk i 2 c sla v e pclk pclk t r ansf er/sampling cloc k source (division r atio in usi) u ar t t16f ch.0 (f source /8) t16f ch.1 (f source /8) spi master nor mal mode: t16f ch.0 (f source /2) f ast mode: pclk (f pclk ) nor mal mode: t16f ch.1 (f source /2) f ast mode: pclk (f pclk ) i 2 c master t16f ch.0 (f source /8) t16f ch.1 (f source /8) i 2 c sla v e t16f ch.0 (f source ) f or sampling t16f ch.1 (f source ) f or sampling f or controlling the t16f module and setting the output clock, refer to the fine mode 16-bit t imers (t16f) chapter . note: when the usi is set to i 2 c sla v e mode , i2c_scl (i 2 c cloc k) is supplied from the e xter nal i 2 c mas- ter . the t16f output cloc k frequency (f source ) should be deter mined according to the i2c_scl fre- quency . t16f output clock scl controlled by i 2 c master scl controlled by i 2 c slave us_sckx pin ab cd ef 3.1 i figure 19. 2 c cloc k in i 2 c sla v e mode tbf = ti2c_baud_r ate tbc = ti2c_baud_r ate_high tcf = ti2c_baud_r ate_lo w tce: the i 2 c master occupies the scl line b y dr iving it to lo w . t ac: the i 2 c master releases the scl line . tdf: i n o r d e r t o f i n i s h t h e i n t e r n a l o p e r a t i o n s , t h e i 2 c s l a v e o c c u p i e s t h e s c l l i n e f o r t w o source cloc k (t16f output cloc k) cycles b y dr iving it to lo w after detecting that the i 2 c m aster dr iv es the scl line to lo w . the t16f output cloc k frequency (f source ) m ust be set so that the conditions sho wn belo w are satisfied. f source > 3/tbc f source > 4/tce be a w are that the actual scl signal will be dela y ed, as the i 2 c sla v e f orcib ly dr iv es the scl line to lo w . the figure belo w sho ws an e xample in which the timing becomes w orse . t16f output clock scl controlled by i 2 c master scl controlled by i 2 c slave us_sckx pin ab cd e 3.2 example of dela y ed i figure 19. 2 c cloc k 19 universal serial interf a ce (usi) [s1c17564] 19-4 seiko epson corporation s1c17554/564 t echnical m anual usi module settings 19.4 mak e the follo wing settings before starting data transfers using the usi module. (1) conf igure the pins to be used for usi according to the interf ace mode. (see section 19.2.) (2) program the clock source module to supply the clock required to the usi module. (see section 19.3.) (3) reset the usi module. (4) set the usi interf ace mode and a general condition (msb f irst/lsb f i rst) to be applied to all interf ace modes. (5) set the data format and operating conditions for the interf ace mode selected. (6) set interrupt conditions if necessary . (see section 19.7.) usi module software reset 19.4.1 writing 0x0 to usimod[2:0]/usi_gcfgx re gister resets the usi module circuits. be sure to perform softw are reset before setting the interf ace mode. interface mode 19.4.2 the usi module pro vides f i v e serial interf ace functions sho wn in section 19.1. each channel can be conf igured to one of them using the usimod[2:0]/usi_gcfgx re gister . 4.2.1 interf ace mode selection t ab le 19. usimod[2:0] interface mode 0x7C0x6 reser v ed 0x5 i 2 c sla v e 0x4 i 2 c master 0x3 reser v ed 0x2 spi master 0x1 u ar t 0x0 softw are reset (def ault: 0x0) note: be sure to perf or m softw are reset and set the interf ace mode bef ore changing other usi configu- r ations . general settings f or all interface modes 19.4.3 msb fir st/lsb fir st selection use lsbfst/usi_gcfgx re gister to select whether the data msb or lsb is input/output f irst . lsb f irst is selected when lsbfst is set to 0 (def ault). msb f irst is selected when lsbfst is set to 1. settings f or u ar t mode 19.4.4 when the usi is used in u ar t mode, conf igure the data length, stop bit, and parity bit. the start bit length is f ix ed at 1 bit. data length use uchln/usi_ucfgx re gister to select the data length. setting uchln to 0 (def ault) conf igures the data length to 7 bits. se tting uchln to 1 conf igures it to 8 bits. stop bit use ustpb/usi_ucfgx re gister to select the stop bit length. setting ustpb to 0 (def ault) conf igures the stop bit length to 1 bit. setting ustpb to 1 conf igures it to 2 bits. p arity bit use upren/usi_ucfgx re gister to select whether the parity function is enabled or not. setting upren to 0 (def ault) disables the parity function. in this case, no pari ty bit will be added to transfer data and recei v e data will not be check ed for parity . setting upren to 1 enables the parity function. in this case, a parity bit will be added to transfer data and recei v e data will be check ed for parity . 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-5 when the parity function is enabled, the parity mode should be selected using upmd/usi_ucfgx re gister . setting upmd to 0 (def ault) adds a parity bit and checks for odd parity . setting upmd to 1 adds a parity bit and checks for e v en parity . sampling clock uchln = 0, upren = 0, ustpb = 0 uchln = 0, upren = 1, ustpb = 0 uchln = 0, upren = 0, ustpb = 1 uchln = 0, upren = 1, ustpb = 1 uchln = 1, upren = 0, ustpb = 0 uchln = 1, upren = 1, ustpb = 0 uchln = 1, upren = 0, ustpb = 1 uchln = 1, upren = 1, ustpb = 1 s1 d0 d1 d2 d3 d4 d5 d6 s2 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s1 d0 d1 d2 d3 d4 d5 d6 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 p s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s1 d0 d1 d2 d3 d4 d5 d6 d7 s2 s3 s1 d0 d1 d2 d3 d4 d5 d6 d7 p s2 s3 s1: start bit, s2 & s3: stop bit, p: parity bit 4.4.1 t r ansf er data f or mat in u ar t mode (lsb first) figure 19. settings f or spi master mode 19.4.5 when the usi is used in spi master mode, conf igure the spi clock polarity/phase, clock mode, and data length. also enable/disable the recei v e data mask function. spi c loc k polarity and phase settings use scpol/usi_scfgx re gister to select the spi clock polarity . setting scpol to 1 treats the spi clock as acti v e lo w . setting it to 0 (def ault) treats it as acti v e high. the spi clock phase can be selected using scpha/usi_scfgx re gister . these control bits set transfer timing as sho wn in figure 19.4.5.1. us_sckx (scpol = 1, scpha = 1) us_sckx (scpol = 1, scpha = 0) us_sckx (scpol = 0, scpha = 1) us_sckx (scpol = 0, scpha = 0) us_sdix/us_sdox fetching received data into shift register d7 (msb) d0 (lsb) 4.5.1 cloc k and data t r ansf er timing (msb first) figure 19. cloc k mode either normal or f ast clock mode can be selected using sfstmod/usi_scfgx re gister . setting sfstmod to 0 (def ault) places the usi into normal mode and the usi generates the transfer clock by di viding the t16f out- put by 2. setting sfstmod to 1 places the usi into f ast mode and the usi uses pclk supplied from the clg directly as t he transfer clock. the f ast mode does not use the t16f . data length the data length can be selected using schln/usi_scfgx re gister . setting schln to 0 (def ault) conf igures the data length to 8 bits. setting schln to 1 conf igures the data length to 9 bits. in 9-bit mode, 8-bit data is pref ix ed with a command b i t ( 1 b i t ) . t h e c o m m a n d b i t i s u s e d f o r c o n t r o l l i n g t h e s p i l c d c o n t r o l l e r c o n n e c t e d t o t h e u s i . t h e c o m m a n d bit v alue to be transmitted can be specif ied using scmd/usi_scfgx re gister . setting scmd to 1 conf igures the command bit to high. setting scmd to 0 conf igures the command bit to lo w . 19 universal serial interf a ce (usi) [s1c17564] 19-6 seiko epson corporation s1c17554/564 t echnical m anual schln = 0, scmd = * schln = 1, scmd = 0 schln = 1, scmd = 1 command bit d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) 4.5.2 9-bit t r ansf er data f or mat in spi master mode figure 19. receive data mask function the usi in spi master mode pro vides a recei v e data mask (data retransmission) function. setting smsken/ usi_scfgx re gister to 1 enables this function. when the recei v e data mask function is enabled, the usi trans- mits the data stored in the transmit data b uf fer (td[7:0]/usi_tdx re gister) repeatedly until the sl a v e de vice sends back a v alue other than the mask data set to smsk[7:0]/usi_smskx re gister . in this case, the transmit b uf fer empty and recei v e data b uf fer full interrupt flags are not set and no interrupt is generated. in other w ords, the usi does not accept the recei v e data while the sla v e de vice is transmitting the mask data. f or e xample, when smsk[7:0] is 0xf f, no interrupt occurs until data o ther than 0xf f is recei v ed. f or normal data transfer , set smsken to 0 (def ault) to disable the recei v e data mask function. settings f or i 19.4.6 2 c mode the i 2 c mode does not need to set data format and other conditions. the data length in i 2 c mode is f ix ed at 8 bits. data t ransf er contr ol 19.5 this section describes ho w to control data transfers. the follo wing e xplanations assume that the conf igura tions de- scribed abo v e and interrupt settings ha v e already been f inished. data t ransf er in u ar t mode 19.5.1 data transmission t o start data transmission in u ar t mode, write the transmit data to the transmit data b uf fer (td[7:0]/usi_tdx re gister). the b uf fer data is sent to the transmit shift re gister , and the start bit is output from the us_sdox pin. the data in the shift re gister is then output in sequence. f ollo wing output of the eighth data bit, the parity bit (if parity is enabled) and the stop bit are output. the transmitter circuit includes tw o status flags: utdif/usi_uifx re gister and utbsy/usi_uifx re gister . the utdif flag indicates the transmit data b uf fer status. this flag is set to 1 indicating that the transmit data b uf fer becomes empty when data written to the transmit data b uf fer is sent to the transmit shift re gister . utdif is an interrupt flag. an interrupt request can be generated when this flag is set to 1 (see section 19.7). write subsequent data to the transmit data b uf fer to start the follo wing transmission using this interrupt. the transmit d a t a b u f f e r s i z e i s 1 b y t e , b u t a s h i f t r e g i s t e r i s p r o v i d e d s e p a r a t e l y t o a l l o w d a t a t o b e w r i t t e n w h i l e t h e p r e v i o u s dat a is being sent. if an interrupt is not used for transmission, be sure to conf irm that the transmit data b uf fer is empty before writing transmit data. writing data before utdif has been set will o v erwrite earlier transmit data inside the transmit data b uf fer . after utdif is set to 1, it can be reset to 0 by writing 1. the utbsy flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and re v erts to 0 once the data is sent. read this flag to check wheth- er the transmitter circuit is operating or at standby . 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-7 sampling cloc k td[7:0] shift register us_sdox pin utbsy utdif interr upt star t stop stop a d7 a d6 a d5 a d4 a d3 a d2 a d1 a d0 par ity par ity b d0 wr ite wr ite tr ansmit b uff er empty interr upt reset by wr iting 1 reset by wr iting 1 tr ansmit b uff er empty interr upt (msb first) data a data b star tb d7 b d6 5.1.1 data t r ansmission timing char t (u ar t mode) figure 19. data reception when the e xternal serial de vice sends a start bit, the recei v er circuit detects its lo w le v el and starts sampling the follo wing data bits. once the 8-bit data has been recei v ed into the shift re gister , the recei v ed data is loaded into the recei v e data b uf fer (rd[7:0]/usi_rdx re gister). if parity checking is enabled, the rece i v er circuit checks the recei v ed data at the same time by checking the parity bit recei v ed immediately after the eighth data bit. the recei v er circuit includes tw o status flags: urdif/usi_uifx re gister and urbsy/usi_uifx re gister . t h e u r d i f f l a g i n d i c a t e s t h e r e c e i v e d a t a b u f f e r s t a t u s . t h i s f l a g i s s e t t o 1 i n d i c a t i n g t h a t t h e r e c e i v e d d a t a c a n be read out when data recei v ed in the shift re gister is loaded to the recei v e data b uf fer . urdif is an interrupt flag. an interrupt request can be generated when this flag is set to 1 (see section 19.7). read the recei v ed data from the recei v e data b uf fer using this interrupt. the recei v e data b uf fer size is 1 byte, therefore the recei v ed data must be read before the subsequent data reception has completed. furthermore, urdif must be reset by writi ng 1. if the subsequent recei v e data is written to the recei v e data b uf fer when urdif is 1, an o v errun error occurs. the urbsy flag indicates the shift re gister status. this flag is set to 1 while data is being recei v ed in the shift r e g i s t e r a n d r e v e r t s t o 0 o n c e t h e r e c e i v e d d a t a i s l o a d e d t o t h e r e c e i v e d a t a b u f f e r . r e a d t h i s f l a g t o c h e c k whether the recei v er circuit is operating or at standby . sampling cloc k us_sdix pin shift register rd[7:0] urbsy urdif interr upt star t stop stop a d7 par ity par ity (msb first) data a data b data c star tb d7 stop par ity a d0 c d0 b d0 star tc d7 receiv e b uff er full interr upt receiv e b uff er full interr upt ov err un error interr upt (when data b has not been read) read reset by wr iting 1 5.1.2 data receiving timing char t (u ar t mode) figure 19. data t ransf er in spi master mode 19.5.2 data transmission t o start data transmission in spi master mode, write the transmit data to the transmit data b uf fer (td[7:0]/usi_ tdx re gister). the b uf fer data is sent to the transmit shift re gister , and the module starts clock output from the us_sckx pin. the data in the shift re gister is shifted in s equence at the clock rising or f alling edge (see figure 19.4.5.1) and sent from the us_sdox pin. the spi controller includes tw o status flags for transfer control: stdif/usi_sifx re gister and ssif/usi_sifx re gister . 19 universal serial interf a ce (usi) [s1c17564] 19-8 seiko epson corporation s1c17554/564 t echnical m anual the stdif flag indicates the transmit data b uf fer status. stdif is set to 1 indicating that the transmit data b uf- fer becomes empty when data written to the transmit data b uf fer is sent to the transmit shift re gister . stdif is an interrupt flag. an interrupt request can be generated when this flag is set to 1 (see section 19.7). write sub- sequent data to the transmit data b uf fer to start the foll o wing transmission using this interrupt. the transmit data b uf fer size is 1 byte, b ut a shift re gister is pro vided separately to allo w data to be written while the pre vious data is being sent. if an interrupt is not used for transmission, be sure to conf irm that the transmit data b uf fer is empty before writing transmit data. writing data before stdif has been set will o v erwrite earlier transmit da ta inside the transmit data b uf fer . in spi master mode, the ssif flag indicates the shift re gister status. this flag switches to 1 when transmit data is loaded from the transmit data b uf fer to the shift re gister and re v erts to 0 once the data is sent. read this flag to check whether the spi controller is operating or at standby . spi_sc k td[7:0] shift register us_sckx pin (scpol = 0, scpha = 1) us_sckx pin (scpol = 0, scpha = 0) us_sdox pin ssif stdif interr upt a d7 a d6 a d5 a d4 a d3 a d2 a d1 b d5 b d4 b d3 b d2 b d1 a d0 b d0 wr ite wr ite tr ansmit b uff er empty interr upt reset by wr iting 1 reset by wr iting 1 tr ansmit b uff er empty interr upt (msb first) data a data b b d7 b d6 5.2.1 data t r ansmission timing char t (spi master mode) figure 19. data reception write dummy data to the transmit data b uf fer . writing to the transmit data b uf fer creates the trigger for recep- tion as well as transmission start. writing actual transmit data enables simultaneous transmission and reception. this starts the spi clock output from the us_sckx pin. the data is recei v ed in sequence in the shift re gister at the spi clock edge (see figure 19.4.5.1). the recei v ed data is loaded into the recei v e data b uf fer once the 8 bits of data are recei v ed in the shift re gister . the recei v ed data in the b uf fer can be read from rd[7:0]/usi_rdx re gister . the spi controller includes tw o status flags for transfer control: srdif/usi_sifx re gister and ssif/usi_sifx re gister . the srdif flag indicates the recei v e data b uf fer status. this flag is set to 1 when the data recei v ed in the shift re gister is loaded into the recei v e data b uf fer , indicating that the recei v ed data can be read out. srdif is an interrupt flag. an interrupt request can be generated when this flag is set to 1 (see section 19.7). read the re- cei v ed data from the recei v e data b uf fer using this interrupt. the recei v e data b uf fer s ize is 1 byte, therefore the recei v ed data must be read before the subsequent data reception has completed. furthermore, srdif must be reset by writing 1. if the subsequent recei v e data is written to the recei v e data b uf fer when srdif is 1, an o v er - run error occurs. the ssif flag indicates the shift re gister status. this flag switches to 1 at the be ginning of data reception and re v erts to 0 once t he data is recei v ed. read this flag to check whether the spi controller is operating or at stand- by . 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-9 spi_sc k td[7:0] us_sckx pin (scpol = 0, scpha = 1) us_sckx pin (scpol = 0, scpha = 0) us_sdix pin shift register rd[7:0] ssif srdif interr upt a d7 a d6 a d1 a d0 b d1 b d0 wr ite wr ite wr ite receiv e b uff er full interr upt receiv e b uff er full interr upt ov err un error interr upt (when data b has not been read) (msb first) dumm y dumm y data a data b data c dumm y b d7 b d6 c d1 c d0 c d7 c d6 read reset by wr iting 1 5.2.2 data receiving timing char t (spi master mode) figure 19. sla ve select signal if a sla v e select output is required in spi master mode, use a general-purpose i/o port and control its output with softw are. data t ransf er in i 19.5.3 2 c mode contr ol method in i 2 c master mode data transfer in i 2 c master mode is controlled using imtgmod[2:0]/usi_imtgx re gister and imtg/usi_ imtgx re gister . select an i 2 c master operation using imtgmod[2:0] and write 1 to imtg as the trigger . the i 2 c controller controls the i 2 c b us to generate the specif ied operating status. 5.3.1 t r igger list in i t ab le 19. 2 c master mode imtgmod[2:0] t rig g er 0x7 reser v ed 0x6 a ck/nak reception 0x5 nak tr ansmission 0x4 a ck tr ansmission 0x3 data reception 0x2 data tr ansmission 0x1 stop condition 0x0 star t condition (def ault: 0x0) writing 1 to imtg sets imbsy/usi_imifx re gister to 1 indicating that the i 2 c controller is b usy (operating). when the specif ied operation has f inished, imbsy is reset to 0. at the same time, the interrupt flag (imif/usi_ imifx re gister) is also set to 1. after an interrupt occurs, read the status bits (imst a[2:0]/usi_imifx re gister) to check the operation f inished. then clear imif by writing 1. imst a[2:0] will be automatically cleared to 0x0. 5.3.2 i t ab le 19. 2 c master status bits imst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been gener ated. 0x0 star t condition has been gener ated. (def ault: 0x0) 19 universal serial interf a ce (usi) [s1c17564] 19-10 seiko epson corporation s1c17554/564 t echnical m anual data transmission in i 2 c master mode the follo wing describes the data transmission procedure in i 2 c master mode. st ar t end generate star t condition generate stop condition send sla ve address and transf er direction bit ack receiv ed? ye s ack receiv ed? ye s no finished? ye s send data error handling no no 5.3.1 i figure 19. 2 c master data t r ansmission flo w char t t16f output cloc k us_sckx pin (output) us_sckx pin (input) us_sdix pin (output) us_sdix pin (input) imtgmod[2:0] imtg (wr ite) imbsy imst a[2:0] td[7:0] imif interr upt a6 address 0x0 0x2 0x2 0x6 0x5 0x2 0x6 tr ansf er data 2 0x2 a5 a4 a3 a2 a1 a0 d7 d6 r/w = 0 ac k star t condition sla ve address transmission data transmission star t condition generated tr ansmit b uff er empty a ck receiv ed tr ansmit b uff er empty * * * * reset by wr iting 1 0x0 tr ansf er data 1 (1) star t condition data tr ansmission 0x6 0x2 tr ansf er data (n -1) 0x2 0x5 0x6 0x2 0x5 0x1 0x1 tr ansf er data n a ck receiv ed tr ansmit b uff er empty stop condition generated ac k receiv ed * * * * reset by wr iting 1 d5 d4 d3 d2 d1 d0 d7 d6 d0 ac k ac k t16f output cloc k us_sckx pin (output) us_sckx pin (input) us_sdix pin (output) us_sdix pin (input) imtgmod[2:0] imtg (wr ite) imbsy imst a[2:0] td[7:0] imif interr upt data transmission data transmission stop condition (2) data tr ansmission stop condition 5.3.2 i figure 19. 2 c master data t r ansmission timing char t 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-11 (1) generating start condition i 2 c data transfer starts when the i 2 c master de vice generates a start condition. the start condition applies when the scl line is maintained at high and the sd a line is pulled do wn to lo w . t o generate a start condition in this i 2 c master , set imtgmod[2:0] to 0x0 (def ault) and write 1 to imtg. sda (us_sdix) scl (us_sckx) start condition 5.3.3 star t condition figure 19. imbsy is set to 1 while a start condition is being generated. when the start condition is generated, imbsy is reset to 0 and imst a[2:0] is set to 0x0. the i 2 c b us is b usy from this point on. note: other oper ations cannot be star ted bef ore a star t condition is gener ated. (2) sending sla v e address and transfer direction bit after a start condition has been generated, send the address of the sla v e de vice to be communicated and a transfer direction bit. i 2 c sla v e addresses are either 7-bit or 10-bit. this module uses an 8-bit transfer data b uf fer to send the sla v e address and transfer direction bit, enabling single transfers in 7-bit address mode. in 10-bit mode, data is sent twice under softw are control. figure 19.5.3.4 sho ws the conf iguration of the ad- dress data. slave address 7-bit address transfer direction 0: master slave (transmission) 1: slave master (reception) a6 a5 d7 d6 a4 d5 a3 d4 a2 d3 a1 d2 a0 d1 r/w d0 8 low order slave address bits a7 a6 d7 d6 a5 d5 a4 d4 a3 d3 a2 d2 a1 d1 a0 d0 2 high order slave address bits 10-bit address transfer direction 0: master slave (transmission) 1: slave master (reception) 1 first transmit data second transmit data 1 d7 d6 1 d5 1 d4 0 d3 a9 d2 a8 d1 r/w d0 5.3.4 t r ansmit data specifying sla v e address and t r ansf er direction figure 19. the transfer direction bit indicates the data transfer direction after the sla v e address has been sent. set this bit to 0 when sending data from the master to the sla v e. t o send a sla v e address, set the address with the transfer direction bit to the transmit data b uf fer (td[7:0]/ usi_tdx re gister). then set imtgmod[2:0] to 0x2 and write 1 to imtg. t o send a 10-bit address, e x ecute this procedure twice as sho wn in figure 19.5.3.4. writing 1 to imtg sets imbsy to 1. when data in the transmit data b uf fer is sent to the transmit shift re g- ister , imbsy re v erts to 0 and imst a[2:0] is set to 0x2. conf irm that the sla v e address (each byte) has been sent by reading imbsy or using an interrupt. after a sla v e address has b een sent, the selected sla v e de vice sends back an a ck by pulling do wn the scl line to lo w . if the scl line maintains high, it is re g arded as a n ak. in this case, the i 2 c controller cannot communicate with the sla v e de vice specif ied. 19 universal serial interf a ce (usi) [s1c17564] 19-12 seiko epson corporation s1c17554/564 t echnical m anual sda (us_sdix) (output) sda (us_sdix) (input) scl (us_sckx) start condition 12 89 d7 d6 d0 ack nak 5.3.5 a ck and nak figure 19. it is necessary to check that an a ck has been recei v ed before sending data. t o do this, set imtgmod[2:0] to 0x6 and write 1 to imtg after the sla v e address has been sent. imbsy is set to 1 while an a ck/n ak is being detected and it re v erts to 0 when the detection has com- p l e t e d . r e c e i v i n g a n a c k s e t s i m s t a [2:0] t o 0x5; r e c e i v i n g a n a k s e t s i t t o 0x6. c h e c k i m s t a [2:0] af ter conf irming imbsy or using an interrupt. when an a ck has been recei v ed, perform data transmission. when a n ak has been recei v ed, perform an error handling. (3) data transmission the data transmission procedure is the same as that of the sla v e address transmission. 1. write an 8-bit transmit data to the transmit data b uf fer (td[7:0]). 2. set imtgmod[2:0] to 0x2 and imtg to 1. this trigger transfe rs the b uf fer data to the transmit shift re gister to start transmission. the module starts clock output from the us_sckx pin. the data in the shift re gister is shifted in sequence with the clock and sent from the us_sdox pin. writing 1 to imtg sets imbsy to 1. when data in the transmit data b uf fer is sent to the transmit shift re g- ister , imbsy re v erts to 0 and imst a[2:0] is set to 0x2 (transmit da ta b uf fer empty). an interrupt request can be generated at this point. write subsequent data to the transmit data b uf fer to start the follo wing trans- mission using this interrupt. ho we v er , as in the case of the sla v e address transmission, check that the sla v e de vice has sent back an a ck (by setting imtgmod[2:0] to 0x6 and imtg to 1) before starting the follo wing 8-bit data transmission. repeat an 8-bit data transmission and a ck recei ving check for the required number of times. (4) generating stop condition t o end i 2 c communication after all data has been sent, the i 2 c master must generate a stop condition. the stop condition applies when the scl line is maintained at high and the sd a line is pulled up from lo w to high. t o generate a stop condition in this i 2 c master , set imtgmod[2:0] to 0 x1 and write 1 to imtg. stop condition sda (us_sdix) scl (us_sckx) 5.3.6 stop condition figure 19. imbsy is set to 1 while a stop condition is being generated. when the stop condition is generated, imbsy is reset to 0 and imst a[2:0] is set to 0x1. read imbsy or use an interrupt to check that a stop condition has been generated. the i 2 c b us subsequently switches to free state. (5) generating repeated start condition t o mak e it possible to continue with a dif ferent data transfer after a data transmission has completed, the i 2 c master can omit stop condition generation and generate a repeated start condition. t o generate a re- peated start condition, perform a start condition generation procedure described in step (1). sla v e address transmission is subsequently possible with the i 2 c b us remaining in the b usy state. sda (us_sdix) scl (us_sckx) repeated start condition 5.3.7 repeated star t condition figure 19. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-13 data reception in i 2 c master mode the follo wing describes the data recei ving procedure in i 2 c master mode. st ar t end generate star t condition generate stop condition send sla ve address and transf er direction bit ack receiv ed? ye s no finished? ye s receiv e data send ac k error handling no 5.3.8 i figure 19. 2 c master data receiving flo w char t] t16f output cloc k us_sckx pin (output) us_sckx pin (input) us_sdix pin (output) us_sdix pin (input) imtgmod[2:0] imtg (wr ite) imbsy imst a[2:0] rd[7:0] imif interr upt a6 0x0 0x2 0x6 0x5 0x3 0x2 a5 a4 a3 a2 a1 a0 d7 d6 r/w = 1 ac k star t condition sla ve address transmission data reception star t condition generated tr ansmit b uff er empty a ck receiv ed * * * reset by wr iting 1 0x0 (1) star t condition data reception 0x3 0x5 0x4 0x5 0x3 receiv ed data (n - 1) 0x3 0x5 0x3 0x4 0x1 0x1 receiv ed data n receiv e b uff er full ac k sent stop condition generated receiv e b uff er full nak sent * * * * * reset by wr iting 1 d5 d4 d3 d2 d1 d0 d7 d6 d0 ac k t16f output cloc k us_sckx pin (output) us_sckx pin (input) us_sdix pin (output) us_sdix pin (input) imtgmod[2:0] imtg (wr ite) imbsy imst a[2:0] rd[7:0] imif interr upt data reception data reception stop condition nak (2) data reception stop condition 5.3.9 i figure 19. 2 c master data receiving timing char t note: the timing char t abo v e sho ws a basic tr ansf er oper ation that does not include an actual i 2 c tr ans- f er procedure . see receiving control b yte in i 2 c sla v e mode in 19.9 precautions . 19 universal serial interf a ce (usi) [s1c17564] 19-14 seiko epson corporation s1c17554/564 t echnical m anual (1) generating start condition the procedure is the same as that of data transmission in i 2 c master mode. (2) sending sla v e address and transfer direction bit the procedure is the same as that of data transmission in i 2 c master mode. ho we v er , send the sla v e address with the transfer direction bit set to 1. then check that the sla v e de vice sends back an a ck. (3) data reception t o start data receptio n, set imtgmod[2:0] to 0x3 and write 1 to imtg. this trigger starts outputting 8 clocks from the us_sckx pin. the us_sdox pin status is sampled in sync w i t h t h e c l o c k a n d l o a d e d t o t h e s h i f t r e g i s t e r . t h e r e c e i v e d d a t a i s l o a d e d t o t h e r e c e i v e d a t a b u f f e r ( r d [ 7 : 0 ] / usi_rdx re gister) once the 8-bit data has been recei v ed in the shift re gister . writing 1 to imtg sets imbsy to 1. when the recei v ed dat a is loaded to the recei v e data b uf fer , imbsy re v erts to 0 and imst a[2:0] is set to 0x3 (recei v e data b uf fer full). an interrupt request can be generated at this point. read the recei v ed data from the recei v e data b uf fer using this interrupt. it is necessary to send back an a ck or n ak to the sla v e de vice after an 8-bit data has been recei v ed. t o send back an a ck, set imtgmod[2:0] to 0x4 and write 1 to imtg. t o send back a n ak, set imtg- mod[2:0] to 0x5 and write 1 to imtg. imbsy is set to 1 while an a ck/n ak is being sent and it re v erts to 0 when the transmission has complet- ed. an interrupt request can be generated at this point. when an a ck or n ak has been sent, imst a[2:0] is set to 0x4. repeat an 8-bit data reception and a ck (n ak) transmission for the required number of times. (4) generati ng stop condition the procedure is the same as that of data transmission in i 2 c master mode. (5) generating repeated start condition the procedure is the same as that of data transmission in i 2 c master mode. cloc k stretc h function during transmitting/recei ving data, the sla v e de vice may issue a w ait request to the master de vice by pulling do wn the scl line to lo w until the sla v e de vice becomes read y to transmit/recei v e the subsequent data. the master de vice enters a standby state until the w ait request is canceled (the scl line goes high). this i 2 c controller supports this clock stretch function. when a clock stretch condition is detected after a sla v e address or data has been sent/recei v ed, this module enters a w aiting status and it does not start operating e v en if it accepts a trigger fo r data transfer until the clock stretch status is canceled. imbsy is maintained at 1 until the triggered operation has completed including a w aiting status. us_sckx pin (master output) us_sckx pin (sla ve output) cloc k stretch cloc k stretch 5.3.10 cloc k stretch figure 19. contr ol method in i 2 c sla ve mode data transfer in i 2 c sla v e mode is controlled using istgmod[2:0]/usi_istgx re gister and istg/usi_istgx re gister . select an i 2 c sla v e operation using istgmod[2:0] and write 1 to istg as the trigger . the i 2 c con- troller controls the i 2 c b us to generate the specif ied operating status. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-15 5.3.3 t r igger list in i t ab le 19. 2 c sla v e mode istgmod[2:0] t rig g er 0x7 reser v ed 0x6 a ck/nak reception 0x5 nak tr ansmission 0x4 a ck tr ansmission 0x3 data reception 0x2 data tr ansmission 0x1 reser v ed 0x0 w ait f or star t condition (def ault: 0x0) writing 1 to istg sets isbsy/usi_isifx re gister to 1 indicating that the i 2 c controller is b usy (operating). when the specif ied operation has f inished, isbsy is reset to 0. at the same time, the interrupt flag (isif/usi_ is ifx re gister) is also set to 1. after an interrupt occurs, read the status bits (isst a[2:0]/usi_isifx re gister) to check the operation f inished. 5.3.4 i t ab le 19. 2 c sla v e status bits isst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been detected. 0x0 star t condition has been detected. (def ault: 0x0) data transmission in i 2 c sla ve mode the follo wing describes the data transmission procedure in i 2 c sla v e mode. st ar t end star t condition? receiv e sla ve address and transf er direction bit address matched? ye s ack receiv ed? ye s no no ye s send ac k send data no no ye s error handling stop condition? 5.3.11 i figure 19. 2 c sla v e data t r ansmission flo w char t 19 universal serial interf a ce (usi) [s1c17564] 19-16 seiko epson corporation s1c17554/564 t echnical m anual us_sckx pin (input) us_sckx pin (output) us_sdix pin (input) us_sdix pin (output) istgmod[2:0] istg (wr ite) isbsy isst a[2:0] td[7:0] isif interr upt a6 tr ansf er data 1 0x0 0x3 0x2 0x4 0x4 0x2 0x6 tr ansf er data 2 0x3 a5 a4 a3 a2 a1 a0 r/w = 1 ac k star t condition sla ve address reception data transmission star t condition detected ac k sent receiv e b uff er full tr ansmit b uff er empty * reset by wr iting 1 * * * 0x0 d7 d6 (1) star t condition data tr ansmission 0x6 0x2 tr ansf er data (n -1) 0x2 0x5 0x6 0x2 0x6 0x0 0x1 tr ansf er data n a ck receiv ed tr ansmit b uff er empty stop condition detected nak receiv ed * * * * reset by wr iting 1 d5 d4 d3 d2 d1 d0 d7 d6 d0 ac k us_sckx pin (input) us_sckx pin (output) us_sdix pin (input) us_sdix pin (output) istgmod[2:0] istg (wr ite) isbsy isst a[2:0] td[7:0] isif interr upt data transmission stop condition nak (2) data tr ansmission stop condition 5.3.12 i figure 19. 2 c sla v e data t r ansmission timing char t note: the timing char t abo v e sho ws a basic tr ansf er oper ation that does not include an actual i 2 c tr ans- f er procedure . see receiving control b yte in i 2 c sla v e mode in 19.9 precautions . (1) w aiting for start condition i 2 c data transfer starts when the i 2 c master de vice generates a start condition (see fi gure 19.5.3.3). first enable this i 2 c sla v e to detect a start condition by setting istgmod[2:0] to 0x0 (def ault) and writing 1 to istg. the i 2 c controller starts detecting a start condition and sets isbsy to 1. isbsy is set to 1 while a start condition is being detected. isbsy re v erts to 0 and isst a[2:0] is set to 0x0 when the detection has completed. check if a start condition is generated by rea ding isbsy or using an interrupt. note: other oper ations cannot be star ted bef ore a star t condition is detected. (2) recei ving sla v e address and transfer direction data bit the i 2 c master sends the address of the sla v e de vice to be communicated and a transfer direction bit (see figure 19.5.3.4) after it has generated a start condition. set this i 2 c sla v e into recei ving status to recei v e the sla v e addr ess. t o start reception, set istgmod[2:0] to 0x3 and write 1 to istg. this trigger starts sampling clocks input from the us_sckx pin. when clocks are input, the i 2 c controller loads the us_sdox pin status to the shift re gister in sync with each clock. the recei v ed data is loaded to the recei v e data b uf fer (rd[7:0]/usi_rdx re gister) once the 8-bit data has been recei v ed in the shift re gis- ter . writ ing 1 to istg sets isbsy to 1. when the recei v ed data is loaded to the recei v e data b uf fer , isbsy re v erts to 0 and isst a[2:0] is set to 0x3 (recei v e data b uf fer full). an interrupt request can be generated at this point. read the recei v ed data from the recei v e data b uf fer using this interrupt. when a 7-bit address is used, the sla v e address and transfer direction bit can be obtained in one operati on. when a 10-bit address is used, sa v e the f irst data recei v ed in the recei v e data b uf fer into the memory and perform data reception ag ain to obtain the remaining address bits. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-17 check whether the recei v ed address is matched to this i 2 c sla v e address or not. when the y are matched, send back an a ck to the i 2 c master by setting istgmod[2:0] to 0x4 and write 1 to istg. isbsy is set to 1 while an a ck is being sent and it re v erts to 0 when the transmission has completed. an interrupt request can be generated at this point. when an a ck has been sent, isst a[2:0] is set to 0x4. i f the recei v ed address is not for this i 2 c sla v e, abort data reception and return to step (1) to w ait the subse- quent start condition. (3) data transmission wh en the tr an sf er dir ec tion bit r ec ei v ed wi th t he sla v e a ddr es s i n st ep (2 ) i s 1 , s ta rt dat a t ra nsm iss ion by the follo wing procedure: 1. write an 8-bit transmit data to the transmit data b uf fer (td[7:0]). 2. set istgmod[2:0] to 0x2 and istg to 1. this trigger transfers the b uf fer data to the transmit shift re gister to start transmission. when clocks are in- put from the us_sckx pin, the data in the shift re gister is shifted in sequence with the clock and sent from the us_sdox pin. writing 1 to istg sets isbsy to 1. when data in the transmit data b uf fer is sent to the transmit shift re gis- ter , isbsy re v erts to 0 and isst a[2:0] is set to 0x2 (transmit data b uf fer empty). an interrupt request can be generated at this point. write subsequent data to the transmit data b uf fer to start the follo wing transmis- sion using this interrupt. ho we v er , check that the master de vice has sent back an a ck or n ak (by setting istgmod[2:0] to 0x6 and istg to 1) before starting the follo wing 8-bit data transmission. isbsy is set to 1 while an a ck/n ak is being detected and it re v erts to 0 when the detection has complet- ed. recei ving an a ck sets isst a[2:0] to 0x5; recei ving a n ak sets it to 0x6. check isst a[2:0] after con- f irming isbsy or using an interrupt. when an a ck has been recei v ed, perform data transmission. when a n ak has been recei v ed, perform the appropriate handling. (4) when a stop condition is recei v ed if the isst a[2:0] v alue read d uring data transmission is 0x1, the i 2 c master de vice has generated a stop condition (see figure 19.5.3.6). in this case, abort data transmission. data reception in i 2 c sla ve mode the follo wing describes the data recei ving procedure in i 2 c sla v e mode. st ar t end no receiv e data send ac k star t condition? stop condition? receiv e sla ve address and transf er direction bit address matched? ye s ye s send ac k no no ye s 5.3.13 i figure 19. 2 c sla v e data receiving flo w char t 19 universal serial interf a ce (usi) [s1c17564] 19-18 seiko epson corporation s1c17554/564 t echnical m anual us_sckx pin (input) us_sckx pin (output) us_sdix pin (input) us_sdix pin (output) istgmod[2:0] istg (wr ite) isbsy isst a[2:0] rd[7:0] isif interr upt a6 0x0 0x3 0x4 0x4 0x3 0x3 a5 a4 a3 a2 a1 a0 r/w = 0 ac k star t condition sla ve address reception data reception star t condition detected ac k sent receiv e b uff er full * reset by wr iting 1 ** 0x0 d7 d6 (1) star t condition data reception 0x3 0x5 0x4 0x5 0x3 receiv ed data (n - 1) 0x3 0x5 0x3 0x4 0x1 0x1 receiv ed data n receiv e b uff er full ac k sent stop condition detected receiv e b uff er full nak sent * * * * * reset by wr iting 1 us_sckx pin (input) us_sckx pin (output) us_sdix pin (input) us_sdix pin (output) istgmod[2:0] istg (wr ite) isbsy isst a[2:0] rd[7:0] isif interr upt data reception stop condition d5 d4 d3 d2 d1 d0 d7 d6 d0 ac k ac k (2) data reception stop condition 5.3.14 i figure 19. 2 c sla v e data receiving timing char t note: the timing char t abo v e sho ws a basic tr ansf er oper ation that does not include an actual i 2 c tr ans- f er procedure . see receiving control b yte in i 2 c sla v e mode in 19.9 precautions . (1) w aiting for start condition the procedure is the same as that of data transmission in i 2 c sla v e mode. (2) recei ving sla v e address and transfer direction data bit the procedure is the same as that of data transmission in i 2 c sla v e mode. (3) data reception when the transfer direction bit recei v ed with the sla v e address in step (2) is 0, start data reception by set- ting istgmod[2:0] to 0x3 and writing 1 to istg. when clocks are input, the i 2 c controller loads the us_sdox pin status to the shift re gister in sync with e a c h c l o c k . t h e r e c e i v e d d a t a i s l o a d e d t o t h e r e c e i v e d a t a b u f f e r ( r d [ 7 : 0 ] / u s i _ r d x r e g i s t e r ) o n c e t h e 8 - b i t data has been recei v ed in the shift re gister . writing 1 to istg sets isbsy to 1. when the recei v ed data is loaded to the recei v e data b uf fer , isbsy re v erts to 0 and isst a[2:0] is set to 0x3 (recei v e data b uf fer full). an interrupt request can be generated at this point. read the recei v ed data f rom the recei v e data b uf fer using this interrupt. it is necessary to send back an a ck or n ak to the master de vice after an 8-bit data has been recei v ed. t o s e n d b a c k a n a c k , s e t i s t g m o d [ 2 : 0 ] t o 0 x 4 a n d w r i t e 1 t o i s t g . t o s e n d b a c k a n a k , s e t istgmod[2:0] to 0x5 and write 1 to istg. isbsy is set to 1 while an a ck/n ak is being sent and it re v erts to 0 when the transmission has completed. an interru pt request can be generated at this point. when an a ck or n ak has been sent, isst a[2:0] is set to 0x4. repeat an 8-bit data reception and a ck (n ak) transmission for the required number of times. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-19 (4) when a stop condition is recei v ed if the isst a[2:0] v alue read during data reception is 0x1, the i 2 c master de vice has generated a stop condi- tion (see figure 19.5.3.6). in this case, abort data reception. cloc k stretc h function while data is being sent/recei v ed, this i 2 c sla v e generates a clock stretch status by pulling do wn the scl line to lo w to mak e a w ait request to the master de vice afte r an a ck is sent/recei v ed until the follo wing data transfer is started. receive err or s 19.6 in u ar t mode, three dif ferent recei v e errors (o v errun error , framing error , and parity error) may be detected while recei ving data. in spi master and i 2 c modes, o v errun errors may be detected while recei ving data. since recei v e errors are interrupt causes, the y can be processed by generating interrupts. f or m ore information on interrupt control, see section 19.7. overrun err or (all interface modes) if data is recei v ed before the pre viously recei v ed data in the recei v e data b uf fer has not been read, the recei v e data b uf fer is o v erwritten and an o v errun error occurs. when an o v errun error occurs, the o v errun error flag for the current interf ace mode is set to 1. ov errun error flags: uoeif/usi_uifx re gist er (u ar t mode) seif/usi_sifx re gister (spi master mode) imeif/usi_imifx re gister (i 2 c master mode) iseif/usi_isifx re gister (i 2 c sla v e mode) the recei ving operation continues e v en if this error occurs. the o v errun error flag is reset to 0 by writing 1. framing err or (u ar t mode onl y) if the stop bit is recei v ed as 0 in u ar t mode, the u ar t controller determines loss of sync and a framing error occurs. if the stop bit is conf igured to tw o bits, only the f irst bit is check ed. the framing error flag (useif/usi_uifx re gister) is set to 1 if this error occurs. the recei v ed data is still trans- ferred to the recei v e data b uf fer if this error occurs and the recei ving operation continues, b ut the data cannot be guaranteed, e v en if no framing error occurs for subsequent data recei ving. the framin g error flag is reset to 0 by writing 1. p arity err or (u ar t mode onl y) if upren/usi_ucfgx re gister has been set to 1 (parity enabled), data recei v ed is check ed for parity in u ar t mode. data recei v ed in the shift re gister is check ed for parity when sent to the recei v e data b uf fer . the match- ing is check ed ag ainst the upmd/usi_ucfgx re gister setting (odd or e v en parity). if the result is a non-match, a parity error is issued, and the parity error flag (upeif/usi_uifx re gister) is set to 1. ev en if this error occurs, the data recei v ed is sent to the recei v e data b uf fer , and the recei ving operation continues. ho we v er , the recei v ed data cannot be guaranteed if a parity error occurs. the upeif flag is reset to 0 by writing 1. usi interrupts 19.7 this section describes the usi interrupts generated in each interf ace mode. f or more information on interrupt processing, see the interrupt controller (itc) chapter . each usi channel outputs one interrupt signal (tw o signals for tw o channels) shared by the all interrupt causes to the interrupt controller (itc). inspect the interrupt flags a v ailable in each mode to determine the interrupt cause oc- curred. 19 universal serial interf a ce (usi) [s1c17564] 19-20 seiko epson corporation s1c17554/564 t echnical m anual interrupts in u ar t mode 19.7.1 the u ar t mode includes a function for generating the follo wing three dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? recei v e b uf fer full interrupt ? recei v e error interrupt t ransmit b uff er empty interrupt t o use this interrupt, set utdie/usi_uiex re gister to 1. if utdie is set to 0 (def ault), interrupt requests for this cause will not be sent to the it c. when transmit data written to the transmit data b uf fer is transferred to the shift re gister , the usi module sets utdif/usi_uifx re gister to 1, indicating that the transmit data b uf fer is empty . if transmit b uf fer empty inter - rupts are enabled (utdie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the utdif flag in the interrupt handler routine to determine w h e t h e r t h e u s i ( u a r t m o d e ) i n t e r r u p t i s a t t r i b u t a b l e t o a t r a n s m i t b u f f e r e m p t y . i f u t d i f i s 1 , t h e n e x t t r a n s - mit data can be written to the transmit data b uf fer by the interrupt handler routine. receive b uff er full interrupt t o use this interrupt, set urdie/usi_uiex re gister to 1. if urdie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if a recei v ed data is loaded into the recei v e data b uf fer , the usi module sets urdif/usi_uifx re gister to 1. i f r e c e i v e b u f f e r f u l l i n t e r r u p t s a r e e n a b l e d ( u r d i e = 1) , a n i n t e r r u p t r e q u e s t i s s e n t s i m u l t a n e o u s l y t o t h e itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the urdif flag in the interrupt handler routine to determine whether th e usi (u ar t mode) interrupt is attrib utable to a recei v e b uf fer full. i f u r d i f i s 1, t h e r e c e i v e d d a t a c a n b e r e a d f r o m t h e r e c e i v e d a t a b u f f e r b y t h e i n t e r r u p t h a n d l e r r o u t i n e . ho we v er , be sure to check whether a recei v e error has occurred or not. receive err or interrupt t o use this interrupt, set ueie/usi_uiex re gister to 1. if ueie is set to 0 (def ault), interrupt requests for this cause will no t be sent to the itc. the usi module sets an error flag (upeif/usi_uifx re gister , useif/usi_uifx re gister , or uoeif/usi_uifx re gister) to 1 if a parity error , framing error , or o v errun error is detected when recei ving data. if recei v e error interrupts are enabled (ueie = 1), an interrupt request is sent simultaneously to the itc. if other interrupt con- ditions are satisf ied, an interrupt occurs. y ou can inspect the upeif , useif , and uoeif flags in the interrupt handler routine to determine whether the usi (u ar t mode) interrupt w as caused by a recei v e error . if an y of the error flags has the v alue 1, the interrupt handler routine will proceed with error reco v ery . interrupts in spi master mode 19.7.2 the spi master mode include a function for generating the follo wing three dif ferent types of interrupts. ? t ransmit b uf fer empty interrupt ? recei v e b uf fer full interrupt ? recei v e error interrupt t ransmit b uff er empty interrupt t o use this interrupt, set stdie/usi_siex re gister to 1. if stdie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when transmit data written to the transmit data b uf fer is transferred to the shift re gister , the usi module sets std if/usi_sifx re gister to 1, indicating that the transmit data b uf fer is empty . if transmit b uf fer empty inter - rupts are enabled (stdie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the stdif flag in the interrupt handler routine to determine whether the usi (spi master mode) interrupt is attrib utable to a tra nsmit b uf fer empty . if stdif is 1, the ne xt transmit data can be written to the transmit data b uf fer by the interrupt handler routine. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-21 receive b uff er full interrupt t o use this interrupt, set srdie/usi_siex re gister to 1. if srdie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if a recei v ed data is loaded into the recei v e data b uf fer , the usi module sets srdif/usi_sifx re gister to 1. if r e c e i v e b u f f e r f u l l i n t e r r u p t s a r e e n a b l e d ( s r d i e = 1 ) , a n i n t e r r u p t r e q u e s t i s s e n t s i m u l t a n e o u s l y t o t h e i t c . a n interrupt occurs if other interrupt conditions are met. y ou can inspect the srdif flag in the interrupt handler routine to determine whether the usi (spi master mode) interrupt is attrib utable to a recei v e b uf fer full. if sr- dif is 1, the recei v ed data can be read from the recei v e data b uf fer by the interrupt handler routine. ho we v er , be sure to check whether a recei v e error has occurred or not. receive err or interrupt t o use this interrupt, set seie/usi_siex re gister to 1. if seie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. the usi module sets seif/usi_sifx re gister to 1 if an o v errun error is detected when recei ving data. if recei v e error interrupts are enabled (seie = 1), an interrupt request is sent simultaneously to the itc. an interru pt oc- curs if other interrupt conditions are met. y ou can inspect the seif flags in the interrupt handler routine to de- termine whether the usi (spi master mode) interrupt w as caused by a recei v e error . if seif is 1, the interrupt handler routine will proceed with error reco v ery . interrupts in i 19.7.3 2 c master mode the i 2 c master mode includes a function for generating the follo wing tw o dif ferent types of interrupts. ? operation completion interrupt ? recei v e error interrupt operation completion interrupt t o use this interrupt, set imie/usi_imiex re gister to 1. if imie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when the operation that initiated by a softw are trigger has completed, the usi module sets imif/usi_imifx re gister to 1. if operation complet ion interrupts are enabled (imie = 1), an interrupt request is sent simultane- ously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the imst a[2:0]/ usi_imifx re gister in the interrupt handler routine to determine the i 2 c operation/status that causes the inter - rupt. 7.3.1 i t ab le 19. 2 c master status bits imst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been gener ated. 0x0 star t condition has been gener ated. (def ault: 0x0) receive err or interrupt t o use this interrupt, set imeie/usi_imiex re gister to 1. if imeie is set to 0 (def ault), interrupt requests fo r this cause will not be sent to the itc. the usi module sets imeif/usi_imifx re gister to 1 if an o v errun error is detected when recei ving data. if recei v e error interrupts are enabled (imeie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the imeif flags in the interrupt handler routine to determine whether t he usi (i 2 c master mode) interrupt w as caused by a recei v e error . if imeif is 1, the interrupt handler routine will proceed with error reco v ery . 19 universal serial interf a ce (usi) [s1c17564] 19-22 seiko epson corporation s1c17554/564 t echnical m anual interrupts in i 19.7.4 2 c sla ve mode the i 2 c sla v e mode includes a function for generating the follo wing tw o dif ferent types of interrupts. ? operation completion interrupt ? recei v e error interrupt operation completion interrupt t o use this interrupt, set isie/usi_isiex re gister to 1. if isie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. w h e n t h e o p e r a t i o n t h a t i n i t i a t e d b y a s o f t w a r e t r i g g e r h a s c o m p l e t e d , t h e u s i m o d u l e s e t s i s i f / u s i _ i s i f x r e g - ister to 1. if operation completion interrupts are enabled (isie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect the isst a[2:0]/usi_isifx re gister in the interrupt handler routine to determine the i 2 c operation/status that c auses the interrupt. 7.4.1 i t ab le 19. 2 c sla v e status bits isst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been detected. 0x0 star t condition has been detected. (def ault: 0x0) receive err or interrupt t o use this interrupt, set iseie/usi_isiex re gister to 1. if iseie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. the usi module sets iseif/usi_isifx re gister to 1 if an o v errun error is detected when recei ving data. if re- cei v e error interrupts are enabled (iseie = 1), an interrupt request is sent simultaneously to the itc. an inter - rupt occurs if other interrupt conditions are met. y ou can inspect the iseif flags in the interrupt handler routine to determine whether t he usi (i 2 c sla v e mode) interrupt w as caused by a recei v e error . if iseif is 1, the inter - rupt handler routine will proceed with error reco v ery . contr ol register details 19.8 8.1 list of usi registers t ab le 19. ad dress register name function 0x50c0 usi_gcfg0 usi ch.0 global configur ation register sets interf ace and msb/lsb mode . 0x50c1 usi_td0 usi ch.0 t r ansmit data buff er register t r ansmit data b uff er 0x50c2 usi_rd0 usi ch.0 receiv e data buff er register receiv e data b uff er 0x50c3 usi_ucfg0 usi ch.0 u ar t mode configur ation register sets u ar t tr ansf er conditions . 0x50c4 usi_uie0 usi ch.0 u ar t mode interr upt enab le register ena b les interr upts . 0x50c5 usi_uif0 usi ch.0 u ar t mode interr upt flag register indicates interr upt occurrence status . 0x50c6 usi_scfg0 usi ch.0 spi master mode configur ation register sets spi tr ansf er conditions . 0x50c7 usi_sie0 usi ch.0 spi master mode interr upt enab le register enab les interr upts . 0x50c8 usi_sif0 usi ch.0 spi master mode interr upt flag register indicates interr upt occurrence status . 0x50c9 usi_smsk0 u si ch.0 spi master mode receiv e data mask register sets receiv e data mask. 0x50ca usi_imtg0 usi ch.0 i 2 c master mode t r igger register star ts i 2 c master oper ations . 0x50cb usi_imie0 usi ch.0 i 2 c master mode interr upt enab le register enab les interr upts . 0x50cc usi_imif0 usi ch.0 i 2 c master mode interr upt flag register indicates interr upt occurrence status . 0x50cd usi_istg0 usi ch.0 i 2 c sla v e mode t r igger register st ar ts i 2 c sla v e oper ations . 0x50ce usi_isie0 usi ch.0 i 2 c sla v e mode interr upt enab le register enab les interr upts . 0x50cf usi_isif0 usi ch.0 i 2 c sla v e mode interr upt flag register indicates interr upt occurrence status . 0x50e0 usi_gcfg1 usi ch.1 global configur ation register sets interf ace and msb/lsb mode . 0x50e1 usi_td1 usi ch.1 t r ansmit data buff er register t r ansmit data b uff er 0x50e2 usi_rd1 usi ch.1 receiv e data buff er register receiv e data b uff er 0x50e3 usi_ucfg1 usi ch.1 u ar t mode configur ation register sets u ar t tr ansf er conditions . 0x50e4 usi_uie1 usi ch.1 u ar t mode interr upt enab le register enab les interr upts . 0x50e5 usi_uif1 usi ch.1 u ar t mode interr upt flag register indicates interr upt occurrence status . 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-23 0x50e6 usi_scfg1 usi ch.1 spi master mode configur ation register sets spi tr ansf er conditions . 0x50e7 usi_sie1 usi ch.1 spi master mode interr upt enab le register enab les interr upts . 0x50e8 usi_sif1 usi ch.1 spi master mode interr upt flag register indicates interr upt occurrence status . 0x50e9 usi_smsk1 usi ch.1 spi master mode receiv e data mask register sets receiv e data mask. 0x50ea usi_imtg1 usi ch.1 i 2 c master mo de t r igger register star ts i 2 c master oper ations . 0x50eb usi_imie1 usi ch.1 i 2 c master mode interr upt enab le register enab les interr upts . 0x50ec usi_imif1 usi ch.1 i 2 c master mode interr upt flag register indicates interr upt occurrence status . 0x50ed usi_istg1 usi ch.1 i 2 c sla v e mode t r igger register star ts i 2 c sla v e oper ations . 0x50ee usi_isie1 usi ch.1 i 2 c sla v e mode interr upt enab le register enab les interr upts . 0 x50ef usi_isif1 usi ch.1 i 2 c sla v e mode interr upt flag register indicates interr upt occurrence status . the usi re gisters are described in detail belo w . these are 8-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. usi ch.x global configuration registers (usi_gcfgx) register name ad dress bit name function setting init. r/w remarks usi ch.x global configuration register (usi_gcfgx) 0x50c0 0x50e0 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 lsbfst msb/lsb first mode select 1 msb first 0 lsb first 0 r/w d2C0 usimod [2:0] interf ace mode configur ation usimod[2:0] i/f mode 0x0 r/w 0x7C0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed i 2 c sla v e i 2 c master reser v ed spi master u ar t softw are reset note: this register m ust be configured bef ore setting other usi registers . d[7:4] reserved d3 lsbfst: msb/lsb first mode select bit selects whether serial data will be transferred from the msb or lsb. 1 (r/w ): msb f irst 0 (r/w): lsb f irst (def ault) this setting af fects all interf ace modes. d[2:0] usimod[2:0]: interface mode configuration bits selects an interf ace mode. 8.2 interf ace mode selection t ab le 19. usimod[2:0] interface mode 0x7C0x6 reser v ed 0x5 i 2 c sla v e 0x4 i 2 c master 0x3 reser v ed 0x2 spi master 0x1 u ar t 0x0 softw are reset (def ault: 0x0) p e r f o r m s o f t w a r e r e s e t ( s e t u s i m o d [2:0] t o 0x0) a n d t h e n s e t t h e i n t e r f a c e m o d e b e f o r e c h a n g i n g other usi conf igurations. usi ch.x transmit data buffer registers (usi_tdx) register name ad dress bit name function setting init. r/w remarks usi ch.x transmit data buffer register (usi_tdx) 0x50c1 0x50e1 (8 bits) d7C0 td[7:0] usi tr ansmit data b uff er td7 = msb td0 = lsb 0x0 to 0xff 0x0 r/w d[7:0] td[7:0]: usi transmit data buffer bits sets transmit data to be written to the transmit data b uf fer . (def ault: 0x0) 19 universal serial interf a ce (usi) [s1c17564] 19-24 seiko epson corporation s1c17554/564 t echnical m anual in u ar t and spi master mode, transmission be gins immediately after writing data to this re gister . in i 2 c master/sla v e mode, transmission be gins by the softw are trigger for data transmission. the data written to this re gister is con v erted into serial data through the shift re gister and is output from the us_sdox pin with the bit set to 1 as high le v el and the bit set to 0 as lo w le v el. a transmit b uf fer empty interrupt can be generated when data written to this re gister has been trans- ferred to the shift re gister . the subsequent transmit data can then be written, e v en while data is being sent. usi ch.x receive data buffer registers (usi_rdx) register name ad dress bit name function setting init. r/w remarks usi ch.x receive data buffer register (usi_rdx) 0x50c2 0x50e2 (8 bits) d7C0 rd[7:0] usi receiv e data b uff er rd7 = msb rd0 = lsb 0x0 to 0xff 0x0 r d[7:0] rd[7:0]: usi receive data buffer bits contains the recei v ed data. (def ault: 0x0) serial data input from the us_sdix pin is con v erted to parallel, with the high le v el bit set to 1 and the lo w le v el bit set to 0, and then it is loaded to this re gister . a recei v e b uf fer full interrupt can be generated when the data recei v ed in the shift re gister has been loa ded to this re gister . data can then be read until subsequent data is recei v ed. if recei ving the subse- quent data is completed before the re gister has been read out, the ne w recei v ed data o v erwrites the con- tents. this re gister is read-only . usi ch.x uart mode configuration registers (usi_ucfgx) register name ad dress bit name function setting init. r/w remarks usi ch.x uart mode configuration register (usi_ucfgx) 0x50c3 0x50e3 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 uchln char acter length select 1 8 bits 0 7 bits 0 r/w d2 ustpb stop bit select 1 2 bits 0 1 bit 0 r/w d1 upmd p ar ity mode select 1 ev en 0 odd 0 r/w d0 upren p ar ity enab le 1 with par ity 0 no par ity 0 r/w note: this register is eff ectiv e only in u ar t mode . configure the usi channel to u ar t mode bef ore setting this register . d[7:4] reserved d3 uchln: character length select bit selects the serial transfer data length. 1 (r/w): 8 bits 0 (r/w): 7 bits (def ault) when 7-bit data length is selected, d7 in the transmit data b uf fer is ignored and d7 in the recei v e data b uf fer is al w ays set to 0. d2 ustpb: stop bit select bit selects the stop bit length. 1 (r/w): 2 bits 0 (r/w): 1 bit (def ault) writing 1 to ustpb selects 2 stop bits; writing 0 to it selects 1 bit. the start bit is f ix ed at 1 bit. d1 upmd: parity mode select bit selects the parity mode. 1 (r/w): ev en parity 0 (r/w): odd parity (def ault) p arit y checking and parity bit addition are enabled only when upren is set to 1. the upmd setting is disabled if upren is 0. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-25 d0 upren: parity enable bit enables the parity function. 1 (r/w): w ith parity 0 (r/w): no parity (def ault) upren is used to select whether recei v ed data parity checking is performed and whether a parity bit is added to transmit data. setting upren to 1 parity-checks the recei v ed data. a parity bit is automati- cally added to the transmit data. if upren is set to 0, no parity bit is check ed or added. usi ch.x uart mode interrupt enable registers (usi_uiex) register name ad dress bit name function setting init. r/w remarks usi ch.x uart mode interrupt enable register (usi_uiex) 0x50c4 0x50e4 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 ueie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 urdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 utdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w note: this register is eff ectiv e only in u ar t mode . configure the usi channel to u ar t mode bef ore this register can be used. d[7:3] reserved d2 ueie: receive error interrupt enable bit enables interrupt requests to the itc when a recei v e error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process recei v e errors using interrupts. d1 urdie: receive buffer full interrupt enable bit enables interrupt requests to the itc when recei v ed data is loaded to the recei v e data b uf fer . 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to read recei v ed data using interrupts. d0 utdie: transmit buffer empty interrupt enable bit enables interrupt requests to the itc when data written to the transmit data b uf fer is sent to the shift re gister (i.e. when data transmission be gins). 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to write data to the transmit data b uf fer using interrupts. usi ch.x uart mode interrupt flag registers (usi_uifx) register name ad dress bit name function setting init. r/w remarks usi ch.x uart mode interrupt flag register (usi_uifx) 0x50c5 0x50e5 (8 bits) d7 C reser v ed C C C 0 when being read. d6 urbsy receiv e b usy flag 1 busy 0 idle 0 r d5 utbsy t r ansmit b usy flag 1 busy 0 idle 0 r d4 upeif p ar ity error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d3 useif f r aming error flag 1 error 0 nor mal 0 r/w d2 uoeif ov err un error flag 1 error 0 nor mal 0 r/w d1 urdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 utdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w note: this register is eff ectiv e only in u ar t mode . configure the usi channel to u ar t mode bef ore this register can be used. d7 reserved d6 urbsy: receive busy flag bit indicates the recei v e shift re gister status. 1 (r): busy 0 (r): idle (def ault) 19 universal serial interf a ce (usi) [s1c17564] 19-26 seiko epson corporation s1c17554/564 t echnical m anual u r b s y i s s e t t o 1 w h e n t h e f i r s t s t a r t b i t i s d e t e c t e d ( w h e n d a t a r e c e p t i o n b e g i n s ) a n d i s r e s e t t o 0 w h e n the data recei v ed in the shift re gister is loaded into the recei v e data b uf fer . inspect urbsy to determine whether the recei ving circuit is operating or at standby . d5 utbsy: transmit busy flag bit indicates the transmit shift re gister status. 1 (r): busy 0 (r): idle (def ault) utbsy is set to 1 when transmit data is loaded from the transmit data b uf fer into the shift re gister and is reset to 0 when the data transfer is completed. inspect utbsy to determine whether the transmit cir - cuit is operating or at standby . d4 upeif: parity error flag bit indicates whether a parity error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored upeif is set to 1 when a parity error occurs. at the same time a rece i v e error interrupt request is sent to the itc if ueie/usi_uiex re gister is 1. p arity checking is enabled only when upren/usi_ucfgx r e g i s t e r i s s e t t o 1 a n d i s p e r f o r m e d w h e n r e c e i v e d d a t a i s t r a n s f e r r e d f r o m t h e s h i f t r e g i s t e r t o t h e recei v e data b uf fer . upeif is reset by writing 1. d3 useif: framing error flag bit indicates whether a framing error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): rese t to 0 0 (w): ignored useif is set to 1 when a framing error occurs. at the same time a recei v e error interrupt request is sent to the itc if ueie/usi_uiex re gister is 1. a framing error occurs when data is recei v ed with the stop bit set to 0. useif is reset by writing 1. d2 uoeif: overrun error flag bit indicates whether an o v errun error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w ): ignored uoeif is set to 1 when an o v errun error occurs. at the same time a recei v e error interrupt request is sent to the itc if ueie/usi_uiex re gister is 1. an o v errun error occurs when the pre vious recei v ed data in the recei v e data b uf fer before reading is o v erwritten with a ne w recei v ed data. uoeif is reset by writing 1. d1 urdif: receive buffer full flag bit indicates the recei v e data b uf fer status. 1 (r): data full 0 (r): no d ata (def ault) 1 (w): reset to 0 0 (w): ignored urdif is set to 1 when data recei v ed in the shift re gister is sent to the recei v e data b uf fer (when recei v- ing is completed), indicating that the data can be read. at the same time a recei v e b uf fer full interrupt request is sent to the itc if urdie/usi_uiex re gister is 1. urdif is reset by writing 1. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-27 d0 utdif: transmit data buffer empty flag bit indicates the transmit data b uf fer status. 1 (r): empty (def ault) 0 (r): data e xists 1 (w): reset to 0 0 (w): ignored utdif is set to 1 when the transmit data written to the transmit data b uf fer is transferred to the shift re gister (when transmission starts), indicating that the ne xt transmit data can be written to. at the same t i m e a t r a n s m i t b u f f e r e m p t y i n t e r r u p t r e q u e s t i s s e n t t o t h e i t c i f u t d i e / u s i _ u i e x r e g i s t e r i s 1. utdif is reset by writing 1. usi ch.x spi master mode configuration registers (usi_scfgx) register name ad dress bit name function setting init. r/w remarks usi ch.x spi master mode configuration register (usi_scfgx) 0x50c6 0x50e6 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 scmd command bit (f or 9-bit data) 1 high 0 lo w 0 r/w d4 schln char acter length select 1 9 bits 0 8 bits 0 r/w d3 scpha cloc k phase select 1 phase 1 0 phase 0 0 r/w d2 scpol cloc k polar ity select 1 activ e l 0 activ e h 0 r/w d1 smsken receiv e data mask enab le 1 enab le 0 disab le 0 r/w d0 sfstmod f ast mode select 1 f ast 0 nor mal 0 r/w note: this register is eff ectiv e only in spi master mode . configure the usi channel to spi mas ter mode bef ore this register can be used. d[7:6] reserved d5 scmd: command bit (for 9-bit data) sets the command bit v alue for 9-bit data (see schln belo w). 1 (r/w): high 0 (r/w): lo w (def ault) d4 schln: character length select bit selects the serial transfer data length. 1 (r/w): 9 bits 0 (r/w): 8 bits (def ault) in 9-bit mode, 8-bit data is pref ix ed with a command bit (1 bit). the command bit is used for control- ling the spi lcd controller connected to the usi. the command bit v alue to be transmitted can be specif ied using scmd. schln = 0, scmd = * schln = 1, scmd = 0 schln = 1, scmd = 1 command bit d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) d7 (d0) d6 (d1) d5 (d2) d4 (d3) d3 (d4) d2 (d5) d1 (d6) d0 (d7) 8.1 9-bit t r ansf er data f or mat in spi master mode figure 19. d3 scpha: clock phase select bit selects the spi clock phase. 1 (r/w): phase 1 0 (r/w): phase 0 (def ault) set the data transfer timing together with scpol. (see figure 19.8.2.) d2 scpol: clock polarity select bit selects the spi clock polarity . 1 (r/w): acti v e lo w 0 (r/w): acti v e high (def ault) set the data transfer timing together with scpha. (see figure 19.8.2.) 19 universal serial interf a ce (usi) [s1c17564] 19-28 seiko epson corporation s1c17554/564 t echnical m anual us_sckx (scpol = 1, scpha = 1) us_sckx (scpol = 1, scpha = 0) us_sckx (scpol = 0, scpha = 1) us_sckx (scpol = 0, scpha = 0) us_sdix/us_sdox fetching received data into shift register d7 (msb) d0 (lsb) 8.2 cloc k and data t r ansf er timing figure 19. d1 smsken: receive data mask enable bit enables the recei v e data mask function. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting smsken to 1 enables the recei v e data mask function. when the recei v e data mask function is enabled, the usi transmits the data stored in the transmit data b uf fer repeatedly until the sla v e de vice sends back a v alue other than the mask data set to smsk[7:0]/usi _smskx re gister . in this case, the transmit b uf fer empty and recei v e data b uf fer full interrupt flags are not set and no interrupt is generated. f or normal data transfer , set smsken to 0 (def ault) to disable the recei v e data mask function. d0 sfstmod: fast mode select bit selects f ast mode. 1 (r/w): f ast mode 0 (r/w): normal mode (def ault) either normal or f ast clock mode can be selected using sfstmod. setting sfstmod to 0 (def a ult) places the usi into normal mode and the usi generates the transfer clock by di viding the t16f output by 2. setting sfstmod to 1 places the usi into f ast mode and the usi uses pclk supplied from the clg directly as the transfer clock. the f ast mode does not use the t16f . usi ch.x spi master mode interrupt enable registers (usi_siex) register name ad dress bit name function setting init. r/w remarks usi ch.x spi master mode interrupt enable register (usi_siex) 0x50c7 0x50e7 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 seie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 srdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 stdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w note: this register is eff ectiv e only in spi master mode . configure the usi channel to spi master mode bef ore this register can be used. d[7:3] reserved d2 seie: receive error interrupt enable bit enables interrupt requests to the itc when an o v errun error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process o v errun errors using interrupts. d1 srdie: receive buffer full interrupt enable bit enables interrupt requests to the itc when recei v ed data is loaded to the recei v e data b uf fer . 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to read recei v ed data using interrupts. 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-29 d0 stdie: transmit buffer empty interrupt enable bit enables interrupt requests to the itc when data written to the transmit data b uf fer is sent to the shift re gister (i.e. when data transmission be gins). 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to write data to the transmit data b uf fer using interrupts. usi ch.x spi master mode interrupt flag registers (usi_sifx) register name ad dress bit name function setting init. r/w remarks usi ch.x spi master mode interrupt flag register (usi_sifx) 0x50c8 0x50e8 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ssif t r ansf er b usy flag 1 busy 0 idle 0 r d2 seif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d1 srdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 stdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w note: this register is eff ectiv e only in spi master mode . configure the usi channel to spi master mode bef ore this register can be used. d[7:4] reserved d3 ssif: transfer busy flag bit indicates the spi transfer status. 1 (r): operating 0 (r): standby (def ault) ssif is set to 1 when the spi starts data transfer in master mode and is maintained at 1 while transfer is underw ay . it is cleared to 0 once the transfer is completed. d2 seif: overrun error flag bit indicates whether an o v errun error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored seif is set to 1 when an o v errun error occur s. at the same time a recei v e error interrupt request is sent to the itc if seie/usi_siex re gister is 1. an o v errun error occurs when the pre vious recei v ed data in t h e r e c e i v e d a t a b u f f e r b e f o r e r e a d i n g i s o v e r w r i t t e n w i t h a n e w r e c e i v e d d a t a . s e i f i s r e s e t b y w r i t i n g 1 . d1 srdif: receive buffer full flag bit indicates the recei v e data b uf fer status. 1 (r): data full 0 (r): no data (def ault) 1 (w): reset to 0 0 (w): ignored srdif is s et to 1 when data recei v ed in the shift re gister is sent to the recei v e data b uf fer (when recei v- ing is completed), indicating that the data can be read. at the same time a recei v e b uf fer full interrupt request is sent to the itc if srdie/usi_siex re gister is 1. srdif is reset by writing 1. d0 stdif: transmit data buffer empty flag bit indicates the transmit data b uf fer status. 1 (r): empty (def ault) 0 (r): data e xists 1 (w): reset to 0 0 (w ): ignored stdif is set to 1 when the transmit data written to the transmit data b uf fer is transferred to the shift re gister (when transmission starts), indicating that the ne xt transmit data can be written to. at the same t i m e a t r a n s m i t b u f f e r e m p t y i n t e r r u p t r e q u e s t i s s e n t t o t h e i t c i f s t d i e / u s i _ s i e x r e g i s t e r i s 1. stdif is reset by writing 1. 19 universal serial interf a ce (usi) [s1c17564] 19-30 seiko epson corporation s1c17554/564 t echnical m anual usi ch.x spi master mode receive data mask registers (usi_smskx) register name ad dress bit name function setting init. r/w remarks usi ch.x spi master mode receive data mask register (usi_smskx) 0x50c9 0x50e9 (8 bits) d7C0 smsk[7:0] receiv e data mask bit smsk7 = msb smsk0 = lsb 0x0 to 0xff 0x0 r/w note: this register is eff ectiv e only in spi master mode . configure the usi channel to spi master mode bef ore this register can be used. d[7:0] smsk[7:0]: receive data mask bits sets the mask data for the recei v e data mask function. (def ault: 0x0) the usi in spi master mode pro vides a recei v e data mask (data retransmission) function. setting sm- sken/usi_scf gx to 1 enables this function. when the recei v e data mask function is enabled, the usi transmits the data stored in the transmit data b uf fer repeatedly until the sla v e de vice sends back a v alue other than the mask data set to smsk[7:0]. in this case, the transmit b uf fer empty and recei v e data b uf- fer full interrupt flags are not set and no interrupt is generated. in other w ords, the usi does not a ccept the recei v e data while the sla v e de vice is transmitting the mask data. usi ch.x i 2 c master mode trigger registers (usi_imtg x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c master mode trigger register (usi_imtgx) 0x50ca 0x50ea (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 imtg i 2 c master oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 imtgmod [2:0] i 2 c master tr igger mode select imtgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data stop condition star t condition note: this register is eff ectiv e only in i 2 c master mode . configure the usi channel to i 2 c master mode bef ore this register can be used. d[7:5] reserved d4 imtg: i 2 c master operation trigger bit starts an i 2 c master operation. 1 (w): t rigger 0 (w): ignored 1 (r): w aiting for starting operation 0 (r): t rigger has f inished (def ault) select an i 2 c master operation using imtgmod[2:0] and write 1 to imtg as the trigger . the i 2 c con- troller controls the i 2 c b us to generate the specif ied operating status. d3 reserved d[2:0] imtgmod[2:0]: i 2 c master trigger mode select bits se lects an i 2 c master operation. 8.3 t r igger list in i t ab le 19. 2 c master mode imtgmod[2:0] t rig g er 0x7 reser v ed 0x6 a ck/nak reception 0x5 nak tr ansmission 0x4 a ck tr ansmission 0x3 data reception 0x2 data tr ansmission 0x1 stop condition 0x0 star t condition (def ault: 0x0) 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-31 usi ch.x i 2 c master mode interrupt enable registers (usi_imie x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c master mode interrupt enable register (usi_imiex) 0x50cb 0x50eb (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 imeie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 imie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w note: this register is eff ectiv e only in i 2 c master mode . configure the usi channel to i 2 c master mode bef ore this register can be used. d[7:2] reserved d1 imeie: receive error interrupt enable bit enables interrupt requests to the itc when an o v errun error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process o v errun errors using interrupts. d0 imie: operation completion interrupt enable bit enables interrupt requests to the itc when the triggered operation has completed. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to conf irm whether the triggered operation has completed or not using interrupts. usi ch.x i 2 c master mode interrupt flag registers (usi_imif x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c master mode interrupt flag register (usi_imifx) 0x50cc 0x50ec (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 imbsy i 2 c master b usy flag 1 busy 0 standb y 0 r d4C2 imsta[2:0] i 2 c master status imst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y s t o p g e n e r a t e d s t a r t g e n e r a t e d d1 imeif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 imif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w note: this register is eff ect iv e only in i 2 c master mode . configure the usi channel to i 2 c master mode bef ore this register can be used. d[7:6] reserved d5 imbsy: i 2 c master busy flag bit indicates the i 2 c master operation status. 1 (r): busy 0 (r): standby (def ault) writing 1 to imtg/usi_imtgx re gister (starting an i 2 c master operation) sets imbsy to 1 indicating t h a t t h e i 2 c c o n t r o l l e r i s b u s y ( o p e r a t i n g ) . w h e n t h e s p e c i f i e d o p e r a t i o n h a s f i n i s h e d , i m b s y i s r e s e t t o 0 . d[4:2] imsta[2:0]: i 2 c master status bits indicates the i 2 c master status. 19 universal serial interf a ce (usi) [s1c17564] 19-32 seiko epson corporation s1c17554/564 t echnical m anual 8.4 i t ab le 19. 2 c master status bits imst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been gener ated. 0x0 star t condition has been gener ated. (def ault: 0x0) when an operation completion interrupt occurs, read imst a[2:0] to check the operation that has been f inished. d1 imeif: overrun error flag bit indicates whether an o v errun error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored imeif is set to 1 when an o v errun error occurs. at the same time a recei v e error interrupt request is sent to the itc if imeie/usi_imiex re gister is 1. an o v errun error occurs when the pre vious recei v ed data in the recei v e data b uf fer before reading is o v erwritten with a ne w recei v ed d ata. imeif is reset by writ- ing 1. d0 imif: operation completion flag bit indicates whether the triggered operation has completed or not. 1 (r): completed 0 (r): not completed (def ault) 1 (w): reset to 0 0 (w): ignored imif is set to 1 when the operation that is specif ied and triggered using the usi_imtgx re gister has completed. at the same time an operation completion interrupt request is sent to the itc if imie/usi_ imiex re gister is 1. imif is reset by writing 1. usi ch.x i 2 c slave mode trigger registers (usi_istg x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c slave mode trigger register (usi_istgx) 0x50cd 0x50ed (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 istg i 2 c sla v e oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 istgmod [2:0] i 2 c sla v e tr igger mode select istgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data reser v ed w ait f or star t note: this register is eff ectiv e only in i 2 c sla v e mode . configure the usi channel to i 2 c sla v e mode be- f ore this register can be used. d[7:5] reserved 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-33 d4 istg: i 2 c slave operation trigger bit starts an i 2 c sla v e operation. 1 (w): t rigger 0 (w): ignored 1 (r): w aiting for starting operation 0 (r): t rigger has f inished (def ault) select an i 2 c sla v e operation using istgmod[2:0] and write 1 to istg as the trigger . the i 2 c control- ler controls the i 2 c b us to generate the specif ied operating status. d3 reserved d[2:0] istgmod[2:0]: i 2 c slave trigger mode select bits selects an i 2 c sla v e operation. 8.5 t r igger list in i t ab le 19. 2 c sla v e mode istgmod[2:0] t rig g er 0x7 reser v ed 0x6 a ck/nak reception 0x5 nak tr ansmission 0x4 a ck tr ansmission 0x3 data reception 0x2 data tr ansmission 0x1 reser v ed 0x0 w ait f or star t condition (def ault: 0x0) usi ch.x i 2 c slave mode interrupt enable registers (usi_isie x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c slave mode interrupt enable register (usi_isiex) 0x50ce 0x50ee (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 iseie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 isie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w note: this register is eff ectiv e only in i 2 c sla v e mode . configure the usi channel to i 2 c sla v e mode be- f ore this register can be used. d[7:2] reserved d1 iseie: receive error interrupt enable bit enables interrupt requests to the itc when an o v errun error occurs. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to process o v errun errors using interrupts. d0 isie: operation completion interrupt enable bit enables interrupt requests to the itc when the triggered operation has completed. 1 (r/w): enabled 0 (r/w): disabled (def ault) set this bit to 1 to conf irm whether the triggered operation has completed or not using interrupts. 19 universal serial interf a ce (usi) [s1c17564] 19-34 seiko epson corporation s1c17554/564 t echnical m anual usi ch.x i 2 c slave mode interrupt flag registers (usi_isif x) register name ad dress bit name function setting init. r/w remarks usi ch.x i 2 c slave mode interrupt flag register (usi_isifx) 0x50cf 0x50ef (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 isbsy i 2 c sla v e b usy flag 1 busy 0 standb y 0 r d4C2 issta[2:0] i 2 c sla v e status isst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y stop detected star t detected d1 iseif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 isif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w note: this register is eff ectiv e only in i 2 c sla v e mode . configure the usi channel to i 2 c sla v e mode be- f ore this register can be used. d[7:6] reserved d5 isbsy: i 2 c slave busy flag bit indicates the i 2 c sla v e operation status. 1 (r): busy 0 (r): standby (def ault) writing 1 to istg/usi_istgx re gister (starting an i 2 c sla v e operation) sets isbsy to 1 indicating that the i 2 c controller is b usy (operating). when the specif ied operation has f inished, isbsy is reset to 0. d[4:2] issta[2:0]: i 2 c slave status bits ind icates the i 2 c sla v e status. 8.6 i t ab le 19. 2 c sla v e status bits isst a[2:0] status 0x7 reser v ed 0x6 nak has been receiv ed. 0x5 a ck has been receiv ed. 0x4 a ck or nak has been tr ansmitted. 0x3 receiv e data b uff er is full. 0x2 t r ansmit data b uff er is empty . 0x1 stop condition has been detected. 0x0 star t condition has been detected. (def ault: 0x0) when an operation completion interrupt occurs, read isst a[2:0] to check the operation that has been f inished. d1 iseif: overrun error flag bit indicates whether an o v er run error has occurred or not. 1 (r): error occurred 0 (r): no error (def ault) 1 (w): reset to 0 0 (w): ignored iseif is set to 1 when an o v errun error occurs. at the same time a recei v e error interrupt request is sent to the itc if iseie/usi_isiex re gister is 1. an o v errun error occurs when the pre vious recei v ed data in t h e r e c e i v e d a t a b u f f e r b e f o r e r e a d i n g i s o v e r w r i t t e n w i t h a n e w r e c e i v e d d a t a . i s e i f i s r e s e t b y w r i t i n g 1 . d0 isif: operation completion flag bit indicates whether the triggered operation has completed or not. 1 (r): completed 0 (r): not completed (def ault) 1 (w): reset to 0 0 (w): ignored 19 universal serial interf a ce (usi) [s1c17564] s1c17554/564 t echnical m anual seiko epson corporation 19-35 isif is set to 1 when the operation that is specif ied and triggered using the usi_istgx re gister has completed. at the same time an operation completion interrupt request is sent to the itc if isie/usi_ isiex re gister is 1. isif is reset by writing 1. precautions 19.9 interface mode setting be sure to perform softw are reset (usimod[2:0]/usi_gcfgx re gister = 0x0) and set the interf ace mode (usi- mod[ 2:0]/usi_gcfgx re gister = 0x1, 0x2, 0x4, or 0x5) before changing other usi conf igurations. busy fla gs the b usy flags listed belo w may be set with delay . when checking the b usy status after performing an operation that sets the b usy flag, w ait for at least one t16f output clock c ycle before reading the flag. if the b usy flag is read with no w ait time inserted, the flag may not indicate the current s tatus properly . 9.1 busy flags and dela y conditions t ab le 19. interface mode busy fla g timing with dela y occurred u ar t mode utbsy/usi_uifx register after tr ansmit data is wr itten to the tr ansmit data b uff er spi master mode ssif/usi_sifx register after tr ansmit data is wr itten to the tr ansmit data b uff er in nor mal mode (no dela y will occur in f ast mode .) i 2 c master mode imbsy/usi_imifx register after the tr igger bit is set i 2 c sla v e mode isbsy/usi_isifx register after the tr igger bit is set pclk t16f output cloc k tr ansmit data b uff er tr ansmit shift register busy flag w ait time da da the b usy flag can be checked. 9.1 w aiting bef ore reading busy flag figure 19. receiving contr ol b yte in i 2 c sla ve mode the e xternal i 2 c master de vice sends a control byte to the i 2 c sla v e de vice when an a ck has been recei v ed af- ter sending a sla v e address. the subsequent operations of the sla v e de vice are determined by the control byte. sd a line 1: wr ite (b y master) 0: read (b y master) 11: reser ve d 10: 32-bit address 01: 16-bit address 00: 8-bit address star t condition d7 d6 d5 d4 d3 d2 d1 d0 st a reser ve d addr siz e r/w ac k r/w ac k ac k sla ve address access address control b yte 9.2 control byte sent from i figure 19. 2 c master i 2 c master write (data receiving fr om master) sd a line star t condition wr ite 16-bit address and data wr ite st a stop condition access address stp ac k ac k ac k slv_addr addr[15:8] ac k addr[7:0] ac k da 0 ac k da 1 0x02 write data 0 9.3 i figure 19. 2 c master wr ite (data receiving from master) the control byte specif ies the access address size and writing operations. the recei v ed data that follo w the control byte should be used as the address and the data to be written according to the access address size. 19 universal serial interf a ce (usi) [s1c17564] 19-36 seiko epson corporation s1c17554/564 t echnical m anual i 2 c master read (data transmission to master) sd a line star t condition st a stop condition tr igger to w ait f or star t condition stp ac k 0 wr ite 32-bit address and data read ac k ac k slv_addr star t condition st a ac k 1 read slv_addr addr[31:24] ac k addr[23:16] ac k addr[15:8] ac k addr[7:0] ac k da 0 nak da 1 0x05 access address read data 9.4 i figure 19. 2 c master read (data t r ansmission to master) the master sends the access address follo wing the control byte. perform data reception for the control byte a n d a d d r e s s d a t a t o d e t e r m i n e t h e a d d r e s s f r o m w h i c h t r a n s m i t d a t a i s r e a d . a f t e r s e n d i n g a n a c k f o r a d d r 0 , set istgmod[2:0]/usi_istgx re gister to 0x0 and istg/usi_istgx re gister to 1 to w ait for a start condi- tion that will be se nt from the master for reading data (for the sla v e to sent the read data). 20 ir remo te contr oller (remc) s1c17554/564 t echnical m anual seiko epson corporation 20-1 ir remote contr oller (remc) 20 remc module over vie w 20.1 the s1c17554/564 includes an ir remote controller (remc) module for transmitting/recei ving infrared remote control communication signals. the follo wing sho ws the features of the remc module: ? supports input and output infrared remote control communication signals. ? includes a carrier generator for generating a carrier signal. ? includes an 8- bit do wn-counter for counting the transfer data length. ? includes a modulator for generating transmission data of the specif ied carrier length. ? includes an edge detector for detecting input signal rising and f alling edges. ? can generate counter underflo w interrupts indicating that the specif ied data length has been sent and input rising/ f alling edge detection interrupts for data recei v e processin g. figure 20.1.1 sho ws the conf iguration of the remc module. carrier generator internal bus ir remote controller bus i/f and control registers data length counter remo remi edge detector modulator interrupt control pclk clg divider (1/1C1/16k) itc 1.1 remc module configur ation figure 20. remc input/output pins 20.2 t able 20.2.1 lists the remc input/output pins. 2.1 list of remc pins t ab le 20. pin name i/o qty function remi i 1 remote control receiv e data input pin inputs receiv e data. remo o 1 remote control tr ansmit data output pin outputs modulated remote control tr ansmit data. the remc input/output pins (remi, remo) are shared with i/o ports and are initially set as general purpose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as remc input/output pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . carrier generation 20.3 the remc module includes a carrier generator that generates a carrier signal for transmission in accordance with the clock set by softw are and carrier h and l section lengths. 20 ir remo te contr oller (remc) 20-2 seiko epson corporation s1c17554/564 t echnical m anual the carrier generation clock is generated by di viding pclk into 1/1 to 1/16k. the di vision ratio can be selected from the 15 types sho wn belo w using cgclk[3:0]/remc_cfg re gister . 3.1 carr ier gener ation cloc k (pclk division ratio) selection t ab le 20. cgclk[3:0] division ratio cgclk[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) notes: ? the cloc k gener ator (clg) m ust be configured to supply pclk to the per ipher al modules be- f ore r unning the remc . ? mak e sure the remc is halted bef ore setting the cloc k. f or detailed information on the clg con trol, see the clock generator (clg) chapter . the carrier h and l section lengths are set by remch[5:0]/remc_car re gister and remcl[5:0]/remc_car re gister , respecti v ely . set a v alue corresponding to the number of clock (selected as abo v e) c ycles + 1 to these re gis- ters. the carrier h and l section lengths can be calculated as follo ws: remch + 1 carrier h section length = [s] cg_clk remcl + 1 carrier l section length = [s] cg_clk remch: carrier h section length data v alue remcl: carrier l section length data v alue cg_clk: carrier generation clock frequenc y the carrier signal is generated from these settings as sho wn in figure 20.3.1. example: cgclk[3:0] = 0x2 (pclk/4), remch[5:0] = 2, remcl[5:0] = 1 pclk carr ier generation cloc k count carr ier 0 1 2 0 1 0 carr ier h section length carr ier l section length 3.1 carr ier signal gener ation figure 20. data length counter cloc k settings 20.4 the data length counter is an 8-bit counter for setting data lengths when transmitting data. when a v alue corresponding to the data pulse width is written during data transmission, the data length counter be gins counting do wn from that v alue and stops after generating an underflo w interrupt cause when the counter reach es 0. the subsequent transmit data is set using this interrupt. this counter is also used for data recei ving, enabling measurement of the recei v ed data length. interrupts can be generated at the input signal rising or f alling edges when recei ving data. the data pulse length can be obtained from the dif ference between data pulse edges by setting the data length counter to 0xf f using the interrupt w hen the input changes and by reading out the count v alue when a subsequent interrupt occurs due to input changes. 20 ir remo te contr oller (remc) s1c17554/564 t echnical m anual seiko epson corporation 20-3 this data length counter clock also uses a di vided pclk clock and can select one of 15 dif ferent types. the di vi- sion ratio to generate the data length counter clock is selected by lcclk[3:0]/remc_cfg re gister pro vided sepa- rately to the carrier generation clock select bits. 4.1 data length counter cloc k (pclk division ratio) selection t ab le 20. lcclk[3:0] division ratio lcclk[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) the data length counter can count up to 256. the count clock should be selected to ensure that the data length f its within this range. data t ransf er contr ol 20.5 mak e the follo wing settings before starting data t ransfers. (1) conf igure the carrier signal. (see section 20.3.) (2) select the data length counter clock. (see section 20.4.) (3) set the interrupt conditions. (see section 20.6.) note: mak e sure the remc module is halted (remen/remc_cfg register = 0) bef ore changing the abo v e settings . data transmission contr ol remdt remo pin output carr ier remdt remo pin output 5.1 data t r ansmission figure 20. pclk data length counter cloc k remlen[7:0] interr upt signal 4 3 2 1 0 5.2 underflo w interr upt gener ation timing figure 20. (1) data tr ansmit mode setting set remc to transmit mode by writing 0 to remmd/remc_cfg re gister . (2) enab ling data tr ansmission enable remc operation by setting remen/remc_cfg re gister to 1. this initiates remc transmission. s e t r e m d t / r e m c _ l c n t r e g i s t e r t o 0 a n d r e m l e n [7:0] / r e m c _ l c n t r e g i s t e r t o 0x0 b e f o r e s e t t i n g remen to 1 to pre v ent unnecessar y data transmission. 20 ir remo te contr oller (remc) 20-4 seiko epson corporation s1c17554/564 t echnical m anual (3) t r ansmission data setting set the data to be transmitted (high or lo w) to remdt/remc_lcnt re gister . setting remdt to 1 outputs high; setting it to 0 outputs lo w from the remo pin after being modulated by the carrier signal. (4) data pulse length setting set the v alue corresponding to the data pulse length (high or lo w section) to remlen[7:0]/remc_lcnt re gister to set to the data length counter . gi v en belo w is the v alue to which the data length counter is set: setting v alue = data pulse length (seconds) data length counter clock frequenc y (hz) the data length counter starts counting do wn from the v alue written using the data length counter clock selected. a cause of underflo w interrupt occurs when the data length counter v alue reaches 0. if the interrupt is enabled, an remc interrupt r equest is output to the interrupt controller (itc). the data length counter stops counting at the same time with the counter v alue 0 maintained. (5) interr upt handling t o transmit the subsequent data, set the subsequent data (step 3) and set the data pulse length (step 4) in the interrupt handler routine e x ecuted by the data length counter underflo w . (6) t er minating data tr ansmission t o terminate da ta transmission, set remen to 0 after the f inal data transmission has completed (after an under - flo w interrupt has occurred). data reception contr ol pclk data length counter cloc k remi input remdt (sampled wave fo rm ) remrif remfif interr upt signal remlen[7:0] wr ite 0xff x+2 x+1 x 0xff 0xf e 0xfd 0xff wr ite 0xff wr ite 1 wr ite 1 5.3 data reception figure 20. (1) data receiv e mode setting set remc to recei v e mode by writing 1 to remmd/remc_cfg re gister . (2) enab ling data reception enable remc operation by setting remen/remc_cfg re gister to 1. this initiates remc reception (input edge detection). remc detects an input transition (signal rising or f alling edges) by sampling the input signal from the remi pin using the carrier generation clock. if a signal edge is detected, a cause of rising or f alling edge interrupt is generated. an remc interrupt request is output to the itc if the interrupt is enabled. rising edge and f alling edge interrupts can be indi vidually enabled or disabled. note that if the signal le v el after the input has changed is not detected for at least tw o continuous sampling clock c ycles, the input si gnal transition is interpreted as noise, and no rising or f alling edge interrupt is gener - ated. 20 ir remo te contr oller (remc) s1c17554/564 t echnical m anual seiko epson corporation 20-5 (3) interr upt handling when a rising edge or f alling edge interrupt occurs, write 0xf f to remlen[7:0]/remc_lcnt re gister in the interrupt handler routine to set the v alue to the data length counter . the data length counter starts counting do wn using the selected data length counter clock from the v alue writ- ten. the data recei v ed can be read out from remdt/remc_lcnt re gister . the subsequent f allin g or rising edge interrupt is generated at the termination of the data pulse. read the data length counter at that point. the data length can be calculated from the dif ference between 0xf f and the v alue read. t o recei v e the subsequent data, set the data length counter to 0xf f once ag ain, then w ait for the subsequent interrupt. if the data length counter becomes 0 after being set to 0xf f without th e occurrence of an edge interrupt, either no more data is left or a recei v e error has occurred. data length counter underflo w interrupts are generated e v en when recei ving data and should be used for terminate/error handling. (4) t er minating data reception t o terminate data reception, write 0 to remen after the f inal data has been recei v ed. remc interrupts 20.6 the remc module includes a function for generating the follo wing three dif ferent types of interrupts. ? underflo w interrupt ? rising edge interrupt ? f alling edge interrupt the remc module outputs one interrupt signal shared by the three interrupt causes abo v e to the interrupt controller (itc). t o identify the cause of interrupt occurred, check the interrupt flag status in the remc module. underflo w interrupt generated when the data length counter has counted do wn to 0, this interrupt cause sets the interrupt flag re- muif/remc_int re gister inside the remc to 1. when data is being transmitted, the underflo w interrupt indicates that the specif ied data length has been trans- mitted. when recei ving data, the underflo w interrupt indicates that data has been recei v ed or a recei v e error has occurred. t o use this interrupt, set remuie/remc_i nt re gister to 1. if remuie is set to 0 (def ault), the interrupt re- quest attrib utable to this cause will not be sent to the itc. when remuif is set to 1, remc outputs an interrupt request to the itc. an interrupt will be generated if the itc and s1c17 core interrupt conditions are met. remuif should be inspected in the remc interrupt handler routine to determine whether the remc interrupt is attr ib utable to data length counter underflo w . the interrupt cause should be cleared in the interrupt handler routine by resetting (writing 1 to) remuif . rising edg e interrupt generated when the remi pin input signal changes from lo w to high, this interrupt cause sets the interrupt flag remrif/remc_int re gister to 1 within the remc. by running the data length counter between this interrupt and a f allin g edge interrupt when data is being re- cei v ed, the recei v ed data pulse width can be calculated from that count v alue. t o use this interrupt, set remrie/remc_int re gister to 1. if remrie is set to 0 (def ault), the interrupt re- quest attrib utable to this cause will not be sent to the itc. when remrif is set to 1, remc outputs an interrupt request to the itc. an interrupt will be generated if the itc and s1c17 core interrupt conditions are met. remrif should be inspected in the remc interrupt handler routine to determine whether the remc interrupt is attrib utable to input signal rising edge. the interrupt cause should be cleared in the interrupt handler routine by resetting (writing 1 to) remrif . 20 ir remo te contr oller (remc) 20-6 seiko epson corporation s1c17554/564 t echnical m anual f alling edg e interrupt generated when the remi pin input signal changes from high to lo w , this interrupt cause sets the interrupt flag remfif/remc_int re gister to 1 within the remc. by running the data length counter between this interrupt and a rising edge interrupt when data is being re- cei v ed, the recei v ed data pulse width can be calculated from that count v alue. t o use this interrupt, set remf ie/remc_int re gister to 1. if remfie is set to 0 (def ault), the interrupt re- quest attrib utable to this cause will not be sent to the itc. when remfif is set to 1, remc outputs an interrupt request to the itc. an interrupt will be generated if the itc and s1c17 core interrupt conditions are met. remfif should be inspected in the remc interrupt handler routine to determine whether the remc interrup t is attrib utable to input signal f alling edge. the interrupt cause should be cleared in the interrupt handler routine by resetting (writing 1 to) remfif . f or more information on interrupt processing, see the interrupt controller (itc) chapter . contr ol register details 20.7 7.1 list of remc registers t ab le 20. ad dress register name function 0x5340 remc_cfg remc configur ation register controls the cloc k and data tr ansf er . 0x5342 remc_car remc carr ier length setup register sets the carr ier h/l section lengths . 0x5344 remc_lcnt remc length counter register sets the tr ansmit/receiv e data length. 0x5346 remc_int remc interr upt control register controls interr upts . the remc re gisters are described in detail belo w . these are 16- bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. remc configuration register (remc_cfg) register name ad dress bit name function setting init. r/w remarks remc configuration register (remc_cfg) 0x5340 (16 bits) d15C12 cgclk[3:0] carr ier gener ator cloc k division r atio select cgclk[3:0] lcclk[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d11C8 lcclk[3:0] length counter cloc k division r atio select 0x0 r/w d7C2 C reser v ed C C C 0 when being read. d1 remmd remc mode select 1 receiv e 0 t r ansmit 0 r/w d0 remen remc enab le 1 enab le 0 disab le 0 r/w d[15:12] cgclk[3:0]: carrier generator clock division ratio select bits selects a carrier generation clock (pclk di vision ratio). 7.2 carr ier gener ation cloc k (pclk division ratio) selection t ab le 20. cgclk[3:0] division ratio cgclk[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) 20 ir remo te contr oller (remc) s1c17554/564 t echnical m anual seiko epson corporation 20-7 d[11:8] lcclk[3:0]: length counter clock division ratio select bits selects a data length counter clock (pclk di vision ratio). 7.3 data length counter cloc k (pclk division ratio) selection t ab le 20. lcclk[3:0] division ratio lcclk[3:0] division ratio 0xf reser v ed 0x7 1/128 0x e 1/16384 0x6 1/64 0xd 1/8192 0x5 1/32 0xc 1/4096 0x4 1/16 0xb 1/2048 0x3 1/8 0xa 1/1024 0x2 1/4 0x9 1/512 0x1 1/2 0x8 1/256 0x0 1/1 (def ault: 0x0) note: the cloc k should be set only while the remc module is stopped (remen = 0). d[7:2] reserved d1 remmd: remc mode select bit selects the transfer direction. 1 (r/w): reception 0 (r/w): t ransmission (def ault) d0 remen: remc enable bit enables or disables data transfer by the remc mo dule. 1 (r/w): enabled 0 (r/w): disabled (def ault) setting remen to 1 starts transmission or recei ving in accordance with remmd settings. setting remen to 0 disables remc module operations. remc carrier length setup register (remc_car) register name ad dress bit name function setting init. r/w remarks remc carrier length setup register (remc_car) 0x5342 (16 bits) d15C14 C reser v ed C C C 0 when being read. d13C8 remcl[5:0] carr ier l length setup 0x0 to 0x3f 0x0 r/w d7C6 C reser v ed C C C 0 when being read. d5C0 remch[5:0] carr ier h length setup 0x0 to 0x3f 0x0 r/w d[15:14] reserved d[13:8] remcl[5:0]: carrier l length setup bits sets the carrier signal l section length. (def ault: 0x0) s p e c i f y a v a l u e c o r r e s p o n d i n g t o t h e n u m b e r o f c a r r i e r g e n e r a t i o n c l o c k c y c l e s s e l e c t e d b y c g c l k [ 3 : 0 ] / remc_cfg re gister + 1. calculate carrier l section length as follo w s: remcl + 1 carrier l section length = [s] cg_clk remcl: remcl[5:0] setting cg_clk: carrier generation clock frequenc y the h section length is specif ied by remch[5:0]. the carrier signal is generated from these settings as sho wn in figure 20.7.1. d[7:6] reserved d[5:0] remch[5:0]: carrier h length setup bits sets the carrier signal h section length. (def ault: 0x0) s p e c i f y a v a l u e c o r r e s p o n d i n g t o t h e n u m b e r o f c a r r i e r g e n e r a t i o n c l o c k c y c l e s s e l e c t e d b y c g c l k [ 3 : 0 ] / remc_cfg re gister + 1. calculate carrier h section length as follo ws: 20 ir remo te contr oller (remc) 20-8 seiko epson corporation s1c17554/564 t echnical m anual remch + 1 carrier h section length = [s] cg_clk remch: remch[5:0] setting cg_clk: carrier generation clock frequenc y the l section length is specif ied by remcl[5:0]. the carrier signal is generated from these settings as sho wn in figure 20.7.1. example: cgclk[3:0] = 0x2 (pclk/4), remch[5:0] = 2, remcl[5:0] = 1 pclk carr ier generation cloc k count carr ier 0 1 2 0 1 0 carr ier h section length carr ier l section length 7.1 carr ier signal gener ation figure 20. remc length counter register (remc_lcnt) register name ad dress bit name function setting init. r/w remarks remc length counter register (remc_lcnt) 0x5344 (16 bits) d15C8 remlen[7:0] t r ansmit/receiv e data length count (do wn counter) 0x0 to 0xff 0x0 r/w d7C1 C reser v ed C C C 0 when being read. d0 remdt t r ansmit/receiv e data 1 1 (h) 0 0 (l) 0 r/w d[15:8] remlen[7:0]: transmit/receive data length count bits sets the data length counter v alue and starts counting. (def ault: 0x0) the counter stops when it reaches 0 and generates a cause of underflo w interrupt. f or data tr ansmission set the transmit data length for data transmission. when a v alue corresponding to the data pulse width is written, the data length counter starts counting do wn from that v alue. the counter stops counting and generates a cause of underflo w interrupt when it reaches 0. set the subsequent transmit data using this interrupt. f or data receiving i n t e r r u p t s c a n b e g e n e r a t e d a t t h e i n p u t s i g n a l r i s i n g o r f a l l i n g e d g e s w h e n r e c e i v i n g d a t a . t h e d a t a pulse length can be o btained from the dif ference between 0xf f set to the data length counter using the interrupt when the input changes and the count v alue read out when the ne xt interrupt occurs due to an input change. d[7:1] reserved d0 remdt: transmit/receive data bit sets the transmit data for data transmission. recei v e data can be read when recei ving data. 1 (r/w): 1 (h) 0 (r/w): 0 (l) (def ault) if remen/remc_cfg re gister is set to 1, the remdt setting is modula ted by the carrier signal for data transmission and output from the remo pin. f or data recei ving, this bit is set to the v alue corre- sponding to the signal le v el of the data pulse input. 20 ir remo te contr oller (remc) s1c17554/564 t echnical m anual seiko epson corporation 20-9 remc interrupt control register (remc_int) register name ad dress bit name function setting init. r/w remarks remc interrupt control register (remc_int) 0x5346 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10 remfif f alling edge interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d9 remrif rising edge interr upt flag 0 r/w d8 remuif underflo w interr upt flag 0 r/w d7C3 C reser v ed C C C 0 when being read. d2 remfie f alling edge interr upt enab le 1 enab le 0 disab le 0 r/w d1 remrie rising edge interr upt enab le 1 enab le 0 disab le 0 r/w d0 remuie underflo w interr upt enab le 1 enab le 0 d isab le 0 r/w this re gister controls the data length counter underflo w , input signal rising edge, and input signal f alling edge inter - rupts. the interrupt flag is set to 1 when the data length counter underflo ws, or when an input signal rising edge or f alling edge is detected. if the corresponding interrupt enable bit has been set to 1, the remc outputs an interrupt request signal to the itc at the s ame time. an interrupt will be generated if the itc and s1c17 core interrupt con- ditions are met. when an remc interrupt occurs, check the interrupt flag status in this re gister to identify the cause of interrupt occurred. if the interrupt enable bit is set to 0, the interrupt is disabled. notes: ? t o pre v ent interr upt recurrences , the remc module interr upt flag m ust be reset in the inter- r upt handler routine after an remc interr upt has occurred. ? t o p r e v e n t g e n e r a t i n g u n n e c e s s a r y i n t e r r u p t s , r e s e t t h e i n t e r r u p t f l a g b e f o r e e n a b l i n g i n t e r - r upts b y the interr upt enab le bit. d[15:11] reserved d10 remfif: falling edge interrupt flag bit indicates the f alling edge interrupt cause occurrence status. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored remfif is set to 1 at the input s ignal f alling edge. remfif is reset to 0 by writing 1. d9 remrif: rising edge interrupt flag bit indicates the rising edge interrupt cause occurrence status. 1 (r): cause of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored remrif is set to 1 at the input signal rising edge. remrif is reset to 0 by writing 1. d8 remuif: underflow interrupt flag bit indicates the underflo w interrupt cause occurrence status. 1 (r): ca use of interrupt has occurred 0 (r): no cause of interrupt has occurred (def ault) 1 (w): flag is reset 0 (w): ignored remuif is set to 1 when a data length counter underflo w occurs. remuif is reset to 0 by writing 1. d[7:3] reserved d2 remfie: falling edge interrupt enable bit enables or disables input signal f alling edge interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) 20 ir remo te contr oller (remc) 20-10 seiko epson corporation s1c17554/564 t echnical m anual d1 remrie: rising edge interrupt enable bit enables or disables input signal rising edge interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) d0 remuie: underflow interrupt enable bit enables or disables data length counter underflo w interrupts. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-1 a/d con v erter (adc10) 21 adc10 module over vie w 21.1 t h e s 1 c 1 7 5 5 4 / 5 6 4 i n c l u d e s a n a / d c o n v e r t e r ( a d c 1 0 ) t h a t c o n v e r t s a n a l o g i n p u t s i g n a l s i n t o 1 0 - b i t d i g i t a l v a l u e s . the follo wing sho ws the features of the adc10 module: ? con v ersion method: successi v e approximation type ? resolution: 10 bits ? input channels: max. 4 channels ? a/d con v ersion clock: max. 2 mhz ? sampling rate: max. 100 ksps ? analog input v oltage range: v ss to a v dd ? sampling & hold circuit included ? supports tw o con v ersion modes: one-time con v ersion mode (for single channel or multi-channels) continuous con v ersion mode (for single channel or multi-channels, terminated with softw are) ? supports three con v ersion triggers: softw are trigger external trigger (input from the #adtrg pin) t16 ch.0 underflo w trigger ? the co n v ersion results can be read as 16-bit data with the 10-bit con v erted data aligned to left or right. ? t w o types of interrupts can be generated: con v ersion completion interrupt con v ersion data o v erwrite error interrupt figure 21.1.1 sho ws the adc10 conf iguration. bus i/f and control registers interrupt request trigger signals adc10 external trigger successive approximation control circuit d/a converter internal data bus av dd #adtrg + C pclk clg divider (1/2C1/32k) t16 ch.0 itc adclk mux ain3 ain2 ain1 ain0 1.1 a/d con v er ter configur ation figure 21. 21 a/d conver ter (adc10) 21-2 seiko epson corporation s1c17554/564 t echnical m anual adc10 input pins 21.2 t able 21.2.1 lists the adc10 input pins. 2.1 list of adc10 input pins t ab le 21. pin name i/o qty function ain[3:0] i 4 analog signal input pins ain0 (ch.0) to ain3 (ch.3) (see note belo w) input the analog signals to be a/d con v er ted. the analog input v oltage a v in m ust be within the r ange of v ss a v in a v dd . #adtrg i 1 exter nal tr igger input pin input a tr igger signal to star t a/d con v ersion from an e xter nal source . a v dd C 1 analog po w er-supply pin note: the pins go to high impedance status wh en the por t function is s witched. the a/d con v erter input pins (ain[3:0], #adtrg) are shared with i/o ports and are initially set as general pur - pose i/o port pins. the pin functions must be switched using the port function select bits to use the general purpose i/o port pins as a/d con v erter input pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . a/d con ver te r settings 21.3 mak e the follo wing settings before starting a/d con v ersion. (1) set the analog input pins. see section 21.2. (2) set the a/d con v ersion clock. (3) select the a/d con v ersion start and end channels. (4) select the a/d con v ersion mode. (5) select the a/d con v ersion trigger source. (6) set the sampling time. (7) select the con v ersion result storing mode. (8) when using a/d con v erter interrupts , set interrupt conditions. see section 21.5. note: mak e sure the a/d con v er ter is disab led (aden/adc10_ctl register = 0) bef ore changing the abo v e settings . changing the settings while the a/d con v er ter is enab led ma y cause a malfunc- tion. a/d con ver sion cloc k setting 21.3.1 t o use the a/d con v erter , the clock used in the a/d con v erter must be supplied by turning on the peripheral module clock (pclk) output from the clock generator (clg). f or more information on clock control, see the clock gen- erator (clg) chapters. the a/d con v ersion is generated by di viding pclk. the di vision ratio can be selected from the 15 types sho wn in t able 21.3.1.1 using addf[3:0]/adc10_clk re gister . note: f or the a/d con v ersion cloc k frequency r ange that can be used f or this a/d con v er ter , see a/d con v er ter char acter i stics in the electr ical char acter istics chapter . 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-3 3.1.1 a/d con v ersion cloc k (pclk division ratio) selection t ab le 21. addf[3:0] division ratio 0xf reser v ed 0x e 1/32768 0xd 1/16384 0xc 1/8192 0xb 1/4096 0xa 1/2048 0x9 1/1024 0x8 1/512 0x7 1/256 0x6 1/128 0x5 1/64 0x4 1/32 0x3 1/16 0x2 1/8 0x1 1/4 0x0 1/2 (def ault: 0x0) selecting a/d con ver sion star t and end channels 21.3.2 select the channel in which the a/d con v ersion is to be performed from among the pins (channels) that ha v e been set for analog input . t o enable a/d con v ersions in multiple channels to be performed successi v ely through one con- v ert operation, specify the con v ersion start and con v ersion end channels using adcs[2:0]/adc10_trg re gister and adce[2:0]/adc10_trg re gister , respecti v ely . 3.2.1 relationship betw een adcs/adce and input channels t ab le 21. adcs[2:0]/adce[2:0] channel selected 0x7C0x4 reser v ed 0x3 ain3 0x2 ain2 0x1 ain1 0x0 ain0 (def ault: 0x0) example: operation of one a/d con v ersion adcs[2:0] = 0, adce[2:0] = 0 con v erted only in ain0 adcs[2:0] = 0, adce[2:0] = 3 con v erted in the follo wing order: ain0ain1ain2ain3 adcs[2:0] = 2, adce[2:0] = 1 con v erted in the follo wing order: ain2ain3(ain4ain5ain6ain7)ain0ain1 note: the control circuits in the a/d con v er ter suppor ts up to eight channels f or e xpansion in the future , and it perf or ms a/d con v ersion if a channel (ain4Cain7) without an analog input is specified. in this case , the results that will be stored to add[15:0]/adc10_add register is 0x0. t o a v oid a / d c o n v e r s i o n f o r t h e c h a n n e l s w i t h o u t a n i n p u t , s e t t h e a d c s [2:0] t o e q u a l o r s m a l l e r t h a n adce[2:0] within the a v ailab le analog inputs . a/d con ver sion mode setting 21.3.3 the a/d con v erter pro vides tw o con v ersion modes that can be selected using adms/adc10_trg re gister: one- time con v ersion mode and continuous con v ersion mode. 1. one-time con ver sion mode (adms = 0) the a/d con v erter performs a/d con v ersion for all analog inputs within the range from the start channel speci- f i e d b y a d c s [ 2 : 0 ] / a d c 1 0 _ t r g r e g i s t e r t o t h e e n d c h a n n e l s p e c i f i e d b y t h e a d c e [ 2 : 0 ] / a d c 1 0 _ t r g r e g i s t e r once and then stops automatically . 21 a/d conver ter (adc10) 21-4 seiko epson corporation s1c17554/564 t echnical m anual 2. contin uous con ver sion mode (adms = 1) the a/d con v erter repeatedly performs a/d con v ersion for the channels in the range specif ied by adcs[2:0] and adce[2:0] until stopped with softw are. at initial reset, the a/d con v erter is set to one-time con v ersion mode. t rig g er selection 21.3.4 s e l e c t a t r i g g e r s o u r c e t o s t a r t a / d c o n v e r s i o n f r o m a m o n g t h e t h r e e t y p e s l i s t e d i n t a b l e 2 1 . 3 . 4 . 1 u s i n g a d t s [ 1 : 0 ] / adc10_trg re gister . 3.4.1 t r igger selection t ab le 21. adts[1:0] t rig g er sour ce 0x3 exter nal tr igger (#adtrg) 0x2 reser v ed 0x1 16-bit timer ch.0 0x0 softw are tr igger (def ault: 0x0) 1. external trig g er (#adtrg) the signal input to the #adtrg pin is used as a trigger . t o use this trigger source, the i/o port pin must be conf igured for the #adtrg input using the port function select bit (see the i/o ports (p) chapter). an a/d con v ersion starts when a f allin g edge of the #adtrg signal is detected. note: when using an e xter nal tr igger to star t a/d con v ersion, ensure to maintain the lo w per iod of the tr igger signal input to the #adtrg pin f or tw o or more s1c17 core oper ating cloc k cycles . 2. 16-bit timer (t16) ch.0 the underflo w signal of t16 ch.0 is used as a trigger . since the t16 underflo w c ycle can be programmed with fle xibility , this trigger source i s ef fecti v e when periodic a/d con v ersions are required. f or more information on timer settings, see the 16-bit t imers (t16) chapter . 3. software trig g er writing 1 to adctl/adc10_ctl re gister with softw are serv es as a trigger to start a/d con v ersion. sampling time setting 21.3.5 the analog signal input sampling time in this a/d con v erter can be conf igured to eight steps (tw o to nine a/d con- v ersio n clock c ycles) using adst[2:0]/adc10_trg re gister . 3.5.1 sampling time settings t ab le 21. adst[2:0] sampling time (in a/d con ver sion c loc k c yc les) 0x7 9 cycles 0x6 8 cycles 0x5 7 cycles 0x4 6 cycles 0x3 5 cycles 0x2 4 cycles 0x1 3 cycles 0x0 2 cycles (def ault: 0x7) the sampling time must satisfy the acquisition time condition (t a cq , time required for acquiring input v oltage). fig- ure 21.3.5.1 sho ws an equi v alent circuit of the analog input portion. 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-5 r s : source impedance r ain : analog input resistance c ain : analog input capacitance av dd v ss r ain r s ainx c ain 3.5.1 equiv alent circuit of analog input p or tion figure 21. determine f adclk and adst[2:0] settings to satisfy the e xpression belo w . t a cq = 8 (r s + r ain ) c ain (see electrical characteristics for the r ain and c ain v alues.) 1 (number of clock c ycles set by adst[2:0]) > t a cq f adclk f adclk : a/d con v ersion clock frequenc y [hz] setting con ver sion result storing mode 21.3.6 the a/d con v erter loa ds the 10-bit con v ersion results into add[15:0]/adc10_add re gister (16-bit re gister) after an a/d con v ersion has completed. at this time, the 10-bit con v ersion results are aligned in the 16-bit re gister ac- cording to the con v ersion result storing mode set with stmd/adc10_trg re gister either as the high-order 10 bits (left justify mode) or the lo w-order 10 bits (right justify mode). the remaining s ix bits are all set to 0. add bit 15 ... 10 9 ... 6 5 ... 0 left justify mode (stmd = 1) (msb) 10-bit con v ersion results (lsb) 0 ... 0 right justify mode (stmd = 0) 0 ... 0 (msb) 10-bit con v ersion results (lsb) 3.6.1 con v ersion data alignment figure 21. a/d con ver sion contr ol and operations 21.4 the a/d con v erter should be controlled in the sequence sho wn belo w . 1. acti v ate the a/d con v erter . 2. start a/d con v ersion. 3. read the a/d con v ersion re sults. 4. t erminate a/d con v ersion. activ ating a/d con ver ter 21.4.1 after the settings described in section 21.3 ha v e been completed, write 1 to aden/adc10_ctl re gister to enable the a/d con v erter . the a/d con v erter is thereby ready to accept a trigger to start a/d con v ersion. t o set up the a/d con v erter ag ain, or when the a/d con v erter is not used, aden must be set to 0. star ting a/d con ver sion 21.4. 2 the a/d con v erter starts a/d con v ersion when a trigger is input while aden is 1. when softw are trigger is select- ed, an a/d con v ersion starts by writing 1 to adctl/adc10_ctl re gister . the a/d con v erter accepts triggers from only the trigger source selected by adts[1:0]/adc10_trg re gister . once a trigger is input, the a/d con v erter starts sampling of the analog input signal and a/d con v ersion be gi nning with the con v ersion start channel selected by adcs[2:0]/adc10_trg re gister . the softw are trigger bit adctl functions as an a/d con v ersion status bit that goes 1 while a/d con v ersion is un- derw ay e v en if it has started by another trigger source. the channel in which con v ersion is underw ay can be identi- f ied by reading adich[2:0]/adc10_ctl re gister . 21 a/d conver ter (adc10) 21-6 seiko epson corporation s1c17554/564 t echnical m anual reading a/d con ver sion results 21.4.3 upon completion of the a/d con v ersion in the start channel, the a/d con v erter loads the con v ersion results into add[15:0]/adc10_add re gister and sets the con v ersion completion flag adcf/adc10_ctl re gister . if mul- tiple channels are specif ied using adcs[2:0]/adc10_trg re gister and adce[2:0]/adc10_trg re gister , the a/ d con v erter continues a/d con v ersions in the subsequent channels. the results of a/d con v ersion are stored in add[15:0] each time con v ersion in one channel is completed. at the same time, a con v ersion completion interrupt can be generated, enabling to read out the con v erted data. if no con- v ersion completion interrupt is used, read the con v ersion results from add[15:0] after conf irming that adcf is set to 1 indicating completion of con v ersion . adcf is reset to 0 when add[15:0] is read. when a single channel or multiple channels are being con v erted continuously , the con v ersion results must be read out from add[15:0] before the follo wing con v ersion has completed. if the a/d con v ersion currently underw ay is completed while adcf is set to 1 (before reading the pre vious con v ersion results), add[15:0] is o v erwritten and the o v erwrite error f lag ado we/adc10_ctl re gister is set to 1. at this time, a con v ersion data o v erwrite error interrupt can be generated. after the con v ersion results are read from add[15:0], ado we should be read to check whether the read data is v alid or not. or enable con v ersion data o v erwrite error interrupts and perform error han- dling using the interrupt. once ado we is set, it will not be reset until softw are wr ites 1. since adcf is also set simultaneously with ado we, read out the con v erted data to reset adcf . note: occurrence of an o v erwr ite error does not stop contin uous con v ersion. t erminating a/d con ver sion 21.4.4 one-time con ver sion mode (adms = 0) in one-time mode, the a/d con v erter performs a/d con v ersion within the channel range successi v ely be ginning with the con v ersion start channel specif ied by adc s[2:0]/adc10_trg re gister and terminates once the con- v ersion end channel specif ied by adce[2:0]/adc10_trg re gister has been completed. adctl/adc10_ctl re gister is reset to 0 upon completion of the con v ersion sequence. contin uous con ver sion mode (adms = 1) in continuous con v ersion mode, the a/d con v erter repeatedly performs a/d con v ersion from the con v ersion start channel to the con v ersion end chan nel. the hardw are does not stop the con v ersion sequence. t o stop a/d con v ersion, write 0 to adctl. since the con v ersion sequence is forcibly terminated, the results of the con v er - sion then underw ay cannot be obtained. timing char ts 21.4.5 figure 21.4.5.1 sho ws the operations of the a/d con v erter . aden trigger adibs a/d operation add[15:0] adcf conversion result read adowe interrupt request ain0 ch.0 ain0 sampling conversion clear ain0 converted data (1) single channel (ain0) one-time con v ersion mode (adcs = 0, adce = 0, adms = 0) 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-7 aden trigger adibs a/d operation add[15:0] adcf conversion result read adowe interrupt request ain0 ch.0 ch.1 ch.2 ain0 sampling conversion ain1 ain1 sampling clear conversion ain2 ain0 converted data ain1 converted data ain2 converted data add[15:0] is overwritten ain2 sampling conversion (2) multi-channel (ain0Cain2) one-time con v ersion mode (adcs = 0, adce = 2, adms = 0) aden trigger adibs a/d operation add[15:0] adcf conversion result read adowe interrupt request ain0 ch.0 ch.0 ch.0 ain0 sampling conversion ain0 ain0 sampling clear clear conversion ain0 converted data ain0 converted data 0 is written to adctl to stop conversion. sampling conversion ain0 invalid (3) single channel (ain0) contin uous con v ersion mode (adcs = 0, adce = 0, adms = 1) aden trigger adibs a/d operation add[15:0] adcf conversion result read adowe interrupt request ain0 ch.0 ch.1 ch.0 ain0 sampling conversion ain1 ain1 sampling clear clear conversion ain0 converted data ain1 converted data 0 is written to adctl to stop conversion. sampling conversion ain0 invalid (4) multi-channel (ain0Cain1) contin uous con v ersion mode (adcs = 0, adce = 1, adms = 1) 4.5.1 a/d con v er ter oper ations figure 21. a/d con ver ter interrupts 21.5 the a/d con v erter includes a function for generating the follo wing tw o dif ferent types of interrupts. ? con v ersion completion interrupt ? con v ersion data o v erwrite error interrupt the a/d con v erter outputs one interrupt signal shared by the tw o abo v e interrupt causes to the interrupt controller (itc). inspect the status flag to determine the interrupt cause occurred. 21 a/d conver ter (adc10) 21-8 seiko epson corporation s1c17554/564 t echnical m anual con ver sion completion interrupt t o use this interrupt, set adcie/adc10_ctl re gister to 1. if adcie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. when a/d con v ersion in a channel has completed, the a/d con v erter sets adcf/adc10_ctl re gister to 1, i n d i c a t i n g t h a t t h e c o n v e r t e d d a t a c a n b e r e a d o u t . i f c o n v e r s i o n c o m p l e t i o n i n t e r r u p t s a r e e n a b l e d ( a d c i e = 1 ) , a n interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect adcf in the adc10 interrupt handler routine to determine whether the adc10 interrupt is attrib utable to a completion of con v ersion. if adcf is 1, the con v erted data can be read out from add[15:0]/ a d c10_ a d d r e g i s t e r b y t h e i n t e r r u p t h a n d l e r r o u t i n e . t h e i n t e r r u p t c a u s e a d c f i s r e s e t t o 0 b y r e a d i n g add[15:0] and this interrupt will not be generated until the subsequent con v ersion has completed. con ver sion data o verwrite err or interrupt t o use this interrupt, set adoie/adc10_ctl re gister to 1. if adoie is set to 0 (def ault), interrupt requests for this cause will not be sent to the itc. if the follo wing a/d con v ersion has completed when add[15:0] has not been rea d (adcf = 1), the a/d con- v erter sets ado we/adc10_ctl re gister to 1, indicating that add[15:0] is o v erwritten. if con v ersion data o v erwrite error interrupts are enabled (adoie = 1), an interrupt request is sent simultaneously to the itc. an interrupt occurs if other interrupt conditions are met. y ou can inspect ado we in the adc10 interrupt handler routine to determine whether the adc10 interrupt is attrib utable to an o v erwrite error . if ado we is 1, perform error handling by the interrupt handler routine. the interrupt cause ado we is reset to 0 by writing 1. f or more information on interrupt processing, see the interrupt controller (itc) chapter . notes: ? t o pre v ent interr upt recurrences , the adcf/adc10_ctl register and ado we/adc10_ctl register m ust be reset in the interr upt handler routine af ter an adc10 interr upt has occurred. ? t o pre v ent unw anted interr upts , reset adcf and ado we bef ore enab ling interr upts with ad- cie/adc10_ctl register and adoie/adc10_ctl register . contr ol register details 21.6 6.1 list of adc10 registers t ab le 21. ad dress register name function 0x5380 adc10_add a/d con v ersion result register a/d con v er ted data 0x5382 adc10_trg a/d t r igger/channel select register sets star t/end channels and con v ersion mode . 0x5384 adc10_ctl a/d control/status register controls a/d con v er ter and indicates con v ersion status . 0x5386 adc10_clk a/d cloc k control register controls a/d con v er ter cloc k. 0x5388 adc10_com a/d compar ator setting register ad justs a/d con v ersion char acter istics . the a/d con v erter re gisters are described in detail belo w . these are 16-bit re gisters. note: when data is wr itten to the registers , the reser v ed bits m ust alw a ys be wr itten as 0 and not 1. a/d conversion result register (adc10_add) register name ad dress bit name function setting init. r/w remarks a/d conversion result register (adc10_add) 0x5380 (16 bits) d15C0 add[15:0] a/d con v er ted data add[9:0] are eff ectiv e when stmd = 0 (add[15:10] = 0) add[15:6] are eff ectiv e when stmd = 1 (add[5:0] = 0) 0x0 to 0x3ff 0x0 r d[15:0] add[15:0]: a/d converted data bits the a/d con v ersion results are stored. (def ault: 0x0) the data alignment in this 16-bit re gister (con v ersion result storing mode) can be selected using the stmd/adc10_trg re gister . 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-9 add bit 15 ... 10 9 ... 6 5 ... 0 left justify mode (stmd = 1) (msb) 10-bit con v ersion results (lsb) 0 ... 0 right justify mode (stmd = 0) 0 ... 0 (msb) 10-bit con v ersion results (lsb) 6.1 con v ersion data alignment figure 21. this re gister is a read-only , so writing to this re gister is ignored. a/d trigger/channel select register (adc10_trg) register name ad dress bit name function setting init. r/w remarks a/d trigger/ channel select register (adc10_trg ) 0x5382 (16 bits) d15C14 C reser v ed C C C 0 when being read. d13C11 adce[2:0] end channel select 0x0 to 0x3 0x0 r/w d10C8 adcs[2:0] star t channel select 0x0 to 0x3 0x0 r/w d7 stmd con v ersion result stor ing mode 1 add[15:6] 0 add[9:0] 0 r/w d6 adms con v ersion mode select 1 contin uous 0 single 0 r/w d5C4 adts[1:0] con v ersion tr igger select adts[1:0] t r igger 0x0 r/w 0x3 0x2 0x1 0x0 #adtrg pin reser v ed t16 ch.0 softw are d3 C reser v ed C C C 0 when being read. d2C0 adst[2:0] sampling time setting adst[2: 0] sampling time 0x7 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles d[15:14] reserved d[13:11] adce[2:0]: end channel select bits sets the con v ersion end channel with a channel number from 0 to 3. (def ault: 0x0 = ain0) a n a l o g i n p u t s c a n b e a / d - c o n v e r t e d c o n t i n u o u s l y f r o m t h e c h a n n e l s e t b y a d c s [ 2 : 0 ] t o t h e c h a n n e l s e t by adce[2:0] in one a/d con v ersion. if only one channel is to be a/d con v erted, set the same chann el number in both adcs[2:0] and adce[2:0]. 6.2 relationship betw een adcs/adce and input channels t ab le 21. adcs[2:0]/adce[2:0] channel selected 0x7C0x4 reser v ed 0x3 ain3 0x2 ain2 0x1 ain1 0x0 ain0 (def ault: 0x0) d[10:8] adcs[2:0]: start channel select bits sets the con v ersion start channel with a channel number from 0 to 3. (def ault: 0x0 = ain0) d7 stmd: conversion result storing mode bit selects the data alignment when the con v ersion results are loaded into add[15:0]. 1 (r/w): left justify mode (10-bit con v ersion results add[15:6], add[5:0] = 0) 0 (r/w): right justify mode (10-bit con v ersion res ults add[9:0], add[15:10] = 0) (def ault) d6 adms: conversion mode select bit selects an a/d con v ersion mode. 1 (r/w): continuous con v ersion mode 0 (r/w): one-time con v ersion mode (def ault) writing 1 to adms sets the a/d con v erter to continuous con v ersion mode. in this mode, a/d con v er - sions in the range of the channels selected by adcs[2:0] and adce[2:0] are e x ecuted continuously until stopped with softw are. when adms is 0, the a/d con v erter operates in one-time con v ersion mode. in this mode, a/d con v er - sion is terminated after all inputs in the range of the channels selected by adcs[2:0] and adce[2:0] ha v e been con v erted once. 21 a/d conver ter (adc10) 21-10 seiko epson corporation s1c17554/564 t echnical m anual d[5:4] adts[1:0]: conversion trigger select bits selects a trigger source to start a/d con v ersion. 6.3 t r igger selection t ab le 21. adts[1:0] t rig g er sour ce 0x3 exter nal tr igger (#adtrg) 0x2 reser v ed 0x1 16-bit timer ch.0 0x0 softw are tr igger (def ault: 0x0) when an e xternal trigger is used, the #adtrg pin must be conf igured in adv ance using the port func- tion select bit (see the i/o ports (p) chapter). a/d con v ersion is started when a f alling edge of the #adtrg signal is detected. when 16-bit timer (t16) ch.0 is used, since its u nderflo w signal serv es as a trigger , set the underflo w c ycle and other conditions for the timer . d3 reserved d[2:0] adst[2:0]: sampling time setting bits sets the analog input sampling time. 6.4 sampling time settings t ab le 21. adst[2:0] sampling time (in a/d con ver sion c loc k c yc les) 0x7 9 cycles 0x6 8 cycles 0x5 7 cycles 0x4 6 cycles 0x3 5 cycles 0x2 4 cycles 0x1 3 cycles 0x0 2 cycles (def ault: 0x7) a/d control/status register (adc10_ctl) register name ad dress bit name function setting init. r/w remarks a/d control/ status register (adc10_ctl ) 0x5384 (16 bits) d15 C reser v ed C C C 0 when being read. d14C12 adich[2:0] con v ersion channel indicator 0x0 to 0x3 0x0 r d11 C reser v ed C C C 0 when being read. d10 adibs adc10 status 1 busy 0 idle 0 r d9 adowe ov erwr ite error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d8 adcf con v ersion completion flag 1 completed 0 run/stand- b y 0 r r e s e t w h e n a d c 1 0 _ add is read. d7C6 C reser v ed C C C 0 when being read. d5 adoie ov erwr ite error interr upt enab le 1 enab le 0 disab le 0 r/w d4 adcie con v ersion completion int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 adctl a/d con v ersion control 1 star t 0 stop 0 r/w d0 aden adc10 enab le 1 enab le 0 disab le 0 r/w d15 reserved d[14:12] adich[2:0]: conversion channel indicator bits indicates the channel number (0 to 3) currently being a/d-con v erted. (def ault: 0x0 = ain0) when a/d con v ersion is performed in multiple channels, read this bit to identify the channel in which con v ersion is underw ay . d11 reserved 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-11 d10 adibs: adc10 status bit indicates the a/d con v erter status. 1 (r): being con v erted 0 (r): con v ersion completed/standby (def ault) adibs is set to 1 at the input trigger signal edge (at the be ginning of sampling) and is reset to 0 upon completion of con v ersion (when adctl is set to 0). d9 adowe: overwrite error flag bit indicates that the con v erted results in add[15:0]/adc10_add re gister ha v e been o v erwritten before reading. 1 (r): ov erwrite error (caus e of interrupt has occurred) 0 (r): normal (cause of interrupt has not occurred) (def ault) 1 (w): flag is reset 0 (w): ignored w h e n a s i n g l e c h a n n e l o r m u l t i p l e c h a n n e l s a r e b e i n g c o n v e r t e d c o n t i n u o u s l y , a d d [ 1 5 : 0 ] i s o v e r w r i t t e n and ado we is set to 1 if the a/d con v ersion currently underw ay is completed while adcf is set to 1 (before reading the pre vious con v ersion results). after the con v ersion r esults are read from add[15:0], ado we should be read to check whether the read data is v alid or not. ado we is a cause of adc10 interrupt. when ado we is set to 1, a con v ersion data o v erwrite error interrupt request is output to the itc if adoie has been set to 1 (interrupt enabled). an interrupt is generated if the itc and s1c17 core interrupt conditions are satisf ied. ado we is reset by writing 1. d8 adcf: conversion completion flag bit indicates that a/d con v ersion has been completed. 1 (r): con v ersion completed (cause of interrupt has occurred) 0 (r): being con v erted/standby (cause of interrupt has not occurred) (def ault) adcf is set to 1 when a/d con v ersion is completed, and the con v erted data is loaded into add[15:0]/ adc10_add re gister . adcf is a cause of adc10 interrupt. when adcf is set to 1, a con v ersion completion interr upt re- q u e s t i s o u t p u t t o t h e i t c i f a d c i e h a s b e e n s e t t o 1 ( i n t e r r u p t e n a b l e d ) . a n i n t e r r u p t i s g e n e r a t e d i f t h e itc and s1c17 core interrupt conditions are satisf ied. adcf is reset to 0 by reading add[15:0]. an o v erwrite error occurs if the ne xt a/d con v ersion is completed while adcf is set (see ado we abo v e), adcf must be reset by reading add[15:0] before an o v erwrite occurs. when an o v erwrite error oc- curs, adcf is also set due to completion of con v ersion. d[7:6] reserved d5 adoie: overwrite error interrupt enable bit enables or disables interrupts caused by occurrences of con v ersion data o v erwrite errors. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting adoie to 1 enables con v ersion data o v erwrite error interrupt requests to the itc; setting to 0 disables interrupts. d4 adcie: conversion completion interrupt enable bit enables or disables interrupts caused by completion o f con v ersion. 1 (r/w): interrupt enabled 0 (r/w): interrupt disabled (def ault) setting adcie to 1 enables con v ersion completion interrupt requests to the itc; setting to 0 disables interrupts. d[3:2] reserved 21 a/d conver ter (adc10) 21-12 seiko epson corporation s1c17554/564 t echnical m anual d1 adctl: a/d conversion control bit controls a/d con v ersion. 1 (w): softw are trigger 0 (w): stop a/d con v ersion 1 (r): being con v erted 0 (r): con v ersion completed/standby (def ault) write 1 to adctl to start a/d con v ersion by a softw are trigger . if an y other trigger is used, adctl is automatically set to 1 by the hardw are. adctl remains set while a/d con v ersion is underw ay . in one-time con v ersion mode, upon completion of a/d con v er sion in the specif ied channels, adctl is reset to 0 and the a/d con v ersion circuit stops operating. t o stop a/d con v ersion during operation in continuous con v ersion mode, reset adctl by writing 0. when aden is 0 (a/d con v ersion disabled), adctl is f ix ed to 0, with no trigger accepted. d0 aden: adc10 enable bit enables or disables the a/d con v erter operations. 1 (r/w): enabled 0 (r/w): disabled (def ault) writing 1 to aden enables the a/d con v erter , meaning it is ready to start a/d con v ersion (i.e., ready to accept a trigger). when aden is 0, the a/d con v erter is disabled, meaning it is unable to accept a trigger . before setting the modes, start/end channels, or other a/d con v erter conditions, be sure to reset aden to 0. this helps to pre v ent the a/d con v erter from operating erratically . a/d clock control register (adc10_clk) register name ad dress bit name function setting init. r/w remarks a/d clock control register (adc10_clk) 0x5386 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 addf[3:0] a/d con v er ter cloc k division r atio select addf[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/32768 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 d[15:4] reserved d[3:0] addf[3:0]: a/d converter clock division ratio select bits selects a pclk di vision ratio to generate the a/d con v erter clock. 21 a/d conver ter (adc10) s1c17554/564 t echnical m anual seiko epson corporation 21-13 6.5 a/d con v ersion cloc k (pclk division ratio) selection t ab le 21. addf[3:0] division ratio 0xf reser v ed 0x e 1/32768 0xd 1/16384 0xc 1/8192 0xb 1/4096 0xa 1/2048 0x9 1/1024 0x8 1/512 0x7 1/256 0x6 1/128 0x5 1/64 0x4 1/32 0x3 1/16 0x2 1/8 0x1 1/4 0x0 1/2 (def ault: 0x0) note: t o use the a/d con v er ter , the cloc k used in the a/d con v er ter m ust be supplied b y tur ning on the per ipher al module cloc k (pclk) output from the cloc k gener ator (clg). a/d comparator setting register (adc10_com) register name ad dress bit name function setting init. r/w remarks a/d comparator setting register (adc10_com ) 0x5388 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 fsel[1:0] a/d compar ator adjustment 0x0 to 0x3 0x0 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 xpd[1:0] a/d compar ator adjustment 0x0 to 0x3 0x3 r/w d[15:6], d[3:2] reserved d[5:4], d[1:0] fsel[1:0], xpd[1:0]: a/d comparator adjustment bits adjusts the comparator for optimal a/d con v ersion according to the a/d operating v oltage used. 6.6 a/d compar ator adjustment t ab le 21. a v dd rang e fsel[1:0] xpd[1:0] 3.3 to 2.7 v 2 3 3.6 to 3.0 v 3 2 4.3 to 3.3 v 0 3 5.0 to 4.0 v 2 1 5.5 to 4.7 v 0 2 22 on-chip deb ugger (dbg) s1c17554/564 t echnical m anual seiko epson corporation 22-1 on-chip deb ugger (dbg) 22 resour ce requirements and deb ug ging t ools 22.1 deb ug ging w ork area deb ugging requires a 64-byte deb ugging w ork area. f or more information on the w ork area location, see the memory map, bus control chapter . the start address for this deb ugging w ork area can be read from the dbram re gister (0xf f f f90). deb ug ging tools deb ugging in v olv es connecting icdmini to the s1c17554/56 4 deb ug pins and inputting the deb ug instruction from the deb ugger on the personal computer . the follo wing tools are required: ? s1c17 f amily in-circuit deb ugger icdmini ? s1c17 f amily c compiler package (e.g., s5u1c17001c) deb ug pins the follo wing deb ug pins are used to connect icdmini. 1.1 list of deb ug pins t ab le 22. pin name i/o qty function dclk o 1 on-chip deb ugger cloc k output pin outputs a cloc k to the icdmini. dsio i/o 1 on-chip deb ugger data input/output pin used to input/output deb ugging data and input the break signal. dst2 o 1 on-chip deb ugger status signal output pin outputs the processor status dur ing deb ugging. the on-chip deb ugger input/output pins (dclk, dst2, dsio) are shared with i/o ports and are initially set as the deb ug pins. if the deb ugging function is not used, these pins can be switched using the port function select bits to enable use as general-purpose i/o port pins. f or detailed information on pin function switching, see the i/o ports (p) chapter . deb ug break operation status 22.2 the s1c17 core enters deb ug mode when the brk instruction is e x ecuted or a deb ug interrupt is generated by a bre ak signal (lo w) input to the dsio pin. this state persists until the retd instruction is e x ecuted. during this time, hardw are interrupts and nmis are disabled. the def ault setting halts peripheral circuit operations. this setting can be modif ied e v en when deb ugging is under - w ay . the peripheral circuits that operate with pclk will continue running in deb ug mode by setting dbr un1/misc_ dmode1 re gister to 1. setting dbr un1 to 0 (def ault) will stop these peripheral circuits in deb ug mode. the peripheral circuits that operate with a clock other than pclk will continue running in deb ug mode by setting dbr un2/misc_dmode2 re gister to 1. setting dbr un2 to 0 (def ault) will stop these peripheral circuits in de- b ug mode. some peripheral circuits, such as spi, i2cs, and t16a, that run with an e xternal inpu t clock will not stop operating e v en if the s1c17 core enters deb ug mode. 22 on-chip deb ugger (dbg) 22-2 seiko epson corporation s1c17554/564 t echnical m anual ad ditional deb ug ging function 22.3 the s1c17554/564 e xpands the follo wing on-chip deb ugging functions of the s1c17 core. branc hing destination in deb ug mode when a deb ug interrupt is generated, the s1c17 core enters deb ug mode and branches to the deb ug processing routine. in this process, the s1c17 core is designed to branch to address 0xf f fc00. in addition to this branching destination, the s1c175 54/564 also allo ws designation of address 0x0 (be ginning address of the internal ram) as the branching destination when deb ug mode is acti v ated. the branching destination address is selected using db adr/misc_iramsz re gister . when the db adr is set to 0 (def ault), the branching destination is set to 0xf f fc00. when it is set to 1, the branching destination is set to 0x0. ad ding instruction breaks t h e s1c17 c o r e s u p p o r t s t w o i n s t r u c t i o n b r e a k s ( h a r d w a r e p c b r e a k s ) . t h e s1c17554/564 i n c r e a s e d t h i s number to f i v e, adding the control bits and re gisters gi v en belo w . ? ibe2/dcr re gister: enables instruction breaks #2. ? ibe3/dcr re gister: enables instruction breaks #3. ? ibe4/dcr re gister: enables instruction breaks #4. ? ib ar2[23:0]/ib ar2 re gister: set instruction break address #2. ? ib ar3[23:0]/ib ar3 re gister: set instruction break address #3. ? ib ar4[23:0]/ib ar4 re gister: set instruction break address #4. note that the deb ugger included in the s5u1c17001c (v er . 1.2.1) or later is required to use f i v e hardw are pc breaks. contr ol register details 22.4 4.1 list of deb ug registers t ab le 22. ad dress register name function 0x4020 misc_dmode1 deb ug mode control register 1 enab les per ipher al oper ations in deb ug mode (pclk). 0x5322 misc_dmode2 deb ug mode control register 2 enab les per ipher al oper ations in deb ug mode (e xcept pclk). 0x5326 misc_iramsz iram siz e select register selects the iram siz e . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register c ontrols deb ugging. 0xffffb8 ibar2 instr uction break address register 2 sets instr uction break address #2. 0xffffbc ibar3 instr uction break address register 3 sets instr uction break address #3. 0xffffd0 ibar4 instr uction break address register 4 sets instr uction break address #4. the deb ug re gisters are described in detail belo w . notes: ? w h e n d a t a i s w r i t t e n t o t h e r e g i s t e r s , t h e r e s e r v e d b i t s m u s t a l w a y s b e w r i t t e n a s 0 a n d n o t 1 . ? f or deb ug registers not descr ibed here , ref er to the s1c17 core man ual. debug mode control register 1 (misc_dmode1) register name ad dress bit name function setting init. r/w remarks debug mode control register 1 (misc_dmode1) 0x4020 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 dbrun1 run/stop select in deb ug mode 1 run 0 stop 0 r/w d0 C reser v ed C C C 0 when being read. d[7:2] reserved d1 dbrun1: run/stop select bit in debug mode selects the operating status of the peripheral circuits that operate with pclk in deb ug mode. 1 (r/w): run 0 (r/w): stop (def ault) 22 on-chip deb ugger (dbg) s1c17554/564 t echnical m anual seiko epson corporation 22-3 setting dbr un1 to 1 enables the peripheral circuits that operate with pclk to run e v en in deb ug mode. setting it to 0 will stop them when the s1c17 core enters deb ug mode. set dbr un1 to 1 to maintain running status for these peripheral circuits in deb ug mode. d0 reserved debug mode control register 2 (misc_dmode2) register name ad dress bit name function setting init. r/w remarks debug mode control register 2 (misc_dmode2) 0x5322 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 dbrun2 run/stop select in deb ug mode (e xcept pclk per ipher al circuits) 1 run 0 stop 0 r/w d[15:1] reserved d0 dbrun2: run/stop select bit in debug mode (except pclk peripheral circuits) selects the operating status of the peripheral circuits that operate with a clock other than pclk in deb ug mode. 1 (r/w): run 0 (r/w): stop (def ault) s e t t i n g d b r u n2 t o 1 e n a b l e s t h e p e r i p h e r a l c i r c u i t s t h a t o p e r a t e w i t h a c l o c k o t h e r t h a n p c l k t o run e v en in deb ug mode. setting it to 0 will stop them when the s1c17 core enters deb ug mode. set dbr un2 to 1 to maintain running status for these peripheral circuits in deb ug mode. s ome peripheral circuits, such as spi, i2cs, and t16a, that run with an e xternal input clock will not stop operating e v en if the s1c17 core enters deb ug mode. iram size select register (misc_iramsz) register name ad dress bit name function setting init. r/w remarks iram size register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x6 (= 16kb) 0x6 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x6 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 16kb 512b 1kb 2kb 4kb 8kb 12kb d[15:9] reserved d8 dbadr: debug base address select bit selects the branching destination address when a deb ug interrupt occurs. 1(r/w): 0x0 0(r/w): 0xf f fc00 ( def ault) d7 reserved d[6:4] iramactsz[2:0]: iram actual size bits indicates the actual internal ram size embedded. (def ault: 0x6) d3 reserved d[2:0] iramsz[2:0]: iram size select bits selects the size of the internal ram to be used. 22 on-chip deb ugger (dbg) 22-4 seiko epson corporation s1c17554/564 t echnical m anual 4.2 inter nal ram siz e selection t ab le 22. iramsz[2:0] internal ram siz e 0x7 reser v ed 0x6 16kb 0x5 512b 0x4 1kb 0x3 2kb 0x2 4kb 0x1 8kb 0x0 12kb (def ault: 0x6) note: the misc_iramsz register is wr ite-protected. t o alter this register settings , y ou m ust o v err ide this wr ite-protection b y wr iting 0x96 to the misc_pr o t register . nor mally , the misc_pr o t reg- ister should be set to a v alue other than 0x96, e xcept when alter ing the misc_iramsz register . unnecessar y re w r iting of the misc_iramsz register ma y result in system malfunctions . debug ram base register (dbram) register name ad dress bit name function setting init. r/w remarks debug ram base register (dbram) 0xffff90 (32 bits) d31C24 C un used (fix ed at 0) 0x0 0x0 r d23C0 dbram[23:0] deb ug ram base address 0x2fc0 0x2f c0 r d[31:24] not used (fixed at 0) d[23:0] dbram[23:0]: debug ram base address bits read-only re gister containing the be ginning address of the deb ugging w ork area (64 bytes). debug control register (dcr) register name ad dress bit name function setting init. r/w remarks debug control register (dcr) 0xffffa0 (8 bits) d7 ibe4 instr uction break #4 enab le 1 enab le 0 disab le 0 r/w d6 ibe3 instr uction break #3 enab le 1 enab le 0 disab le 0 r/w d5 ibe2 instr uction break #2 enab le 1 enab le 0 disab le 0 r/w d4 dr deb ug request flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. d3 ibe1 instr uction break #1 enab le 1 enab le 0 disab le 0 r/w d2 ibe0 instr uction break #0 enab le 1 enab le 0 disab le 0 r/w d1 se single step enab le 1 enab le 0 disab le 0 r/w d0 dm deb ug mode 1 d e b u g m o d e 0 user mode 0 r d7 ibe4: instruction break #4 enable bit enables or disables instruction break #4. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar4 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d6 ibe3: instruction break #3 enable bit enables or disables instruction break #3. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar3 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d5 ibe2: instruction break #2 enable bit enables or disables instruction break #2. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar2 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. 22 on-chip deb ugger (dbg) s1c17554/564 t echnical m anual seiko epson corporation 22-5 d4 dr: debug request flag bit indicates the presence or absence of an e xternal deb ug request. 1 (r): request generated 0 (r): request not generated (def ault) 1 (w): flag is reset 0 (w): ignored this flag is cleared (reset to 0) when 1 is written. it must be cleared before the deb ug processing routine is terminated by the retd instruction. d3 ibe1: instruction break #1 enable bit enables or disables instruction break #1. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar1 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d2 ibe0: instruction break #0 enable bit enables or disables instruction break #0. 1 (r/w): enabled 0 (r/w): disabled (def ault) if this bit is set to 1, the instruction fetch address and the v alue set in the ib ar0 re gister are compared. if the y match, an instruction break is generated. if this bit is set to 0, no comparison is performed. d1 se: single step enable bit enables or disables single-step operations. 1 (r/w): enabled 0 (r/w): disabled (def ault) d0 dm: debug mode bit indicates the processor operating mode (deb ug mode or user mode). 1 (r): deb ug mode 0 (r): user mode (def ault) instruction break address register 2 (ibar2) register name ad dress bit name function setting init. r/w remarks instruction break address register 2 (ibar2) 0xffffb8 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar2[23:0] instr uction break address #2 ibar223 = msb ibar20 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar2[23:0]: instruction break address #2 bits sets instruction break address #2. (def ault: 0x000000) instruction break address register 3 (ibar3) register name ad dress bit name function setting init. r/w remarks instruction break address register 3 (ibar3) 0xffffbc (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar3[23:0] instr uction break address #3 ibar323 = msb ibar30 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar3[23:0]: instruction break address #3 bits sets instruction break address #3. (def ault: 0x000000) 22 on-chip deb ugger (dbg) 22-6 seiko epson corporation s1c17554/564 t echnical m anual instruction break address register 4 (ibar4) register name ad dress bit name function setting init. r/w remarks instruction break address register 4 (ibar4) 0xffffd0 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar4[23:0] instr uction break address #4 ibar423 = msb ibar40 = lsb 0x0 to 0xffffff 0x0 r/w d[31:24] reserved d[23:0] ibar4[23:0]: instruction break address #4 bits sets instruction break address #4. (def ault: 0x000000) 23 mul tiplier/divider (copr o) s1c17554/564 t echnical m anual seiko epson corporation 23-1 multiplier/di vider (copr o) 23 over vie w 23.1 the s1c17554/564 has an embedded coprocessor that pro vides multiplier/di vider functions. the follo wing sho ws the features of the multiplier/di vider: ? multiplication: supports signed/unsigned multiplications. (16 bits 16 bits = 32 bits) can be e x ecuted in 1 c ycle. ? multiplication and accumulation (ma c): supports signed ma c operations with o v erflo w det ection function (16 bits 16 bits + 32 bits = 32 bits) can be e x ecuted in 1 c ycle. ? di vision: supports signed/unsigned di visions. (16 bits 16 bits = 16 bits with 16-bit residue) can be e x ecuted in 17 to 20 c ycles. s1c17 core ar ithmetic unit operation result register mode setting selector argument 2 argument 1 coprocessor output flag output operation result 1.1 multiplier/divider bloc k diag r am figure 23. operation mode and output mode 23.2 the multiplier/di vider operates according to the operation mode specif ied by the application program. as listed in t able 23.2.1, the multiplier/di vider supports nine operations. the multiplication, di vision and ma c results are 32-bit data, therefore, the s1c17 core cannot read them in one access c ycle. the output mod e is pro vided to specify the high-order 16 bits or lo w-order 16 bits of the operation results to be read from the multiplier/di vider . the operation and output modes can be specif ied with a 7-bit data by writing it to the mode setting re gister in the multiplier/di vider . use a ld.cw instruction for this writing. ld.cw %rd,%rs %rs[6:0] is written to the mode setting re gister . (%rd: not used) ld.cw %rd,imm7 imm7[6:0] is written to the mode setting re gister . (%rd: not used) 6 4 3 0 output mode setting v alue oper ation mode setting v alue 2.1 mode setting register figure 23. 23 mul tiplier/divider (copr o) 23-2 seiko epson corporation s1c17554/564 t echnical m anual 2.1 mode settings t ab le 23. setting v alue (d[6:4]) output mode setting v alue (d[3:0]) operation mode 0x0 16 low-order bits output mode t h e l o w - o r d e r 16- b i t s o f o p e r a t i o n r e s u l t s can be read as the coprocessor output. 0x0 initialize mode 0 clears the oper ation result register to 0x0. 0x1 16 high-order bits output mode t h e h i g h - o r d e r 16- b i t s o f o p e r a t i o n r e s u l t s can be read as the coprocessor output. 0x1 initialize mode 1 l o a d s t h e 16- b i t a u g e n d i n t o t h e l o w - o r d e r 16 bits of the oper ation result register . 0x2C0x7 reser v ed 0x2 initialize mode 2 l o a d s t h e 32- b i t a u g e n d i n t o t h e o p e r a t i o n result register . 0x3 operation result read mode outputs the data in the oper ation result reg- ister without computation. 0x4 unsigned multiplication mode p erf or ms unsigned m ultiplication. 0x5 signed multiplication mode p erf or ms signed m ultiplication. 0x6 reser v ed 0x7 signed mac mode p erf or ms signed ma c oper ation. 0x8 unsigned division mode p erf or ms unsigned division. 0x9 signed division mode p erf or ms signed division. 0xaC0xf reser v ed multiplication 23.3 the multiplication function performs a (32 bits) = b (16 b its) c (16 bits). t o perform a multiplication, set the operation mode to 0x4 (unsigned multiplication) or 0x5 (signed multiplication). then send the 16-bit multiplicand (b) and 16-bit multiplier (c) to the multiplier/di vider using a ld.ca instruc- tion. the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status will be returned to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits coprocessor output (16 bits) flag output operation result 3.1 data p ath in multiplication mode figure 23. 23 mul tiplier/divider (copr o) s1c17554/564 t echnical m anual seiko epson corporation 23-3 3.1 oper ation in multiplication mode t ab le 23. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x04 or 0x05 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[15:0] psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k eeps the oper ation result until i t i s r e w r i t t e n b y o t h e r o p e r a - tion. (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[15:0] 0x14 or 0x15 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[31:16] (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[31:16] res: oper ation result register example: ld.cw %r0,0x4 ; sets the modes unsigned multiplication mode and 16 lo w-order bits output mode. ld.ca %r0,%r1 ; performs res = %r0 ld.cw %r0,0x13 ; sets the modes operation result read mode and 16 high-order bits output mode. ld.ca %r1,%r0 ; loads the 16 high-order bits of the result to %r1. division 23.4 the di vision function performs b (16 bits) ld.ca instruction. the quotient and the residue will be stored in the lo w-order 16 bits and the high-order 16 bits of the operation result re gister , respec- ti v ely . the 16-bit quotient or residue according to the output m ode specif ication and the flag status will be returned to the cpu re gisters. another 16-bit result should be read by setting the multiplier/di vider into operation result read mode. s1c17 core operation result register selector argument 2 argument 1 16 bits 16 bits coprocessor output (16 bits) flag output operation result 4.1 data p ath in division mode figure 23. 4.1 oper ation in division mode t ab le 23. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x08 or 0x09 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[15:0] (quotient) psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k eeps the oper ation result until i t i s r e w r i t t e n b y o t h e r o p e r a - tion. (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[15:0] (quotient) 0x018 or 0x19 ld.ca %rd,%rs res[31:0] %rd %rs %rd res[31:16] (residue) (ext imm9) ld.ca %rd,imm7 res[31:0] %rd imm7/16 %rd res[31:16] (residue) res: o per ation result register 23 mul tiplier/divider (copr o) 23-4 seiko epson corporation s1c17554/564 t echnical m anual example: ld.cw %r0,0x8 ; sets the modes (unsigned di vision mode and 16 lo w-order bits output mode). ld.ca %r0,%r1 ; performs res = %r0 %r1 and loads the 16 lo w-order bits of the result (quotient) to %r0. ld.cw %r0,0x13 ; sets the modes (operation result read mode and 16 high-order bits output mode). ld.ca %r1,%r0 ; loads the 16 high-order bits of the result (residue) to %r1. ma c 23.5 the ma c (multiplication and accumulation) function performs a (32 bits) = b (16 bits) c (16 bits) + a (32 bits). before performing a ma c operation, the initial v alue (a) must be set to the operation result re gister . t o clear the operation result re gister (a = 0), just set the operation mode to 0x0. it is not necessary to send 0x0 to the multiplier/di vider with another instruction. t o load a 16-bit v alue or a 32-bit v alue to the operation result re gister , se t the operation mode to 0x1 (16 bits) or 0x2 (32 bits), respecti v ely . then send the initial v alue to the multiplier/di vider using a ld.cf instruction. s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits coprocessor output (16 bits) flag output 5.1 data p ath in initializ e mode figure 23. 5.1 initializing the oper ation result register t ab le 23. m o d e s e t t i n g v alue instruction operations remarks 0x0 C res[31:0] 0x0 setting the oper ating mode e x ecutes the initialization without sending data. 0x1 ld.cf %rd,%rs res[31:16] 0x0 res[15:0] %rs (ext imm9) ld.cf %rd,imm7 res[31:16] 0x0 res[15:0] imm7/16 0x2 ld.cf %rd,%rs res[31:16] %rd res[15:0] %rs (ext imm9) ld.cf %rd,imm7 res[31:16] %rd res[15:0] imm7/16 res: oper ation result register t o perform a ma c operation, set the operation mode to 0x7 (signed ma c). then send t he 16-bit multiplicand (b) and 16-bit multiplier (c) to the multiplier/di vider using a ld.ca instruction. the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status will be returned to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. the o v erflo w (v) flag in the psr may be set to 1 according to the result. other flags are set to 0. when repeating the ma c operation without operation result read mode inserted, send multiplicand and multiplier data for number of required times. in this case it is not necessary to set the ma c mode e v ery time. 23 mul tiplier/divider (copr o) s1c17554/564 t echnical m anual seiko epson corporation 23-5 s1c17 core operation result register selector argument 2 argument 1 16 bits 32 bits 32 bits coprocessor output (16 bits) flag output operation result 5.2 data p ath in ma c mode figure 23. 5.2 oper ation in ma c mode t ab le 23. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x07 ld.ca %rd,%rs res[31:0] %rd %rs + res[31:0] %rd res[15:0] psr (cvzn) 0b0100 if an o v erflo w has oc- curred otherwise psr (cvzn) 0b0000 t h e o p e r a t i o n r e s u l t r e g i s t e r k e e p s t h e o p e r a t i o n r e s u l t u n - t i l i t i s r e w r i t t e n b y other oper ation. (ext imm9) ld.ca %rd,imm7 r e s [ 3 1 : 0 ] % r d imm7/16 + r e s [ 3 1 : 0 ] %rd res[15:0] 0x17 ld.ca %rd,%rs res[31:0] %rd %rs + res[31:0] %rd res[31:16] (ext imm9) ld.ca %rd,imm7 r e s [ 3 1 : 0 ] % r d imm7/16 + r e s [ 3 1 : 0 ] %rd res[31:16] res: oper ation result register example: ld.cw %r0,0x7 ; sets the modes signed ma c mode and 16 lo w-order bits output mode. ld.ca %r0,%r1 ; performs res = %r0 ld.cw %r0,0x13 ; sets the modes operation result read mode and 16 high-order bits output mode. ld.ca %r1,%r0 ; loads the 16 high-order bits of the result to %r1. conditions to set the o verflo w (v) fla g an o v erflo w occurs in a ma c operation and the o v erflo w flag is set to 1 when the signs of the multiplication result, operation result re gister v alue, and multiplication & accumulation result match the follo wing conditions: 5.3 conditions to set the ov erflo w (v) flag t ab le 23. mode setting v alue sign of m ultiplication result sign of operation result register v alue sign of m ultiplication & ac- cum ulation result 0x07 0 (positiv e) 0 (positiv e) 1 (negativ e) 0x07 1 (negativ e) 1 (negativ e) 0 (positiv e) an o v erflo w occurs when a ma c operation performs addition of positi v e v alues and a ne g ati v e v alue results, or it performs addition of ne g ati v e v alues and a positi v e v alue results. the copr ocessor holds the operation result when the o v erflo w (v) flag is cleared. conditions to c lear the o verflo w (v) fla g the o v erflo w (v) flag that has been set will be cleared when an o v erflo w has not been occurred during e x ecu- tion of the ld.ca instruction for ma c operation or when the ld.ca or ld.cf instruction is e x ecuted in an operation mode other than operation result read mode. 23 mul tiplier/divider (copr o) 23-6 seiko epson corporation s1c17554/564 t echnical m anual reading results 23.6 t h e ld.ca i n s t r u c t i o n c a n n o t l o a d a 3 2 - b i t o p e r a t i o n r e s u l t t o a c p u r e g i s t e r , s o a m u l t i p l i c a t i o n o r m a c o p e r a - tion returns the one-half (16 bits according to the output mode) result (a[15:0] or a[31:16]) and the flag status to the cpu re gisters. another one-half should be read by setting the multiplier/di vider into operation result read mode. the operation result re gister k eep s the loaded operation result until it is re written by other operation. s1c17 core operation result register selector argument 2 argument 1 coprocessor output (16 bits) flag output 6.1 data p ath in oper ation result read mode figure 23. 6.1 oper ation in oper ation result read mode t ab le 23. m o d e s e t t i n g v alue instruction operations fla gs remarks 0x03 ld.ca %rd,%rs %rd res[15:0] psr (cvzn) 0b0000 t h i s o p e r a t i o n m o d e d o e s n o t aff ect the oper ation result reg- ister . ld.ca %rd,imm7 %rd res[15:0] 0x13 ld.ca %rd,%rs %rd res[31:16] ld.ca %rd,imm7 %rd res[31:16] res: oper ation result register 24 electrical chara cteristics s1c17554/564 t echnical m anual seiko epson corporation 24-1 electrical characteristics 24 absolute maxim um ratings 24.1 (v ss = 0v) item symbol condition rated v alue unit core po w er supply v oltage l v dd -0.3 to 2.5 *2 v i/o po w er supply v oltage hv dd -0.3 to 7.0 *2 v analog po w er supply v oltage a v dd -0.3 to 7.0 v flash prog r amming v oltage v pp 8 v input v oltage v i -0.3 to hv dd + 0.5 v output v oltage v o -0.3 to hv dd + 0.5 v high le v el output current i oh 1 pin -10 ma t otal of all pins -20 ma lo w le v el output current i ol 1 pin 10 ma t otal of all pins 20 ma p er missib le loss *1 v o 2 00 mw stor age temper ature tstg -65 to 150 c solder ing temper ature/time tsol 260c , 10 seconds (lead section) C *1 in case of plastic pac kage *2 hv dd l v dd recommended operating conditions 24.2 s1c17554 item symbol condition min. t yp. max. unit core po w er supply v oltage l v dd 1.65 1.80 1.95 v i/o po w er supply v oltage hv dd 1.65 C 5.5 v analog po w er supply v oltage a v dd 2.7 C 5.5 v flash prog r amming v oltage v pp p 6.8 7.0 7.2 v flash er asing v oltage v pp e 7.3 7.5 7.7 v oper ating frequency f osc3 cr ystal/cer amic oscillation 0.2 C 24 mhz f osc1 cr ystal oscillation C 32.768 C khz oper ating temper ature t a -40 C 85 c s1c17564 item symbol condition min. t yp. max. unit core po w er supply v oltage l v dd when the regulator is not used 1.65 1.80 1.95 v regulator input v oltage v in regen = v in 2.0 C 5.5 v i/o po w er supply v oltage hv dd when the regulator is not used 1.65 C 5.5 v when the regulator is used 2.0 C 5.5 v analog po w er supply v oltage a v dd 2.7 C 5.5 v flash prog r amming v oltage v pp p 6.8 7.0 7.2 v flash er asing v oltage v pp e 7.3 7.5 7.7 v oper ating frequency f osc3 cr ystal/ce r amic oscillation 0.2 C 24 mhz f osc1 cr ystal oscillation C 32.768 C khz oper ating temper ature t a -40 C 85 c 24 electrical chara cteristics 24-2 seiko epson corporation s1c17554/564 t echnical m anual current consumption 24.3 unless otherwise specified: l v dd = 1.8v , hv dd = a v dd = 5.5v , v ss = 0v , t a = 25c , pcken[1:0] = 0x3 (on), rd w ait[1:0] = 0x1 (no w ait), cclkgr[1:0] = 0x0 (gear r atio 1/1) item symbol condition min. t yp. max. unit current consumption in sleep mode i slp osc1 = off , iosc = off , osc3 = off C 0.8 4.5 a current consumption in hal t mode i hal t1 osc1 = 32khz, iosc = off , osc3 = off , pcken[1:0] = 0x0 (off) C 2.7 7 a osc1 = 32khz, iosc = off , osc3 = off C 4.7 9 a i hal t2 osc1 = 32khz, iosc = off , osc3 = 8mhz (cer amic) C 650 750 a osc1 = 32khz, iosc = off , osc3 = 24mhz (cer amic) 2000 2300 a i hal t3 *2 osc1 = 32 khz, iosc = on (12mhz), osc3 = off C 1400 1600 a current consumption dur ing e x ecution *1 i exe1 osc1 = 32khz, iosc = off , osc3 = off , cpu = osc1 C 16 20 a osc1 = 32khz, iosc = off , osc3 = off , cclkgr[1:0] = 0x2 ( gear r atio 1/4), cpu = osc1 C 9.5 14 a i exe2 osc1 = 32khz, iosc = off , osc3 = 1mhz (cer amic), cpu = osc3 C 450 550 a osc1 = 32khz, iosc = off , osc3 = 8mhz (cer amic), cpu = osc3 C 3000 3400 a osc1 = 32khz, iosc = o ff , osc3 = 24mhz ( cer amic ), cpu = osc3, rd w ait[1:0] = 0x3 (2 w ait) 6000 6900 a osc1 = 32khz, iosc = off , osc3 = 8mhz (cer amic), cclkgr[1:0] = 0x2 ( gear r atio 1/4), cpu = osc3 C 1600 2000 a i exe3 *2 osc1 = 32khz, iosc = on (2mhz), osc3 = off , cpu = iosc C 1000 1300 a osc1 = 32khz, iosc = on (12mhz), osc3 = off , cpu = iosc C 4500 5300 a *1 the v alues of current consumption dur ing e x ecution w ere measured when a test prog r am consisting of 60.5% alu instr uctions , 17% br anch instr uctions , 12% memor y read instr uctions , and 10.5% memor y wr ite instr uctions w as e x ecuted contin uously in the flash memor y . *2 s1c17564 current consumption-temperature c haracteristic current consumption-temperature c haracteristic in hal t mode (osc1 operation) during e x ecution with osc1 osc1 = 32.768khz, iosc = off , osc3 = off , osc1 = 32.768 khz, iosc = off , osc3 = off , pcken[1:0] = 0x0 (off), cclkgr[1:0] = 0x0 (1/1), t yp . v alue pcken[1:0] = 0x3 (on), cclkgr[1:0] = 0x0 (1/1), t yp . v alue -50 20.0 15.0 10.0 5.0 0.0 -25 02 55 07 5 100 ta [c] i ha lt1 [a] -50 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 -25 02 55 07 5 100 ta [c] i exe1 [a] 24 electrical chara cteristics s1c17554/564 t echnical m anual seiko epson corporation 24-3 current consumption-temperature c haracteristic current consumption-temperature c haracteristic during e x ecution with osc3 during e x ecution with iosc osc1 = on, iosc = off , osc3 = on (24mhz, cer amic), osc1 = on, iosc = on (12mhz), osc3 = off , pcken[1:0] = 0x3 (on), t yp . v alue pcken[1:0] = 0x3 (on), t yp . v alue -50 7000 6000 5000 4000 3000 2000 1000 0 -25 02 55 07 5 100 ta [c] i exe2 [a] -50 6000 5000 4000 3000 2000 1000 0 -25 02 55 07 5 100 ta [c] i exe3 [a] flash read current consumption c haracteristic cloc k g ear c haracteristic (osc3 operation) (osc3 operation) osc1 = on, iosc = off , osc3 = on, pcken[1:0] = 0x3 (on), osc1 = on, i osc = off , osc3 = on, pcken[1:0] = 0x3 (on), t a = 25c , t yp . v alue rd w ait[1:0] = 0x1 (no w ait) , t a = 25c , t yp . v alue 05 10 15 20 25 8000 7000 6000 5000 4000 3000 2000 1000 0 f osc3 [mhz] i exe2 [a] rdwait[1:0] = 0x1 rdwait[1:0] = 0x2 rdwait[1:0] = 0x3 05 10 15 7000 6000 5000 4000 3000 2000 1000 0 f osc3 [mhz] i exe2 [a] gear ratio 1/1 1/2 1/4 1/8 dc regulator characteristics 24.4 dc regulator current consumption unless otherwise specified: t a = 25c , no load item symbol condition min. t yp. max. unit dc regulator current consumption *1 i reg1 econom y mode v in = 2.0 to 3.6v C 0.4 0.7 a v in = 3.6 to 5.5v C 0.5 0.8 a i reg2 nor mal mode v in = 2.0 to 5.5v C 22 33 a *1 the current v alue should be added to the current consumption dur ing sleep/hal t/e x ecution when the dc regulator is used. 24 electrical chara cteristics 24-4 seiko epson corporation s1c17554/564 t echnical m anual oscillation characteristics 24.5 oscillation characteristics change depending on conditions (board pattern, components used, etc.). use the follo w- ing characteristics as reference v alues. osc1 cr ystal oscillation unless otherwise specified: l v dd = 1.65 to 1.95v , v ss = 0v , t a = 25c , c g1 = c d1 = 10pf e xter nal, r f1 = 10mw e xter nal item symbol condition min. t yp. max. unit oscillation star t time *1 *2 t sta C C 3 s *1 cr ystal resonator = mc-146: man uf actured b y epson t o y ocom (r 1 = 65kw max., c l = 12.5pf) *2 the oscillation star t time v ar ies according to the cr ystal resonator used and the c g1 and c d1 v alues . osc3 cr ystal oscillation unless otherwise specified: l v dd = 1.65 to 1.95v , v ss = 0v , t a = 25c , c g3 = c d3 = 8pf e xter nal, r f3 = 1mw e xt er nal item symbol condition min. t yp. max. unit oscillation star t time *1 *2 t sta C C 20 ms *1 cr ystal resonator = ma-406: man uf actured b y epson t o y ocom (r 1 = 150w, c l = 10pf) *2 the oscillation star t time v ar ies according to the cr ystal resonator used and the c g3 and c d3 v alues . osc3 ceramic oscillation unless otherwise specified: l v dd = 1.65 to 1.95v , v ss = 0v , t a = 25c , r f3 = 1mw e xter nal item symbol condition min. t yp. max. unit oscillation star t time *1 *2 t sta C C 1 ms *1 cer amic resonator = cstcg24m0v51: man uf actured b y mur ata man uf actur ing co ., ltd. (c g3 = c d3 = 5pf b uilt-in) *2 the oscillation star t time v ar ies according to the cer amic resonator used and the c g3 and c d3 v alues . iosc oscillation unless otherwise specified: l v dd = 1.8v , v ss = 0v , t a = 25c item symbol condition min. t yp. max. unit oscillation star t time t sta C C 5 s oscillation frequency f iosc ioscsel[1:0] = 0x3 1.86 2 2.14 mhz ioscsel[1:0] = 0x2 3.76 4 4.24 mhz ioscsel[1:0] = 0x0 6.8 8 9.2 mhz ioscsel[1:0] = 0x1 11.4 12 12.6 mhz iosc oscillation frequenc y-temperature iosc oscillation frequenc y-v olta g e c haracteristic c haracteristic t yp . v alue t yp . v alue -50 12 mhz 8 mhz 4 mhz 2 mhz 14 12 10 8 6 4 2 0 -25 02 55 07 5 100 ta [c] f iosc [mhz] 1.6 1.7 1.8 1.9 2.0 12 mhz 8 mhz 4 mhz 2 mhz 14 12 10 8 6 4 2 0 lv dd [v] f iosc [mhz] 24 electrical chara cteristics s1c17554/564 t echnical m anual seiko epson corporation 24-5 external cloc k input characteristics 24.6 osc1, osc3 osc1 t osc1h t osc1l t osc3h t osc3l t cf1 t cr1 v ih v il osc3 t cf3 t cr3 v ih v il unless otherwise specified: l v dd = 1.65 to 1.95v , v ss = 0v , v ih = 0.8l v dd , v il = 0.2l v dd , t a = -40 to 85c item symbol min. t yp. max. unit osc1 input high pulse width t osc1h 14 C C s osc1 input lo w pulse width t osc1l 14 C C s osc1 input r ise time t cr1 C C 200 ns osc1 input f all time t cf1 C C 200 ns osc3 input high pulse width t osc3h 19 C C ns osc3 input lo w pulse width t osc3l 19 C C ns osc3 input r ise time t cr3 C C 10 ns osc3 input f all time t cf3 C C 10 ns excl, sclk exclx t ech t ecl t cf t cr v ih v il sclkx t cf t cr v ih v il unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , v ih = 0.8hv dd , v il = 0.2hv dd , t a = -40 to 85c item symbol min. t yp. max. unit exclx input high pulse width t ech 21 C C ns exclx input lo w pulse width t ecl 21 C C ns u ar t tr ansf er r ate r u C C 960000 bps u ar t tr ansf er r ate (ird a mode) r uird a C C 115200 bps input r ise time t cr C C 80 ns input f all time t cf C C 80 ns system cloc k characteristics 24.7 unless otherwise specified: l v dd = 1.65 to 1.95v , v ss = 0v item symbol condition min. t yp. max. unit system cloc k frequency f sysclk rd w ait[1:0] = 0x1, t a = 0 to 70c C C 14.75 mhz rd w ait[1:0] = 0x2, t a = 0 to 70c C C 22.5 mhz rd w ait[1:0] = 0x3, t a = 0 to 70c C C 24 mhz rd w ait[1:0] = 0x1, t a = -40 to 85c C C 14.6 mhz rd w ait[1:0] = 0x2, t a = -40 to 85c C C 22.5 mhz rd w ait[1:0] = 0x3, t a = -40 to 85c C C 24 mhz 24 electrical chara cteristics 24-6 seiko epson corporation s1c17554/564 t echnical m anual input/output pin characteristics 24.8 common c haracteristics unless otherwise specified: hv dd = 1.65 to 5.5v , l v dd = 1.65 to 1.95v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit pin capacitance c in f = 1mhz, hv dd = 0v C C 8 pf reset lo w pulse width t sr v ih = 0.8hv dd , v il = 0.2hv dd 100 C C s input leakage current i li pxx, #reset -100 C 100 na unless otherwise specified: hv dd = l v dd = 1.65 to 1.95v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit high le v el output current i oh v oh = hv dd - 0.4v , hv dd = min. -0.4 C C ma lo w le v el output current i ol v ol = 0.4v , hv dd = min. 0.4 C C ma p ositiv e tr igger v oltage v t+ l vcmos schmitt 0.66 C 1.36 v negativ e tr igger v oltage v t - l vcmos schmitt 0.42 C 1.07 v hysteresis v oltage dv l vcmos schmitt 0.17 C C v pull-up resistance r pu t ype 1, v i = 0v 120 300 1200 kw pull-do wn resistance r pd t ype 1, v i = hv dd 120 300 1200 k w unless otherwise specified: hv dd = 2.2 to 2.6v , l v dd = 1.65 to 1.95v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit high le v el output current i oh v oh = hv dd - 0.4v , hv dd = min. -0.8 C C ma lo w le v el output current i ol v ol = 0.4v , hv dd = min. 0.8 C C ma p ositiv e tr igger v oltage v t+ l vcmos schmitt 0.88 C 1.82 v negativ e tr igger v oltage v t - l vcmos schmitt 0.55 C 1.43 v hysteresis v oltage dv l vcmos schmitt 0.22 C C v pull-up resistance r pu t ype 1, v i = 0v 60 150 450 kw pull-do wn resistance r pd t ype 1, v i = hv dd 60 150 450 kw unl ess otherwise specified: hv dd = 3.0 to 3.6v , l v dd = 1.65 to 1.95v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit high le v el output current i oh v oh = hv dd - 0.4v , hv dd = min. -1.4 C C ma lo w le v el output current i ol v ol = 0.4v , hv dd = min. 1.4 C C ma p ositiv e tr igger v oltage v t+ l vcmos schmitt 1.2 C 2.52 v negativ e tr igger v oltage v t - l vcmos schmitt 0.75 C 1.98 v hysteresis v oltage dv l vcmos schmitt 0.3 C C v pull-up resistance r pu t ype 1, v i = 0v 32 80 224 kw pull-do wn resistance r pd t ype 1, v i = hv dd 32 80 224 kw unless otherwise specified: hv dd = 4.5 to 5.5v , l v dd = 1.65 to 1.95v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit high le v el output current i oh v oh = hv dd - 0.4v , hv dd = min. -2 C C ma lo w le v el output current i ol v ol = 0.4v , hv dd = min. 2 C C ma p ositiv e tr igger v oltage v t+ l vcmos schmitt 2 C 4 v negativ e tr igger v oltage v t - l vcmos schmitt 0.8 C 3.1 v hysteresis v oltage dv l vcmos schmitt 0.3 C C v pull-up resistance r pu t ype 1, v i = 0v 20 50 120 kw pull-do wn resistance r pd t ype 1, v i = hv dd 20 50 120 kw sc hmitt input thre shold v olta g e hv dd 0 v t + v t - 0 v in (v) v out (v) hv dd 24 electrical chara cteristics s1c17554/564 t echnical m anual seiko epson corporation 24-7 reset pulse #reset t sr v ih v il spi characteristics 24.9 spiclkx (cpol = 0) spiclkx (cpol = 1) sdix sdox t spck t sdo t sdh t sds master mode unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spiclkx cycle time t spck 250 C C ns sdix setup time t sds 70 C C ns sdix hold time t sdh 10 C C ns sdox output dela y time t sdo C C 20 ns sla ve mode unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spiclkx cycle time t spck 250 C C ns sdix setup time t sds 10 C C ns sdix hold time t sdh 10 C C ns sdox output dela y time t sdo C C 80 ns i 24.10 2 c characteristics sclx sdax t scl t sth t sdd t sph unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit scl cycle time t scl 2500 C C ns star t condition hold time t sth 1/f sys C C ns data output dela y time t sdd 1/f sys C C ns stop condition hold time t sph 1/f sys C C ns * f sys : system oper ating cloc k frequency 24 electrical chara cteristics 24-8 seiko epson corporation s1c17554/564 t echnical m anual usi characteristics (s1c17564) 24.11 spi master mode spi_sck (us_sckx) (falling edge sampling) spi_sck (us_sckx) (rising edge sampling) spi_sdi (us_sdix) spi_sdo (us_sdox) t spck t sdo t sdh t sds spi master mode (8 or 9 bits, normal mode) unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spi_sc k cycle time t spck 85 + t pclk C C ns spi_sdi setup time t sds 85 + t pclk C C ns spi_sdi hold time t sdh 0 C C ns spi_sdo output dela y time t sdo C C 10 ns t pclk : pclk (per ipher al module cloc k supplied from the clg) cloc k cycle time spi master mode (8 or 9 bits, fast mode) unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit spi_sc k cycle time t spck 85 C C ns spi_sdi setup time t sds 85 C C ns spi_sdi hold time t sdh 0 C C ns spi_sdo output dela y time t sdo C C 10 ns i 2 c master/sla ve mode t rep t sdo t sph t sth t16f output clock i2c_scl (us_sckx) (master) i2c_scl (us_sckx) (slave) i2c_sda (us_sdix/us_ssix) input i2c_sda (us_sdix/us_ssix) output input data sampling point for master and slave i 2 c master mode unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit i2c_scl cycle time t scl 2500 C C ns i2c_sda output dela y time t sdo C C 2*t t16 ns star t condition hold time t sth 4*t t16 C C ns stop condition hold time t sph 3*t t16 C C ns i 2 c sla ve mode unless otherwise specified: hv dd = 1.65 to 5.5v , v ss = 0v , t a = -40 to 85c item symbol min. t yp. max. unit i2c_scl cycle time t scl 2500 C C ns i2c_scl input cloc k response dela y time t rep C C 4*t t16 ns i2c_sda output dela y time t sdo C C 2*t t16 ns star t condition hold time t sth 7*t pclk C C ns stop condition hold time t sph 7*t pclk C C ns t pclk : pclk (per ipher al module cloc k supplied from the clg) cloc k cycle time t t16 = t16f output cloc k cycle time 24 electrical chara cteristics s1c17554/564 t echnical m anual seiko epson corporation 24-9 a/d con ver ter characteristics 24.12 analog c haracteristics unless otherwise specified: a v dd = 2.7 to 5.5v , v ss = 0v , t a = -40 to 85c , adst[2:0] = 0x7 (9 cycles) item symbol condition min. t yp. max. unit resolution C C 10 C bit a/d con v ersion cloc k f adclk 10 C 2000 khz sampling r ate *1 f smp 0.5 C 100 ksps zero-scale error e zs a v dd = 2.7 to 3.6v C C 3 lsb a v dd = 3.6 to 5.5v C C 5 lsb full-scale error e fs a v dd = 2.7 to 3.6v C C 3 lsb a v dd = 3.6 to 5.5v C C 5 lsb integ r al linear ity error *2 e inl C C 1.5 lsb diff erential linear ity error e dnl C C 1 lsb analog input resistance r ain C 12 20 kw analog input capacitance c ain C 16 18 pf *1 condition f or max. v alue: a/d con v er ter cloc k frequency f adclk = 2mhz. condition f or min. v alue: a/d con v er ter cloc k frequency f adclk = 10khz. *2 integ r al linear ity error is measured at the end point line . *3 these char acter istics assume that fsel[1:0] and xpd[1:0] are set correctly according to the a v dd v oltage . a/d con ver ter current consumption unless otherwise specified: t a = 25c , adst[2 :0] = 0x7 (9 cycles) , pcken[1:0] = 0x3 (on), a in = a v dd /2v , f smp = 100ksps item symbol condition min. t yp. max. unit fsel[1:0] xpd[1:0] a v dd a/d con v er ter oper ating current *1 i adc 0x2 0x3 2.7 C 290 C a 3 C 450 C a 3.3 C 640 C a 0x3 0x2 3 C 280 C a 3.3 C 400 C a 3.6 C 540 C a 0x0 0x3 3.3 C 280 C ? 3.6 C 380 C a 4 C 520 C a 4.3 C 640 C a 0x2 0x1 4 C 400 C a 4.3 C 490 C a 4.7 C 630 C a 5 C 740 C a 0x0 0x2 4.7 C 410 C a 5 C 480 C a 5.5 C 620 C a *1 this v alue is added to the current consumption in hal t mode (only when pcken[1:0] = 0x3 (on)) or current consumptio n dur ing e x ecution when the a/d con v er ter is activ e . a/d con ver ter current consumption-v olta g e c haracteristic osc3 = 4mhz, osc1 = 32khz, sampling = 9 cloc ks , a v dd = hv dd , l v dd = 1.95v , pcken[1:0] = 0x3 (on) , t a = 25c , t yp . v alue 23 (1) (2) (3) (4) (5) 456 800 700 600 500 400 300 200 100 0 av dd [v] i adc [a] no . (1) (2) (3) (4) (5) av dd 3.3 to 2.7 v 3.6 to 3.0 v 4.3 to 3.3 v 5.0 to 4.0 v 5.5 to 4.7 v fsel[1:0] 0x2 0x3 0x0 0x2 0x0 xpd[1:0] 0x3 0x2 0x3 0x1 0x2 24 electrical chara cteristics 24-10 seiko epson corporation s1c17554/564 t echnical m anual flash memor y characteristics 24.13 unless otherwise specified: l v dd = 1.65 to 1.95v , v pp = 7.0v , v ss = 0v , t a = -40 to 85c item symbol condition min. t yp. max. unit er ase/prog r am count *1 c fep 1 C C times *1 the er ase/prog r am count assumes that er asing + prog r amming or o v erwr ite prog r amming is one count and the prog r ammed data is guar anteed to be retained f or 10 y ears . 25 b asic external connection dia gram s1c17554/564 t echnical m anual seiko epson corporation 25-1 basic exter nal connection diagram 25 s1c17554 p00/ain0 p01/ain1 p02/ain2 p03/ain3 p10/sdi0 p11/sdo0 p12/spiclk0 p13/#spiss0/tout5/cap5 p14/sin1/sdi1 p15/sout1/sdo1 p16/sclk1/spiclk1 p17/scl0 p20/tout2/cap2 p21/tout3/cap3 p22(excl1)/foutb p23(excl2)/sdi2 p24(excl3)/sdo2 p25/#bfr/#spiss2 p26/sda1 p27/scl1 p30/tout0/cap0 p31/#bfr/#adtrg p32/tout4/cap4/fouta p33/remi/spiclk2 p34/remo/#spiss1 dclk/p35 dsio/p36 dst2/p37 p40/sin0/tout6/cap6 p41/sout0/tout7/cap7 p42/sclk0/tout1/cap1 p43/sda1/remi p44/scl1/remo p45(excl0)/sda0 p50Cp55 s1c17554 r 1 i/o [the potential of the substrate (back of the chip) is v ss .] hv dd icdmini or i/o v pp av dd hv dd lv dd #reset osc1 osc2 osc3 osc4 test v ss dsio/p36 dst2/p37 dclk/p35 2.7C5.5 v 1.65C5.5 v 1.65C1.95 v c g3 r f3 x'tal3 or ceramic c d3 c g1 r f1 x'tal1 c d1 r 2 hv dd cres c p + c p + c p + 25 b asic external connection dia gram 25-2 seiko epson corporation s1c17554/564 t echnical m anual s1c17564 (when the regulator is not used) s1c17564 [the potential of the substrate (back of the chip) is v ss .] 2.7C5.5 v 1.65C5.5 v 1.65C1.95 v p00/ain0 p01/ain1 p02/ain2/us_ssi0 p03/ain3/us_ssi1 p10/sdi0 p11/sdo0 p12/spiclk0 p13/#spiss0/tout5/cap5 p14/sin1/sdi1 p15/sout1/sdo1 p16/sclk1/spiclk1 p17/scl0 p20/tout2/cap2 p21/tout3/cap3 p22(excl1)/foutb p23(excl2)/sdi2 p24(excl3)/sdo2 p25/#bfr/#spiss2 p26/sda1 p27/scl1 p30/tout0/cap0 p31/#bfr/#adtrg p32/tout4/cap4/fouta p33/remi/spiclk2 p34/remo/#spiss1 dclk/p35 dsio/p36 dst2/p37 p40/sin0/tout6/cap6 p41/sout0/tout7/cap7 p42/sclk0/tout1/cap1 p43/sda1/remi p44/scl1/remo p45(excl0)/sda0 p50/us_sdi0 p51/us_sdo0 p52/us_sck0 p53/us_sdi1 p54/us_sdo1 p55/us_sck1 i/o r 1 c g3 r f3 x'tal3 or ceramic c d3 hv dd icdmini or i/o v pp av dd hv dd vin regen vout lv dd #reset osc1 osc2 osc3 osc4 test v ss dsio/p36 dst2/p37 dclk/p35 c p + c p + c p + c g1 r f1 x'tal1 c d1 r 2 hv dd cres 25 b asic external connection dia gram s1c17554/564 t echnical m anual seiko epson corporation 25-3 s1c17564 (when the regulator is used) s1c17564 [the potential of the substrate (back of the chip) is v ss .] p00/ain0 p01/ain1 p02/ain2/us_ssi0 p03/ain3/us_ssi1 p10/sdi0 p11/sdo0 p12/spiclk0 p13/#spiss0/tout5/cap5 p14/sin1/sdi1 p15/sout1/sdo1 p16/sclk1/spiclk1 p17/scl0 p20/tout2/cap2 p21/tout3/cap3 p22(excl1)/foutb p23(excl2)/sdi2 p24(excl3)/sdo2 p25/#bfr/#spiss2 p26/sda1 p27/scl1 p30/tout0/cap0 p31/#bfr/#adtrg p32/tout4/cap4/fouta p33/remi/spiclk2 p34/remo/#spiss1 dclk/p35 dsio/p36 dst2/p37 p40/sin0/tout6/cap6 p41/sout0/tout7/cap7 p42/sclk0/tout1/cap1 p43/sda1/remi p44/scl1/remo p45(excl0)/sda0 p50/us_sdi0 p51/us_sdo0 p52/us_sck0 p53/us_sdi1 p54/us_sdo1 p55/us_sck1 i/o r 1 c g3 r f3 x'tal3 or ceramic c d3 hv dd icdmini or i/o v pp av dd hv dd vin regen vout lv dd #reset osc1 osc2 osc3 osc4 test v ss dsio/p36 dst2/p37 dclk/p35 c g1 r f1 x'tal1 c d1 2.7C5.5 v c p + 2.0C5.5 v c p c p + + r 2 hv dd cres 25 b asic external connection dia gram 25-4 seiko epson corporation s1c17554/564 t echnical m anual recommended v alues f or e xternal par ts symbol name recommended v alue xtal1 cr ystal resonator 32.768 khz c g1 *1 gate capacitor 5 to 25 pf c d1 *1 dr ain capacitor 5 to 25 pf r f1 f eedbac k resistor 10 mw xtal3 cr ystal resonator 0.2 to 24 mhz cer amic cer amic resonator 0.2 to 24 mhz c g3 *1, 2 gate capacitor 10 to 30 pf c d3 *1, 2 dr ain capacitor 10 to 30 pf r f3 f eedbac k resistor 1 mw cp capacitor f or po w er supply 1 f cres capacitor f or #reset pin 0.47 f r 1 pull-up resistor 10 kw r 2 pull-up resistor 10 kw *1 the capacitances listed abo v e include str a y capacitance of the board. please contact the resonator man uf acturer f or an optim um capacitance . *2 there are cer amic resonators with b uilt-in capacitance a v ailab le . 26 p a cka ge s1c17554/564 t echnical m anual seiko epson corporation 26-1 p ackage 26 tqfp13-64pin pac ka g e (s1c17554, s1c17564) (unit: mm) 10 12 33 48 10 12 17 32 index 0.17C0.27 16 1 64 49 1 0.1 1.2 max 1 0.3C0.75 0C10 0.09C0.2 0.5 26 p a cka ge 26-2 seiko epson corporation s1c17554/564 t echnical m anual wcsp-48 pac ka g e (s1c17554) d z d g f e d c b a 1234567 a1 cor ner inde x a1 cor ner e a 2 z e 2 a 1 a t op vi ew bottom vi ew s y b m e 1 e symbol d e a a 1 a 2 e 1 e 2 b x y z d z e dimension in millimeters min 3.037 3.037 0.630 0.170 0.460 C C 0.200 C C C C nom 3.137 3.137 0.690 0.200 0.490 0.40 0.40 0.230 C C 0.369 0.369 max 3.237 3.237 0.750 0.230 0.520 C C 0.260 0.08 0.05 C C appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-1 a ppendix a list of i/o registers internal peripheral cir cuit area 1 (0x4000C0x43ff) p eripheral ad dress register name function misc registers (8-bit de vice) 0x4020 misc_dmode1 deb ug mode control register 1 e n a b l e s p e r i p h e r a l o p e r a t i o n s i n d e b u g m o d e (pclk). u ar t (with ird a) ch.0 (8-bit de vice) 0x4100 u ar t_st0 u ar t ch.0 status register indicates tr ansf er , b uff er and error statuses . 0x4101 u ar t_txd0 u ar t ch.0 t r ansmit data register t r ansmit data 0x4102 u ar t_rxd0 u ar t ch.0 receiv e data register receiv e dat a 0x4103 u ar t_mod0 u ar t ch.0 mode register sets tr ansf er data f or mat. 0x4104 u ar t_ctl0 u ar t ch.0 control register controls data tr ansf er . 0x4105 u ar t_exp0 u ar t ch.0 expansion register sets ird a mode . 0x4106 u ar t_br0 u ar t ch.0 baud rate register sets baud r ate . 0x4107 u ar t_fmd0 u ar t ch.0 fine mode register sets fine mode . u ar t (with ird a) ch.1 (8-bit de vice) 0x4120 u ar t_st1 u ar t ch.1 status register indicates tr ansf er , b uff er and error statuses . 0x4121 u ar t_txd1 u ar t ch.1 t r ansmit data register t r ansmit data 0x4122 u ar t_rxd1 u ar t ch.1 receiv e data register receiv e data 0x4123 u ar t_mod1 u ar t ch.1 mode register sets tr ansf er data f or mat. 0x4124 u ar t_ctl1 u ar t ch.1 control register controls data tr ansf er . 0x4125 u ar t_exp1 u ar t ch.1 expansion register sets ird a mode . 0x4126 u ar t_br1 u ar t ch.1 baud rate register sets baud r ate . 0x4127 u ar t_fmd1 u a r t ch.1 fine mode register sets fine mode . fine mode 16-bit timer ch. 0 (16-bit de vice) 0x4200 t16f_clk0 t16f ch.0 count cloc k select register selects a count cloc k. 0x4202 t16f_tr0 t16f ch.0 reload data register sets reload data. 0x4204 t16f_tc0 t16f ch.0 counter data register counter data 0x4206 t16f_ctl0 t16f ch.0 control register sets the timer mode and star ts/stops the timer . 0x4208 t16f_int0 t16f ch.0 interr upt co ntrol register controls the interr upt. 16-bit timer ch. 0 (16-bit de vice) 0x4220 t16_clk0 t16 ch.0 count cloc k select register selects a count cloc k. 0x4222 t16_tr0 t16 ch.0 reload data register sets reload data. 0x4224 t16_tc0 t16 ch.0 counter data register counter data 0x4226 t16_ctl0 t16 ch.0 control register sets the timer mode and star ts/stops the timer . 0x4228 t16_int0 t16 ch.0 interr upt control register controls the interr upt. 16-bit timer ch. 1 (16-bit de vice) 0x4240 t16_clk1 t16 ch.1 count cloc k select register selects a count cloc k. 0x4242 t16_tr1 t16 ch.1 reload data register sets reload data. 0x4244 t16_tc1 t16 ch.1 counter data register counter data 0x4246 t16_ctl1 t16 ch.1 control register sets the timer mode and star ts/stops the timer . 0x4248 t16_int1 t16 ch.1 interr upt control register controls the interr upt. 16-bit ti mer ch. 2 (16-bit de vice) 0x4260 t16_clk2 t16 ch.2 count cloc k select register selects a count cloc k. 0x4262 t16_tr2 t16 ch.2 reload data register sets reload data. 0x4264 t16_tc2 t16 ch.2 counter data register counter data 0x4266 t16_ctl2 t16 ch.2 control register sets the timer mode and star ts/stops the timer . 0x4268 t16_int2 t16 ch.2 interr upt control register controls the interr upt. fine mode 16-bit timer ch. 1 (16-b it de vice) 0x4280 t16f_clk1 t16f ch.1 count cloc k select register selects a count cloc k. 0x4282 t16f_tr1 t16f ch.1 reload data register sets reload data. 0x4284 t16f_tc1 t16f ch.1 counter data register counter data 0x4286 t16f_ctl1 t16f ch.1 control register sets the timer mode and star ts/stops the timer . 0x4288 t16f_int1 t16f ch.1 interr upt control register controls the interr upt. interr upt controller (16-bit de vice) 0 x4306 itc_l v0 interr upt le v el setup register 0 sets the p0 and p1 interr upt le v els . 0x4308 itc_l v1 interr upt le v el setup register 1 sets the swt and ct interr upt le v els . 0x430a itc_l v2 interr upt le v el setup register 2 sets the t16a ch.2 and p4 interr upt le v els . 0x430c itc_l v3 interr upt le v el setup register 3 sets the spi ch.2 and t16a ch.0 interr upt le v els . 0x430e itc_l v4 interr upt le v el setup register 4 sets the t1 6f ch.0 & ch.1/usi ch.0 & ch.1 and t16 ch.0 interr upt le v els . 0x4310 itc_l v5 interr upt le v el setup register 5 sets the t16 ch.1 and t16 ch.2/t16a ch.3 interr upt le v els . 0x4312 itc_l v6 interr upt le v el setup register 6 sets the u ar t ch.0 and ch.1 interr upt le v els . 0x4314 itc_l v7 interr upt le v el setup register 7 sets the spi ch.0 and i2cm interr upt le v els . 0x4316 itc_l v8 interr upt le v el setup register 8 sets the rem c/spi ch.1 and t16a ch.1 interr upt le v els . 0x4318 itc_l v9 interr upt le v el setup register 9 sets the adc10 and p5 interr upt le v els . 0x431a itc_l v10 interr upt le v el setup register 10 sets the p2 and p3 interr upt le v els . 0x431c itc_l v11 interr upt le v el setup register 11 sets the i2cs interr upt le v el. appendix a list of i/o registers ap-a-2 seiko epson corporation s1c17554/564 t echnical m anual p eripheral ad dress register name function spi ch.0 (16-bit de vice) 0x4320 spi_st0 spi ch.0 status register indicates tr ansf er and b uff er statuses . 0x4322 spi_txd0 spi ch.0 t r ansmit data register t r ansmit data 0x4324 spi_rxd0 spi ch.0 receiv e data register receiv e data 0x4326 spi_ctl0 spi ch.0 control register sets the spi mode and enab les data tr ansf er . i 2 c master (16-bit de vice) 0x4340 i2cm_en i 2 c master enab le register en ab les the i 2 c master module . 0x4342 i2cm_ctl i 2 c master control register controls the i 2 c master oper ation and indicates tr ansf er status . 0x4344 i2cm_d a t i 2 c master data register t r ansmit/receiv e data 0x4346 i2cm_ictl i 2 c master interr upt control register controls the i 2 c master interr upt. i 2 c sla v e (16-bit de vice) 0x4360 i2cs_trns i 2 c sla v e t r ansmit data register i 2 c sla v e tr ansmit data 0x4362 i2cs_recv i 2 c sla v e rec eiv e data register i 2 c sla v e receiv e data 0x4364 i2cs_sadrs i 2 c sla v e address setup register sets the i 2 c sla v e address . 0x4366 i2cs_ctl i 2 c sla v e control register controls the i 2 c sla v e module . 0x4368 i2cs_st a t i 2 c sla v e status register indicates the i 2 c b us status . 0x436a i2cs_ast a t i 2 c sla v e access status register indicates the i 2 c sla v e access status . 0x436c i2cs_ictl i 2 c sla v e interr upt control register controls the i 2 c sla v e interr upt. spi ch.1 (16-bit de vice) 0x4380 spi_st1 spi ch.1 status register indicates tr ansf er and b uff er statuses . 0x4382 spi_txd1 spi ch.1 t r ansmit data register t r ansmit data 0x4384 spi_rxd1 spi ch.1 receiv e data register receiv e data 0x4386 spi_ctl1 spi ch.1 control register sets the spi mode and enab les data tr ansf er . spi ch.2 (16-bit de vice) 0x43a0 spi_st2 spi ch.2 status register indicates tr ansf er a nd b uff er statuses . 0x43a2 spi_txd2 spi ch.2 t r ansmit data register t r ansmit data 0x43a4 spi_rxd2 spi ch.2 receiv e data register receiv e data 0x43a6 spi_ctl2 spi ch.2 control register sets the spi mode and enab les data tr ansf er . internal p eripheral cir cuit area 2 (0x5000C0x5fff) p eripheral ad dress register name function cloc k timer (8-bit de vice) 0x5000 ct_ctl cloc k timer control register resets and star ts/stops the timer . 0x5001 ct_cnt cloc k timer counter register counter data 0x5002 ct_imsk cloc k timer interr upt mask register enab les/disab les interr upt. 0x5003 ct_iflg cloc k timer interr upt flag register indicates/resets interr upt occurrence status . stopw atch timer (8-bit de vice) 0x5020 swt_ctl s topw atch timer control register resets and star ts/stops the timer . 0x5021 swt_bcnt stopw atch timer bcd counter register bcd counter data 0x5022 swt_imsk stopw atch timer interr upt mask register enab les/disab les interr upt. 0x5023 swt_iflg stopw atch timer interr upt flag register indicates/resets interr upt occurrence status . w atchdog timer (8-bit de vice) 0x5040 wdt_ctl w atchdog timer control register resets and star ts/s tops the timer . 0x5041 wdt_st w atchdog timer status register s e t s t h e t i m e r m o d e a n d i n d i c a t e s n m i s t a t u s . c l o c k g e n e r a t o r (8-bit de vice) (t16a, u ar t) 0x5060 clg_src cloc k source select register selects the cloc k source . 0x5061 clg_ctl oscillation control register controls oscillation. 0x5062 clg_nfen noise filter enab le register t ur ns oscillation stabilization w ait circuit/ noise filter on/off . 0x5064 clg_fout a fout a c ontrol register controls fout a cloc k output. 0x5065 clg_foutb foutb control register controls foutb cloc k output. 0x5068 t16a_clk0 t16a cloc k control register ch.0 controls the t16a ch.0 cloc k. 0x5069 t16a_clk1 t16a cloc k control register ch.1 controls the t16a ch.1 cloc k. 0x506a t16a_clk2 t16a cloc k control register ch.2 controls the t16a ch.2 cloc k. 0x506b t16a_clk3 t16a cloc k control register ch.3 controls the t16a ch.3 cloc k. 0x506c u ar t_clk0 u ar t ch.0 cloc k control register selects the baud r ate gener ator cloc k. 0x506d u ar t_clk1 u ar t ch.1 cloc k control register selects the baud r ate gener ator cloc k. 0x506e clg_iosc iosc control register configures iosc oscillation frequency . 0x5080 clg_pclk pclk control register controls the pclk supply . 0x5081 clg_cclk cclk control register configures the cclk division r atio . usi ch.0 (8-bit de vice) 0x50c0 usi_gcfg0 usi ch.0 global configur ation register sets interf ace and msb/lsb mode . 0x50c1 usi_td0 usi ch.0 t r ansmit data buff er register t r ansmit data b uff er 0x50c2 usi_rd0 usi ch.0 receiv e data buff er register receiv e data b uff er 0x50c3 usi_ucfg0 usi ch.0 u ar t mode configur ation register sets u ar t tr ansf er conditions . 0x50c4 usi_uie0 usi ch.0 u ar t mode interr upt enab le register enab les interr upts . 0x50c 5 usi_uif0 usi ch.0 u ar t mode interr upt flag register indicates interr upt occurrence status . 0x50c6 usi_scfg0 usi ch.0 spi master mode configur ation register sets spi tr ansf er conditions . 0x50c7 usi_sie0 usi ch.0 spi master mode interr upt enab le register enab les interr upts . 0x50c8 usi_sif0 usi ch.0 spi master mode interr upt flag register indicates interr upt occurrence status . 0x50c9 usi_smsk0 u s i c h . 0 s p i m a s t e r m o d e r e c e i v e d a t a m a s k register sets receiv e data mask. 0x50ca usi_imtg0 usi ch.0 i 2 c master mode t r igger register star ts i 2 c master oper ations . appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-3 p eripheral ad dress register name function usi ch.0 (8-bit de vice) 0x50cb usi_imie0 usi ch.0 i 2 c master mode interr upt enab le register enab les interr upts . 0x50cc usi_imif0 usi ch.0 i 2 c master mode interr upt flag register indicates interr upt occurrence status . 0x50cd usi_istg0 usi ch.0 i 2 c sla v e mode t r igger register star ts i 2 c sla v e oper ations . 0x50ce usi_isie0 usi ch.0 i 2 c sla v e mode interr upt enab le register enab les interr upts . 0x50cf usi_isif0 usi ch.0 i 2 c sla v e mode interr upt flag register indicates interr upt occurrence status . usi ch.1 (8-bit de vice) 0x50e0 usi_gcfg1 usi ch.1 global configur ation register sets interf ace and msb/lsb mode . 0x50e1 usi_td1 usi ch.1 t r ansmit data buff er register t r ansmit data b uff er 0x50e2 usi_rd1 usi ch.1 receiv e data buff er register receiv e data b uff er 0x50e3 usi_ucfg1 usi ch.1 u ar t mode configur ation register sets u ar t tr ansf er conditions . 0x50e4 usi_uie1 usi ch.1 u ar t mode interr upt enab le register enab les interr upts . 0x50e5 usi_uif1 usi ch.1 u ar t mode interr upt flag register indicates interr upt occurrence status . 0x50e6 usi_scfg1 usi ch.1 spi master mode configur ation register sets spi tr ansf er conditions . 0x50e7 usi_sie1 usi ch.1 spi master mode interr upt enab le register enab les interr upts . 0x50e8 usi_s if1 usi ch.1 spi master mode interr upt flag register indicates interr upt occurrence status . 0x50e9 usi_smsk1 u s i c h . 1 s p i m a s t e r m o d e r e c e i v e d a t a m a s k register sets receiv e data mask. 0x50ea usi_imtg1 usi ch.1 i 2 c master mode t r igger register star ts i 2 c master oper ations . 0x50eb usi_imie1 usi ch.1 i 2 c master mode interr upt enab le register enab les interr upts . 0x50ec usi_imif1 usi ch.1 i 2 c master mode interr upt fla g register indicates interr upt occurrence status . 0x50ed usi_istg1 usi ch.1 i 2 c sla v e mode t r igger register star ts i 2 c sla v e oper ations . 0x50ee usi_isie1 usi ch.1 i 2 c sla v e mode interr upt enab le register enab les interr upts . 0x50ef usi_isif1 usi ch.1 i 2 c sla v e mode interr upt flag register indicates interr upt occurrence status . p o w er gener ator (8-bit de vice) 0x5121 vd1_ctl v d1 control register controls the regulator o per ation mode . p por t & por t mux (8-bit de vice) 0x5200 p0_in p0 p or t input data register p0 por t input data 0x5201 p0_out p0 p or t output data register p0 por t output data 0x5202 p0_oen p0 p or t output enab le register enab les p0 por t outputs . 0x5203 p0_pu p0 p or t pull-up control register controls the p0 por t pull-up resistor . 0x5205 p0_imsk p0 p or t interr upt mask register enab les p0 por t interr upts . 0x5206 p0_edge p0 p or t i nterr upt edge select register selects the signal edge f or gener ating p0 por t interr upts . 0x5207 p0_iflg p0 p or t interr upt flag register indicates/resets the p0 por t interr upt occur- rence status . 0x5208 p0_cha t p0 p or t chatter ing filter control register controls the p0 por t chatter ing filter . 0x5209 p0_krst p0 p or t k e y-entr y reset configur ation register c o n f i g u r e s t h e p 0 p o r t k e y - e n t r y r e s e t f u n c t i o n . 0x520a p0_i en p0 p or t input enab le register enab les p0 por t inputs . 0x5210 p1_in p1 p or t input data register p1 por t input data 0x5211 p1_out p1 p or t output data register p1 por t output data 0x5212 p1_oen p1 p or t output enab le register enab les p1 por t outputs . 0x5213 p1_pu p1 p or t pull-up control register controls the p1 por t pull-up resistor . 0x5215 p1_imsk p1 p or t interr upt mask register enab les p1 por t interr upts . 0x5216 p1_edge p1 p or t interr upt edge select register selects the signal edge f or gener ating p1 por t interr upts . 0x5217 p1_iflg p1 p or t interr upt flag register indicates/resets the p1 por t interr upt occur- rence status . 0x5218 p1_cha t p1 p or t chatter ing filter control register controls the p1 por t chatter ing filter . 0x521a p1_ien p1 p or t input enab le register enab les p1 por t inputs . 0x5220 p2_in p2 p or t input data register p2 por t input data 0x5221 p2_out p2 p or t output data register p2 por t output data 0x5222 p2_oen p2 output enab le register enab les p2 por t outputs . 0x5223 p2_pu p2 p or t pull-up control register controls the p2 por t pull-up resistor . 0x5225 p2_imsk p2 p or t interr upt mask register enab les p2 por t interr upts . 0x5226 p2_edge p2 p or t interr upt edge select register selects the signal edge f or gener ating p2 por t interr upts . 0x5227 p 2_iflg p2 p or t interr upt flag register indicates/resets the p2 por t interr upt occur- rence status . 0x5228 p2_cha t p2 p or t chatter ing filter control register controls the p2 por t chatter ing filter . 0x522a p2_ien p2 p or t input enab le register enab les p2 por t inputs . 0x5230 p3_in p3 p or t input data register p3 por t input data 0x5231 p3_out p3 p or t output data register p3 por t output data appendix a list of i/o registers ap-a-4 seiko epson corporation s1c17554/564 t echnical m anual p eripheral ad dress register name function p por t & por t mux (8-bit de vice) 0x5232 p3_oen p3 p or t output enab le register enab les p3 por t outputs . 0x5233 p3_pu p3 p or t pull-up control register controls the p3 por t pull-up resistor . 0x5235 p3_imsk p3 p or t interr upt mask register enab les p3 por t interr upts . 0x5236 p3_edge p3 p or t interr upt edge select register selects the signal edge f or gener ating p3 por t interr upts . 0x52 37 p3_iflg p3 p or t interr upt flag register indicates/resets the p3 por t interr upt occur- rence status . 0x5238 p3_cha t p3 p or t chatter ing filter control register controls the p3 por t chatter ing filter . 0x523a p3_ien p3 p or t input enab le register enab les p3 por t inputs . 0x5240 p4_in p4 p or t input data register p4 por t input data 0x5241 p4_out p4 p or t output data register p4 por t output data 0x5242 p4_oen p4 p or t output en ab le register enab les p4 por t outputs . 0x5243 p4_pu p4 p or t pull-up control register controls the p4 por t pull-up resistor . 0x5245 p4_imsk p4 p or t interr upt mask register enab les p4 por t interr upts . 0x5246 p4_edge p4 p or t interr upt edge select register selects the signal edge f or gener ating p4 por t interr upts . 0x5247 p4_iflg p4 p or t interr upt flag register indicates/resets the p4 por t interr upt occur- rence status . 0x5248 p4_cha t p4 p or t chatter ing filter control register controls the p4 por t chatter ing filter . 0x524a p4_ien p4 p or t input enab le register enab les p4 por t inputs . 0x5250 p5_in p5 p or t input data register p5 por t input data 0x5251 p5_out p5 p or t output data register p5 por t output data 0x5252 p5_oen p5 p or t output enab le register enab les p5 por t outputs . 0x5253 p5_pu p5 p or t pull-up control register controls the p5 po r t pull-up resistor . 0x5255 p5_imsk p5 p or t interr upt mask register enab les p5 por t interr upts . 0x5256 p5_edge p5 p or t interr upt edge select register selects the signal edge f or gener ating p5 por t interr upts . 0x5257 p5_iflg p5 p or t interr upt flag register indicates/resets the p5 por t interr upt occur- rence status . 0x5258 p5_cha t p5 p or t chatter ing filter control register controls the p5 por t chatter ing filter . 0x52 5a p5_ien p5 p or t input enab le register enab les p5 por t inputs . 0x52a0 p00_03pmux p0[3:0] p or t function select register selects the p0[3:0] por t functions . 0x52a2 p10_13pmux p1[3:0] p or t function select register selects the p1[3:0] por t functions . 0x52a3 p14_17pmux p1[7:4] p or t function select register selects the p1[7:4] por t functions . 0x52a4 p20_23pmux p2[3:0] p or t function select register selects the p2[3:0] por t functions . 0x52a5 p24_27pmux p2[7:4] p or t function select register selects the p2[7:4] por t functions . 0x52a6 p30_33pmux p3[3:0] p or t function select register selects the p3[3:0] por t functions . 0x52a7 p34_37pmux p3[7:4] p or t function select register selects the p3[7:4] por t functions . 0x52a8 p40_43pmux p4[3:0] p or t function select register selects the p4[3:0] por t functions . 0x52a9 p44_45pmux p4[5:4] p or t functio n select register selects the p4[5:4] por t functions . 0x52aa p50_53pmux p5[3:0] p or t function select register selects the p5[3:0] por t functions . 0x52ab p54_55pmux p5[5:4] p or t function select register selects the p5[5:4] por t functions . misc registers (16-bit de vice) 0x5322 misc_dmode2 deb ug mode control register 2 e n a b l e s p e r i p h e r a l o p e r a t i o n s i n d e b u g m o d e (e xcept pclk). 0x5324 misc_pr o t misc protect register ena b les wr iting to the misc registers . 0x5326 misc_iramsz iram siz e register selects the iram siz e . 0x5328 misc_ttbrl v ector t ab le address lo w register sets v ector tab le address . 0x532a misc_ttbrh v ector t ab le address high register 0x532c misc_psr psr register indicates the s1c17 core psr v alues . ir remote controller (16-bit de vice) 0x5340 remc_cfg remc configur ation register controls the cloc k and data tr ansf er . 0x5342 re mc_car remc carr ier length setup register sets the carr ier h/l section lengths . 0x5344 remc_lcnt remc length counter register sets the tr ansmit/receiv e data length. 0x5346 remc_int remc interr upt control register controls interr upts . a/d con v er ter (16-bit de vice) 0x5380 adc10_add a/d con v ersion result register a/d con v er ted data 0x5382 adc10_trg a/d t r igger/channel select register sets star t/end channels and con v ersi on mode . 0x5384 adc10_ctl a/d control/status register controls a/d con v er ter and indicates con v er- sion status . 0x5386 adc10_clk a/d cloc k control register controls a/d con v er ter cloc k. 0x5388 adc10_com a/d compar ator setting register adjusts a/d con v ersion char acter istics . 16-bit pwm timer ch.0 (16-bit de vice) 0x5400 t16a_ctl0 t16a counter ch.0 control register controls the counter . 0x5402 t16a_tc0 t16a counter ch.0 d ata register counter data 0x5404 t16a_ccctl0 t16a compar ator/capture ch.0 control register controls the compar ator/capture b loc k and t out . 0x5406 t16a_cca0 t16a compare/capture ch.0 a data register compare a/capture a data 0x5408 t16a_ccb0 t16a compare/capture ch.0 b data register compare b/capture b data 0x540a t16a_ien0 t16a compare/capture ch.0 interr upt enab le register enab les/disab les interr upts . 0x540c t16a_i flg0 t16a compare/capture ch.0 interr upt flag register displa ys/sets interr upt occurrence status . appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-5 p eripheral ad dress register name function 16-bit pwm timer ch.1 (16-bit de vice) 0x5420 t16a_ctl1 t16a counter ch.1 control register controls the counter . 0x5422 t16a_tc1 t16a counter ch.1 data register counter data 0x5424 t16a_ccctl1 t16a compar ator/capture ch.1 control register controls the compar ator/capture b loc k and t out . 0x5426 t16a_cca1 t16a compare/capture ch.1 a data register compare a/capture a data 0x5428 t16 a_ccb1 t16a compare/capture ch.1 b data register compare b/capture b data 0x542a t16a_ien1 t16a compare/capture ch.1 interr upt enab le register enab les/disab les interr upts . 0x542c t16a_iflg1 t16a compare/capture ch.1 interr upt flag register displa ys/sets interr upt occurrence status . 16-bit pwm timer ch.2 (16-bit de vice) 0x5440 t16a_ctl2 t16a counter ch.2 control register controls the counter . 0x5442 t16a_tc2 t16a cou nter ch.2 data register counter data 0x5444 t16a_ccctl2 t16a compar ator/capture ch.2 control register controls the compar ator/capture b loc k and t out . 0x5446 t16a_cca2 t16a compare/capture ch.2 a data register compare a/capture a data 0x5448 t16a_ccb2 t16a compare/capture ch.2 b data register compare b/capture b data 0x544a t16a_ien2 t16a compare/capture ch.2 interr upt enab le register enab les/disab les interr upts . 0 x544c t16a_iflg2 t16a compare/capture ch.2 interr upt flag register displa ys/sets interr upt occurrence status . 16-bit pwm timer ch.3 (16-bit de vice) 0x5460 t16a_ctl3 t16a counter ch.3 control register controls the counter . 0x5462 t16a_tc3 t16a counter ch.3 data register counter data 0x5464 t16a_ccctl3 t16a compar ator/capture ch.3 control register controls the compar ator/capture b loc k and t out . 0x5466 t16a_cca3 t16a c ompare/capture ch.3 a data register compare a/capture a data 0x5468 t16a_ccb3 t16a compare/capture ch.3 b data register compare b/capture b data 0x546a t16a_ien3 t16a compare/capture ch.3 interr upt enab le register enab les/disab les interr upts . 0x546c t16a_iflg3 t16a compare/capture ch.3 interr upt flag register displa ys/sets interr upt occurrence status . flash controller (16-bit de vice) 0x54b0 flashc_ w ait flashc read w ait control register sets flash read w ait cycle . core i/o reser ved area (0xffff84C0xffffd0) p eripheral ad dress register name function s1c17 core i/o 0xffff84 idir processor id register indicates the processor id . 0xffff90 dbram deb ug ram base register indicates the deb ug ram base address . 0xffff a0 dcr deb ug control register controls deb ugging. 0xffffb4 ibar1 instr uction break address register 1 sets instr uction break address #1. 0xffffb8 ibar2 instr uction break address register 2 sets instr uction break address #2. 0xffffbc ibar3 instr uction break address register 3 sets instr uction break address #3. 0xffffd0 ibar4 instr uction break address register 4 sets instr uction break address #4. note: addresses mar k ed as reser v ed or un used per ipher al circuit areas not mar k ed in the tab le m ust not be accessed b y application prog r ams . 0x4100C0x4107, 0x506c uart (with irda) ch.0 register name ad dress bit name function setting init. r/w remarks uart ch.0 status register (uart_st0) 0x4100 (8 bits) d7 tred end of tr ansmission flag 1 completed 0 n o t c o m p l e t e d 0 r/w reset b y wr iting 1. d6 fer f r aming error flag 1 error 0 nor mal 0 r/w d5 per p ar ity error flag 1 error 0 nor mal 0 r/w d4 oer ov err un error flag 1 error 0 nor mal 0 r/w d3 rd2b second b yte receiv e flag 1 ready 0 empty 0 r d2 trbs t r ansmit b usy flag 1 busy 0 idle 0 r shift register status d1 rdry receiv e data ready flag 1 ready 0 empty 0 r d0 tdbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r uart ch.0 transmit data register (uart_txd0) 0x4101 (8 bits) d7C0 txd[7:0] t r ansmit data txd7(6) = msb txd0 = lsb 0x0 to 0xff (0x7f) 0x0 r/w uart ch.0 receive data register (uart_rxd0) 0x4102 (8 bits) d7C0 rxd[7:0] receiv e data in the receiv e data b uff er rxd7(6) = msb rxd0 = lsb 0x0 to 0xff (0x7f) 0x0 r o l d e r d a t a i n t h e b u f - f er is read out first. appendix a list of i/o registers ap-a-6 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks uart ch.0 mode register (uart_mod0) 0x4103 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 chln char acter length select 1 8 bits 0 7 bits 0 r/w d3 pren p ar ity enab le 1 with par ity 0 no par ity 0 r/w d2 pmd p ar ity mode select 1 odd 0 ev en 0 r/w d1 stpb stop bit select 1 2 bits 0 1 bit 0 r/w d0 C reser v ed C C C 0 when being read. uart ch.0 control register (uart_ctl0) 0x4104 (8 bits) d7 teien end of tr ansmission int. enab le 1 enab le 0 disab le 0 r/w d6 reien receiv e error int. enab le 1 enab le 0 disab le 0 r/w d5 rien receiv e b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 tien t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 rbfi r e c e i v e b u f f e r f u l l i n t . c o n d i t i o n s e t u p 1 2 b ytes 0 1 b yte 0 r/w d0 rxen u ar t enab le 1 enab le 0 disab le 0 r/w uart ch.0 expansion register (uart_exp0) 0x4105 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 irmd ird a mode select 1 on 0 off 0 r/w uart ch.0 baud rate register (uart_br0) 0x4106 (8 bits) d7C0 br[7:0] baud r ate setting 0x0 to 0xff 0x0 r/w uart ch.0 fine mode register (uart_fmd0) 0x4107 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 fmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. uart ch.0 clock control register (uart_clk0) 0x506c (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 clkdiv [1:0] cloc k division r atio select clkdiv[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C 0 when being read. d0 clken count cloc k enab le 1 enab le 0 disab le 0 r/w 0x4120C0x4127, 0x506d uart (with irda) ch.1 register name ad dress bit name function setting init. r/w remarks uart ch.1 status register (uart_st1) 0x4120 (8 bits) d7 tred end of tr ansmission flag 1 completed 0 n o t c o m p l e t e d 0 r/w reset b y wr iting 1. d6 fer f r aming error flag 1 error 0 nor mal 0 r/w d5 per p ar ity error flag 1 error 0 nor mal 0 r/w d4 oer ov err un error flag 1 error 0 nor mal 0 r/w d3 rd2b second b yte receiv e flag 1 ready 0 empty 0 r d2 trbs t r ansmit b usy flag 1 busy 0 idle 0 r shift register status d1 rdry receiv e data ready flag 1 ready 0 empty 0 r d0 tdbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r uart ch.1 transmit data register (uart_txd1) 0x4121 (8 bits) d7C0 txd[7:0] t r ansmit data txd7(6) = msb txd0 = lsb 0x0 to 0xff (0x7f) 0x0 r/w uart ch.1 receive data register (uart_rxd1) 0x4122 (8 bits) d7C0 rxd[7:0] receiv e data in the receiv e data b uff er rxd7(6) = msb rxd0 = lsb 0x0 to 0xff (0x7f) 0x0 r o l d e r d a t a i n t h e b u f - f er is read out first. uart ch.1 mode register (uart_mod1) 0x4123 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 chln char acter length select 1 8 bits 0 7 bits 0 r/w d3 pren p ar ity enab le 1 with par ity 0 no par ity 0 r/w d2 pmd p ar ity mode select 1 odd 0 ev en 0 r/w d1 stpb stop bit select 1 2 bits 0 1 bit 0 r/w d0 C reser v ed C C C 0 when being read. uart ch.1 control register (uart_ctl1) 0x4124 (8 bits) d7 teien end of tr ansmission int. enab le 1 enab le 0 disab le 0 r/w d6 reien receiv e error int. enab le 1 enab le 0 disab le 0 r/w d5 rien receiv e b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 tien t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 rbfi r e c e i v e b u f f e r f u l l i n t . c o n d i t i o n s e t u p 1 2 b ytes 0 1 b yte 0 r/w d0 rxen u ar t enab le 1 enab le 0 disab le 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-7 register name ad dress bit name function setting init. r/w remarks uart ch.1 expansion register (uart_exp1) 0x4125 (8 bits) d7C1 C reser v ed C C C 0 when being read. d0 irmd ird a mode select 1 on 0 off 0 r/w uart ch.1 baud rate register (uart_br1) 0x4126 (8 bits) d7C0 br[7:0] baud r ate setting 0x0 to 0xff 0x0 r/w uart ch.1 fine mode register (uart_fmd1) 0x4127 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 fmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. uart ch.1 clock control register (uart_clk1) 0x506d (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 clkdiv [1:0] cloc k division r atio select clkdiv[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C 0 when being read. d0 clken count cloc k enab le 1 enab le 0 disab le 0 r/w 0x4200C0x4208 fine mode 16-bit timer ch.0 register name ad dress bit name function setting init. r/w remarks t16f ch.0 count clock select register (t16f_clk0) 0x4200 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t16f ch.0 reload data register (t16f_tr0) 0x4202 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w t16f ch.0 counter data register (t16f_tc0) 0x4204 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r t16f ch.0 control register (t16f_ctl0) 0x4206 (16 bits) d15C12 C reser v ed C C C 0 when being read. d11C8 tfmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. d7C5 C reser v ed C C C 0 when being read. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w t16f ch.0 interrupt control register (t16f_int0) 0x4208 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16fie t16f interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16fif t16f interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. appendix a list of i/o registers ap-a-8 seiko epson corporation s1c17554/564 t echnical m anual 0x4220C0x4228 16-bit timer ch.0 register name ad dress bit name function setting init. r/w remarks t16 ch.0 count clock select register (t16_clk0) 0x4220 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t16 ch.0 reload data register (t16_tr0) 0x4222 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w t16 ch.0 counter data register (t16_tc0) 0x4224 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r t16 ch.0 control register (t16_ctl0) 0x4226 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w t16 ch.0 interrupt control register (t16_int0) 0x4228 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16ie t16 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16if t16 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. 0x4240C0x4248 16-bit timer ch.1 register name ad dress bit name function setting init. r/w remarks t16 ch.1 count clock select register (t16_clk1) 0x4240 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t16 ch.1 reload data register (t16_tr1) 0x4242 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w t16 ch.1 counter data register (t16_tc1) 0x4244 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r t16 ch.1 control register (t16_ctl1) 0x4246 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-9 register name ad dress bit name function setting init. r/w remarks t16 ch.1 interrupt control register (t16_int1) 0x4248 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16ie t16 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16if t16 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. 0x4260C0x4268 16-bit timer ch.2 register name ad dress bit name function setting init. r/w remarks t16 ch.2 count clock select register (t16_clk2) 0x4260 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t16 ch.2 reload data register (t16_tr2) 0x4262 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w t16 ch.2 counter data register (t16_tc2) 0x4264 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r t16 ch.2 control register (t16_ctl2) 0x4266 (16 bits) d15C5 C reser v ed C C C do not wr ite 1. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w t16 ch.2 interrupt control register (t16_int2) 0x4268 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16ie t16 interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16if t16 interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. 0x4280C0x4288 fine mode 16-bit timer ch.1 register name ad dress bit name function setting init. r/w remarks t16f ch.1 count clock select register (t16f_clk1) 0x4280 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 df[3:0] count cloc k division r atio select df[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 t16f ch.1 reload data register (t16f_tr1) 0x4282 (16 bits) d15C0 tr[15:0] reload data tr15 = msb tr0 = lsb 0x0 to 0xffff 0x0 r/w t16f ch.1 counter data register (t16f_tc1) 0x4284 (16 bits) d15C0 tc[15:0] counter data tc15 = msb tc0 = lsb 0x0 to 0xffff 0xffff r appendix a list of i/o registers ap-a-10 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks t16f ch.1 control register (t16f_ctl1) 0x4286 (16 bits) d15C12 C reser v ed C C C 0 when being read. d11C8 tfmd[3:0] fine mode setup 0x0 to 0xf 0x0 r/w s e t a n u m b e r o f t i m e s to inser t dela y into a 16-underflo w per iod. d7C5 C reser v ed C C C 0 when being read. d4 trmd count mode select 1 one shot 0 repeat 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 preser timer reset 1 reset 0 ignored 0 w d0 prun timer r un/stop control 1 run 0 stop 0 r/w t16f ch.1 interrupt control register (t16f_int1) 0x4288 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 t16fie t16f interr upt enab le 1 enab le 0 disab le 0 r/w d7C1 C reser v ed C C C 0 when being read. d0 t16fif t16f interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. 0x4306C0x431c interrupt controller register name ad dress bit name function setting init. r/w remarks interrupt level setup register 0 (itc_lv0) 0x4306 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv1[2:0] p1 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv0[2:0] p0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 1 (itc_lv1) 0x4308 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv3[2:0] ct interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv2[2:0] swt interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 2 (itc_lv2) 0x430a (16 bits) d15C1 C reser v ed C C C 0 when being read. d10C8 ilv5[2:0] p4 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv4[2:0] t16a ch.2 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 3 (itc_lv3) 0x430c (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv7[2:0] t16a ch.0 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv6[2:0] spi ch.2 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 4 (itc_lv4) 0x430e (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv9[2:0] t16 ch.0 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv8[2:0] t16f ch.0 & 1/usi ch.0 & 1 inter- r upt le v el 0 to 7 0x0 r/w interrupt level setup register 5 (itc_lv5) 0x4310 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv11[2:0] t16 ch.2/t16a ch.3 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv10[2:0] t16 ch.1 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 6 (itc_lv6) 0x4312 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv13[2:0] u ar t ch.1 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv12[2:0] u ar t ch.0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 7 (itc_lv7) 0x4314 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv15[2:0] i2cm interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv14[2:0] spi ch.0 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 8 (itc_lv8) 0x4316 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv17[2:0] t16a ch.1 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv16[2:0] remc/spi ch.1 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 9 (itc_lv9) 0x4318 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv19[2:0] p5 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv18[2:0] adc10 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 10 (itc_lv10) 0x431a (16 bits) d15C11 C reser v ed C C C 0 when being read. d10C8 ilv21[2:0] p3 interr upt le v el 0 to 7 0x0 r/w d7C3 C reser v ed C C C 0 when being read. d2C0 ilv20[2:0] p2 interr upt le v el 0 to 7 0x0 r/w interrupt level setup register 11 (itc_lv11) 0x431c (16 bits) d15C3 C reser v ed C C C 0 when being read. d2C0 ilv22[2:0] i2cs interr upt le v el 0 to 7 0x0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-11 0x4320C0x4326 spi ch.0 register name ad dress bit name function setting init. r/w remarks spi ch.0 status register (spi_st0) 0x4320 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r spi ch.0 transmit data register (spi_txd0) 0x4322 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w spi ch.0 receive data register (spi_rxd0) 0x4324 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r spi ch.0 control register (spi_ctl0) 0x4326 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t16 ch.1 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar ity selec t 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w 0x4340C0x4346 i 2 c master register name ad dress bit name function setting init. r/w remarks i 2 c master enable register (i2cm_en) 0x4340 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 i2cmen i 2 c master enab le 1 enab le 0 disab le 0 r/w i 2 c master control register (i2cm_ctl) 0x4342 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 rbusy receiv e b usy flag 1 busy 0 idle 0 r d8 tbusy t r ansmit b usy flag 1 busy 0 idle 0 r d7C5 C reser v ed C C C 0 when being read. d4 nserm noise remo v e on/off 1 on 0 off 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 stp stop control 1 stop 0 ignored 0 r/w d0 strt star t control 1 star t 0 ignored 0 r/w i 2 c master data register (i2cm_dat) 0x4344 (16 bits) d15C12 C reser v ed C C C 0 when being read. d11 rbrdy receiv e b uff er ready flag 1 ready 0 empty 0 r d10 rxe receiv e e x ecution 1 receiv e 0 ignored 0 r/w d9 txe t r ansmit e x ecution 1 t r ansmit 0 ignored 0 r/w d8 rtack receiv e/tr ansmit a ck 1 error 0 a ck 0 r/w d7C0 rtdt[7:0] receiv e/tr ansmit data r tdt7 = msb r tdt0 = lsb 0x0 to 0xff 0x0 r/w i 2 c master interrupt control register (i2cm_ictl) 0x4346 (16 bits) d15C2 C reser v ed C C C 0 when being read. d1 rinte receiv e interr upt enab le 1 enab le 0 disab le 0 r/w d0 tinte t r ansmit interr upt enab le 1 enab le 0 disab le 0 r/w 0x4360C0x436c i 2 c slave register name ad dress bit name function setting init. r/w remarks i 2 c slave transmit data register (i2cs_trns) 0x4360 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sdata[7:0] i 2 c sla v e tr ansmit data 0C0xff 0x0 r/w i 2 c slave receive data register (i2cs_recv) 0x4362 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 rdata[7:0] i 2 c sla v e receiv e data 0C0xff 0x0 r i 2 c slave address setup register (i2cs_sadrs) 0x4364 (16 bits) d15C7 C reser v ed C C C 0 when being read. d6C0 sadrs[6:0] i 2 c sla v e address 0C0x7f 0x0 r/w appendix a list of i/o registers ap-a-12 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks i 2 c slave control register (i2cs_ctl) 0x4366 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 tbuf_clr i2cs_trns register clear 1 clear state 0 nor mal 0 r/w d7 i2csen i 2 c sla v e enab le 1 enab le 0 disab le 0 r/w d6 softreset softw are reset 1 reset 0 cancel 0 r/w d5 nak_ans nak ans w er 1 nak 0 a ck 0 r/w d4 bfreq_en bus free request enab le 1 enab le 0 disab le 0 r/w d3 clkstr_en cloc k stretch on/off 1 on 0 off 0 r/w d2 nf_en noise filter on/off 1 on 0 off 0 r/w d1 asdet_en async.address detection on/off 1 on 0 off 0 r/w d0 com_mode i 2 c sla v e comm unication mode 1 activ e 0 standb y 0 r/w i 2 c slave status register (i2cs_stat) 0x4368 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7 bstat bus status tr ansition 1 changed 0 unchanged 0 r d6 C reser v ed C C C 0 when being read. d5 txudf t r ansmit data underflo w 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. rxovf receiv e data o v erflo w d4 bfreq bus free request 1 occurred 0 n o t o c c u r r e d 0 r/w d3 dms output data mismatch 1 error 0 nor mal 0 r/w d2 asdet async. address detection status 1 detected 0 n o t d e t e c t e d 0 r/w d1 da_nak nak receiv e status 1 nak 0 a ck 0 r/w d0 da_stop st op condition detect 1 detected 0 n o t d e t e c t e d 0 r/w i 2 c slave access status register (i2cs_astat) 0x436a (16 bits) d15C5 C reser v ed C C C 0 when being read. d4 rxrdy receiv e data ready 1 ready 0 not ready 0 r d3 txemp t r ansmit data empty 1 empty 0 not empty 0 r d2 busy i 2 c b us status 1 busy 0 f ree 0 r d1 selected i 2 c sla v e select status 1 selected 0 n o t s e l e c t e d 0 r d0 r/w read/wr ite direction 1 output 0 input 0 r i 2 c slave interrupt control register (i2cs_ictl) 0x436c (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 bstat_ien bus status interr upt enab le 1 enab le 0 disab le 0 r/w d1 rxrdy_ien receiv e interr upt enab le 1 enab le 0 disab le 0 r/w d0 txemp_ien t r ansmit interr upt enab le 1 enab le 0 disab le 0 r/w 0x4380C0x4386 spi ch.1 register name ad dress bit name function setting init. r/w remarks spi ch.1 status register (spi_st1) 0x4380 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r spi ch.1 transmit data register (spi_txd1) 0x4382 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w spi ch.1 receive data register (spi_rxd1) 0x4384 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r spi ch.1 control register (spi_ctl1) 0x4386 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t16 ch.1 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar ity selec t 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w 0x43a0C0x43a6 spi ch.2 register name ad dress bit name function setting init. r/w remarks spi ch.2 status register (spi_st2) 0x43a0 (16 bits) d15C3 C reser v ed C C C 0 when being read. d2 spbsy t r ansf er b usy flag (master) 1 busy 0 idle 0 r ss signal lo w flag (sla v e) 1 ss = l 0 ss = h d1 sprbf receiv e data b uff er full flag 1 full 0 not full 0 r d0 sptbe t r ansmit data b uff er empty flag 1 empty 0 not empty 1 r spi ch.2 transmit data register (spi_txd2) 0x43a2 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sptdb[7:0] spi tr ansmit data b uff er sptdb7 = msb sptdb0 = lsb 0x0 to 0xff 0x0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-13 register name ad dress bit name function setting init. r/w remarks spi ch.2 receive data register (spi_rxd2) 0x43a4 (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 sprdb[7:0] spi receiv e data b uff er sprdb7 = msb sprdb0 = lsb 0x0 to 0xff 0x0 r spi ch.2 control register (spi_ctl2) 0x43a6 (16 bits) d15C10 C reser v ed C C C 0 when being read. d9 mclk spi cloc k source select 1 t16 ch.1 0 pclk/4 0 r/w d8 mlsb lsb/msb first mode select 1 lsb 0 msb 0 r/w d7C6 C reser v ed C C C 0 when being read. d5 sprie receiv e data b uff er full int. enab le 1 enab le 0 disab le 0 r/w d4 sptie t r ansmit data b uff er empty int. enab le 1 enab le 0 disab le 0 r/w d3 cpha cloc k phase select 1 data out 0 data in 0 r/w these bits m ust be set bef ore setting spen to 1. d2 cpol cloc k polar ity selec t 1 activ e l 0 activ e h 0 r/w d1 mssl master/sla v e mode select 1 master 0 sla v e 0 r/w d0 spen spi enab le 1 enab le 0 disab le 0 r/w 0x5000C0x5003 clock timer register name ad dress bit name function setting init. r/w remarks clock timer control register (ct_ctl) 0x5000 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 ctrst cloc k timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 ctrun cloc k timer r un/stop control 1 run 0 stop 0 r/w clock timer counter register (ct_cnt) 0x5001 (8 bits) d7C0 ctcnt[7:0] cloc k timer counter v alue 0x0 to 0xff 0 r clock timer interrupt mask register (ct_imsk) 0x5002 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctie32 32 hz interr upt enab le 1 enab le 0 disab le 0 r/w d2 ctie8 8 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 ctie2 2 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 ctie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w clock timer interrupt flag register (ct_iflg) 0x5003 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ctif32 32 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d2 ctif8 8 hz interr upt flag 0 r/w d1 ctif2 2 hz interr upt flag 0 r/w d0 ctif1 1 hz interr upt flag 0 r/w 0x5020C0x5023 stopwatch timer register name ad dress bit name function setting init. r/w remarks stopwatch timer control register (swt_ctl) 0x5020 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 swtrst stopw atch timer reset 1 reset 0 ignored 0 w d3C1 C reser v ed C C C d0 swtrun stopw atch timer r un/stop control 1 run 0 stop 0 r/w stopwatch timer bcd counter register (swt_bcnt) 0x5021 (8 bits) d7C4 bcd10[3:0] 1/10 sec. bcd counter v alue 0 to 9 0 r d3C0 bcd100[3:0] 1/100 sec. bcd counter v alue 0 to 9 0 r stopwatch timer interrupt mask register (swt_imsk) 0x5022 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 sie1 1 hz interr upt enab le 1 enab le 0 disab le 0 r/w d1 sie10 10 hz interr upt enab le 1 enab le 0 disab le 0 r/w d0 sie100 100 hz interr upt enab le 1 enab le 0 disab le 0 r/w stopwatch timer interrupt flag register (swt_iflg) 0x5023 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 sif1 1 hz interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d1 sif10 10 hz interr upt flag 0 r/w d0 sif100 100 hz interr upt flag 0 r/w 0x5040C0x5041 watchdog timer register name ad dress bit name function setting init. r/w remarks watchdog timer control register (wdt_ctl) 0x5040 (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 wdtrst w atchdog timer reset 1 reset 0 ignored 0 w d3C0 wdtrun[3:0] w atchdog timer r un/stop control o t h e r t h a n 1 0 1 0 run 1010 stop 1010 r/w watchdog timer status register (wdt_st) 0x5041 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 wdtmd nmi/reset mode select 1 reset 0 nmi 0 r/w d0 wdtst nmi status 1 n m i o c c u r r e d 0 n o t o c c u r r e d 0 r appendix a list of i/o registers ap-a-14 seiko epson corporation s1c17554/564 t echnical m anual 0x5060C0x5081 clock generator register name ad dress bit name function setting init. r/w remarks clock source select register (clg_src) s1c17554 0x5060 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x2 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed clock source select register (clg_src) s1c17564 0x5060 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 clksrc[1:0] system cloc k source select clksrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc oscillation control register (clg_ctl) s1c17554 0x5061 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 osc3wt[1:0] osc3 w ait cycle select osc3wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3C2 C reser v ed C C C 0 when being read. d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3en osc3 enab le 1 enab le 0 disab le 1 r/w oscillation control register (clg_ctl) s1c17564 0x5061 (8 bits) d7C6 ioscwt[1:0] iosc w ait cycle select ioscwt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 8 cycles 16 cycles 32 cycles 64 cycles d5C4 osc3wt[1:0] osc3 w ait cycle select osc3wt[1:0] w ait cycle 0x0 r/w 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles d3 C reser v ed C C C 0 when being read. d2 ioscen iosc enab le 1 enab le 0 disab le 1 r/w d1 osc1en osc1 enab le 1 enab le 0 disab le 0 r/w d0 osc3en osc3 enab le 1 enab le 0 disab le 0 r/w noise filter enable register (clg_nfen) 0x5062 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 osc1wce osc1 w ait cycle enab le 1 enab le 0 disab le 1 r/w d4 osc3wce osc3 w ait cycle enab le 1 enab le 0 disab le 1 r/w d3C0 C reser v ed C C C 0 when being read. fouta control register (clg_fouta ) s1c17554 0x5064 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutad [1:0] fout a cloc k division r atio select fout ad[1:0] division r atio 0x0 r/w when the cloc k source is osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w fouta control register (clg_fouta ) s1c17564 0x5064 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutad [1:0] fout a cloc k division r atio select fout ad[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutasrc [1:0] fout a cloc k source select fout asrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc d1 C reser v ed C C C 0 when being read. d0 foutae fout a output enab le 1 enab le 0 disab le 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-15 register name ad dress bit name function setting init. r/w remarks foutb control register (clg_foutb ) s1c17554 0x5065 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutbd [1:0] foutb cloc k division r atio select foutbd[1:0] division r atio 0x0 r/w when the cloc k source is osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 reser v ed d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w foutb control register (clg_foutb ) s1c17564 0x5065 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C4 foutbd [1:0] foutb cloc k division r atio select foutbd[1:0] division r atio 0x0 r/w when the cloc k source is iosc or osc3 0x3 0x2 0x1 0x0 reser v ed 1/4 1/2 1/1 d3C2 foutbsrc [1:0] foutb cloc k source select foutbsrc[1:0] cloc k source 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed osc3 osc1 iosc d1 C reser v ed C C C 0 when being read. d0 foutbe foutb output enab le 1 enab le 0 disab le 0 r/w iosc control register (clg_iosc ) s1c17564 0x506e (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 ioscsel [1:0] iosc frequency select ioscsel[1:0] f requency 0x1 r/w 0x3 0x2 0x1 0x0 2 mhz 4 mhz 12 mhz 8 mhz pclk control register (clg_pclk ) 0x5080 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 pcken[1:0] pclk enab le pcken[1:0] pclk supply 0x3 r/w 0x3 0x2 0x1 0x0 enab le not allo w ed not allo w ed disab le cclk control register (clg_cclk ) 0x5081 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 cclkgr[1:0] cclk cloc k gear r atio select cclkgr[1:0] gear r atio 0x0 r/w 0x3 0x2 0x1 0x0 1/8 1/4 1/2 1/1 0x50c0C0x50cf usi ch.0 register name ad dress bit name function setting init. r/w remarks usi ch.0 global configuration register (usi_gcfg0) 0x50c0 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 lsbfst msb/lsb first mode select 1 msb first 0 lsb first 0 r/w d2C0 usimod [2:0] interf ace mode configur ation usimod[2:0] i/f mode 0x0 r/w 0x7C0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed i 2 c sla v e i 2 c master reser v ed spi master u ar t softw are reset usi ch.0 transmit data buffer register (usi_td0) 0x50c1 (8 bits) d7C0 td[7:0] usi tr ansmit data b uff er td7 = msb td0 = lsb 0x0 to 0xff 0x0 r/w usi ch.0 receive data buffer register (usi_rd0) 0x50c2 (8 bits) d7C0 rd[7:0] usi receiv e data b uff er rd7 = msb rd0 = lsb 0x0 to 0xff 0x0 r usi ch.0 uart mode configuration register (usi_ucfg0) 0x50c3 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 uchln char acter length select 1 8 bits 0 7 bits 0 r/w d2 ustpb stop bit select 1 2 bits 0 1 bit 0 r/w d1 upmd p ar ity mode select 1 ev en 0 odd 0 r/w d0 upren p ar ity enab le 1 with par ity 0 no par ity 0 r/w usi ch.0 uart mode interrupt enable register (usi_uie0) 0x50c4 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 ueie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 urdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 utdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w appendix a list of i/o registers ap-a-16 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks usi ch.0 uart mode interrupt flag register (usi_uif0) 0x50c5 (8 bits) d7 C reser v ed C C C 0 when being read. d6 urbsy receiv e b usy flag 1 busy 0 idle 0 r d5 utbsy t r ansmit b usy flag 1 busy 0 idle 0 r d4 upeif p ar ity error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d3 useif f r aming error flag 1 error 0 nor mal 0 r/w d2 uoeif ov err un error flag 1 error 0 nor mal 0 r/w d1 urdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 utdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w usi ch.0 spi master mode configuration register (usi_scfg0) 0x50c6 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 scmd command bit (f or 9-bit data) 1 high 0 lo w 0 r/w d4 schln char acter length select 1 9 bits 0 8 bits 0 r/w d3 scpha cloc k phase select 1 phase 1 0 phase 0 0 r/w d2 scpol cloc k polar ity select 1 activ e l 0 activ e h 0 r/w d1 smsken receiv e data mask enab le 1 enab le 0 disab le 0 r/w d0 sfstmod f ast mode select 1 f ast 0 nor mal 0 r/w usi ch.0 spi master mode interrupt enable register (usi_sie0) 0x50c7 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 seie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 srdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 stdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w usi ch.0 spi master mode interrupt flag register (usi_sif0) 0x50c8 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ssif t r ansf er b usy flag 1 busy 0 idle 0 r d2 seif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d1 srdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 stdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w usi ch.0 spi master mode receive data mask register (usi_smsk0) 0x50c9 (8 bits) d7C0 smsk[7:0] receiv e data mask bit smsk7 = msb smsk0 = lsb 0x0 to 0xff 0x0 r/w usi ch.0 i 2 c master mode trigger register (usi_imtg0) 0x50ca (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 imtg i 2 c master oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 imtgmod [2:0] i 2 c master tr igger mode select imtgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data stop condition star t condition usi ch.0 i 2 c master mode interrupt enable register (usi_imie0) 0x50cb (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 imeie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 imie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w usi ch.0 i 2 c master mode interrupt flag register (usi_imif0) 0x50cc (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 imbsy i 2 c master b usy flag 1 busy 0 standb y 0 r d4C2 imsta[2:0] i 2 c master status imst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y s t o p g e n e r a t e d s t a r t g e n e r a t e d d1 imeif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 imif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w usi ch.0 i 2 c slave mode trigger register (usi_istg0) 0x50cd (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 istg i 2 c sla v e oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 istgmod [2:0] i 2 c sla v e tr igger mode select istgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data reser v ed w ait f or star t appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-17 register name ad dress bit name function setting init. r/w remarks usi ch.0 i 2 c slave mode interrupt enable register (usi_isie0) 0x50ce (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 iseie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 isie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w usi ch.0 i 2 c slave mode interrupt flag register (usi_isif0) 0x50cf (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 isbsy i 2 c sla v e b usy flag 1 busy 0 standb y 0 r d4C2 issta[2:0] i 2 c sla v e status isst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y stop detected star t detected d1 iseif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 isif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w 0x50e0C0x50ef usi ch.1 register name ad dress bit name function setting init. r/w remarks usi ch.1 global configuration register (usi_gcfg1) 0x50e0 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 lsbfst msb/lsb first mode select 1 msb first 0 lsb first 0 r/w d2C0 usimod [2:0] interf ace mode configur ation usimod[2:0] i/f mode 0x0 r/w 0x7C0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed i 2 c sla v e i 2 c master reser v ed spi master u ar t softw are reset usi ch.1 transmit data buffer register (usi_td1) 0x50e1 (8 bits) d7C0 td[7:0] usi tr ansmit data b uff er td7 = msb td0 = lsb 0x0 to 0xff 0x0 r/w usi ch.1 receive data buffer register (usi_rd1) 0x50e2 (8 bits) d7C0 rd[7:0] usi receiv e data b uff er rd7 = msb rd0 = lsb 0x0 to 0xff 0x0 r usi ch.1 uart mode configuration register (usi_ucfg1) 0x50e3 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 uchln char acter length select 1 8 bits 0 7 bits 0 r/w d2 ustpb stop bit select 1 2 bits 0 1 bit 0 r/w d1 upmd p ar ity mode select 1 ev en 0 odd 0 r/w d0 upren p ar ity enab le 1 with par ity 0 no par ity 0 r/w usi ch.1 uart mode interrupt enable register (usi_uie1) 0x50e4 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 ueie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 urdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 utdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w usi ch.1 uart mode interrupt flag register (usi_uif1) 0x50e5 (8 bits) d7 C reser v ed C C C 0 when being read. d6 urbsy receiv e b usy flag 1 busy 0 idle 0 r d5 utbsy t r ansmit b usy flag 1 busy 0 idle 0 r d4 upeif p ar ity error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d3 useif f r aming error flag 1 error 0 nor mal 0 r/w d2 uoeif ov err un error flag 1 error 0 nor mal 0 r/w d1 urdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 utdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w usi ch.1 spi master mode configuration register (usi_scfg1) 0x50e6 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 scmd command bit (f or 9-bit data) 1 high 0 lo w 0 r/w d4 schln char acter length select 1 9 bits 0 8 bits 0 r/w d3 scpha cloc k phase select 1 phase 1 0 phase 0 0 r/w d2 scpol cloc k polar ity select 1 activ e l 0 activ e h 0 r/w d1 smsken receiv e data mask enab le 1 enab le 0 disab le 0 r/w d0 sfstmod f ast mode select 1 f ast 0 nor mal 0 r/w usi ch.1 spi master mode interrupt enable register (usi_sie1) 0x50e7 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2 seie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d1 srdie receiv e b uff er full interr upt enab le 1 enab le 0 disab le 0 r/w d0 stdie t r ansmit b uff er empty int. enab le 1 enab le 0 disab le 0 r/w usi ch.1 spi master mode interrupt flag register (usi_sif1) 0x50e8 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3 ssif t r ansf er b usy flag 1 busy 0 idle 0 r d2 seif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d1 srdif receiv e b uff er full flag 1 full 0 not full 0 r/w d0 stdif t r ansmit b uff er empty flag 1 empty 0 not empty 0 r/w appendix a list of i/o registers ap-a-18 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks usi ch.1 spi master mode receive data mask register (usi_smsk1) 0x50e9 (8 bits) d7C0 smsk[7:0] receiv e data mask bit smsk7 = msb smsk0 = lsb 0x0 to 0xff 0x0 r/w usi ch.1 i 2 c master mode trigger register (usi_imtg1) 0x50ea (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 imtg i 2 c master oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 imtgmod [2:0] i 2 c master tr igger mode select imtgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data stop condition star t condition usi ch.1 i 2 c master mode interrupt enable register (usi_imie1) 0x50eb (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 imeie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 imie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w usi ch.1 i 2 c master mode interrupt flag register (usi_imif1) 0x50ec (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 imbsy i 2 c master b usy flag 1 busy 0 standb y 0 r d4C2 imsta[2:0] i 2 c master status imst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y s t o p g e n e r a t e d s t a r t g e n e r a t e d d1 imeif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 imif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w usi ch.1 i 2 c slave mode trigger register (usi_istg1) 0x50ed (8 bits) d7C5 C reser v ed C C C 0 when being read. d4 istg i 2 c sla v e oper ation tr igger 1 t r igger 0 ignored 0 w 1 w aiting 0 finished r d3 C reser v ed C C C 0 when being read. d2C0 istgmod [2:0] i 2 c sla v e tr igger mode select istgmod[2:0] t r igger mode 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed r e c e i v e a c k / n a k t r ansmit nak t r ansmit a ck receiv e data t r ansmit data reser v ed w ait f or star t usi ch.1 i 2 c slave mode interrupt enable register (usi_isie1) 0x50ee (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 iseie receiv e error interr upt enab le 1 enab le 0 disab le 0 r/w d0 isie oper ation completion int. enab le 1 enab le 0 disab le 0 r/w usi ch.1 i 2 c slave mode interrupt flag register (usi_isif1) 0x50ef (8 bits) d7C6 C reser v ed C C C 0 when being read. d5 isbsy i 2 c sla v e b usy flag 1 busy 0 standb y 0 r d4C2 issta[2:0] i 2 c sla v e status isst a[2:0] status 0x0 r 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed nak receiv ed a ck receiv ed a ck/nak sent rx b uff er full t x b u f f e r e m p t y stop detected star t detected d1 iseif ov err un error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d0 isif oper ation completion flag 1 completed 0 n o t c o m p l e t e d 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-19 0x5121 power generator register name ad dress bit name function setting init. r/w remarks v d1 control register (vd1_ctl) s1c17564 0x5121 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 vd1eco [1:0] regulator oper ation mode select vd1eco[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed a uto-control econom y nor mal 0x5200C0x52ab p port & port mux register name ad dress bit name function setting init. r/w remarks p0 port input data register (p0_in) 0x5200 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0in[3:0] p0[3:0] por t input data 1 1 (h) 0 0 (l) r p0 port output data register (p0_out) 0x5201 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0out[3:0] p0[3:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p0 port output enable register (p0_oen) 0x5202 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0oen[3:0] p0[3:0] por t output enab le 1 enab le 0 disab le 0 r/w p0 port pull-up control register (p0_pu) 0x5203 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0pu[3:0] p0[3:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xf) r/w p0 port interrupt mask register (p0_imsk) 0x5205 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0ie[3:0] p0[3:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p0 port interrupt edge select register (p0_edge) 0x5206 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0edge[3:0] p0[3:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p0 port interrupt flag register (p0_iflg) 0x5207 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0if[3:0] p0[3:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p0 port chattering filter control register (p0_chat) 0x5208 (8 bits) d7C3 C reser v ed C C C 0 when being read. d2C0 p0cf1[2:0] p0[3:0] chatter ing filter time p0cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p0 port key- entry reset configuration register (p0_krst) 0x5209 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1C0 p0krst[1:0] p0 por t k e y-entr y reset configur ation p0krst[1:0] configur ation 0x0 r/w 0x3 0x2 0x1 0x0 p0[3:0] = 0 p0[2:0] = 0 p0[1:0] = 0 disab le p0 port input enable register (p0_ien) 0x520a (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C0 p0ien[3:0] p0[3:0] por t input enab le 1 enab le 0 disab le 0xf r/w p1 port input data register (p1_in) 0x5210 (8 bits) d7C0 p1in[7:0] p1[7:0] por t input data 1 1 (h) 0 0 (l) r p1 port output data register (p1_out) 0x5211 (8 bits) d7C0 p1out[7:0] p1[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p1 port output enable register (p1_oen) 0x5212 (8 bits) d7C0 p1oen[7:0] p1[7:0] por t output enab le 1 enab le 0 disab le 0 r/w p1 port pull-up control register (p1_pu) 0x5213 (8 bits) d7C0 p1pu[7:0] p1[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w p1 port interrupt mask register (p1_imsk) 0x5215 (8 bits) d7C0 p1ie[7:0] p1[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w appendix a list of i/o registers ap-a-20 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks p1 port interrupt edge select register (p1_edge) 0x5216 (8 bits) d7C0 p1edge[7:0] p1[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p1 port interrupt flag register (p1_iflg) 0x5217 (8 bits) d7C0 p1if[7:0] p1[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p1 port chattering filter control register (p1_chat) 0x5218 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p1cf2[2:0] p1[7:4] chatter ing filter time p1cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p1cf1[2:0] p1[3:0] chatter ing filter time p1cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p1 port input enable register (p1_ien) 0x521a (8 bits) d7C0 p1ien[7:0] p1[7:0] por t input enab le 1 enab le 0 disab le 0xff r/w p2 port input data register (p2_in) 0x5220 (8 bits) d7C0 p2in[7:0] p2[7:0] por t input data 1 1 (h) 0 0 (l) r p2 port output data register (p2_out) 0x5221 (8 bits) d7C0 p2out[7:0] p2[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p2 port output enable register (p2_oen) 0x5222 (8 bits) d7C0 p2oen[7:0] p2[7:0] por t output enab le 1 enab le 0 disab le 0 r/w p2 port pull-up control register (p2_pu) 0x5223 (8 bits) d7C0 p2pu[7:0] p2[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w p2 port interrupt mask register (p2_imsk) 0x5225 (8 bits) d7C0 p2ie[7:0] p2[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p2 port interrupt edge select register (p2_edge) 0x5226 (8 bits) d7C0 p2edge[7:0] p2[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p2 port interrupt flag register (p2_iflg) 0x5227 (8 bits) d7C0 p2if[7:0] p2[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p2 port chattering filter control register (p2_chat) 0x5228 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p2cf2[2:0] p2[7:4] chatter ing filter time p2cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p2cf1[2:0] p2[3:0] chatter ing filter time p2cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-21 register name ad dress bit name function setting init. r/w remarks p2 port input enable register (p2_ien) 0x522a (8 bits) d7C0 p2ien[7:0] p2[7:0] por t input enab le 1 enab le 0 disab le 0xff r/w p3 port input data register (p3_in) 0x5230 (8 bits) d7C0 p3in[7:0] p3[7:0] por t input data 1 1 (h) 0 0 (l) r p3 port output data register (p3_out) 0x5231 (8 bits) d7C0 p3out[7:0] p3[7:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p3 port output enable register (p3_oen) 0x5232 (8 bits) d7C0 p3oen[7:0] p3[7:0] por t output enab le 1 enab le 0 disab le 0 r/w p3 port pull-up control register (p3_pu) 0x5233 (8 bits) d7C0 p3pu[7:0] p3[7:0] por t pull-up enab le 1 enab le 0 disab le 1 (0xff) r/w p3 port interrupt mask register (p3_imsk) 0x5235 (8 bits) d7C0 p3ie[7:0] p3[7:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p3 port interrupt edge select register (p3_edge) 0x5236 (8 bits) d7C0 p3edge[7:0] p3[7:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p3 port interrupt flag register (p3_iflg) 0x5237 (8 bits) d7C0 p3if[7:0] p3[7:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p3 port chattering filter control register (p3_chat) 0x5238 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p3cf2[2:0] p3[7:4] chatter ing filter time p3cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p3cf1[2:0] p3[3:0] chatter ing filter time p3cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p3 port input enable register (p3_ien) 0x523a (8 bits) d7C0 p3ien[7:0] p3[7:0] por t input enab le 1 enab le 0 disab le 0xff r/w p4 port input data register (p4_in) 0x5240 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4in[5:0] p4[5:0] por t input data 1 1 (h) 0 0 (l) r p4 port output data register (p4_out) 0x5241 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4out[5:0] p4[5:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p4 port output enable register (p4_oen) 0x5242 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4oen[5:0] p4[5:0] por t output enab le 1 enab le 0 disab le 0 r/w p4 port pull-up control register (p4_pu) 0x5243 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4pu[5:0] p4[5:0] por t pull-up enab le 1 enab le 0 disab le 1 (0x2f) r/w p4 port interrupt mask register (p4_imsk) 0x5245 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4ie[5:0] p4[5:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p4 port interrupt edge select register (p4_edge) 0x5246 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4edge[5:0] p4[5:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p4 port interrupt flag register (p4_iflg) 0x5247 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4if[5:0] p4[5:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. appendix a list of i/o registers ap-a-22 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks p4 port chattering filter control register (p4_chat) 0x5248 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p4cf2[2:0] p4[5:4] chatter ing filter time p4cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p4cf1[2:0] p4[3:0] chatter ing filter time p4cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p4 port input enable register (p4_ien) 0x524a (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p4ien[5:0] p4[5:0] por t input enab le 1 enab le 0 disab le 0x2f r/w p5 port input data register (p5_in) 0x5250 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5in[5:0] p5[5:0] por t input data 1 1 (h) 0 0 (l) r p5 port output data register (p5_out) 0x5251 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5out[5:0] p5[5:0] por t output data 1 1 (h) 0 0 (l) 0 r/w p5 port output enable register (p5_oen) 0x5252 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5oen[5:0] p5[5:0] por t output enab le 1 enab le 0 disab le 0 r/w p5 port pull-up control register (p5_pu) 0x5253 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5pu[5:0] p5[5:0] por t pull-up enab le 1 enab le 0 disab le 1 (0x2f) r/w p5 port interrupt mask register (p5_imsk) 0x5255 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5ie[5:0] p5[5:0] por t interr upt enab le 1 enab le 0 disab le 0 r/w p5 port interrupt edge select register (p5_edge) 0x5256 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5edge[5:0] p5[5:0] por t interr upt edge select 1 f alling edge 0 rising edge 0 r/w p5 port interrupt flag register (p5_iflg) 0x5257 (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5if[5:0] p5[5:0] por t interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. p5 port chattering filter control register (p5_chat) 0x5258 (8 bits) d7 C reser v ed C C C 0 when being read. d6C4 p5cf2[2:0] p5[5:4] chatter ing filter time p5cf2[2:0] filter time 0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none 0x0 r/w d3 C reser v ed C C C 0 when being read. d2C0 p5cf1[2:0] p5[3:0] chatter ing filter time p5cf1[2:0] filter time 0x0 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 16384/f pclk 8192/f pclk 4096/f pclk 2048/f pclk 1024/f pclk 512/f pclk 256/f pclk none p5 port input enable register (p5_ien) 0x525a (8 bits) d7C6 C reser v ed C C C 0 when being read. d5C0 p5ien[5:0] p5[5:0] por t input enab le 1 enab le 0 disab le 0x2f r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-23 register name ad dress bit name function setting init. r/w remarks p0[3:0] port function select register (p00_03pmux) 0x52a0 (8 bits) d7C6 p03mux[1:0] p03 por t function select p03mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed us_ssi1* ain3 p03 d5C4 p02mux[1:0] p02 por t function select p02mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed us_ssi0* ain2 p02 d3C2 p01mux[1:0] p01 por t function select p01mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed ain1 p01 d1C0 p00mux[1:0] p00 por t function select p00mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed ain0 p00 p1[3:0] port function select register (p10_13pmux) 0x52a2 (8 bits) d7C6 p13mux[1:0] p13 por t function select p13mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out5/cap5 #spiss0 p13 d5C4 p12mux[1:0] p12 por t function select p12mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed spiclk0 p12 d3C2 p11mux[1:0] p11 por t function select p11mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdo0 p11 d1C0 p10mux[1:0] p10 por t function select p10mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdi0 p10 p1[7:4] port function select register (p14_17pmux) 0x52a3 (8 bits) d7C6 p17mux[1:0] p17 por t function select p17mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed scl0 p17 d5C4 p16mux[1:0] p16 por t function select p16mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk1 sclk1 p16 d3C2 p15mux[1:0] p15 por t function select p15mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdo1 sout1 p15 d1C0 p14mux[1:0] p14 por t function select p14mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed sdi1 sin1 p14 appendix a list of i/o registers ap-a-24 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks p2[3:0] port function select register (p20_23pmux) 0x52a4 (8 bits) d7C6 p23mux[1:0] p23 por t function select p23mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdi2 p23/excl2 d5C4 p22mux[1:0] p22 por t function select p22mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed foutb p22/excl1 d3C2 p21mux[1:0] p21 por t function select p21mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out3/cap3 p21 d1C0 p20mux[1:0] p20 por t function select p20mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out2/cap2 p20 p2[7:4] port function select register (p24_27pmux) 0x52a5 (8 bits) d7C6 p27mux[1:0] p27 por t function select p27mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed scl1 p27 d5C4 p26mux[1:0] p26 por t function select p26mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sd a1 p26 d3C2 p25mux[1:0] p25 por t function select p25mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss2 #bfr p25 d1C0 p24mux[1:0] p24 por t function select p24mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sdo2 p24/excl3 p3[3:0] port function select register (p30_33pmux) 0x52a6 (8 bits) d7C6 p33mux[1:0] p33 por t function select p33mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed spiclk2 remi p33 d5C4 p32mux[1:0] p32 por t function select p32mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed fout a t out4/cap4 p32 d3C2 p31mux[1:0] p31 por t function select p31mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #adtrg #bfr p31 d1C0 p30mux[1:0] p30 por t function select p30mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed t out0/cap0 p30 appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-25 register name ad dress bit name function setting init. r/w remarks p3[7:4] port function select register (p34_37pmux) 0x52a7 (8 bits) d7C6 p37mux[1:0] p37 por t function select p37mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p37 dst2 d5C4 p36mux[1:0] p36 por t function select p36mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p36 dsio d3C2 p35mux[1:0] p35 por t function select p35mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed p35 dclk d1C0 p34mux[1:0] p34 por t function select p34mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed #spiss1 remo p34 p4[3:0] port function select register (p40_43pmux) 0x52a8 (8 bits) d7C6 p43mux[1:0] p43 por t function select p43mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed remi sd a1 p43 d5C4 p42mux[1:0] p42 por t function select p42mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out1/cap1 sclk0 p42 d3C2 p41mux[1:0] p41 por t function select p41mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out7/cap7 sout0 p41 d1C0 p40mux[1:0] p40 por t function select p40mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed t out6/cap6 sin0 p40 p4[5:4] port function select register (p44_45pmux) 0x52a9 (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C2 p45mux[1:0] p45 por t function select p45mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed sd a0 p45/excl0 d1C0 p44mux[1:0] p44 por t function select p44mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed remo scl1 p44 p5[3:0] port function select register (p50_53pmux) 0x52aa (8 bits) d7C6 p53mux[1:0] p53 por t function select p53mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdi1* p53 d5C4 p52mux[1:0] p52 por t function select p52mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sck0* p52 d3C2 p51mux[1:0] p51 por t function select p51mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdo0* p51 d1C0 p50mux[1:0] p50 por t function select p50mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdi0* p50 appendix a list of i/o registers ap-a-26 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks p5[5:4] port function select register (p54_55pmux) 0x52ab (8 bits) d7C4 C reser v ed C C C 0 when being read. d3C2 p55mux[1:0] p55 por t function select p55mux[1:0] function 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sck1* p55 d1C0 p54mux[1:0] p54 por t function select p54mux[1:0] function 0x0 r/w 0x3 0x2 0x1 0x0 reser v ed reser v ed us_sdo1* p54 0x4020, 0x5322C0x532c misc registers register name ad dress bit name function setting init. r/w remarks debug mode control register 1 (misc_dmode1) 0x4020 (8 bits) d7C2 C reser v ed C C C 0 when being read. d1 dbrun1 run/stop select in deb ug mode 1 run 0 stop 0 r/w d0 C reser v ed C C C 0 when being read. debug mode control register 2 (misc_dmode2) 0x5322 (16 bits) d15C1 C reser v ed C C C 0 when being read. d0 dbrun2 run/stop select in deb ug mode (e xcept pclk per ipher al circuits) 1 run 0 stop 0 r/w misc protect register (misc_prot) 0x5324 (16 bits) d15C0 prot[15:0] misc register wr ite protect wr iting 0x96 remo v es the wr ite protection of the misc regis- ters (0x5326C0x532a). wr iting another v alue set the wr ite protection. 0x0 r/w iram size register (misc_iramsz) 0x5326 (16 bits) d15C9 C reser v ed C C C 0 when being read. d8 dbadr deb ug base address select 1 0x0 0 0xfffc00 0 r/w d7 C reser v ed C C C 0 when being read. d6C4 iramactsz [2:0] iram actual siz e 0x6 (= 16kb) 0x6 r d3 C reser v ed C C C 0 when being read. d2C0 iramsz[2:0] iram siz e select iramsz[2:0] siz e 0x6 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 16kb 512b 1kb 2kb 4kb 8kb 12kb vector table address low register (misc_ttbrl) 0x5328 (16 bits) d15C8 ttbr[15:8] v ector tab le base address a[15:8] 0x0C0xff 0x80 r/w d7C0 ttbr[7:0] v ector tab le base address a[7:0] (fix ed at 0) 0x0 0x0 r vector table address high register (misc_ttbrh) 0x532a (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C0 ttbr[23:16] v ector tab le base address a[23:16] 0x0C0xff 0x0 r/w psr register (misc_psr) 0x532c (16 bits) d15C8 C reser v ed C C C 0 when being read. d7C5 psril[2:0] psr interr upt le v el (il) bits 0x0 to 0x7 0x0 r d4 psrie psr interr upt enab le (ie) bit 1 1 (enab le) 0 0 (disab le) 0 r d3 psrc psr carr y (c) flag 1 1 (set) 0 0 (cleared) 0 r d2 psrv psr o v erflo w (v) flag 1 1 (set) 0 0 (cleared) 0 r d1 psrz psr z ero (z) flag 1 1 (set) 0 0 (cleared) 0 r d0 psrn psr negativ e (n) flag 1 1 (set) 0 0 (cleared) 0 r appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-27 0x5340C0x5346 ir remote controller register name ad dress bit name function setting init. r/w remarks remc configuration register (remc_cfg) 0x5340 (16 bits) d15C12 cgclk[3:0] carr ier gener ator cloc k division r atio select cgclk[3:0] lcclk[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d11C8 lcclk[3:0] length counter cloc k division r atio select 0x0 r/w d7C2 C reser v ed C C C 0 when being read. d1 remmd remc mode select 1 receiv e 0 t r ansmit 0 r/w d0 remen remc enab le 1 enab le 0 disab le 0 r/w remc carrier length setup register (remc_car) 0x5342 (16 bits) d15C14 C reser v ed C C C 0 when being read. d13C8 remcl[5:0] carr ier l length setup 0x0 to 0x3f 0x0 r/w d7C6 C reser v ed C C C 0 when being read. d5C0 remch[5:0] carr ier h length setup 0x0 to 0x3f 0x0 r/w remc length counter register (remc_lcnt) 0x5344 (16 bits) d15C8 remlen[7:0] t r ansmit/receiv e data length count (do wn counter) 0x0 to 0xff 0x0 r/w d7C1 C reser v ed C C C 0 when being read. d0 remdt t r ansmit/receiv e data 1 1 (h) 0 0 (l) 0 r/w remc interrupt control register (remc_int) 0x5346 (16 bits) d15C11 C reser v ed C C C 0 when being read. d10 remfif f alling edge interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d9 remrif rising edge interr upt flag 0 r/w d8 remuif underflo w interr upt flag 0 r/w d7C3 C reser v ed C C C 0 when being read. d2 remfie f alling edge interr upt enab le 1 enab le 0 disab le 0 r/w d1 remrie rising edge interr upt enab le 1 enab le 0 disab le 0 r/w d0 remuie underflo w interr upt enab le 1 enab le 0 d isab le 0 r/w 0x5380C0x5388 a/d converter register name ad dress bit name function setting init. r/w remarks a/d conversion result register (adc10_add) 0x5380 (16 bits) d15C0 add[15:0] a/d con v er ted data add[9:0] are eff ectiv e when stmd = 0 (add[15:10] = 0) add[15:6] are eff ectiv e when stmd = 1 (add[5:0] = 0) 0x0 to 0x3ff 0x0 r a/d trigger/ channel select register (adc10_trg ) 0x5382 (16 bits) d15C14 C reser v ed C C C 0 when being read. d13C11 adce[2:0] end channel select 0x0 to 0x3 0x0 r/w d10C8 adcs[2:0] star t channel select 0x0 to 0x3 0x0 r/w d7 stmd con v ersion result stor ing mode 1 add[15:6] 0 add[9:0] 0 r/w d6 adms con v ersion mode select 1 contin uous 0 single 0 r/w d5C4 adts[1:0] con v ersion tr igger select adts[1:0] t r igger 0x0 r/w 0x3 0x2 0x1 0x0 #adtrg pin reser v ed t16 ch.0 softw are d3 C reser v ed C C C 0 when being read. d2C0 adst[2:0] sampling time setting adst[2: 0] sampling time 0x7 r/w 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 9 cycles 8 cycles 7 cycles 6 cycles 5 cycles 4 cycles 3 cycles 2 cycles appendix a list of i/o registers ap-a-28 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks a/d control/ status register (adc10_ctl ) 0x5384 (16 bits) d15 C reser v ed C C C 0 when being read. d14C12 adich[2:0] con v ersion channel indicator 0x0 to 0x3 0x0 r d11 C reser v ed C C C 0 when being read. d10 adibs adc10 status 1 busy 0 idle 0 r d9 adowe ov erwr ite error flag 1 error 0 nor mal 0 r/w reset b y wr iting 1. d8 adcf con v ersion completion flag 1 completed 0 run/stand- b y 0 r r e s e t w h e n a d c 1 0 _ add is read. d7C6 C reser v ed C C C 0 when being read. d5 adoie ov erwr ite error interr upt enab le 1 enab le 0 disab le 0 r/w d4 adcie con v ersion completion int. enab le 1 enab le 0 disab le 0 r/w d3C2 C reser v ed C C C 0 when being read. d1 adctl a/d con v ersion control 1 star t 0 stop 0 r/w d0 aden adc10 enab le 1 enab le 0 disab le 0 r/w a/d clock control register (adc10_clk) 0x5386 (16 bits) d15C4 C reser v ed C C C 0 when being read. d3C0 addf[3:0] a/d con v er ter cloc k division r atio select addf[3:0] division r atio 0x0 r/w s o u r c e c l o c k = p c l k 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reser v ed 1/32768 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 a/d comparator setting register (adc10_com ) 0x5388 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 fsel[1:0] a/d compar ator adjustment 0x0 to 0x3 0x0 r/w d3C2 C reser v ed C C C 0 when being read. d1C0 xpd[1:0] a/d compar ator adjustment 0x0 to 0x3 0x3 r/w 0x5068, 0x5400C0x540c 16-bit pwm timer ch.0 register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.0 (t16a_clk0) 0x5068 (8 bits) d7C4 clkdiv [3:0] cloc k division r atio select clkdiv[3:0] division r atio 0x0 r/w osc3 or iosc osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C C 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 multimd multi-compar ator/capture mode selec t 1 multi 0 nor mal 0 r/w d0 clken count cloc k enab le 1 enab le 0 disab le 0 r/w t16a counter ch.0 control register (t16a_ctl0) 0x5400 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 ccabcnt [1:0] counter select ccabcnt[1:0] counter ch. 0x0 r/w 0x3 0x2 0x1 0x0 ch.3 ch.2 ch.1 ch.0 d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-29 register name ad dress bit name function setting init. r/w remarks t16a counter ch.0 data register (t16a_tc0) 0x5402 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r t16a comparator/ capture ch.0 control register (t16a_ccctl 0 ) 0x5404 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x 1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w t16a comparator/ capture ch.0 a data register (t16a_cca0) 0x5406 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.0 b data register (t16a_ccb0) 0x5408 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.0 interrupt enable register (t16a_ien0) 0x540a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w t16a comparator/ capture ch.0 interrupt flag register (t16a_iflg0) 0x540c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w appendix a list of i/o registers ap-a-30 seiko epson corporation s1c17554/564 t echnical m anual 0x5069, 0x5420C0x542c 16-bit pwm timer ch.1 register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.1 (t16a_clk1) 0x5069 (8 bits) d7C4 clkdiv [3:0] cloc k division r atio select clkdiv[3:0] division r atio 0x0 r/w osc3 or iosc osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C C 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C d0 clken count cloc k enab le 1 en ab le 0 disab le 0 r/w t16a counter ch.1 control register (t16a_ctl1) 0x5420 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 ccabcnt [1:0] counter select ccabcnt[1:0] counter ch. 0x0 r/w 0x3 0x2 0x1 0x0 ch.3 ch.2 ch.1 ch.0 d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w t16a counter ch.1 data register (t16a_tc1) 0x5422 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r t16a comparator/ capture ch.1 control register (t16a_ccctl 1 ) 0x5424 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x 1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w t16a comparator/ capture ch.1 a data register (t16a_cca1) 0x5426 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.1 b data register (t16a_ccb1) 0x5428 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-31 register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.1 interrupt enable register (t16a_ien1) 0x542a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w t16a comparator/ capture ch.1 interrupt flag register (t16a_iflg1) 0x542c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w 0x506a, 0x5440C0x544c 16-bit pwm timer ch.2 register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.2 (t16a_clk2) 0x506a (8 bits) d7C4 clkdiv [3:0] cloc k division r atio select clkdiv[3:0] division r atio 0x0 r/w osc3 or iosc osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C C 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C d0 clken count cloc k enab le 1 en ab le 0 disab le 0 r/w t16a counter ch.2 control register (t16a_ctl2) 0x5440 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 ccabcnt [1:0] counter select ccabcnt[1:0] counter ch. 0x0 r/w 0x3 0x2 0x1 0x0 ch.3 ch.2 ch.1 ch.0 d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w t16a counter ch.2 data register (t16a_tc2) 0x5442 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r appendix a list of i/o registers ap-a-32 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.2 control register (t16a_ccctl 2 ) 0x5444 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x 1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w t16a comparator/ capture ch.2 a data register (t16a_cca2) 0x5446 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.2 b data register (t16a_ccb2) 0x5448 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.2 interrupt enable register (t16a_ien2) 0x544a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w t16a comparator/ capture ch.2 interrupt flag register (t16a_iflg2) 0x544c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w appendix a list of i/o registers s1c17554/564 t echnical m anual seiko epson corporation ap-a-33 0x506b, 0x5460C0x546c 16-bit pwm timer ch.3 register name ad dress bit name function setting init. r/w remarks t16a clock control register ch.3 (t16a_clk3) 0x506b (8 bits) d7C4 clkdiv [3:0] cloc k division r atio select clkdiv[3:0] division r atio 0x0 r/w osc3 or iosc osc1 0xf 0x e 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 C 1/16384 1/8192 1/4096 1/2048 1/1024 1/512 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 C C C C C C C 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1/1 d3C2 clksrc [1:0] cloc k source select clksrc[1:0] cloc k source 0x0 r/w * s1c17564 only 0x3 0x2 0x1 0x0 exter nal cloc k osc3 osc1 iosc* d1 C reser v ed C C C d0 clken count cloc k enab le 1 en ab le 0 disab le 0 r/w t16a counter ch.3 control register (t16a_ctl3) 0x5460 (16 bits) d15C6 C reser v ed C C C 0 when being read. d5C4 ccabcnt [1:0] counter select ccabcnt[1:0] counter ch. 0x0 r/w 0x3 0x2 0x1 0x0 ch.3 ch.2 ch.1 ch.0 d3 cbufen compare b uff er enab le 1 enab le 0 disab le 0 r/w d2 trmd count mode select 1 one-shot 0 repeat 0 r/w d1 preset counter reset 1 reset 0 ignored 0 w 0 when being read. d0 prun counter r un/stop control 1 run 0 stop 0 r/w t16a counter ch.3 data register (t16a_tc3) 0x5462 (16 bits) d15C0 t16atc [15:0] counter data t16a tc15 = msb t16a tc0 = lsb 0x0 to 0xffff 0x0 r t16a comparator/ capture ch.3 control register (t16a_ccctl 3 ) 0x5464 (16 bits) d15C14 capbtrg [1:0] capture b tr igger select capbtrg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x1 0x0 and none d13C12 toutbmd [1:0] t out b mode select t outbmd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d11C10 C reser v ed C C C 0 when being read. d9 toutbinv t out b in v er t 1 in v er t 0 nor mal 0 r/w d8 ccbmd t16a_ccb register mode select 1 capture 0 compar ator 0 r/w d7C6 capatrg [1:0] capture a tr igger select cap a trg[1:0] t r igger edge 0x0 r/w 0x3 0x2 0x 1 0x0 and none d5C4 toutamd [1:0] t out a mode select t out amd[1:0] mode 0x0 r/w 0x3 0x2 0x1 0x0 cmp b: or cmp a: or cmp a: , b: off d3C2 C reser v ed C C C 0 when being read. d1 toutainv t out a in v er t 1 in v er t 0 nor mal 0 r/w d0 ccamd t16a_cca register mode select 1 capture 0 compar ator 0 r/w t16a comparator/ capture ch.3 a data register (t16a_cca3) 0x5466 (16 bits) d15C0 cca[15:0] compare/capture a data cca15 = msb cca0 = lsb 0x0 to 0xffff 0x0 r/w t16a comparator/ capture ch.3 b data register (t16a_ccb3) 0x5468 (16 bits) d15C0 ccb[15:0] compare/capture b data ccb15 = msb ccb0 = lsb 0x0 to 0xffff 0x0 r/w appendix a list of i/o registers ap-a-34 seiko epson corporation s1c17554/564 t echnical m anual register name ad dress bit name function setting init. r/w remarks t16a comparator/ capture ch.3 interrupt enable register (t16a_ien3) 0x546a (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowie capture b o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d4 capaowie capture a o v erwr ite interr upt enab le 1 enab le 0 disab le 0 r/w d3 capbie capture b interr upt enab le 1 enab le 0 disab le 0 r/w d2 capaie capture a interr upt enab le 1 enab le 0 disab le 0 r/w d1 cbie compare b interr upt enab le 1 enab le 0 disab le 0 r/w d0 caie compare a interr upt enab le 1 enab le 0 disab le 0 r/w t16a comparator/ capture ch.3 interrupt flag register (t16a_iflg3) 0x546c (16 bits) d15C6 C reser v ed C C C 0 when being read. d5 capbowif capture b o v erwr ite interr upt flag 1 cause of interr upt occurred 0 cause of interr upt not occurred 0 r/w reset b y wr iting 1. d4 capaowif capture a o v erwr ite interr upt flag 0 r/w d3 capbif capture b interr upt flag 0 r/w d2 capaif capture a interr upt flag 0 r/w d1 cbif compare b interr upt flag 0 r/w d0 caif compare a interr upt flag 0 r/w 0x54b0 flash controller register name ad dress bit name function setting init. r/w remarks flashc read wait control register (flashc_ wait) 0x54b0 (16 bits) d15C2 C reser v ed C C C 0 when being read. d1C0 rdwait [1:0] flash read w ait cycle rd w ait[1:0] w ait 0x3 r/w 0x3 0x2 0x1 0x0 2 w ait 1 w ait no w ait reser v ed 0xffff84C0xffffd0 s1c17 core i/o register name ad dress bit name function setting init. r/w remarks processor id register (idir) 0xffff84 (8 bits) d7C0 idir[7:0] processor id 0x10: s1c17 core 0x10 0x10 r debug ram base register (dbram) 0xffff90 (32 bits) d31C24 C un used (fix ed at 0) 0x0 0x0 r d23C0 dbram[23:0] deb ug ram base address 0x2fc0 0x2f c0 r debug control register (dcr) 0xffffa0 (8 bits) d7 ibe4 instr uction break #4 enab le 1 enab le 0 disab le 0 r/w d6 ibe3 instr uction break #3 enab le 1 enab le 0 disab le 0 r/w d5 ibe2 instr uction break #2 enab le 1 enab le 0 disab le 0 r/w d4 dr deb ug request flag 1 occurred 0 n o t o c c u r r e d 0 r/w reset b y wr iting 1. d3 ibe1 instr uction break #1 enab le 1 enab le 0 disab le 0 r/w d2 ibe0 instr uction break #0 enab le 1 enab le 0 disab le 0 r/w d1 se single step enab le 1 enab le 0 disab le 0 r/w d0 dm deb ug mode 1 d e b u g m o d e 0 user mode 0 r instruction break address register 1 (ibar1) 0xffffb4 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar1[23:0] instr uction break address #1 ibar123 = msb ibar10 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 2 (ibar2) 0xffffb8 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar2[23:0] instr uction break address #2 ibar223 = msb ibar20 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 3 (ibar3) 0xffffbc (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar3[23:0] instr uction break address #3 ibar323 = msb ibar30 = lsb 0x0 to 0xffffff 0x0 r/w instruction break address register 4 (ibar4) 0xffffd0 (32 bits) d31C24 C reser v ed C C C 0 when being read. d23C0 ibar4[23:0] instr uction break address #4 ibar423 = msb ibar40 = lsb 0x0 to 0xffffff 0x0 r/w appendix b po wer sa ving s1c17554/564 t echnical m anual seiko epson corporation ap-b-1 a ppendix b p o wer sa ving c u r r e n t c o n s u m p t i o n w i l l v a r y d r a m a t i c a l l y , d e p e n d i n g o n c p u o p e r a t i n g m o d e , o p e r a t i o n c l o c k f r e q u e n c y , a n d t h e peripheral circuits being operated. listed belo w are the control methods for sa ving po wer . cloc k contr ol p o wer sa ving b.1 this section describes clock systems that can be controlled via softw are and po wer -sa ving control details. f or more information on control re gi sters and control methods, refer to the respecti v e module sections. system sleep (all c loc ks stopped) ? ex ecute the slp instruction ex ecute the slp instruction when the entire system can be stopped. the cpu enters sleep mode and the system clocks stop. this also stops all peripheral circuits using clocks. starting up the cpu from sleep mode is therefore limited to startup using a port (described later). system c loc ks ? select a lo w-speed clock source (clg module) select a lo w-speed oscillator for the system clock source. y ou can reduce current consumption by selecting the osc1 clock when lo w-speed processing is possible. ? disable unnecessary oscillator circuits (clg module) operate the oscillator comprising the system clock source. where possible, stop the other oscillators. y ou can reduce current consumption by using osc1 as the system clock and disable the iosc and osc3 oscillators. cpu c loc k (cclk) ? ex ecute the halt instruction ex ecute the halt instruction when program e x ecution by the cpu is not requiredfor e xample, when only the display is required or for interrupt standby . the cpu enters hal t mode and suspends operations, b ut the peripheral circuits maintain the status in place at the time of the halt instruction, enabling use of peripheral circuits for timers and interrupts. y ou can reduce po wer consumption e v en further by suspending unneces- sary oscillator and peripheral circuits before e x ecuting the halt instruction. the cpu is started from hal t mode by an interrupt from a port or the peripheral circuit operating in hal t mode. ? select a lo w-speed clock gear (clg module) th e cl g mo du le c a n re du c e cp u cl oc k sp ee ds t o be tw ee n 1/ 1 a nd 1 /8 o f th e s ys te m cl oc k vi a the c lo ck g ea r settings. y ou can reduce current consumption by operating the cpu at the minimum speed required for the application. p eripheral c loc k (pclk) ? stop pclk (clg module) s t o p t h e p c l k c l o c k s u p p l i e d f r o m t h e c l g t o p e r i p h e r a l c i r c u i t s i f n o n e o f t h e f o l l o w i n g p e r i p h e r a l c i r c u i t s is required. peripheral circuits th at use pclk ? u ar t ch.0 and ch.1 ? fine mode 16-bit timer ch.0 and ch.1 ? 16-bit timer ch.0 to ch.2 ? spi ch.0 to ch.2 ? usi ch.0 and ch.1 (s1c17564) ? i 2 c master ? i 2 c sla v e ? po wer generator (s1c17564) ? p ports and port mux (control re gisters, chattering f ilters) ? misc re gisters ? ir remote controller ? a/d con v erter appendix b po wer sa ving ap-b-2 seiko epson corporation s1c17554/564 t echnical m anual pclk is not required for the peripheral modules/functions sho wn belo w . peripheral circuits/functions that do not use pclk ? clock timer ? stopw atch timer ? w atchdog timer ? 16-bit pwm timer ch.0 to ch.3 ? fout a/foutb outputs t able b.1.1 sho ws a list of methods for clock control and starting/stopping the cpu. 1.1 cloc k control list t ab le b . current consumption osc1 iosc/osc3 cpu (cclk) pclk peripheral osc1 peripheral cpu stop method cpu star tup method lo w stop stop stop stop stop ex ecute slp instr uction 1 oscillation (system clk) stop stop stop run ex ecute halt instr uction 1, 2 oscillation (system clk) stop stop run run ex ecute halt instr uction 1, 2, 3 oscillation (system clk) stop run (1/1) run run oscillation oscillation (system clk) stop run run ex ecute halt instr uction 1, 2, 3 oscillation oscill ation (system clk) run (lo w gear) run run high oscillation oscillation (system clk) run (1/1) run run hal t and sleep mode cancelation methods (cpu star tup method) 1. star tup b y por t star ted up b y an i/o por t interr upt or a deb ug interr upt (icd f orced break). 2. star tup b y osc1 per ipher al circuit star ted up b y a cloc k timer , stopw atch timer , or w atchdog timer interr upt. 3. star tup b y pclk per ipher al circuit star te d up b y a pclk per ipher al circuit interr upt. reducing p o wer consumption via p o wer suppl y contr ol b.2 the a v ailable po wer supply controls are listed belo w . regulator operating mode (s1c17564) when the embedded re gulator is used in the s1c17564, it should be placed into economy mode (po wer sa v- i n g m o d e ) t o r e d u c e c u r r e n t c o n s u m p t i o n d u r i n g l o w - s p e e d (32 k h z ) o p e r a t i o n o r s t a n d b y m o d e ( h a l t o r sleep). f or controlling economy mode, see the po wer supply chapter . appendix c mounting preca utions s1c17554/564 t echnical m anual seiko epson corporation ap-c-1 a ppendix c mounting pr ecautions this section describes v arious precautions for circuit board design and ic mounting. oscillator cir cuit ? o s c i l l a t i o n c h a r a c t e r i s t i c s d e p e n d o n f a c t o r s s u c h a s c o m p o n e n t s u s e d ( r e s o n a t o r , r f , c g , c d ) a n d c i r c u i t board patterns. in particular , with ceramic or crystal resonators, select the appropriate e xternal resistor (r f ) and capacitors (c g , c d ) only after fully e v aluating components actually mounted on the circuit board. ? oscillator clock disturbances caused by noise may cause malfunctions. t o pre v ent such disturbances, consid- er the follo wing points. the latest de vices, in particular , are manuf actured by microscopic processes, making them especially susceptible to noise. a r e a s i n w h i c h n o i s e c o u n t e r m e a s u r e s a r e e s p e c i a l l y i m p o r t a n t i n c l u d e t h e o s c2 p i n a n d r e l a t e d c i r c u i t c o m p o n e n t s a n d w i r i n g . o s c1 p i n h a n d l i n g i s e q u a l l y i m p o r t a n t . t h e n o i s e p r e c a u t i o n s r e q u i r e d f o r t h e osc1 and osc2 pins are described belo w . w e also recommend applying similar noise countermeasures to the high-speed oscillator circuit, such as the osc3 and osc4 pins and wiring. (1) c o m p o n e n t s s u c h a s a r e s o n a t o r , r e s i s t o r s , a n d c a p a c i t o r s c o n n e c t e d t o t h e o s c 1 ( o s c 3 ) a n d o s c 2 ( o s c 4 ) pins should ha v e the shortest connections possible. (2) where v er possible, a v oid locating digital signal lines within 3 mm of the osc1 (osc3) and osc2 (osc4) pins or related circuit components and wiring. rapidly-switching signals, in particular , should be k ept at a distance from these components. since the spacing between layers of multi-layer printed circuit boards is a mere 0.1 mm to 0.2 mm , the abo v e precautions also apply when positioning digital signal lines on other layers. ne v er place digital signal lines alongside such components or wiring, e v en if more than 3 mm distance or located on other layers. a v oid crossing wires. (3) u s e v s s t o s h i e l d o s c 1 ( o s c 3 ) a n d o s c 2 ( o s c 4 ) p i n s a n d r e l a t e d w i r i n g ( i n c l u d i n g w i r i n g f o r a d j a c e n t c i r c u i t b o a r d l a y e r s ) . l a y e r s w i r e d s h o u l d b e a d e q u a t e l y s h i e l d e d a s s h o w n t o t h e r i g h t . f u l l y g r o u n d a d j a c e n t l a y - ers, where possible. at minimum, shield the area at least 5 mm around the abo v e pins and wiring. ev en after implementing these precautions, a v oid conf iguring digital signal lines in parallel, as described in (2) abo v e. a v oid crossing e v en on discrete layers, e xcept for lines carrying signals with lo w switching frequencies. (4) after imple menting these precautions, check the output clock w a v eform by running the actual application program within the product. use an oscilloscope to check the fout a or foutb pin output. y ou can check the quality of the osc3 output w a v eform via the fout a/b output. conf irm that the fre- quenc y is as designed, is free of noise, and has minimal jitter . y ou can check the quality of the osc1 w a v eform via th e fout a/b output. in particular , enlar ge the areas before and after the clock rising and f alling edges and tak e special care to conf irm that the re gions approxi- mately 100 ns to either side are free of clock or spiking noise. f ailure to observ e precautions (1) to (3) adequately may lead to jitter in the osc3 output and noise in the osc1 output. jitter in the osc3 output will reduce operating frequ encies, while noise in the osc1 output will destabilize timers operated by the osc1 clock as well as cpu core operations when the system clock switches to osc1. reset cir cuit ? the reset signal input to the #reset pin when po wer is turned on will v ary , depending on v arious f actors, such as po wer supply start-up time, components used, and circuit board patterns. constants such as capaci- tance and res istance should be determined through testing with real-w orld products. ? components such as capacitors and resistors connected to the #reset pin should ha v e the shortest connec- tions possible to pre v ent noise-induced resets. osc4 osc3 v ss sample v ss pattern (osc3) appendix c mounting preca utions ap-c-2 seiko epson corporation s1c17554/564 t echnical m anual p o wer suppl y cir cuit sudden po wer supply fluctuations due to noise will cause malfunctions. consider the follo wing issues. (1) connections from the po wer supply to the *v dd (l v dd , hv dd , a v dd ) and v ss pins should be implement- ed via the shortest, thick est patterns possible. (2) if a bypass capacitor is connected between *v dd and v ss , connections between the *v dd and v ss pins should be as short as pos sible. *v dd v ss bypass capacitor connection example *v dd v ss signal line location ? t o pre v ent electromagnetically-induced noise arising from mutual induction, lar ge-current signal lines should not be positioned close to circuits susceptible to noise, such as oscillators. ? locating signal lines in parallel o v er signif icant distances or crossing signal lines operating at high speed will cause malfunctions due to noise generated by mutual interference. specif i cally , a v oid positioning crossing signal lines operating at high speed close to circuits susceptible to noise, such as oscillators. osc1, osc3 osc2, osc4 v ss large current signal line high-speed signal line prohibited pattern noise-induced malfunctions check the follo wing three points if you suspect the presence of noise-induced ic malfunctions. (1) dsio pin lo w-le v el noise to this pin will cause a switch to deb ug mode. the switch to deb ug mode can be conf irmed by the clock output from dclk and a high signal from the dst2 pin. f or the product v ersion, we recommend connecting the dsio pin directly to hv dd or pulling up t he diso pin using a resistor not e xceeding 10 kw. the ic includes an internal pull-up resistor . the resistor has a relati v ely high impedance of 100 kw to 500 kw and is not noise-resistant. (2) #reset pin lo w-le v el noise to this pin will reset the ic. depending on the input w a v eform, the reset may not proceed correctly . this is more lik ely to occur if, due to circuit design choices, the impedance is high when the reset input is high. (3) l v dd , hv dd , a v dd , and v ss po wer supply the ic will malfunction at the instant when noise f alling belo w the rated v oltage is input. incorporate coun- t e r m e as u r e s o n t h e ci r cu i t b o ar d , i n c l u d i n g c l o s e p at t er n s f o r ci r cu i t b o a r d p o w e r s u p p l y ci r cu i t s , n o i s e- f iltering decoupling capacitors, and sur ge/noise pre v ention components on the po wer supply line. perform th e inspections described abo v e using an oscilloscope capable of observing w a v eforms of at least 200 mhz. it may not be possible to observ e high-speed noise e v ents with a lo w-speed oscilloscope. appendix c mounting preca utions s1c17554/564 t echnical m anual seiko epson corporation ap-c-3 if you detect potential noise-induced malfunctions while observing the w a v eform with an oscilloscope, recheck with a lo w-impedance (less than 1 kw) resistor connecting the rele v ant pin to gnd or to the po wer supply . malfunctions at that pin are lik ely if changes are visible, such as the malfunction disappearing, becoming less frequent, or the phenomena changing. the dsio and #reset input circuits described abo v e detect input signal edges and are susceptible to malfunc- tions induced by spik e noise. this mak es these digital signal pins the most susceptible to noise. t o reduce potential noise, k eep the follo wing tw o points in mind when designing circuit boards: (a) it is important to lo wer the signal-dri ving impedance, as described abo v e. connect pins to the po wer supply or gnd, with impedanc e of 1 kw or less, preferably 0 w. the signal lines connected should be no longer than approximately 5 mm. (b) p arallel routing of signal lines with other digital lines on the board is undesirable, since the noise generated when the signal changes from high to lo w or vice v ersa may adv ersely af fect the digital lines. the sig- nal may be subject to the most noise when signal lines are laid between mu ltiple signal lines whose states c h a n g e s i m u l t a n e o u s l y . t a k e c o r r e c t i v e m e a s u r e s b y s h o r t e n i n g t h e p a r a l l e l d i s t a n c e ( t o s e v e r a l c m ) o r separating signal lines (2 mm or more). handling of light (f or bare c hip mounting) the characteristics of semiconductor components can v ary when e xposed to light. ics may malfunction or non- v olatile memory data may be corrupted if ics are e xposed to light. consider the follo wing precautions for circuit boards and products in which this ic is mounted to pre v ent ic malfunctions attrib utable to light e xposure. (1) design and mount the product so that the ic is shielded from light during use. (2) shield the ic from light during inspection processes. (3) shield the ic on the upper , underside, and side f aces of the ic chip. (4) mount the ic chip within one week of op ening the package. if the ic chip must be stored before mounting, tak e measures to ensure light shielding. (5) adequate e v aluations are required to assess non v olatile memory data retention characteristics before prod- uct deli v ery if the product is subjected to heat stress e xceeding re gular reflo w conditions during mounting processes. un used pins (1) i/o port (p) pins unused pins should be left open. the control re gisters should be f ix ed at the initial status (input with pull- up enabled). (2) osc1, osc2, osc3, and osc4 pins if an oscillator circuit is not used, the oscillator pins should be left open. the control re gisters should be f ix ed at the initial status (oscillation disabled). miscellaneous this product series is manuf actured using microscopic processes. although it is designed to ensur e basic ic reliability meeting eiaj and mil standards, minor v ariations o v er time may result in electrical damage arising from disturbances in the form of v oltages e xceeding the absolute maximum rating when mounting the product in addition to ph ysical damage. the follo wing f actors can gi v e rise to these v ariations: (1) electromagnetically-induced noise from industrial po wer supplies used in mountin g reflo w , re w orking after mounting, and indi vidual characteristic e v aluation (testing) processes (2) electromagnetically-induced noise from a solder iron when soldering in particular , during soldering, tak e care to ensure that the soldering iron gnd (tip potential) has the same po- tential as the ic gnd. appendix d initializa tion r outine s1c17554/564 t echnical m anual seiko epson corporation ap-d-1 a ppendix d initialization routine the follo wing lists typical v ector tables and initialization routines: boot.s .org 0x8000 .section .rodata ...(1) ; ====================================================================== ; vector table ; ====================================================================== ; interrupt vector interrupt ; number offset source .long boot ; 0x00 0x00 reset ...(2) .long unalign_handler ; 0x01 0x04 unalign .long nmi_handler ; 0x02 0x08 nmi .long int03_handler ; 0x03 0x0c - .long p0_handler ; 0x04 0x10 p0 port .long p1_handler ; 0x05 0x14 p1 port .long swt_handler ; 0x06 0x18 swt .long ct_handler ; 0x07 0x1c ct .long t16a_2_handler ; 0x08 0x20 t16a ch2 .long p4_handler ; 0x09 0x24 p4 port .long spi_2_handler ; 0x0a 0x28 spi ch2 .long t16a_0_handler ; 0x0b 0x2c t16a ch0 .long t16f_0_1_usi_0_1_handler ; 0x0c 0x30 t16f ch0,ch1/usi ch0,ch1 .long t16_0_handler ; 0x0d 0x34 t16 ch0 .long t16_1_handler ; 0x0e 0x38 t16 ch1 .long t16_2_t16a_3_handler ; 0x0f 0x3c t16 ch2/t16a ch3 .long uart_0_handler ; 0x10 0x40 uart ch0 .long uart_1_handler ; 0x11 0x44 uart ch1 .long spi_0_handler ; 0x12 0x48 spi ch0 .long i2cm_handler ; 0x13 0x4c i2c master .long remc_spi_1_handler ; 0x14 0x50 remc/spi ch1 .long t16a_1_handler ; 0x15 0x54 t16a ch1 .long adc10_handler ; 0x16 0x58 adc10 .long p5_handler ; 0x17 0x5c p5 port .long p2_handler ; 0x18 0x60 p2 port .long p3_handler ; 0x19 0x64 p3 port .long i2cs_handler ; 0x1a 0x68 i2c slave .long int1b_handler ; 0x1b 0x6c - .long int1c_handler ; 0x1c 0x70 - .long int1d_handler ; 0x1d 0x74 - .long int1e_handler ; 0x1e 0x78 - .long int1f_handler ; 0x1f 0x7c - ; ====================================================================== ; program code ; ====================================================================== .text ...(3) .align 1 boot: ; ===== initialize =========================================== ; ----- stack pointer -------------------- xld.a %sp, 0x0f00 ...(4) ; ----- memory controller ---------------- xld.a %r1, 0x54b0 ; flashc register address ; flash read wait cycle xld.a %r0, 0x01 ; no wait under 14.75 mhz ld.b [%r1], %r0 ; [0x54b0] <= 0x01 ...(5) ; ===== main routine ========================================= ... appendix d initializa tion r outine ap-d-2 seiko epson corporation s1c17554/564 t echnical m anual ; ====================================================================== ; interrupt handler ; ====================================================================== ; ----- address unalign -------------------------- unalign_handler: ... ; ----- nmi ------------------------------------- nmi_handler: ... (1) a .rodata section is declared to locate the v ector table in the .vector section. (2) interrupt handler routine addresses are def ined as v ectors. intxx_handler can be used for softw are interrupts. (3) the program code is written in the .text section. (4) sets the stack pointer . (5) sets the number of flash memory w ait c ycles. can be set to no w ait when the system clock is 14.75 mhz or lo wer . (see the memo ry map, bus control chapter .) appendix e recommended resona t ors s1c17554/564 t echnical m anual seiko epson corporation ap-e-1 a ppendix e recommended resonators optimum oscillator component v alues v ary depending on operating conditions such as a printed circuit board and po wer v oltage. please ask the manuf acturer to e v aluate the resonator mounted on the circuit board. (1) osc1 cr ystal resonator oscillation frequenc y [khz] man ufacturer pr oduct n umber 32.768 epson t o y ocom cor por ation mc-146 (smd) (2) osc3 cr ystal resonator oscillation frequenc y [mhz] man ufacturer pr oduct n umber 4 epson t o y ocom cor por ation ma-406 (smd) 16 epson t o y ocom cor por ation f a-238 (smd) 20 epson t o y ocom cor por ation f a-238 (smd) (3) osc3 ceramic resonator s oscillation frequenc y [mhz] man ufacturer pr oduct n umber 2 mur ata man uf actur ing co ., ltd. cstcc2m00g56 (smd) 8 mur ata man uf actur ing co ., ltd. cstce8m00g55 (smd) 14.75 mur ata man uf actur ing co ., ltd. cstce14m7v51 (smd) 24 mur ata man uf actur ing co ., ltd. cstcg24m0v51 (smd) re vision histor y code no. p a g e contents 411914400 all ne w estab lishment america epson electronics america, inc. 2580 orchard parkway, san jose, ca 95131, usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15, 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg., no.89 jinbao st., dongcheng district, beijing 100005, china phone: +86-10-8522-1199 fax: +86-10-8522-1125 shanghai branch 7f, block b, hi-tech bldg., 900 yishan road, shanghai 200233, china phone: +86-21-5423-5577 fax: +86-21-5423-4677 shenzhen branch 12f, dawning mansion, keji south 12th road, hi-tech park, shenzhen 518057, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson hong kong ltd. 20/f, harbour centre, 25 harbour road, wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110, taiwan phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corp. korea office 50f, kli 63 bldg., 60 yoido-dong, youngdeungpo-ku, seoul 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 seiko epson corp. semiconductor operations division ic sales dept. ic international sales group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 international sales operations document code: 411914400 issue apr il 2010 in j ap an l |
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