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sym53c895 pci-ultra2 scsi i/o processor with lvdlink universal transceivers data manual version 3.0 m59983i . scsi lvd/se
the products described in this publication are products of symbios, inc. scripts and lvdlink are trademarks, and tolerant is a registered trademark, of symbios, inc. ultra scsi is the term used by the scsi trade association to describe fast-20 scsi, as documented in the scsi-3 fast-20 parallel interface standard, x3.277- 199x. ultra2 scsi is the term used by the scsi trade association to describe fast-40 scsi, as documented in early versions of the spi-2 draft standard. it is the policy of symbios to improve products as new technology, components, software, and firmware become available. symbios, therefore, reserves the right to change specifications without notice. the products in this manual are not intended for use in life-support appliances, devices, or systems. use of these products in such applications without the written consent of the appropriate symbios officer is prohibited. copyright ? 1998 by symbios, inc. all rights reserved printed in u.s.a. we use comments from our readers to improve symbios product literature. please e-mail any comments regarding technical documentation to pubs@symbios.com.
sym53c895 data manual i preface preface this manual assumes some prior knowledge of current and proposed scsi and pci standards. for back- ground information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-1994 (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2) or x3.253 (scsi-3 parallel interface) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface symbios electronic bulletin board (719) 533-7235 scsi electronic bulletin board (719) 533-7950 symbios internet anonymous ftp site ftp.symbios.com (204.131.200.1) directory: /pub/symchips/scsi symbios world wide web home page www.symbios.com/t10 pci special interest group 2575 n.e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 sym53c8xx family programming guide
ii sym53c895 data manual preface document history page no. date remarks n/a 7/96 ver. 1.0 1-2, 2-5, 2-17, 2-19, 3-11, 3-12, 4-2, 4-4, 4-7, 4-8, 4-9, 4-10, 4-11, 4-13, 5-39, 5- 40, 7-2, 7-3, 7-7, 7- 8, 7-38, 7-42, 7-44 1/97 ver. 2.0. added serial eeprom interface; changed operation of parallel eprom interface; added information on ultra2 scsi termination; added lvd electrical specifications and ultra2 scsi timings; added pci configuration registers for subsystem id and subsystem vendor id; pinout/pin numbering correc- tions. 2-16 - 2-17, 4-3 - 4- 6, 4-11, 4-22, 7-1, 7- 2, 7-4 - 7-5, d1-d4 9/98 ver. 3.0. merged addendum; merged sen892 (diffsens) in chapter 2; chapter 3 - added 292- bga figure/tables and updated mad3-1 signals;chapter 7 - substituted source and sink values, and changed other values. merged sen893 and sen898 into appendix d.
sym53c895 d ata m anual iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents chapter 1: introduction 1-1 what is covered in this manual................................................................................................. 1-1 general description ............................................................................................................ ......... 1-1 new features in the sym53c895 ................................................................................................................. ......1-2 benefits of lvdlink ............................................................................................................ .......... 1-2 benefits of ultra2 scsi........................................................................................................ ......... 1-3 tolerant technology ............................................................................................................ ..... 1-3 sym53c895 benefits summary................................................................................................... 1 -4 scsi performance .............................................................................................................. .....1-4 pci performance ............................................................................................................... ......1-4 integration ................................................................................................................... ............1-4 ease of use ................................................................................................................... ............1-4 flexibility ................................................................................................................... ..............1-5 reliability ................................................................................................................... ..............1-5 testability ................................................................................................................... .............1-5 chapter 2: functional description 2-1 scsi core...................................................................................................................... ................ 2-1 dma core ....................................................................................................................... ............. 2-1 scripts processor .............................................................................................................. ........ 2-1 internal scripts ram ................................................................................................................... .....2-2 designing an ultra2 scsi system................................................................................................ 2-2 using the scsi clock quadrupler .............................................................................................................. .....2-3 prefetching scripts instructions .............................................................................................. 2-3 op code fetch burst capability .............................................................................................................. .........2-4
iv sym53c895 d ata m anual parallel rom interface ......................................................................................................... ....... 2-4 serial eeprom interface ........................................................................................................ .... 2-5 mode a: 4.7 k w pull-ups on mad6 and mad7 ................................................................................. 2-5 mode b: 4.7 k w pull-down on mad6, 4.7 k w pull-up on mad7 ...................................................................................................... 2-5 mode c: 4.7 k w pull-downs on mad6 and mad7 ............................................................................ 2-6 mode d: 4.7 k w pull-up on mad6, 4.7 k w pull-down on mad7 ................................................................................................. 2-6 pci cache mode ................................................................................................................. ......... 2-6 big and little endian support .................................................................................................. ... 2-7 loopback mode .................................................................................................................. ......... 2-8 parity options ................................................................................................................. ............. 2-8 dma fifo....................................................................................................................... ........... 2-10 data paths .................................................................................................................... ......... 2-10 scsi bus interface............................................................................................................. ......... 2-12 lvdlink technology ............................................................................................................ 2-12 high voltage differential mode(hvd) .................................................................................................... 2-1 3 scsi termination .............................................................................................................. ... 2-16 system engineering note ..................................................................................................... 2- 16 (re)select during (re)selection ................................................................................................................. ........ 2-18 synchronous operation.......................................................................................................... ... 2-19 determining the data transfer rate ............................................................................................................ .... 2-19 ultra2 scsi synchronous data transfers ................................................................................................ 2-20 interrupt handling ............................................................................................................. ....... 2-22 polling and hardware interrupts ........................................................................................................... .. 2-22 registers ..................................................................................................................... ........... 2-22 fatal vs. non-fatal interrupts .................................................................................................................... .......... 2-23 masking ....................................................................................................................... .......... 2-23
sym53c895 d ata m anual v stacked interrupts ............................................................................................................ .....2-24 halting in an orderly fashion ............................................................................................................... .....2-24 sample interrupt service routine ............................................................................................................... .......2-25 chained block moves............................................................................................................ ..... 2-25 wide scsi send bit (wss) ..................................................................................................................... ..........2-25 wide scsi receive bit (wsr) ..................................................................................................................... .........2-26 swide register ................................................................................................................ .....2-26 sodl register ................................................................................................................. ......2-26 chained block move scripts instruction ........................................................................................................... .2-26 chapter 3: pci functional description 3-1 pci addressing ................................................................................................................. ............ 3-1 pci bus commands and functions supported.......................................................................... 3-1 pci cache mode................................................................................................................. .......... 3-2 support for pci cache line size register ...................................................................................................... ...3-2 selection of cache line size ..................................................................................................................... ..............3-2 alignment ..................................................................................................................... ...........3-3 memory move misalignment .................................................................................................................. ........3-3 memory write and invalidate command .......................................................................................................3 -3 memory read multiple command .............................................................................................................. ..3-5 configuration registers ........................................................................................................ ....... 3-6 register 00h vendor id read only ..................................................................................................................... ...........3-8 register 02h device id read only ..................................................................................................................... ...........3-8 register 04h
vi sym53c895 d ata m anual command read/write .................................................................................................................... .......... 3-8 register 06h status read/write .................................................................................................................... .......... 3-9 register 08h revision id read only ..................................................................................................................... ......... 3-10 register 09h class code read only ..................................................................................................................... ......... 3-10 register 0ch cache line size read/write .................................................................................................................... ........ 3-11 register 0dh latency timer read/write .................................................................................................................... ........ 3-11 register 0eh header type read only ..................................................................................................................... ......... 3-11 register 10h base address zero (i/o) read/write .................................................................................................................... ........ 3-11 register 14h base address one (memory) read/write .................................................................................................................... ........ 3-11 register 18h ram base address read/write .................................................................................................................... ........ 3-11 register 2c-2d subsystem vendor id read only ..................................................................................................................... ......... 3-11 register 2e-2f subsystem id read only ..................................................................................................................... ......... 3-12 register 30h expansion rom base address read/write .................................................................................................................... ........ 3-12 register 3ch interrupt line read/write .................................................................................................................... ........ 3-12 register 3dh
sym53c895 d ata m anual vii interrupt pin read only ..................................................................................................................... .........3-12 register 3eh min_gnt read only ..................................................................................................................... .........3-13 register 3fh max_lat read only ..................................................................................................................... .........3-13 chapter 4: signal descriptions 4-1 voltage capabilities and limitations .......................................................................................... 4-1 internal pull-ups on sym53c895 pins ....................................................................................... 4-8 pin descriptions ............................................................................................................... ....... 4-9 chapter 5: operating registers 5-1 register 00 (80) ............................................................................................................... .............. scsi control zero (scntl0) read/write .................................................................................................................... ..........5-5 register 01 (81) scsi control one (scntl1) read/write .................................................................................................................... ..........5-7 register 02 (82) scsi control two (scntl2) read/write .................................................................................................................... ..........5-9 register 03 (83) scsi control three (scntl3) read/write .................................................................................................................... ........5-10 register 04 (84) scsi chip id (scid) read/write .................................................................................................................... ........5-12 register 05 (85) scsi transfer (sxfer) read/write .................................................................................................................... ........5-12 register 06 (86) scsi destination id (sdid) read/write .................................................................................................................... ........5-15 register 07 (87) general purpose (gpreg) read/write .................................................................................................................... ........5-15 register 08 (88) scsi first byte received (sfbr)
viii sym53c895 d ata m anual read/write .................................................................................................................... ........ 5-16 register 09 (89) scsi output control latch (socl) read /write ................................................................................................................... ........ 5-16 register 0a (8a) scsi selector id (ssid) read only ..................................................................................................................... ......... 5-17 register 0b (8b) scsi bus control lines (sbcl) read only ..................................................................................................................... ......... 5-17 register 0c (8c) dma status (dstat) read only ..................................................................................................................... ......... 5-18 register 0d (8d) scsi status zero (sstat0) read only ..................................................................................................................... ......... 5-19 register 0e (8e) scsi status one (sstat1) read only ..................................................................................................................... ......... 5-20 register 0f (8f) scsi status two (sstat2) (read only) ................................................................................................................... ........ 5-21 registers 10-13 (90-93) data structure address (dsa) read/write .................................................................................................................... ........ 5-22 register 14 (94) interrupt status (istat) (read/write) .................................................................................................................. ....... 5-23 register 18 (98) chip test zero (ctest0) read/write .................................................................................................................... ........ 5-25 register 19 (99) chip test one (ctest1) read only ..................................................................................................................... ......... 5-25 register 1a (9a) chip test two (ctest2) read/write .................................................................................................................... ........ 5-26 register 1b (9b) chip test three (ctest3) read/write .................................................................................................................... ........ 5-27 registers 1c-1f (9c-9f) temporary (temp)
sym53c895 d ata m anual ix read/write .................................................................................................................... ........5-28 register 20 (a0) dma fifo (dfifo) read only ..................................................................................................................... .........5-28 register 21 (a1) chip test four (ctest4) read/write .................................................................................................................... ........5-29 register 22 (a2) chip test five (ctest5) read/write .................................................................................................................... ........5-30 register 23 (a3) chip test six (ctest6) read/write .................................................................................................................... ........5-31 registers 24-26 (a4-a6) dma byte counter (dbc) read/write .................................................................................................................... ........5-32 register 27 (a7) dma command (dcmd) read/write .................................................................................................................... ........5-32 registers 28-2b (a8-ab) dma next address (dnad) read/write .................................................................................................................... ........5-33 registers 2c-2f (ac-af) dma scripts pointer (dsp) read/write .................................................................................................................... ........5-33 registers 30-33 (b0-b3) dma scripts pointer save (dsps) read/write .................................................................................................................... ........5-34 registers 34-37 (b4-b7) scratch register a (scratch a) read/write .................................................................................................................... ........5-34 register 38 (b8) dma mode (dmode) read/write .................................................................................................................... ........5-35 register 39 (b9) dma interrupt enable (dien) read/write .................................................................................................................... ........5-36 register 3a (ba) scratch byte register (sbr) read/write .................................................................................................................... ........5-37 register 3b (bb) dma control (dcntl)
x sym53c895 d ata m anual read/write .................................................................................................................... ........ 5-37 register 3c-3f (bc-bf) adder sum output (adder) read only ..................................................................................................................... ......... 5-38 register 40 (c0) scsi interrupt enable zero (sien0) read/write .................................................................................................................... ........ 5-39 register 41 (c1) scsi interrupt enable one (sien1) read/write .................................................................................................................... ........ 5-40 register 42 (c2) scsi interrupt status zero (sist0) read only ..................................................................................................................... ......... 5-41 register 43 (c3) scsi interrupt status one (sist1) read only ..................................................................................................................... ......... 5-42 register 44 (c4) scsi longitudinal parity (slpar) read/write .................................................................................................................... ........ 5-43 register 45 (c5) scsi wide residue (swide) read only ..................................................................................................................... ......... 5-44 register 46 (c6) memory access control (macntl) read/write .................................................................................................................... ........ 5-45 register 47 (c7) general purpose pin control (gpcntl) read/write .................................................................................................................... ........ 5-45 register 48 (c8) scsi timer zero (stime0) read /write ................................................................................................................... ........ 5-46 register 49 (c9) scsi timer one (stime1) read/write .................................................................................................................... ........ 5-47 register 4a (ca) response id zero (respid0) read/write .................................................................................................................... ........ 5-48 register 4b (cb) response id one(respid1) read/write .................................................................................................................... ........ 5-48 register 4c (cc) scsi test zero (stest0)
sym53c895 d ata m anual xi read only ..................................................................................................................... .........5-49 register 4d (cd) scsi test one (stest1) read/write .................................................................................................................... ........5-50 register 4e (ce) scsi test two (stest2) read/write .................................................................................................................... ........5-51 register 4f (cf) scsi test three (stest3) read/write .................................................................................................................... ........5-52 register 50-51 (d0-d1) scsi input data latch (sidl) read only ..................................................................................................................... .........5-54 register 52 (d2) scsi test 4 (stest4) read only ..................................................................................................................... .........5-54 registers 54-55 (d4-d5) scsi output data latch (sodl) read/write .................................................................................................................... ........5-55 registers 58-59 (d8-d9) scsi bus data lines (sbdl) read only ..................................................................................................................... .........5-55 registers 5c-5f (dc-df) scratch register b (scratchb) (read/write) .................................................................................................................. .......5-56 registers 60h-7fh (e0h-ffh) scratch registers c-j (scratchc-scratchj) read/write .................................................................................................................... ........5-56 chapter 6: instruction set of the i/o processor 6-1 scsi scripts ................................................................................................................... ........... 6-1 sample operation .............................................................................................................. .....6-2 block move instructions ........................................................................................................ ...... 6-4 first dword ................................................................................................................... ..........6-4 second dword .................................................................................................................. .......6-8 i/o instructions ............................................................................................................... ............. 6-8 first dword ................................................................................................................... ..........6-8 second dword .................................................................................................................. .....6-13 read/write instructions........................................................................................................ ..... 6-13
xii sym53c895 d ata m anual first dword ................................................................................................................... ........ 6-13 second dword .................................................................................................................. ..... 6-15 read-modify-write cycles ........................................................................................................................ ............. 6-15 move to/from sfbr cycles ................................................................................................................... ........ 6-15 transfer control instructions .................................................................................................. . 6-17 first dword ................................................................................................................... ........ 6-17 second dword .................................................................................................................. ..... 6-21 memory move instructions....................................................................................................... 6-21 read/write system memory from a script .......................................................................................................... 6-21 second dword .................................................................................................................. ..... 6-22 third dword ................................................................................................................... ...... 6-22 load and store instructions .................................................................................................... .. 6-23 first dword ................................................................................................................... ........ 6-23 second dword .................................................................................................................. ..... 6-24 chapter 7: electrical characteristics 7-1 dc characteristics ............................................................................................................. .......... 7-1 tolerant technology electrical characteristics ................................................................... 7-6 ac characteristics............................................................................................................. ........... 7-9 pci and external memory interface timing diagrams........................................................... 7-11 timing diagrams included in this section ........................................................................... 7-11 scsi timings................................................................................................................... ........... 7-46 appendix a: register summary a-1 appendix b: mechanical drawing b-1 appendix c: external memory interface diagram examples c-1 appendix d: circuit board layout issues d-1 signal separation.............................................................................................................. ........... d-1 routing signal lines ........................................................................................................... ........ d-1 impedance matching ............................................................................................................. ..... d-1 termination and stub length .................................................................................................... d-1
sym53c895 d ata m anual xiii decoupling..................................................................................................................... .............. d-2 dielectric ..................................................................................................................... ................. d-2 considerations specific to the sym53c895 .............................................................................. d-2 rbias +/- pins ................................................................................................................ .......d-2 physical dimensions ........................................................................................................... ...d-2 power requirements ............................................................................................................ ..d-2 v dd-a pin .......................................................................................................................... .....d-2 terminators ................................................................................................................... .........d-3 capacitive load ............................................................................................................... .......d-3 spi-2 document ................................................................................................................ .....d-3
xiv sym53c895 d ata m anual
sym53c895 d ata m anual xv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of tables table 2-1: external memory support .............................................................................................. 2-4 table 2-2: mode a serial eeprom data format ...........................................................................2-5 table 2-3: mode c serial eeprom data format ...........................................................................2-6 table 2-4: bits used for parity control and generation ................................................................2-8 table 2-5: scsi parity control ................................................................................................. ........2-9 table 2-6: scsi parity errors and interrupts .................................................................................2- 9 table 2-7: transmission mode ................................................................................................... ...2-16 table 3-1: pci bus commands supported ..................................................................................... 3-2 table 3-2: pci configuration register map ....................................................................................3- 7 table 4-1: bga listing location................................................................................................. ..... 4-5 table 4-2: bga listing by name ................................................................................................. .....4-6 table 4-3: sym53c895 internal pull-ups ........................................................................................4 -8 table 4-4: sym53c895 power and ground pins ..........................................................................4-9 table 4-5: system pins ......................................................................................................... ...........4-11 table 4-6: address and data pins ............................................................................................... ..4-11 table 4-7: interface control pins .............................................................................................. ....4-12 table 4-8: arbitration pins .................................................................................................... .........4-13 table 4-9: error reporting pins ................................................................................................ .....4-13 table 4-10: scsi pins, lvdlink mode .........................................................................................4-1 4 table 4-11: scsi pins, single-ended mode ..................................................................................4-16 table 4-12: scsi pins, high voltage differential mode ..............................................................4-17 table 4-13: additional pins .................................................................................................... .......4-19 table 4-14: external memory interface pins ................................................................................4-21 table 5-2: synchronous clock conversion factor .......................................................................5-11 table 5-3: asynchronous clock conversion factor .....................................................................5-11 table 5-4: examples of synchronous transfer periods and rates for scsi-1 ............................5-13
xvi sym53c895 d ata m anual table 5-5: example synchronous transfer periods and rates for fast scsi, ultra scsi, and ultra2 scsi 5-13 table 5-6: scsi synchronous offset values ................................................................................ 5-14 table 5-7: fifo flags bit values ............................................................................................... .... 5-20 table 5-8: burst length bit decoding ........................................................................................... 5-35 table 5-9: handshake-to handshake timer period .................................................................... 5-46 table 5-10: time-out periods, 50 mhz clock ............................................................................. 5-47 table 5-11: time-out periods, 40/160 mhz clock ..................................................................... 5-47 table 5-12: diffsens voltage levels and scsi operating modes ............................................ 5-54 table 6-1: read/write instructions .............................................................................................. . 6-16 table 7-1: absolute maximum stress ratings ................................................................................ 7-1 table 7-2: operating conditions ................................................................................................ ..... 7-1 table 7-3: scsi signals, low voltage differential driverssd (15-0)+/, sdp (1-0)+/-, sreq+/-, sack+/-, smsg+/-, sio+/-, scd+/-, satn+/-, sbsy+/-, ssel+/-, srst+/-* ....................... 7-2 table 7-4: scsi signals, low voltage differential receiverssd (15-0)+/-, sdp (1-0)+/-, sreq+/-, sack+/-, smsg+/-, sio+/-, scd+/-, satn+/-, sbsy+/-, ssel+/-, srst+/-* ...................................................................................................................... .7-2 table 7-5: scsi signal diffsens ............................................................................................... 7-3 table 7-6: scsi signalsrbias+/- ............................................................................................... .7-3 table 7-7: capacitance ......................................................................................................... ............ 7-3 table 7-8: output signal mac/_testout .............................................................................. 7-3 table 7-9: input signalsclk*, rst/*, idsel, gnt/, sclk/ .................................................... 7-4 table 7-10: bidirectional signals ad(31-0), c_be/(3-0), frame/, irdy/, trdy/, devsel/, stop/, perr/, par, req/ irq/, serr/ .................................... 7-4 table 7-11: bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4, mad(7-0) .......................................................................................... 7-4 table 7-12: bidirectional signalsmas/(1-0), mce/, moe/, mwe/ ........................................ 7-5 table 7-13: input signal big_lit/ ............................................................................................. .7-5 table 7-14: tolerant technology electrical characteristics ....................................................... 7-6 table 7-15: configuration register read timings ...................................................................... 7-12 table 7-16: configuration register write timings ..................................................................... 7-13 table 7-17: operating register/scripts ram read timings .................................................. 7-14 table 7-18: operating register/scripts ram write timings ................................................. 7-15 table 7-19: external memory read timings ................................................................................ 7-16
sym53c895 d ata m anual xvii table 7-20: external memory write timings ...............................................................................7-18 table 7-21: op code fetch, non burst timings ...........................................................................7-20 table 7-22: burst op code fetch timings ....................................................................................7-22 table 7-23: back to back read timings .......................................................................................7-2 4 table 7-24: back to back write timings ......................................................................................7-2 6 table 7-25: burst read timings ................................................................................................. ...7-28 table 7-26: burst write timings ................................................................................................ ...7-30 table 7-27: read cycle timings, normal/fast memory ( 3 128 kb), single byte access .............7-32 table 7-28: write cycle timings, normal/fast memory ( 3 128 kb), single byte access ............7-34 table 7-29: read cycle timings, slow memory ( 3 128 kb) .........................................................7-38 table 7-30: write cycle timings, slow memory ( 3 128 kb) ........................................................7-40 table 7-31: read cycle timings, 64 kb rom ...........................................................................7-42 table 7-32: write cycle timings, 64 kb rom ..........................................................................7-44 table 7-33: scsi-1 transfers (single-ended, 5.0 mb/s) ..............................................................7-48 table 7-34: scsi-1 transfers (differential, 4.17 mb/s) ...............................................................7-49 table 7-35: scsi-2 fast transfers 10.0 mb/s (8-bit transfers) or 20.0 mb/s (16-bit transfers), 40 mhz clock .............................................................................................................7-49 table 7-36: scsi-2 fast transfers 10.0 mb/s (8-bit transfers) or 20.0 mb/s (16-bit transfers), 50 mhz clock ..............................................................................................................7-50 table 7-37: ultra scsi single-ended transfers 20.0 mb/s (8-bit transfers) or 40.0 mb/s (16-bit transfers), quadrupled 40 mhz clock ..........................................................................................7-50 table 7-38: ultra scsi high voltage differential transfers 20.0 mb/s (8-bit transfers) or 40.0 mb/s (16-bit transfers), 80 mhz clock .............7-51 table 7-39: ultra2 scsi transfers 40.0 mb/s (8-bit transfers) or 80.0 mb/s (16-bit transfers), quadrupled 40 mhz clock ...........................................................7-51
xviii sym53c895 d ata m anual
sym53c895 d ata m anual xix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . list of figures figure 2-1: dma fifo sections ........................................................................................ 2-10 figure 2-2: sym53c895 host interface data paths .........................................................2-12 figure 2-4: regulated termination for ultra2 scsi ........................................................2-18 figure 2-6: block move and chained block move instructions......................................2-27 figure 3-1: command register layout............................................................................... 3-9 figure 3-2: status register layout .....................................................................................3-10 figure 4-4: sym53c895 functional signal grouping........................................................4-7 figure 6-1: scripts overview ........................................................................................... 6-3 figure 6-2: block move instruction register......................................................................6-5 figure 6-3: i/o instruction register ..................................................................................6-10 figure 6-4: read/write instruction register.....................................................................6-14 figure 6-5: transfer control instruction..........................................................................6-18 figure 6-6: memory move instructions............................................................................6-22 figure 6-7: load and store instruction format................................................................6-24 figure 7-1: lvd transmitter ...............................................................................................7-2 figure 7-2: lvd receiver.....................................................................................................7-2 figure 7-3: rise and fall time test conditions .................................................................7-7 figure 7-4: scsi input filtering ..........................................................................................7-7 figure 7-5: hysteresis of scsi receiver ..............................................................................7-8 figure 7-6: input current as a function of input voltage.................................................7-8 figure 7-7: output current as a function of output voltage...........................................7-8 figure 7-8: external clock timing ......................................................................................7-9 figure 7-9: reset input.......................................................................................................7- 10 figure 7-10: interrupt output ...........................................................................................7-10 figure 7-11: pci configuration register read .................................................................7-12 figure 7-12: pci configuration register write................................................................7-13 figure 7-13: operating register/scripts ram read ....................................................7-14
xx sym53c895 d ata m anual figure 7-14: operating register/scripts ram write................................................... 7-15 figure 7-15: external memory read ................................................................................. 7-17 figure 7-16: external memory write................................................................................ 7-19 figure 7-17: op code fetch, non-burst ........................................................................... 7-21 figure 7-18: burst op code fetch .................................................................................... 7-23 figure 7-19: back-to-back read........................................................................................ 7-25 figure 7-20: back-to-back write ...................................................................................... 7-27 figure 7-21: burst read ..................................................................................................... 7-29 figure 7-22: burst write .................................................................................................... 7-31 figure 7-23: read cycle, normal/fast memory ( 3 128 kb), single byte access............. 7-33 figure 7-24: write cycle, normal/fast memory ( 3 128 kb), single byte access ........... 7-35 figure 7-25: read cycle, normal/fast memory ( 3 128 kb), multiple byte access (continued) ...................................................................................... 7-37 figure 7-26: read cycle, slow memory ( 3 128 kb) ........................................................ 7-39 figure 7-27: write cycle, slow memory ( 3 128 kb) ....................................................... 7-41 figure 7-28: read cycle, 64 kb rom ........................................................................... 7-43 figure 7-29: write cycle, 64 kb rom .......................................................................... 7-45 figure 7-30: initiator asynchronous send ....................................................................... 7-46 figure 7-31: initiator asynchronous receive ................................................................... 7-46 figure 7-32: target asynchronous send........................................................................... 7-47 figure 7-33: target asynchronous receive ...................................................................... 7-47 figure 7-34: initiator and target synchronous transfers ............................................... 7-48 figure b-1: sym53c895 mechanical drawing, 208-pin qfp .......................................... b-1 figure b-2: sym53c895 mechanical drawing, 292-ball bga ..........................................b-2 figure c-1: 16 k interface with 200 ns memory .............................................................. c-1 figure c-2: 64 k interface with 150 ns memory ............................................................... c-2 figure c-3: 256 k interface with 150 ns memory............................................................ c-3 figure c-4: 512 k interface with 150 ns memory............................................................ c-4
introduction what is covered in this manual sym53c895 data manual version 3.0 1-1 chapter 1 introduction what is covered in this manual this manual provides reference information on the sym53c895 pci-scsi i/o processor. it is intended for system designers and programmers who are using this device to design a scsi port for pci-based personal computers, workstations, or embedded applications. n this chapter includes general information about the sym53c895 and other members of the sym53c8xx family of pci-scsi i/o processors. n chapter 2 describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus and external memory. n chapter 3 describes the chips connection to the pci bus, including the pci commands and configuration registers supported. n chapter 4 contains the pin diagrams and definitions of each signal. n chapter 5 describes each bit in the operating registers, organized by address. n chapter 6 defines all of the scsi scripts instructions that are supported by the sym53c895. n chapter 7 contains the electrical characteristics and ac timings for the chip. n the appendixes contain a register summary, a mechanical drawing of the sym53c895, and several example interface drawings to connect the sym53c895 to an external rom. this data manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided in the preface of this document. general description the sym53c895 pci-scsi i/o processor brings ultra2 scsi performance to host adapter, work- station, and general computer designs, making it easy to add a high-performance scsi bus to any pci system. it supports ultra2 scsi transfer rates and allows you to increase scsi connectivity and cable length with low voltage differential (lvd) signaling for scsi. the sym53c895 has a local memory bus for local storage of the devices bios rom in flash mem- ory or standard eproms. the sym53c895 sup- ports big and little endian byte addressing to accommodate a variety of data configurations. the sym53c895 supports programming of local flash memory for updates to bios or scripts programs. the chip is packaged in a 208-pin quad flat pack or a 292-ball bga. system diagrams showing the connections of the sym53c895 with an external rom or flash mem- ory are pictured in appendix c. a block diagram of the sym53c895 is pictured in figure 1-1 on page 1-6. symbios lvdlink? technology is the symbios implementation of lvd. lvdlink transceivers allow the sym53c895 to perform single-ended and low voltage differential transfers, and support external high voltage differential transceivers. the sym53c895 integrates a high-performance scsi core, a pci bus master dma core, and the sym-
1-2 sym53c895 data manual version 3.0 introduction benefits of lvdlink bios scsi scripts? processor to meet the flexi- bility requirements of scsi-3 and ultra2 scsi standards. it is designed to implement multi- threaded i/o algorithms with a minimum of pro- cessor intervention, solving the protocol overhead problems of previous intelligent and non-intelli- gent adapter designs. new features in the sym53c895 the sym53c895 is functionally similar to the sym53c875 pci-scsi i/o processor, with added support for ultra2 scsi. some software enhance- ments, and use of low voltage differential, are needed to enable the chip to transfer data at ultra2 scsi transfer rates. most of the feature enhance- ments in the sym53c895 are included to enable the chip to take advantage of ultra2 scsi transfer rates. n optional 816-byte dma fifo supports large block transfers at ultra2 scsi speeds. the default fifo size is 112 bytes. n thirty-one levels of scsi synchronous offset increases the pace of synchronous transfers to match ultra2 scsi transfer speeds. n on-chip lvdlink transceivers allow increased connectivity, longer cable length, and improved performance. they also automatically sense the type of device connected to the scsi bus and switch as needed to single-ended, lvd, or high voltage differential mode (if the chip is connected to external transceivers). n on-chip scsi clock quadrupler can achieve 160 mhz frequency with an external 40mhz oscillator. n supports subsystem id and subsystem vendor id registers in pci configuration space. n support for serial eeprom interface. benefits of lvdlink the sym53c895 supports low voltage differen- tial (lvd) for scsi, a signaling technology that increases the reliability of scsi data transfers over longer distances than supported by single-ended scsi. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. lvd provides the reliability of high voltage differential scsi without the added cost of exter- nal differential transceivers. ultra2 scsi with lvd allows a longer scsi cable and more devices on the bus, with the same cables defined in the scsi- 3 parallel interface standard for ultra scsi. lvd provides a long-term migration path to even faster scsi transfer rates without compromising signal integrity, cable length, or connectivity. for backward compatibility to existing single- ended devices, the sym53c895 features universal lvdlink transceivers that can switch between lvd scsi and single-ended modes. the lvdlink tech- nology also supports high-power differential signal- ing in legacy systems, when external transceivers are connected to the sym53c895. this allows the sym53c895 to be used in both legacy and ultra2 scsi applications.
introduction benefits of ultra2 scsi sym53c895 data manual version 3.0 1-3 benefits of ultra2 scsi ultra2 scsi is an extension of the spi-2 draft standard that allows faster synchronous scsi transfer rates and defines a new physical layer, lvd scsi, that provides an incremental evolution from scsi-2 and ultra scsi. when enabled, ultra2 scsi performs 40 megatransfers per sec- ond, which results in approximately double the synchronous transfer rates of ultra scsi. the sym53c895 can perform 16-bit, ultra2 scsi synchronous transfers as fast as 80 mb/s. this advantage is most noticeable in heavily loaded sys- tems, or large-block size applications such as video on-demand and image processing. one advantage of ultra2 scsi is that it signifi- cantly improves scsi bandwidth while preserving existing hardware and software investments. the primary software changes required are to enable the chip to perform synchronous negotiations for ultra2 scsi rates, and to enable the clock quadru- pler. ultra2 scsi uses the same connectors as ultra scsi, but can operate with longer cables and more devices on the bus. chapter 2 contains more information on migrating from an ultra scsi design to support ultra2 scsi. to l e r a n t te c h n o l o g y the sym53c895 features tolerant? technol- ogy, which includes active negation on the scsi drivers and input signal filtering on the scsi receivers. active negation causes the scsi request, acknowledge, data, and parity signals to be actively driven high rather than passively pulled up by terminators. active negation is enabled by setting bit 7 in the stest3 register. tolerant receiver technology improves data integrity in unreliable cabling environments, where other devices would be subject to data corruption. tolerant receivers filter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input filters. this improved driver and receiver technology helps eliminate double clocking of data, the single big- gest reliability issue with scsi operations. tolerant input signal filtering is a built in feature of the sym53c895 and all symbios fast scsi, ultra scsi, and ultra2 scsi devices. on the sym53c895, the user can select a filtering period of 30 or 60 ns, with bit 1 in the stest2 register. the benefits of tolerant include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power up or power down, so other devices on the bus are also protected from data corruption. when it is used with the lvdlink transceivers, tolerant provides excellent signal quality and data reliability in real world cabling environments. tolerant is compatible with both the alternative one and alternative two termina- tion schemes proposed by the american national standards institute.
1-4 sym53c895 data manual version 3.0 introduction sym53c895 benefits summary sym53c895 benefits summary scsi performance n integrated lvdlink universal transceivers n support single ended, lvd, and high voltage differential signals (with external transceivers) n allow greater device connectivity and longer cable length n lvdlink transceivers save cost of external differential transceivers n support a long-term performance migration path n with 816-byte fifo, chip can burst up to 512 bytes across the pci bus n performs wide, ultra2 scsi synchronous transfers as fast as 80 mb/s n on-chip scsi clock quadrupler allows the chip to achieve ultra2 scsi transfer rates with 40 mhz clock n includes 4 kb internal ram for scripts instruction storage n thirty-one levels of scsi synchronous offset n supports variable block size and scatter/gather data transfers. n performs sustained memory-to-memory dma transfers faster than 47 mb/s (@ 33 mhz) n minimizes scsi i/o start latency n performs complex bus sequences without interrupts, including restore data pointers n reduces isr overhead through a unique interrupt status reporting method n load and store scripts instruction increases performance of data transfers to and from chip registers n supports target disconnect and later reconnect with no interrupt to the system processor n supports multi-threaded i/o algorithms in scsi scripts with fast i/o context switching n expanded register move instruction supports additional arithmetic capability pci performance n complies with pci 2.1 specification n 32-bit 33 mhz pci interface n bursts 2, 4, 8, 16, 32, 64, or 128 dwords across pci bus n supports 32-bit word data bursts with variable burst lengths n pre-fetches up to 8 dwords of scripts instructions n bursts scripts op code fetches across the pci bus n performs zero wait-state bus master data bursts faster than 110 mb/s (@ 33 mhz) n supports pci cache line size register n supports pci write and invalidate, read line, and read multiple commands integration n integrated lvd transceivers n full 32-bit pci dma bus master n can be used as a third-party pci bus dma controller by using memory to memory move instructions n high performance scsi core n integrated scripts processor ease of use n up to one megabyte of add-in memory support for bios and scripts storage n direct pci-to-scsi connection
introduction sym53c895 benefits summary sym53c895 data manual version 3.0 1-5 n reduced scsi development effort n compiler-compatible with existing sym53c7xx and sym53c8xx family scripts n direct connection to pci, and scsi single- ended and differential buses n development tools and sample scsi scripts available n maskable and pollable interrupts n wide scsi, a or p cable, and up to 16 devices supported n three programmable scsi timers: select/ reselect, handshake-to-handshake, and general purpose. the time-out period is programmable from 100 m s to greater than 25.6 seconds n software for pc-based operating system support n support for relative jumps n scsi selected as id bits for responding with multiple ids flexibility n universal lvd transceivers are backward compatible with single-ended or high-power differential devices n high level programming interface (scsi scripts) n programs local memory bus flash memory n big/little endian support n selectable 112- or 816-byte dma fifo for backward compatibility n tailored scsi sequences execute from main system ram or internal scripts ram n flexible programming interface to tune i/o performance or to adapt to unique scsi devices n support for changes in the logical i/o interface definition n low level access to all registers and all scsi bus signals n fetch, master, and memory access control pins n separate scsi and system clocks n scsi clock quadrupler bits enable ultra2 scsi transfer rates with a 40 mhz scsi clock n selectable irq pin disable bit n ability to route system clock to scsi clock reliability n 2 kv esd protection on scsi signals n protection against bus reflections due to impedance mismatches n controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certification) n latch-up protection greater than 150 ma n voltage feed through protection (minimum leakage current through scsi pads) n more than 25% of pins are power and ground n power and ground isolation of i/o pads and internal chip logic n tolerant technology provides: n active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates n input signal filtering on scsi receivers improves data integrity, even in noisy cabling environments testability n all scsi signals accessible through programmed i/o n scsi loopback diagnostics n scsi bus signal continuity checking n support for single-step mode operation n test mode (and tree) to check pin continuity to the board
1-6 sym53c895 data manual version 3.0 introduction sym53c895 benefits summary figure 1-1: sym53c895 chip block diagram pci master and slave control block data fifo 112 or 816 bytes pci scsi fifo and scsi control block tolerant drivers and receivers scsi scripts processor operating registers config registers scsi bus memory control local memory bus external memory scripts ram lvdlink transceivers scsi clock quadrupler
functional description scsi core sym53c895 data manual 2-1 chapter 2 functional description the sym53c895 contains three functional blocks: the scsi core, the dma core, and the scripts processor. symbios supplies software that supports the sym53c895 and the entire symbios product line of scsi processors and con- trollers. scsi core the scsi core supports an 8- or 16-bit data bus. it supports ultra2 scsi synchronous transfer rates up to 80 mb/s on a 16-bit, low voltage differen- tial (lvd) scsi bus. the scsi core can be pro- grammed with scsi scripts, making it easy to fine tune the system for specific mass storage devices or scsi-3 requirements. the scsi core offers low-level register access or a high-level control interface. like first generation scsi devices, the sym53c895 scsi core can be accessed as a register-oriented device. the ability to sample and/or assert any signal on the scsi bus can be used in error recovery and diagnostic proce- dures. in support of loopback diagnostics, the scsi core may perform a self-selection and oper- ate as both an initiator and a target. the integrated scripts processor controls the sym53c895 scsi core through a high-level logi- cal interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high-speed processor optimized for scsi protocol. dma core the dma core is a bus master dma device that attaches directly to the industry standard pci bus. the dma core is tightly coupled to the scsi core through the scripts processor, which supports uninterrupted scatter/gather memory operations. the sym53c895 supports 32-bit memory and automatically supports misaligned dma transfers. a 112- or 816-byte fifo allows the sym53c895 to support 2, 4, 8, 16, 32, 64, or 128 dword bursts across the pci bus interface. scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores and are executed from 32-bit system ram or internal scripts ram. the scripts processor executes complex scsi bus sequences independently of the host cpu. the scripts processor can begin a scsi i/o operation in approximately 500 ns. algorithms may be designed to tune scsi bus performance to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2 or scsi-3 logical bus defi- nitions without sacrificing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu sys- tem bus.
2-2 sym53c895 data manual functional description designing an ultra2 scsi system internal scripts ram the sym53c895 has 4 kb (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the sym53c895 use the pci bus as if they were exter- nal accesses. the mad5 pin enables the 4k inter- nal ram, when it is connected to v dd through a 4.7 k w resistor. to disable the internal ram, con- nect a 4.7 k w resistor between the mad5 pin and v ss . the ram can be relocated by the pci system bios anywhere in 32-bit address space. the ram base address register in pci configuration space contains the base address of the internal ram. this register is similar to the rom base address register in pci configuration space. to simplify loading of scripts instructions, the base address of the ram will appear in the scratchb regis- ter when bit 3 of the ctest2 register is set. the ram is byte-accessible from the pci bus and will be visible to any bus-mastering device on the bus. external accesses to the ram (that is, by the cpu) follow the same timing sequence as a stan- dard slave register access, except that the target wait states required will drop from 5 to 3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instruc- tions supported by the sym53c895, see chapter 6, instruction set of the i/o processor. designing an ultra2 scsi system since ultra2 scsi is based on existing scsi stan- dards, it can use existing driver programs as long as the software is able to negotiate for ultra2 scsi synchronous transfer rates. additional software modifications may be needed to take advantage of the new features in the sym53c895. in the area of hardware, lvd scsi is required to achieve ultra2 scsi transfer rates and to support the longer cable and additional devices on the bus. all devices on the bus must have lvd scsi to guarantee ultra2 scsi transfer rates. for addi- tional information on ultra2 scsi, refer to the spi-2 working document which is available from the scsi bbs referenced at the beginning of this manual. chapter 7 contains ultra2 scsi timing information. in addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate ultra2 scsi transfers: 1. set the ultra enable bit to enable ultra2 scsi transfers. 2. set the tolerant enable bit, bit 7 in the stest3 register, whenever the ultra enable bit is set. 3. do not extend the sreq/sack filtering period with stest2 bit 1. when the ultra enable bit is set, the filtering period will be fixed at 8 ns for ultra2 scsi or 15 ns for ultra scsi, regardless of the value of the sreq/ sack filtering bit. 4. use the scsi clock quadrupler.
functional description prefetching scripts instructions sym53c895 data manual 2-3 using the scsi clock quadrupler the sym53c895 can quadruple the frequency of a 40 mhz scsi clock, allowing the system to per- form ultra2 scsi transfers. this option is user- selectable with bit settings in the stest1, stest3, and scntl3 registers. at power-on or reset, the quadrupler is disabled and powered down. follow these steps to use the clock quadru- pler: 1. set the sclk quadrupler enable bit (stest1, bit 3). 2. poll bit 5 of the stest4 register. the sym53c895 sets this bit as soon as it locks in the 160 mhz frequency. the frequency lockup takes approximately 100 microseconds. 3. halt the scsi clock by setting the halt scsi clock bit (stest3 bit 5) 4. set the clock conversion factor using the scf and ccf fields in the scntl3 register 5. set the sclk quadrupler select bit (stest1, bit 2) 6. clear the halt scsi clock bit prefetching scripts instructions when enabled (by setting the prefetch enable bit in the dcntl register), the prefetch logic in the sym53c895 fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the dmode register. if the burst size is less than four dwords, the sym53c895 performs normal instruction fetches. while the sym53c895 is prefetching scripts instructions, the pci cache line size register value does not have any effect and the read line, read multiple, and write and invalidate commands will not be used. the sym53c895 may flush the contents of the prefetch buffer under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. when one of these conditions apply, the contents of the prefetch buffer are flushed automatically. 1. on every memory move instruction. the memory move instruction is often used to place modified code directly into memory. to make sure that the chip executes all recent modifications, the prefetch buffer flushes its contents and loads the modified code every time an instruction is issued. to avoid inadvertently flushing the prefetch buffer contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction, refer to chapter 6. 2. on every store instruction. the store instruction may also be used to place modified code directly into memory. to avoid inadvertently flushing the prefetch buffer contents, use the no flush option for all store operations that do not modify code within the next 8 dwords.
2-4 sym53c895 data manual functional description parallel rom interface 3. on every write to the dsp. 4. on all transfer control instructions when the transfer conditions are met. this is necessary because the next instruction to be executed is not the sequential next instruction in the prefetch buffer. 5. when the pre-fetch flush bit (dcntl bit 6) is set. the buffer flushes whenever this bit is set. the bit is self-clearing. op code fetch burst capability setting the burst op code fetch enable bit in the dmode register (38h) causes the sym53c895 to burst in the first two dwords of all instruction fetches. if the instruction is a memory-to-memory move, the third dword will be accessed in a sepa- rate ownership. if the instruction is an indirect type, the additional dword will be accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the sym53c895 will use two accesses to obtain the four dwords required, in two bursts of two dwords each. note: this feature only works if pre-fetching is disabled. parallel rom interface the sym53c895 supports up to one megabyte of external memory in binary increments from 16 kb, to allow the use of expansion rom for add-in pci cards. the device also supports flash rom updates through the add-in interface and the gpio4 pin (used to control v pp , the power supply for programming external memory). this interface is designed for low-speed operations such as down- loading instruction code from rom; it is not intended for dynamic activities such as executing instructions. system requirements include the sym53c895, two or three external 8-bit address holding regis- ters (hct273 or hct374), and the appropriate memory device. the 4.7 k w resistors on the mem- ory address/data (mad) bus require hc or hct external components to be used. if in-system flash rom updates are required, a 7406 (high voltage open collector inverter), an mtd4p05, and sev- eral passive components are also needed. the memory size and speed is determined by pull-up/ pull-down configuration on the 8-bit bidirectional memory bus at power up. the sym53c895 senses this bus shortly after the release of the reset signal and configures the rom base address register and the memory cycle state machines for the appropri- ate conditions. the sym53c895 supports a variety of sizes and speeds of expansion rom, using pull-up and pull- down resistors on the mad(3-0) pins. the encod- ing of pins mad(3-1) allows the user to define how much external memory is available to the sym53c895. table 2-1 shows the memory space associated with the possible values of mad(3-1). the mad(3-1) pins are fully defined in chapter 4, signal descriptions. appendix c shows an example set of interface drawings. to use one of the configurations mentioned above in a host adapter board design, put 4.7 k w pull-up and pull-down resistors on the appropriate mad pins, corresponding to the available memory space. for example, to connect to a 32 kb external rom, use pull-downs on mad(3) and mad(2) and a pull-up on mad(1). note: the sym53c875 contains internal pull- ups on the mad bus. the sym53c895 requires external resistors to pull up the mad bus to v dd . table 2-1: external memory support mad(3-1) available memory space 000 16 kb 001 32 kb 010 64 kb 011 128 kb 100 256 kb 101 512 kb 110 1024 kb 111 no external memory present
functional description serial eeprom interface sym53c895 data manual 2-5 the sym53c895 allows the system to determine the size of the available external memory using the expansion rom base address register in pci configuration space. for more information on how this works, refer to the pci specification or the expansion rom base address register description in chapter 3. mad(0) is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to flash memory. the 12 volt power supply for flash memory, v pp , is enabled and disabled with the gpio4 pin and the gpio4 control bit. for more information on the gpio4 pin, refer to chapter 4, signal descriptions. serial eeprom interface the sym53c895 implements an interface which allows attachment of a serial eeprom device to the gpio0 and gpio1 pins. four different modes of operation are possible; each one relates to differ- ent values for the serial eeprom interface, the subsystem id register, and the subsystem vendor id register. the modes are programmable through the mad6 and mad7 pins, which are sampled at power-up or hard reset. mode a: 4.7 k w pull-ups on mad6 and mad7 in this mode, gpio0 is the serial data signal (sda) and gpio1 is the serial clock signal (scl). certain data in the serial eeprom is automati- cally loaded into chip registers at power-up or hard reset. the format of the serial eeprom data is defined in table 2-2. if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeroes. at power- up or hard reset, only five bytes are loaded into the chip from locations 00h through 04h. mode b: 4.7 k w pull-down on mad6, 4.7 k w pull-up on mad7 in this mode, gpio0 and gpio1 are each defined as either the serial data signal (sda) or the serial clock signal (scl), since both pins are controlled through software. no data is automatically loaded into chip registers at power-up or hard reset. the subsystem id reg- ister and subsystem vendor id registers are read/ write, in violation of the pci specification, with a default value of all zeroes. table 2-2: mode a serial eeprom data format byte description 00h subsystem vendor id, lsb. this byte is loaded into the least significant byte of the subsystem vendor id register in pci configuration space at chip power-up or hard reset. 01h subsystem vendor id, msb. this byte is loaded into the most significant byte of the subsystem vendor id reg- ister in pci configuration space at chip power-up or hard reset. 02h subsystem id, lsb. this byte is loaded into the least significant byte of the subsystem id register in pci con- figuration space at chip power-up or hard reset. 03h subsystem id, msb. this byte is loaded into the most significant byte of the subsystem id register in pci con- figuration space at chip power-up or hard reset. 04h checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 00h-03h to the seed value 55h, and then taking the 2s compliment of the result. 05h - ffh reserved 100h-eom user data
2-6 sym53c895 data manual functional description pci cache mode mode c: 4.7 k w pull-downs on mad6 and mad7 in this mode, gpio1 is the serial data signal (sda) and gpio0 is the serial clock signal (scl). certain data in the serial eeprom is automati- cally loaded into chip registers at power-up or hard reset. the format of the serial eeprom data is defined in table 2-3. if the eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeroes. at power- up or hard reset, only five bytes are loaded into the chip from locations fbh through ffh. mode d: 4.7 k w pull-up on mad6, 4.7 k w pull-down on mad7 this is a reserved mode and should not be used. it may be redefined in future devices. pci cache mode the sym53c895 supports the pci specification for an 8-bit cache line size register located in pci configuration space. the cache line size register provides the ability to sense and react to non- aligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each soft- ware enabled or disabled to allow the user full flex- ibility in using these commands. for more information on pci cache mode operations, refer to chapter 3, pci functional description. table 2-3: mode c serial eeprom data format byte description 00h - fah user data fbh subsystem vendor id, lsb. this byte is loaded into the least significant byte of the subsystem vendor id register in pci configuration space at chip power-up or hard reset. fch subsystem vendor id, msb. this byte is loaded into the most significant byte of the subsystem vendor id reg- ister in pci configuration space at chip power-up or hard reset. fdh subsystem id, lsb. this byte is loaded into the least significant byte of the subsystem id register in pci con- figuration space at chip power-up or hard reset. feh subsystem id, msb. this byte is loaded into the most significant byte of the subsystem id register in pci con- figuration space at chip power-up or hard reset. ffh checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations fbh-feh to the seed value 55h, and then taking the 2s compliment of the result. 100h-eom user data
functional description big and little endian support sym53c895 data manual 2-7 big and little endian support the sym53c895 supports both big and little endian byte ordering through pin selection. in big endian mode, the first byte of an aligned scsi-to- pci transfer will be routed to lane three and suc- ceeding transfers will be routed to descending lanes. this mode of operation also applies to data transfers over the add-in rom interface. the byte of data accessed at location 0000h from memory is routed to lane three, and the data at location 0003h is routed to byte lane 0. in little endian mode, the first byte of an aligned scsi to pci transfer will be routed to lane zero and succeeding transfers will be routed to ascending lanes. this mode of operation also applies to the add-in rom interface. the byte of data accessed at location 0000h from memory is routed to lane zero, and the data at location 0003h is routed to byte lane 3. the big_lit pin gives the sym53c895 the flexi- bility of operating with either big or little endian byte orientation. internally, in either mode, the actual byte lanes of the dma fifo and registers are not modified. the sym53c895 supports slave accesses in big or little endian mode. when a dword is accessed, no repositioning of the individual bytes is necessary since dwords are addressed by the address of the least significant byte. scripts always uses dwords in 32-bit sys- tems, so compatibility is maintained between sys- tems using different byte orientations. when less than a dword is accessed, individual bytes must be repositioned. internally, the sym53c895 adjusts the byte control logic of the dma fifo and regis- ter decodes to access the appropriate byte lanes. the registers will always appear on the same byte lane, but the address of the register will be reposi- tioned. big and little endian mode selection has the most effect on individual byte access. internally, the sym53c895 adjusts the byte control logic of the dma fifo and register decodes to enable the appropriate byte lane. the registers will always appear on the same byte lane, but the address of the register will be repositioned. data to be transferred between system memory and the scsi bus always starts at address zero and continues through address n - there is no byte ordering in the chip. the first byte in from the scsi bus goes to address 0, the second to address 1, etc. going out onto the scsi bus, address zero is the first byte out on the scsi bus, address 1 is the second byte, etc. the only difference is that in a little endian system, address 0 will be on byte lane 0, and in big endian mode address 0 will be on byte lane 3. correct scripts will be generated if the scripts compiler is run on a system that has the same byte ordering as the target system. any scripts patching in memory must patch the instruction with the byte ordering that the scripts processor expects. software drivers for the sym53c895 should access registers by their logical name (that is, scntl0) rather than by their address. the logical name should be equated to the registers big endian address in big endian mode (scntl0 = 03h), and its little endian address in little endian mode (scntl0 = 00h). this way, there is no change to the software when moving from one mode to the other; only the equate statement set- ting the operating modes needs to be changed. addressing of registers from within a scripts instruction is independent of bus mode. internally, the sym53c895 always operates in little endian mode.
2-8 sym53c895 data manual functional description loopback mode loopback mode the sym53c895 loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the stest1 register, the sym53c895 allows control of all scsi sig- nals, whether the sym53c895 is operating in ini- tiator or target mode. for more information on this mode of operation, refer to the symbios pci-scsi programming guide . parity options the sym53c895 implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recov- ery procedures. table 2-4 defines the bits that are involved in parity control and observation. table 2-5 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scntl0 register. table 2-6 describes the options available when a parity error occurs. table 2-4: bits used for parity control and generation bit name location description assert satn/ on parity errors scntl0, bit 1 causes the sym53c895 to automatically assert satn/ when it detects a parity error while operating as an initiator. enable parity checking scntl0, bit 3 enables the sym53c895 to check for parity errors. the sym53c895 checks for odd parity. assert even scsi parity scntl1, bit 2 determines the scsi parity sense generated by the sym53c895 to the scsi bus. disable halt on satn/ or a parity error (target mode only) scntl1, bit 5 causes the sym53c895 not to halt operations when a parity error is detected in target mode. enable parity error interrupt sien0, bit 0 determines whether the sym53c895 w ill generate an interrupt when it detects a scsi parity error. parity error sist0, bit 0 this status bit is set whenever the sym53c895 has detected a parity error on the scsi bus. status of scsi parity signal sstat0, bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal sstat2, bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity sstat 2, bit 3 and sstat1, bit 3 these bits reflect the scsi odd parity signal corresponding to the data latched into the sidl register master parity error enable ctest4, bit 3 enables parity checking during master data phases. master data parity error dstat, bit 6 set when the sym53c895 as a master detects that a target device has signalled a parity error during a data phase. master data parity error interrupt enable dien, bit 6 by clearing this bit, a master data parity error will not cause irq/ to be asserted, but the status bit will be set in the dstat register. enable parity error response command, bit 6 parity checking and parity error reporting are enabled on the pci bus.
functional description parity options sym53c895 data manual 2-9 table 2-5: scsi parity control epc aesp description 0 0 will not check for parity errors. parity is generated when send- ing scsi data. asserts odd parity when sending scsi data. 0 1 will not check for parity errors. parity is generated when send- ing scsi data. asserts even parity when sending scsi data. 1 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. key: epc = enable parity checking (bit 3 scntl0) asep = assert scsi even parity (bit 2 scntl1) this table only applies when the enable parity checking bit is set. table 2-6: scsi parity errors and interrupts dhp par description 0 0 will halt when a parity error occurs in target or initiator mode and will not generate an interrupt. 0 1 will halt when a parity error occurs in target mode and will gen- erate an interrupt in target or initiator mode. 1 0 will not halt in target mode when a parity error occurs until the end of the transfer. an interrupt will not be generated. 1 1 will not halt in target mode when a parity error occurs until the end of the transfer. an interrupt will be generated. key: dhp = disable halt on satn/ or parity error (bit 5 scntl1) par = parity error (bit 0 sien0)
2-10 sym53c895 data manual functional description dma fifo dma fifo the dma fifo is 4-bytes wide and 28 or 204 transfers deep. the dma fifo is illustrated in figure 2-1. to assure compatibility with older products in the sym53c8xx family, the user may set the dma fifo size to 112 bytes by clearing the dma fifo size bit, bit 5 in the ctest5 reg- ister. the 816-byte fifo size is related to the sym53c895 fifo architecture. it does not reflect any specific system design parameters or expectations. data paths the data path through the sym53c895 is depen- dent on whether data is being moved into or out of the chip, and whether scsi data is being trans- ferred asynchronously or synchronously. figure 2-2 shows how data is moved to/from the scsi bus in each of the different modes. the following steps determine if any bytes remain in the data path when the chip halts an operation: asynchronous scsi send 1. if the dma fifo size is set to 112 bytes, look at the dfifo and dbc registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dbc register from the 7- bit value of the dfifo register. and the result with 7fh for a byte count between zero and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits 7-0 of the dma fifo register. and the result with 3ffh for a byte count between 0 and 816. figure 2-1: dma fifo sections 28 or 204 transfers deep 32 bits wide 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0 . . . . . .
functional description dma fifo sym53c895 data manual 2-11 2. read bit 5 in the sstat0 and sstat2 registers to determine if any bytes are left in the sodl register. if bit 5 is set in the sstat0 or sstat2, then the least significant byte or the most significant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. synchronous scsi send 1. if the dma fifo size is set to 112 bytes, look at the dfifo and dbc registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dbc register from the 7- bit value of the dfifo register. and the result with 7fh for a byte count between zero and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits 7-0 of the dma fifo register. and the result with 3ffh for a byte count between 0 and 816. 2. read bit 5 in the sstat0 and sstat2 registers to determine if any bytes are left in the sodl register. if bit 5 is set in the sstat0 or sstat2, then the least significant byte or the most significant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. 3. read bit 6 in the sstat0 and sstat2 registers to determine if any bytes are left in the sodr register. if bit 6 is set in the sstat0 or sstat2, then the least significant byte or the most significant byte in the sodr register is full, respectively. asynchronous scsi receive 1. if the dma fifo size is set to 112 bytes, look at the dfifo and dbc registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 7fh for a byte count between 0 and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits 7-0 of the dma fifo register. and the result with 3ffh for a byte count between 0 and 816. 2. read bit 7 in the sstat0 and sstat2 register to determine if any bytes are left in the sidl register. if bit 7 is set in the sstat0 or sstat2, then the least significant byte or the most significant byte is full, respectively. 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit (scntl2, bit 0) to determine whether a byte is left in the swide register. synchronous scsi receive 1. if the dma fifo size is set to 112 bytes, subtract the seven least significant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 7fh for a byte count between 0 and 112. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits 7-0 of the dma fifo register. and the result with 3ffh for a byte count between 0 and 816.
2-12 sym53c895 data manual functional description scsi bus interface 2. read bits 7-4 of the sstat1 register and bit 4 of the sstat2 register, the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit (scntl2, bit 0) to determine whether a byte is left in the swide register. scsi bus interface the sym53c895 performs single-ended and low voltage differential (lvd) transfers, and supports traditional (high-power) differential operation when the chip is connected to external high-power differential transceivers. to support lvd scsi, all scsi data and control signals have a positive and a negative signal line, as in high voltage differential. in single-ended and high voltage differential operation, the negative sig- nals perform the scsi data and control function. in high voltage differential mode, the positive sig- nals provide directional control and in single- ended mode they are virtual ground drivers. tolerant technology provides signal filtering at the inputs of sreq/ and sack/ to increase immu- nity to signal reflections. lvdlink technology to support greater device connectivity and a longer scsi cable, the sym53c895 features lvdlink technology, the symbios implementation of lvd scsi. lvdlink transceivers provide the inherent reliability of differential scsi, and a long- term migration path of faster scsi transfer rates. lvdlink technology is based on current drive; its low output current reduces the power needed to drive the scsi bus, so that the i/o drivers can be integrated directly onto the chip. this reduces the cost and complexity compared to traditional (high power) differential designs. lvdlink lowers the amplitude of noise reflections and allows higher transmission frequencies. figure 2-2: sym53c895 host interface data paths pci interface dma fifo (32 bits x 28 or 204) sodl register scsi interface asynchronous scsi send pci interface dma fifo (32 bits x 28 or 204) sidl register scsi interface asynchronous scsi receive pci interface dma fifo (32 bits x 28 or 204) sodl register sodr register synchronous scsi send pci interface dma fifo (32 bits x 28 or 204) scsi fifo (8 or 16 bits x 31) scsi interface synchronous scsi receive scsi interface swide register swide register
functional description scsi bus interface sym53c895 data manual 2-13 the symbios lvdlink transceivers operate in lvd and single-ended modes. they allow the chip to detect a high voltage differential signal when the chip is connected to external high voltage differen- tial transceivers. the sym53c895 automatically detects which type of signal is connected, based on voltage detected by the diffsens pin. bits 7 and 6 of the stest4 register contain the encoded value for the type of signal that is detected (lvd, single-ended, or high voltage differential). please see the stest4 register description for encoding and other bit information. high voltage differential mode(hvd) to maintain backward compatibility with legacy systems, the sym53c895 can operate in high volt- age differential mode (when the chip is connected to external differential transceivers). in high volt- age differential mode, the sd+ (15-0), sdp+ (1- 0), req+, ack+, rst+, bsy+, and sel+ sig- nals control the direction of external differential- pair transceivers. the sym53c895 is placed in differential mode by setting the dif bit, bit 5 of the stest2 register (4eh). setting this bit tri- states the bsy-, sel-, and rst- pads so they can be used as pure input pins. in addition to the stan- dard scsi lines, the following signals are used by the sym53c895 during high voltage differential operation: signal function bsy+, sel+, rst+ active high signals used to enable the differential drivers as outputs for scsi signals bsy-, sel-, and rst-, respectively sd+(15-0), sdp+(1-0) active high signals used to control direction of the differential drivers for scsi data and par- ity lines, respectively ack+ active high signal used to control direction of the differential driver for initiator group sig- nals atn- and ack- req+ active high signal used to control direction of the differential drivers for target group signals msg-, c/d-, i/o- and req-/ diffsens input to the sym53c895 used to detect the voltage level of a scsi signal to determine whether it is a single-ended, lvd, or high-power differential signal. the result is displayed in stest4 bits 7-6.
2-14 sym53c895 data manual functional description scsi bus interface in the differential wiring diagram example shown in figure 2-3, the sym53c895 is connected to the ti sn75976a2 differential transceiver for ultra scsi operation. the recommended value of the pull-up resistor on the req-, ack-, msg-, c/d-, i/o-, atn-, sd0-7-, and sdp0- lines is 680 w when the active negation portion of symbios tolerant technology is not enabled. when tolerant is enabled, the recommended resistor value on the req-, ack-, sd7-0-, and sdp0- signals is 1.5 k w . the electrical characteristics of these pins change when tolerant is enabled, per- mitting a higher resistor value. to interface the sym53c895 to the sn75976a2, connect the positive pins in the scsi lvd pair of the sym53c895 directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the sn75976a2. the scsi bidirectional control and data pins (sd7-0- sdp0-, req-, ack-, msg-, i_o-, c_d, and atn-) of the sym53c895 connect to the bidirectional data pins (na) of the sn75976a2 with a pull-up resistor. the pull-up value should be no lower than the transceiver i ol can tolerate, but not so high as to cause rc timing problems. the three remaining pins, sel-, bsy,- and rst-, are connected to the sn75976a2 with a pull-down resistor. the pull-down resistors are required when the pins (na) of the sn75976a2 are configured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the sym53c895 pins (sel-, bsy-, and rst-) and the sn75976a2 data pins. because the sel-, bsy-, and rst- pins on the sym53c895 are inputs only, this configu- ration allows for the sel-, bsy-, and rst- scsi signals to be asserted on the scsi bus. the differ- ential pairs on the scsi bus are reversed when connected to the sn75976a2, due to the active low nature of the scsi bus. 8-bit/16-bit scsi and the high voltage differential interface in an 8-bit scsi bus, the sd15-8 pins on the sym53c895 should be pulled up with a 1.5 k w resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left floating.
functional description scsi bus interface sym53c895 data manual 2-15 figure 2-3: high voltage differential wiring diagram for ultra scsi sd8-15- sdp1- sdp0+ sd7+ sd6+ sd5+ sd4+ sd3+ sd2+ sd1+ sd0+ sdp0- sd7- sd6- sd5- sd4- sd3- sd2- sd1- sd0- diffsens sel+ bsy+ rst+ sel- bsy- rst- req- ack- msg- c/d- i i/o- atn- req+ ack+ 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde0 cde1 cde2 bsr cre 1b+ 1b- 2b+ 2b- 3b+ 3b- 4b+ 4b- 5b+ 5b- 6b+ 6b- 7b+ 7b- 8b+ 8b- 9b+ 9b- sn75976a2 sd0- sd1- sd2- sd3- sd4- sd5- sd5- sd7- sdp0- sd0+ sd1+ sd2+ sd3+ sd4+ sd5+ sd6+ sd7+ sdp0+ 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde0 cde1 cde2 bsr cre 1b+ 1b- 2b+ 2b- 3b+ 3b- 4b+ 4b- 5b+ 5b- 6b+ 6b- 7b+ 7b- 8b+ 8b- 9b+ 9b- sn75976a2 diffsens vdd sel+ bsy+ rst+ sel- bsy- rst- req/ ack- msg- c_d- i_o- atn- -sel (42) +sel (41) -bsy (34) +bsy (33) -rst (38) +rst (37) -req (46) +req (45) -ack (36) +ack (35) -msg (40) +msg (39) -c/d (44) +c/d (43) -i/o (48) +i/o (47) -atn (30) +atn (29) -db0 (4) +db0 (3) -db1 (6) +db1 (5) -db2 (8) +db2 (7) -db3 (10) +db3 (9) -db4 (12) +db4 (11) -db5 (14) +db5 (13) -db6 (16) +db6 (15) -db7 (18) +db7 (17) -dbp (20) +dbp (19) 1.5 k 1.5 k sym53c8xx scsi bus vdd 1.5 k vdd vdd 1.5 k vdd 1.5 k vdd 1.5 k diffsens (pin 21) schottky diode diffsens diffsens 1.5 k
2-16 sym53c895 data manual functional description scsi bus interface scsi termination the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends; no system should ever have more or less than two ter- minators installed and active. scsi host adapters should provide a means of accommodating termi- nators. the terminators should be socketed, so that if not needed they may be removed, or there should be a means of disabling them with software. single-ended cables can use a 220 w pull-up to the terminator power supply (term-power) line and a 330 w pull-down to ground. because of the high- performance nature of the sym53c895, regu- lated (or active) termination is recommended. fig- ure 2-4 shows a unitrode active terminator. for additional information, refer to the scsi-2 speci- fication. tolerant active negation can be used with either termination network. for information on terminators that support lvd, refer to the spi-2 draft standard. note: if the sym53c895 is to be used in a design with only an 8-bit scsi bus, all 16 data lines still must be terminated or pulled high. system engineering note in the sym53c895, transmission mode detection for single-ended (se), high voltage differential (hvd), and low voltage differential (lvd) is implemented by using the diffsens line. table 2-7 shows the corresponding voltages and what mode they indicate. the spi-2 (scsi parallel interconnect 2) specifi- cation, revision 1.1, requires that a bus mode change must be sensed for at least a continuous 100 ms to be valid. additionally, the signal drivers should remain in a high impedance state at power up until the device is capable of full logical opera- tion for at least 100 ms and the bus mode detected by the diffsens line has remained stable for at least another 100 ms after that. in order to achieve the sufficient 100 ms delay required by the stan- dard, the following steps should be taken when a mode change is detected. at power-up: 1. set bit 3 in stest2 (register 4eh), to place the scsi drivers in a high impedance state. 2. enable the sbmc (scsi bus mode change) interrupt by setting bit 4 in sien1 (register 41h). 3. if a scsi bus mode change is detected, then sist1 (register 43h), bit 4 will indicate a sbmc interrupt. 4. clear the interrupt by reading sist0 (register 42h) and sist1. 5. wait 100 ms. 6. check that no more sbmc interrupts have occurred. if not, the diffsens line has not changed voltage levels and the bus mode is stable. read bits 7-6 in stest4 (register 52h). write these two bits to stest0 (register 4ch), bits 5-4. this will force the scsi bus table 2-7: transmission mode mode se lvd hvd voltage -0.35 to +0.5 0.7 to 1.9 2.4 to 5.5
functional description scsi bus interface sym53c895 data manual 2-17 mode to the correct operating mode. (if a sbmc interrupt occurs between steps 4 and 6, handle the interrupt and return to step 3.) note that bits 5-4 in stest0 are normally used as part of the ssaid and are read only. these bits may be written as part of a special test mode that forces the scsi bus mode to one of three operating modes: single-ended, lvd, or high voltage differential. the bit encoding is the same that is shown in the table under stest4 for bits 7-6. 7. clear bit 3 in stest2 to remove the sci drivers from the high impedance state. during normal operation: 1. enable the sbmc (scsi bus mode change) interrupt. bit 4 in sien1 should be set. 2. if a scsi bus mode change is detected, sist1, bit 4 will indicate a sbmc interrupt. 3. clear the interrupt by reading sist0 and sist1. 4. wait 100 ms. 5. check that no more sbmc interrupts have occurred. if not, the diffsens line has not changed voltage levels and the bus mode is stable. read bits 7-6 in stest4. write two bits 5 and 4 to stest0. note that bits 5-4 in stest0 are normally used as part of the ssaid and are read only. these bits may be written as part of a special test mode that forces the scsi bus mode to one of three operating modes: single-ended, lvd, or high voltage differential. the bit encoding is the same that is shown in the table under stest4 for bits 7-6. this will force the scsi bus to the correct operating mode. if a sbmc interrupt did occur between steps 3 and 5 , handle the interrupt and return to step 3. the scsi bus mode change (sbmc) interrupt can cause a problem in systems that use multiple software drivers, where the drivers pass control to one another after a chip reset. this problem occurs when the sym53c895 is connected to a single- ended scsi bus, because the sbmc interrupt is generated after each reset. in particular, this prob- lem occurs with netware when control is passed between the netware and dos drivers. after a soft reset, the sym53c895 defaults to lvd mode. if single-ended devices are on the bus, causing the diffsens line to be pulled low, a sbmc inter- rupt will be generated and the driver will need to respond to it. one solution is to use a soft abort by writing a one to bit 7 in the istat register, instead of a soft reset to stop current scsi transactions. this would halt current transactions without altering chip settings such as the clock quadrupler and the clock divider setup. the pending transactions would then be started over.
2-18 sym53c895 data manual functional description scsi bus interface . (re)select during (re)selection in multi-threaded scsi i/o environments, it is not uncommon to be selected or reselected while try- ing to perform selection/reselection. this situation may occur when a scsi controller (operating in initiator mode) tries to select a target and is rese- lected by another. the select scripts instruc- tion has an alternate address to which the scripts will jump when this situation occurs. the analogous situation for target devices is being selected while trying to perform a reselection. once a change in operating mode occurs, the initi- ator scripts should start with a set initiator instruction or the target scripts should start with a set target instruction. the selection and reselection enable bits (scid bits 5 and 6, respectively) should both be asserted so that the sym53c895 may respond as an initiator or as a target. if only selection is enabled, the sym53c895 cannot be reselected as an initiator. there are also status and interrupt bits in the sist0 and sien0 registers, respectively, indicat- ing that the sym53c895 has been selected (bit 5) and reselected (bit 4). figure 2-4: regulated termination for ultra2 scsi line9- line9+ line8- line8+ line7- line7+ line6- line6+ diff sense ucc5630 32 31 30 29 25 24 23 22 20 sdp0- sdp0+ sd7- sd7+ sd6- sd6+ sd5- sd5+ discnct line1+ line1- line2+ line2- line3+ line3- line4+ line4- line5+ line5- 4 5 6 7 11 12 13 14 15 16 17 sd0+ sd0- sd1+ sd1- sd2+ sd2- sd3+ sd3- sd4+ sd4- diff sense connects to the scsi bus diffsense line to detect what type of devices (single-ended, lvd, or high-voltage differential) are connected to the scsi bus. discnct shuts down the terminator when it is not at the end of the bus. the disconnect pin low enables the terminator. use additional ucc5630 terminators to connect the scsi control signals and additional wide scsi data byte a needed.
functional description synchronous operation sym53c895 data manual 2-19 synchronous operation the sym53c895 can transfer synchronous scsi data in both initiator and target modes. the sxfer register controls both the synchronous off- set and the transfer period. it may be loaded by the cpu before scripts execution begins, from within scripts via a table indirect i/o instruc- tion, or with a read-modify-write instruction. the sym53c895 can receive data from the scsi bus at a synchronous transfer period as short as 25 ns, regardless of the transfer period used to send data. the sym53c895 can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the sym53c895 can send synchronous data at intervals as short as 25 ns for ultra2 scsi, 50 ns for ultra scsi, 100 ns for fast scsi and 200 ns for scsi-1. determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the sym53c895. a brief description of the bits is provided below. figure 2-5 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. scntl3 register, bits 6C4 (scf2C0) the scf2-0 bits select the factor by which the fre- quency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received; this rate must not exceed 160 mhz. the receive rate of synchronous scsi data is 1/4 of the scf divider output. for example, if sclk is 160 mhz and the scf value is set to divide by one, then the maximum rate at which data can be received is 40 mhz (160/(1*4) = 40). scntl3 register, bits 2 C0 (ccf2C0) the ccf2-0 bits select the factor by which the fre- quency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the table. sxfer register, bits 7C5 (tp2C0) the tp2-0 divider bits determine the scsi syn- chronous transfer period when sending synchro- nous scsi data in either initiator or target mode. this value further divides the output from the scf divider.
2-20 sym53c895 data manual functional description synchronous operation ultra2 scsi synchronous data transfers ultra2 scsi is an extension of current ultra scsi synchronous transfer specifications. it allows syn- chronous transfer periods to be negotiated down as low as 25 ns, which is half the 50 ns period allowed under ultra scsi. this will allow a maximum transfer rate of 80 mb/s on a 16-bit, lvd scsi bus. the sym53c895 has a scsi clock quadru- pler that must be enabled for the chip to perform ultra2 scsi transfers with a 40 mhz oscillator. in addition, the following bit values affect the chips ability to support ultra2 scsi synchronous trans- fer rates: 1. clock conversion factor bits, scntl3 register bits 2-0 and synchronous clock conversion factor bits, scntl3 register bits 6-4. these fields support a value of 111 (binary), allowing the 160 mhz sclk frequency to be divided down by 8 for the asynchronous logic. 2. ultra2 scsi enable bit, scntl 3 register bit 7. setting this bit enables ultra2 scsi synchronous transfers in systems that use the internal scsi clock quadrupler. 3. tolerant enable bit, stest3 register bit 7. active negation must be enabled for the sym53c895 to perform ultra2 scsi transfers. note: the clock quadrupler requires a 40 mhz external clock. symbios software assumes that the sym53c895 is connected to a 40 mhz external clock, which is quadrupled to achieve ultra2 scsi transfer rates.
functional description synchronous operation sym53c895 data manual 2-21 figure 2-5: determining the synchronous transfer rate ccf2 ccf1 ccf0 qclk (mhz) 0 0 0 50.1-66.00 0 0 1 16.67-25.00 0 1 0 25.01-37.50 0 1 1 37.51-50.00 1 0 0 50.01-66.00 1 0 1 75.01-80.00 110120 1 1 1 160 example : qclk (quadrupled scsi clock)=160 mhz, scf=1(/1), xferp=0(/4), ccf=7 (/8) synchronous send rate = (qclk/scf)/xferp= (160/1)/4=40mb/s synchronous receive rate=(qclk/scf)/4=(160/1)/4=40mb/s divide by 4 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 sclk scf ccf asynchronous send clock divider divider scsi logic scf2 scf1 scf0 scf divisor 0011 0101.5 0112 1003 0003 1014 1106 1118 this point must not exceed 160 mhz receive clock (to scsi bus) synchronous divider clock quadrupler qclk
2-22 sym53c895 data manual functional description interrupt handling interrupt handling the scripts processor in the sym53c895 per- forms most functions independently of the host microprocessor. however, certain interrupt situa- tions must be handled by the external micropro- cessor. this section explains all aspects of interrupts as they apply to the sym53c895. polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware inter- rupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the sym53c895 will assert the interrupt request (irq/) line that will interrupt the microprocessor, causing the micro- processor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. registers the registers in the sym53c895 that are used for detecting or defining interrupts are: istat, sist0, sist1, dstat, sien0, sien1, dcntl, and dien registers. istat the istat is the only register that can be accessed as a slave during scripts operation, therefore it is the register that is polled when polled interrupts are used. it is also the first register that should be read when the irq/ pin has been asserted in asso- ciation with a hardware interrupt. the intf (interrupt on the fly) bit should be the first inter- rupt serviced. it must be written to one to be cleared. this interrupt must be cleared before ser- vicing any other interrupts. if the sip bit in the istat register is set, then a scsi-type interrupt has occurred and the sist0 and sist1 registers should be read. if the dip bit in the istat regis- ter is set, then a dma-type interrupt has occurred and the dstat register should be read. scsi- type and dma-type interrupts may occur simulta- neously, so in some cases both sip and dip may be set. sist0 and sist1 the sist0 and sist1 registers contain the scsi- type interrupt bits. reading these registers will determine which condition or conditions caused the scsi-type interrupt, and will clear that scsi interrupt condition. if the sym53c895 is receiv- ing data from the scsi bus and a fatal interrupt condition occurs, the sym53c895 will attempt to send the contents of the dma fifo to memory before generating the interrupt. if the sym53c895 is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. if this situation occurs, the dma fifo empty (dfe) bit in dstat should be checked. if this bit is clear, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing. the clf bit is bit 2 in ctest3. the csf bit is bit 1 in stest3. dstat the dstat register contains the dma-type interrupt bits. reading this register will determine which condition or conditions caused the dma- type interrupt, and will clear that dma interrupt condition. bit 7 in dstat, dfe, is purely a status bit; it will not generate an interrupt under any cir- cumstances and will not be cleared when read. dma interrupts will flush neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dstat register should be checked after any dma interrupt. if the dfe bit is clear, then the fifos must be cleared by setting the clf (clear dma fifo) and csf (clear scsi fifo) bits, or flushed by setting the flf (flush dma fifo) bit. sien0 and sien1 the sien0 and sien1 registers are the interrupt enable registers for the scsi interrupts in sist0 and sist1.
functional description interrupt handling sym53c895 data manual 2-23 dien the dien register is the interrupt enable register for dma interrupts in dstat. dcntl when bit 1 in this register is set, the irq/ pin will not be asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but merely masked at the pin. clearing this bit when an interrupt is pending will immediately cause the irq/ pin to assert. as with any register other than istat, this register cannot be accessed except by a scripts instruction during scripts execution. fatal vs. non-fatal interrupts a fatal interrupt, as the name implies, always causes scripts to stop running. all non-fatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. inter- rupt masking will be discussed later in this section. all dma interrupts (indicated by the dip bit in istat and one or more bits in dstat being set) are fatal. some scsi interrupts (indicated by the sip bit in the istat and one or more bits in sist0 or sist1 being set) are non-fatal. when the sym53c895 is operating in initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake to handshake timer expired (hth) interrupts are non-fatal. when operating in target mode cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are non-fatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scntl1 register to configure the chips behavior when the satn/ interrupt is enabled during target mode operation. the interrupt on the fly interrupt is also non-fatal, since scripts can continue when it occurs. the reason for non-fatal interrupts is to prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the sym53c895 has been selected or reselected (sel or rsl set), when the initiator has asserted atn (target mode: satn/ active), or when the general purpose or hand- shake to handshake timers expire. these inter- rupts are not needed for events that occur during high-level scripts operation. masking masking an interrupt means disabling or ignoring that interrupt. interrupts can be masked by clear- ing bits in the sien0 and sien1 (for scsi inter- rupts) registers or dien (for dma interrupts) register. how the chip will respond to masked interrupts depends on: whether polling or hard- ware interrupts are being used; whether the inter- rupt is fatal or non-fatal; and whether the chip is operating in initiator or target mode. if a non-fatal interrupt is masked and that condi- tion occurs, scripts will not stop, the appropri- ate bit in the sist0 or sist1 will still be set, the sip bit in the istat will not be set, and the irq/ pin will not be asserted. see the section on fatal vs. non-fatal interrupts for a list of the non-fatal inter- rupts. if a fatal interrupt is masked and that condition occurs, then scripts will still stop, the appropri- ate bit in the dstat, sist0, or sist1 register will be set, and the sip or dip bits in the istat will be set, but the irq/ pin will not be asserted. when the chip is initialized, enable all fatal inter- rupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, scripts will halt and the system will never know it unless it times out and checks the istat after a certain period of inactivity.
2-24 sym53c895 data manual functional description interrupt handling if you are polling the istat instead of using hard- ware interrupts, then masking a fatal interrupt will make no difference since the sip and dip bits in the istat inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted will not cause irq/ to be deasserted. stacked interrupts the sym53c895 stacks interrupts if they occur one after the other. if the sip or dip bits in the istat register are set (first level), then there is already at least one pending interrupt, and any future interrupts will be stacked in extra registers behind the sist0, sist1, and dstat registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts will set additional bits in the extra regis- ters behind sist0, sist1, and dstat. when the first level of interrupts are cleared, all the inter- rupts that came in afterward will move into the sist0, sist1, and dstat. after the first inter- rupt is cleared by reading the appropriate register, the irq/ pin will be deasserted for a minimum of three clks; the stacked interrupt(s) will move into the sist0, sist1, or dstat; and the irq/ pin will be asserted once again. since a masked non-fatal interrupt will not set the sip or dip bits, interrupt stacking will not occur. a masked, non-fatal interrupt will still post the interrupt in sist0, but will not assert the irq/ pin. since no interrupt is generated, future inter- rupts will move right into the sist0 or sist1 instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked non-fatal interrupt will still be set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stack- ing does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but will not be stacked. these could be multiple scsi interrupts (sip set), multi- ple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts will not attempt to flush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts will not be posted until the dma fifo is clear of data. these locked out scsi interrupts will be posted as soon as the dma fifo is empty. halting in an orderly fashion when an interrupt occurs, the sym53c895 will attempt to halt in an orderly fashion. n if the interrupt occurs in the middle of an instruction fetch, the fetch will be completed, except in the case of a bus fault. execution will not begin, but the dsp will point to the next instruction since it is updated when the current instruction is fetched. n if the dma direction is a write to memory and a scsi interrupt occurs, the sym53c895 will attempt to flush the dma fifo to memory before halting. under any other circumstances only the current cycle will be completed before halting, so the dfe bit in dstat should be checked to see if any data remains in the dma fifo. n scsi sreq/sack handshakes that have begun will be completed before halting. n the sym53c895 will attempt to clean up any outstanding synchronous offset before halting. n in the case of transfer control instructions, once instruction execution begins it will continue to completion before halting. n if the instruction is a jump/call when/if , the dsp will be updated to the transfer address before halting. n all other instructions may halt before completion.
functional description chained block moves sym53c895 data manual 2-25 sample interrupt service routine the following is a sample of an interrupt service routine for the sym53c895. it can be repeated if polling is used, or should be called when the irq/ pin is asserted if hardware interrupts are used. 1. read istat. 2. if the intf bit is set, it must be written to a one to clear this status. 3. if only the sip bit is set, read sist0 and sist1 to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 tell which scsi interrupt(s) occurred and determine what action is required to service the interrupt(s). 4. if only the dip bit is set, read the dstat to clear the interrupt condition and get the dma interrupt status. the bits in the dstat will tell which dma interrupt(s) occurred and determine what action is required to service the interrupt(s). 5. if both the sip and dip bits are set, read sist0, sist1, and dstat to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clk delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the interrupt service routine. it is recommended that the dma interrupt be serviced before the scsi interrupt, because a serious dma interrupt condition could influence how the scsi interrupt is acted upon. 6. when using polled interrupts, go back to step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the first interrupt was cleared. when using hardware interrupts, the irq/ pin will be asserted again if there are any stacked interrupts. this should cause the system to re- enter the interrupt service routine. chained block moves since the sym53c895 has the capability to trans- fer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scntl2 register are used to facilitate these situations. the chained block move instruction is illustrated in figure 2-6. wide scsi send bit (wss) the wss bit is set whenever the scsi core is sending data (data out for initiator or data in for target) and the core detects a partial transfer at the end of a chained block move scripts instruc- tion (this flag will not be set if a normal block move instruction is used). under this condition, the scsi core does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the sodl register and the wss flag is set. the hardware uses the wss flag to determine what behavior must occur at the start of the next data send transfer. when the wss flag is set at the start of the next transfer, the first byte (the high-order byte) of the next data send transfer is married with the stored low-order byte in the sodl register; and the two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the flag is automatically cleared when the married word is sent. the flag can alternately be cleared through scripts or by the microprocessor.
2-26 sym53c895 data manual functional description chained block moves additionally, this bit can be used by the micropro- cessor or scripts for error detection and recov- ery purposes. wide scsi receive bit (wsr) the wsr bit is set whenever the scsi core is receiving data (data in for initiator or data out for target) and the core detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is tempo- rarily stored in the swide register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the bit can alternatively be cleared by the microprocessor or through scripts. the bit can also be used by the micro- processor or scripts for error detection and recovery purposes. swide register this register stores data for partial byte data trans- fers. for receive data, the swide register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be a residue byte (and there- fore ignored) or it may be valid data that will be transferred to memory at the beginning of the next block move instruction. sodl register for send data, the low-order byte of the sodl register holds the low-order byte of a partial mem- ory transfer which has not yet been transferred across the scsi bus. this stored data is usually married with the first byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command. chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without addi- tional op code overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data in for initiator or data out for target), a chained block move instruction indi- cates that if a partial transfer occurred at the end of the instruction, the wsr flag is set.the high order byte of the last scsi transfer is stored in the swide register rather than transferred to mem- ory. the contents of the swide register should be the first byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the swide register is one of the bytes in the byte count. if the wsr bit is clear when a receive data chained block move instruc- tion is executed, the data transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or clear, when a nor- mal block move instruction is executed, the con- tents of the swide register will be ignored and the transfer takes place normally. for n consec- utive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves. for send data (data out for initiator or data in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the sodl register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists.
functional description chained block moves sym53c895 data manual 2-27 for example, if the instruction is an initiator chained block move data out of five bytes (and wss is not previously set), five bytes will be trans- ferred out of memory to the scsi core, four bytes will be transferred from the scsi core across the scsi bus, and one byte will be temporarily stored in the lower byte of the sodl register waiting to be married with the first byte of the next block move instruction. regardless of whether a chained block move or normal block move instruction is used, if the wss bit is set at the start of a data send command, the first byte of the data send command is assumed to be the high-order byte and is mar- ried with the low-order byte stored in the stored in the lower byte of the sodl register before the two bytes are sent across the scsi bus. for n consecutive wide data send block move com- mands, the first through the (nth - 1) block move instructions should be chained block moves. notes: chmov 5, 3 when data_out: moves five bytes from address 03 in the host memory to the scsi bus (bytes 03, 04, 05, and 06 are moved and byte 07 remains in the low order byte of the scsi output data latch register and is married with the first byte of the fol- lowing move instruction). move 5, 9 when data_out: moves five bytes from address 09 in the host memory to the scsi bus. figure 2-6: block move and chained block move instructions 00 04 08 0c 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 10 11 12 13 32 bits host memory 04 05 06 03 07 09 0a 0b 0c 0d 16 bits scsi bus
2-28 sym53c895 data manual functional description chained block moves
pci functional description pci addressing sym53c895 data manual 3-1 chapter 3 pci functional description pci addressing there are three types of pci-defined address spaces: 1. configuration space 2. memory space 3. i/o space configuration space is a contiguous 256 x 8-bit set of addresses dedicated to each slot or stub on the bus. decoding c_be/(3-0) determines if a pci cycle is intended to access configuration register space. the idsel bus signal is a chip select that allows access to the configuration register space only. a configuration read/write cycle without idsel will be ignored. the eight lower order addresses are used to select a specific 8-bit register. ad(10-8) are decoded as well, but they must be zero or the sym53c895 will not respond. accord- ing to the pci specification, ad(10-8) are to be used for multifunction devices. the host processor uses the pci configuration space to initialize the sym53c895. the lower 128 bytes of the sym53c895 configu- ration space holds system parameters while the upper 128 bytes map into the sym53c895 oper- ating registers. for all pci cycles except configura- tion cycles, the sym53c895 registers are located on the 256-byte block boundary defined by the base address assigned through the configured reg- ister. the sym53c895 operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. at initialization time, each pci device is assigned a base address (in the case of the sym53c895, the upper 24 bits of the address are selected) for mem- ory accesses and i/o accesses. on every access, the sym53c895 compares its assigned base addresses with the value on the address/data bus during the pci address phase. if there is a match of the upper 24 bits, the access is for the sym53c895 and the low order eight bits define the register to be accessed. a decode of c_be/ (3-0) determines which registers and what type of access is to be performed. pci defines memory space as a contiguous 32-bit memory address that is shared by all system resources, including the sym53c895. base address register one determines which 256-byte memory area this device will occupy. pci defines i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the sym53c895. base address register zero determines which 256-byte i/o area this device will occupy. pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus com- mands are encoded on the c_be/(3-0) lines dur- ing the address phase. pci bus command encoding and types appear in table 3-1. the i/o read command is used to read data from an agent mapped in i/o address space. all 32 address bits are decoded. the i/o write command is used to write data to an agent when mapped in i/o address space. all 32 address bits are decoded.
pci functional description pci cache mode 3-2 sym53c895 data manual the memory read, memory read multiple, and memory read line commands are used to read data from an agent mapped in memory address space. all 32 address bits are decoded. the memory write and memory write and inval- idate commands are used to write data to an agent when mapped in memory address space. all 32 address bits are decoded. pci cache mode the sym53c895 supports the pci specification for an 8-bit cache line size register located in pci configuration space. the cache line size register provides the ability to sense and react to non- aligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each soft- ware enabled or disabled to allow the user full flex- ibility in using these commands. support for pci cache line size register the sym53c895 supports the pci specification for an 8-bit cache line size register in pci config- uration space; it can sense and react to non-aligned addresses corresponding to cache line boundaries. selection of cache line size the cache logic will select a cache line size based on the values for the burst size in the dmode register, bit 2 in the ctest5 register, and the pci cache line size register. table 3-1: pci bus commands supported c_be(3-0) command type supported as master supported as slave 0000 special interrupt acknowledge no no 0001 special cycle no no 0010 i/o read cycle yes yes 0011 i/o write cycle yes yes 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 memory read yes yes 0111 memory write yes yes 1000 reserved n/a n/a 1001 reserved n/a n/a 1010 configuration read no yes 1011 configuration write no yes 1100 memory read multiple yes** no (defaults to 0110) 1101 dual address cycle no no 1110 memory read line yes* no (defaults to 0110) 1111 memory write and invalidate yes*** no (defaults to 0111) * this operation is selectable by bit 3 in the dmode operating register ** this operation is selectable by bit 2 in the dmode operating register ***this operation is selectable by bit 0 in the ctest3 operating register
pci functional description pci cache mode sym53c895 data manual 3-3 note: the sym53c895 will not automatically use the value in the pci cache line size register as the cache line size value. the chip scales the value of the cache line size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128), compares this value to the burst size defined by the values of the dmode register and bit 2 of the ctest5 register, then selects the smallest as the value for the cache line size. the sym53c895 will use this value for all burst data transfers. alignment the sym53c895 uses the calculated line size value to monitor the current address for alignment to the cache line size. when it is not aligned, the chip attempts to align to the cache boundary by using a smart aligning scheme. this means that it will attempt to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no overflow. this process is a stepping mechanism that will step up to the highest possible burst size based on the cur- rent address. the stepping process begins at a 4-dword bound- ary. the sym53c895 will first try to align to a 4- dword boundary (0x0000, 0x0010, etc.) by using single dword transfers (no bursting). once this boundary has been reached the chip will evaluate the current alignment to various burst sizes allowed, and will select the largest possible as the next burst size, while not exceeding the cache line size. the chip will then issue this burst, and re- evaluate the alignment to various burst sizes, again selecting the largest possible while not exceeding the cache line size, as the next burst size. this step- ping process continues until the chip reaches the cache line size boundary or runs out of data. once a cache line boundary is reached, the chip will use the cache line size as the burst size from then on, except in the case of multiples (explained below). the alignment process is finished at this point. example: cache line size - 16, current address = 0x01 the chip is not aligned to a 4-dword cache bound- ary (the stepping threshold), so it issues four sin- gle-dword transfers (the first is a 3-byte transfer). at address 0x10, the chip is aligned to a 4-dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. so, the sym53c895 will issue a burst of 4. at this point, the address is 0x20, and the chip will evalu- ate that it is aligned not only to a 4-dword bound- ary, but also to an 8-dword boundary. it will select the highest, 8, and burst 8 dwords. at this point, the address is 0x40, which is a cache line size boundary. alignment stops, and the burst size from then on is switched to 16. memory move misalignment the sym53c895 will not operate in a cache align- ment mode when a memory move instruction type is issued and the read and write addresses are dif- ferent distances from the nearest cache line bound- ary. for example, if the read address is 0x21f and the write address is 0x42f, and the cache line size is eight (8), the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. the read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. in this situ- ation, the chip will not align to cache boundaries and will operate as an sym53c825. memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is, the master intends to write all bytes within the addressed cache line in a single pci transaction unless inter- rupted by the target. this command requires implementation of the pci cache line size regis-
pci functional description pci cache mode 3-4 sym53c895 data manual ter at address 0ch in pci configuration space. the sym53c895 enables memory write and invali- date cycles when bit 0 in the ctest3 register (wrie) and bit 4 in the pci command register are set. this will cause memory write and invali- date commands to be issued when the following conditions are met: 1. the clse bit, wrie bit, and pci configuration command register, bit 4 must be set. 2. the cache line size register must contain a legal burst size (2, 4, 8, 16, 32, 64, or 128) value and that value must be less than or equal to the dmode burst size. 3. the chip must have enough bytes in the dma fifo to complete at least one full cache line burst. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the sym53c895 will issue a write and invalidate command instead of a memory write command during all pci write cycles. multiple cache line transfers the write and invalidate command can write mul- tiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer will not automatically be the cache line size, but rather a multiple of the cache line size as allowed for in the revision 2.1 of the pci specifi- cation. the logic will select the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being that determined from the dmode burst size bits and ctest 5, bit 2. if multiple cache line size transfers are not desired, the dmode burst size can be set to exactly the cache line size and the chip will only issue single cache line trans- fers. after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the dmode burst size. the most likely scenario of this scheme is that the chip will select the dmode burst size after alignment, and issue bursts of this size. the burst size will, in effect, throttle down toward the end of a long memory move or block move transfer until only the cache line size burst size is left; the chip will finish the transfer with this burst size. latency in accordance with the pci specification, the chip's latency timer will be ignored when issuing a write and invalidate command such that when a latency time-out has occurred, the sym53c895 will continue to transfer up until a cache line boundary. at that point, the chip will relinquish the bus and finish the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it will continue to transfer until the next cache boundary is reached. pci target retry during a write and invalidate transfer, if the target device issues a retry (stop with no trdy, indi- cating that no data was transferred), the sym53c895 will relinquish the bus and immedi- ately try to finish the transfer on another bus own- ership. the chip will issue another write and invalidate command on the next ownership, in accordance with the pci specification. pci target disconnect during a write and invalidate transfer, if the target device issues a disconnect the sym53c895 will relinquish the bus and immediately try to finish the transfer on another bus ownership. the chip will not issue another write and invalidate command on the next ownership unless the address is aligned.
pci functional description pci cache mode sym53c895 data manual 3-5 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended to be used with bulk sequential data transfers where the memory system and the requesting master might gain some perfor- mance advantage by reading up to a cache line boundary rather than a single memory cycle.the read line mode function that exists in the previ- ous sym53c8xx chips has been modified in the sym53c895 to reflect the pci cache line size register specifications. the functionality of the enable read line bit (bit 3 in dmode) has been modified to more resemble the write and invali- date mode in terms of conditions that must be met before a read line command will be issued. how- ever, the read line option will operate exactly like the previous sym53c8xx chips when cache mode has been disabled by a clse bit reset or when certain conditions exist in the chip (explained below). the read line mode is enabled by setting bit 3 in the dmode register. if cache mode is disabled, read line commands will be issued on every read data transfer, except op code fetches, as in previous sym53c8xx chips. if cache mode has been enabled, a read line com- mand will be issued on all read cycles, except op code fetches, when the following conditions have been met: 1. the clse and enable read line bits must be set. 2. the cache line size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value must be less than or equal to the dmode burst size. 3. the number of bytes to be transferred at the time a cache boundary has been reached must be equal to or greater than the dmode burst size. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the chip will issue a read line command instead of a mem- ory read during all pci read cycles. otherwise, it will issue a normal memory read command. memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the sym53c895 supports pci read multiple functionality and will issue read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 of the dmode register (ermp). if cache mode has been enabled, a read multiple command will be issued on all read cycles, except op code fetches, when the fol- lowing conditions have been met: 1. the clse and ermp bits must be set. 2. the cache line size register must contain a legal burst size value (2, 4, 8, 16, 32, 64, or 128) and that value must be less than or equal to the dmode burst size. 3. the number of bytes to be transferred at the time a cache boundary has been reached must be at least twice the full cache line size. 4. the chip must be aligned to a cache line boundary. when these conditions have been met, the chip will issue a read multiple command instead of a memory read during all pci read cycles. burst size selection the read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to be read is a multiple of the cache line size as allowed for in the pci speci- fication, revision 2.1. the logic will select the larg- est multiple of the cache line size based on the
pci functional description configuration registers 3-6 sym53c895 data manual amount of data to transfer, with the maximum allowable burst size being determined from the dmode burst size bits and ctest 5, bit 2. read multiple with read line enabled when both the read multiple and read line modes have been enabled, the read line com- mand will not be issued if the above conditions are met. instead, a read multiple command will be issued, even though the conditions for read line have been met. if the read multiple mode is enabled and the read line mode has been disabled, read multiple com- mands will still be issued if the read multiple con- ditions are met. unsupported pci commands the sym53c895 does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. it will never generate these commands as a master. configuration registers the configuration registers are accessible only by the system bios during pci configuration cycles, and are not available to the user at any time. no other cycles, including scripts operations, can access these registers. the lower 128 bytes hold configuration data while the upper 128 bytes hold the sym53c895 operating registers, which are described in chapter five, operating registers. these registers can be accessed by scripts or the host processor. note: the configuration register descriptions provide general information only to indicate which pci configuration addresses are supported in the sym53c895. for detailed information, refer to the pci specification. table 3-2 shows the pci configuration registers implemented by the sym53c895. addresses 40h through 7fh are not defined. all pci-compliant devices, such as the sym53c895, must support the vendor id, device id, command, and status registers. sup- port of other pci-compliant registers is optional. in the sym53c895, registers that are not sup- ported are not writable and will return all zeroes when read. only those registers and bits that are currently supported by the sym53c895 are described in this chapter. for more detailed infor- mation on pci registers, please see the pci speci- fication.
pci functional description configuration registers sym53c895 data manual 3-7 table 3-2: pci configuration register map 31 16 15 0 device id = 000ch vendor id = 1000h 00h status command 04h class code = 010000h rev id = 0xh 08h not supported header type latency timer cache line size 0ch base address zero (i/o) 1 10h base address one (memory) 2 14h ram base address 3 18h not supported 1ch not supported 20h not supported 24h reserved 28h subsystem id subsystem vendor id 2ch expansion rom base address 4 30h reserved 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch 1 i/o base is supported 2 memory base is supported note: addresses 40h to 7fh are not defined. all unsupported registers are not writable and will return all zeroes when read. reserved registers will also return zeroes when read. 3 this register powers up enabled and can be disabled by pull-down resistors on the mad5 pin 4 if expansion memory is enabled through pull-down resistors on the mad(7-0) bus.
pci functional description configuration registers 3-8 sym53c895 data manual register 00h vendor id read only this field identifies the manufacturer of the device. the symbios vendor id is 1000h. register 02h device id read only this field identifies the particular device. the sym53c895 device id is 0ch. register 04h command read/write the command register, illustrated in figure 3-1, provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the sym53c895 is logi- cally disconnected from the pci bus for all accesses except configuration accesses. in the sym53c895, bits 3, 5, 7, and 9 are not implemented. bits 10 through 15 are reserved. bits 15-9 reserved bit 8 serr/ enable this bit enables the serr/ driver. serr/ is disabled when this bit is clear. the default value of this bit is zero. bit 8 and bit 6 must be set to report address parity errors. bit 7 reserved bit 6 enable parity error response this bit allows the sym53c895 to detect par- ity errors on the pci bus and report these errors to the system. only data parity checking is enabled. the sym53c895 always generates parity for the pci bus. bit 5 reserved bit 4 write and invalidate mode setting this bit will cause memory write and invalidate cycles to be issued on the pci bus after certain conditions have been met. for more information on these conditions, refer to the section "memory write and invalidate command". to enable write and invalidate mode, bit 0 in the ctest3 register (operating register set) must also be set. bit 3 reserved bit 2 enable bus mastering this bit controls the sym53c895s ability to act as a master on the pci bus. a value of zero disables the device from generating pci bus master accesses. a value of one allows the sym53c895 to behave as a bus master. the sym53c895 must be a bus master in order to fetch scripts instructions and transfer data. bit 1 enable memory space this bit controls the sym53c895s response to memory space accesses. a value of zero dis- ables the device response. a value of one allows the sym53c895 to respond to memory space accesses at the address specified by base address one. bit 0 enable i/o space this bit controls the sym53c895s response to i/o space accesses. a value of zero disables the response. a value of one allows the sym53c895 to respond to i/o space accesses at the address specified in base address zero.
pci functional description configuration registers sym53c895 data manual 3-9 register 06h status read/write the status register, illustrated in figure 3-2, is used to record status information for pci bus- related events. in the sym53c895, bits 0 through 4 are reserved and bits 5, 6, 7, and 11 are not implemented by the sym53c895. reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is reset whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 8000h to the register. bit 15 detected parity error (from slave) this bit will be set by the sym53c895 when- ever it detects a data parity error, even if parity error handling is disabled. bit 14 signaled system error this bit is set whenever a device asserts the serr/ signal. bit 13 master abort (from master ) this bit should be set by a master device when- ever its transaction (except for special cycle) is terminated with master abort. all master devices should implement this bit. bit 12 received target abort (from maste r) this bit should be set by a master device when- ever its transaction is terminated with a target abort. all master devices should implement this bit. bit 11 reserved figure 3-1: command register layout 9876543210 serr/ enable not implemented enable parity response not implemented write and invalidate mode not implemented enable bus mastering enable memory space enable i/o space 151413121110 not implemented reserved reserved reserved reserved reserved reserved
pci functional description configuration registers 3-10 sym53c895 data manual bits 10-9 devsel/ timing these bits encode the timing of devsel/. these are encoded as 00b for fast, 01b for medium, 10b for slow with 11b reserved. these bits are read-only and should indicate the slowest time that a device asserts devsel/ for any bus command except configuration read and configuration write. in the sym53c895, 01b is supported. bit 8 data parity reported this bit is set when the following three condi- tions are met: 1) the bus agent asserted perr/ itself or observed perr/ asserted; 2) the agent setting this bit acted as the bus mas- ter for the operation in which the error occurred; 3) the parity error response bit in the command register is set. bits 7-0 reserved register 08h revision id read only this register specifies device and revision identifi- ers. in the sym53c895, the upper nibble will be 0000b. the lower nibble reflects the current revi- sion level of the device. it should have the same value as the chip revision level bits in the ctest3 register. register 09h class code read only this register identifies the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register-level programming interface. the value of this register is 010000h, which indicates a scsi controller. figure 3-2: status register layout 9876543210 data parity reported reserved (not supported) reserved reserved reserved reserved reserved reserved reserved 151413121110 devsel timing 00 = fast, 01 = medium, 10 = slow reserved (not supported) received target abort (from master) detected parity error (from slave) signaled system error received master abort (from master)
pci functional description configuration registers sym53c895 data manual 3-11 register 0ch cache line size read/write this register specifies the system cache line size in units of 32-bit words. cache mode is enabled and disabled by the cache line size enable (clse) bit, bit 7 in the dcntl register. setting this bit causes the sym53c895 to align to cache line boundaries before allowing any bursting, except during memory moves in which the read and write addresses are not aligned to a burst size boundary. for more information on this register, see the sec- tion "support for pci cache line size register". register 0dh latency timer read/write the latency timer register specifies, in units of pci bus clocks, the value of the latency timer for this pci bus master. the sym53c895 supports this timer. all eight bits are writable, allowing latency values of 0-255 pci clocks. use the follow- ing equation to calculate an optimum latency value for the sym53c895: latency = 2 + (burst size * (typical wait states +1)) . values greater than optimum are also acceptable. register 0eh header type read only this register identifies the layout of bytes 10h through 3fh in configuration space and also whether or not the device contains multiple func- tions. the value of this register is 00h. register 10h base address zero (i/o) read/write this 32-bit register has bit zero hardwired to one. bit 1 is reserved and must return a zero on all reads, and the other bits are used to map the device into i/o space. register 14h base address one (memory) read/write this register has bit 0 hardwired to zero. for detailed information on the operation of this regis- ter, refer to the pci specification. register 18h ram base address read/write this register holds the memory base address of the 4 kb internal ram. the user can read this regis- ter through the scratchb register in the operat- ing register set when bit 3 of the ctest2 register is set. register 2c-2d subsystem vendor id read only this register uniquely identifies the vendor manu- facturing the add-in board or subsystem where the sym53c895 resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendors cards, even if the cards use the same pci controller (and therefore have the same vendor id and device id). see the serial eeprom interface section in chapter 2 for infor- mation about the values to load in this register. if the external serial eeprom interface is enabled, this register is automatically loaded at power-up from the eeprom. all of the bits in this register are cleared if serial eeprom access is not enabled.
pci functional description configuration registers 3-12 sym53c895 data manual register 2e-2f subsystem id read only this register uniquely identifies the board or sub- system where the sym53c895 resides. it provides a mechanism for an add-in card vendor to distin- guish between its cards that use the same pci con- troller (and therefore have the same vendor id, device id, and subsystem vendor id). see the serial eeprom interface section in chapter 2 for information about the values to load in this regis- ter. if the external serial eeprom interface is enabled, this register is automatically loaded at powerup from the eeprom. all of the bits in this register are cleared if serial eeprom access is not enabled. in some operating system implementations, bit 15 of this register indicates whether the sym53c895 is being controlled by symbios software or by a dif- ferent device driver. a value of 0 indicates that the symbios software controls the chip, and a value of 1 indicates another driver. register 30h expansion rom base address read/write this four-byte register handles the base address and size information for expansion rom. it func- tions exactly like the base address zero and base address one registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. the expansion rom enable bit, bit 0, is the only bit defined in this register. this bit is used to con- trol whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device can be used with or without an expansion rom depending on the system configuration. to access the external mem- ory interface, the memory space bit in the com- mand register must also be set. the host system detects the size of the external memory by first writing the expansion rom base address register with all ones and then reading back the register. the sym53c895 will respond with zeros in all dont care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kb, this register, when written with ones and read back, will return ones in the upper 17 bits. register 3ch interrupt line read/write this register communicates interrupt line routing information. post software will write the routing information into this register as it initiates and con- figures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin has been connected to. values in this register are specified by system archi- tecture. register 3dh interrupt pin read only this register tells which interrupt pin the device uses. its value is set to 01h, for the inta/ signal.
pci functional description configuration registers sym53c895 data manual 3-13 register 3eh min_gnt read only register 3fh max_lat read only these registers specify the desired settings for latency timer values. min_gnt specifies how long a burst period the device needs. max_lat specifies how often the device needs to gain access to the pci bus. the value specified in these registers is in units of 0.25 microseconds. values of zero indicate that the device has no major requirements for the settings of latency timers. the sym53c895 sets the min_gnt register to 11h and the max_lat reg- ister to 40h.
pci functional description configuration registers 3-14 sym53c895 data manual
signal descriptions voltage capabilities and limitations sym53c895 data manual version 3.0 4-1 chapter 4 signal descriptions this chapter presents the sym53c895 pin config- uration and signal definitions using tables and illustrations. figure 4-1 through figure 4-3 are the pin diagrams for the sym53c895 and figure 4-4 is the functional signal grouping. table 4-1 and table 4-2 list the bga ball assignments by location and signal name. the pin definitions are in table 4-3 through table 4-14. the pin definitions are organized into the following functional groups: system, address/data, interface control, arbitra- tion, error reporting, scsi, and optional inter- face. a slash (/) at the end of the signal name indicates that the active state occurs when the sig- nal is at a low voltage. when the slash is absent, the signal is active at a high voltage. there are four signal type definitions: i input, a standard input-only signal o totem pole output, a standard out- put driver t/s tri-state, a bi-directional, tri-state input/output pin s/t/s sustained tri-state, an active low tri-state signal owned and driven by one and only one agent at a time voltage capabilities and limitations the sym53c895 uses 5 volt biasing pins to allow the device to handle up to 5 volt input voltage to the pci and external memory interface pins. when the sym53c895 is used in a 5 volt pci system, the biasing pins (v5bias(p)) must be supplied with 5 volts; when they are used in a 3 volt only pci environment, they must be supplied with 3.3 volts. the external memory pins (gpio pins and mad7-0) also use 5 volt-tolerant i/o pads. they also have a 5 volt biasing pin (v5bias(m)). these pins should be supplied with 5 volts when using 5 volt memory devices, and with 3.3 volts when using 3.3 volt memory devices. the sclk input is also a 5v-tolerant input pin. the chip cannot operate normally if the 5 volt biasing pins are grounded or disconnected. in addition, the pci biasing pins should not be shorted to the memory bias pin if mixed voltage environments (such as 5 volt pci with 3 volt memories) are possible. all other v dd supplies to the sym53c895 must be set for 3.3 volt opera- tion. in addition, the chip will only drive 3.3 volts on any of the pins when they operate as outputs.
signal descriptions voltage capabilities and limitations 4-2 sym53c895 data manual version 3.0 the decoupling capacitor arrangement shown above is recommended to maximize the benefits of the internal split ground system. capacitor values between 0.01 and 0.1 m f should provide adequate noise isolation. because of the number of high current drivers on the sym53c895, a multi-layer pc board with power and ground planes is required. figure 4-1: sym53c895 pin diagram, 208-pin qfp sym53c895 208 pin quad flat pack 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 nc vdd-pci ad26 v5bias(p) ad25 ad24 c_be3/ vss-pci idsel ad23 ad22 ad21 vdd-pci ad20 ad19 ad18 ad17 vss-pci ad16 c_be2/ frame/ irdy/ vdd-pci trdy devsel vdd-pci stop/ perr/ serr/ par vss-pci c_be1/ ad15 ad14 ad13 vdd-pci ad12 ad11 ad10 ad9 vss-pci ad8 c_be0/ ad7 ad6 vdd-pci ad5 ad4 v5bias(p) ad3 ad2 nc nc nc nc nc nc vss-scsi sd1+ sd1- sd2+ sd2- sd3+ sd3- vdd-scsi sd4+ sd4- sd5+ sd5- vss-scsi sd6+ sd6- sd7+ sd7- vdd-scsi sdp0+ sdp0- vss-scsi rbias+ rbias- vss-scsi satn+ satn- vdd-scsi sbsy+ sbsy- sack+ sack- vss-scsi srst+ srst- smsg+ smsg- vdd-scsi ssel+ ssel- scd+ scd- vss-scsi nc nc nc nc nc 120 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 3.3 v 2.2 k
signal descriptions voltage capabilities and limitations sym53c895 data manual version 3.0 4-3 figure 4-2: sym53c895 pin diagram, 292-ball bga (bottom view) nc nc ssel- ssel+ smsg+ srst+ sack+ sbsy- satn+ rbias- rbias+ sd7- sd6- sd5- nc sd4+ sd3+ sd2+ nc nc srst- sbsy- nc sd7+ sd5+ sd3- sd1- nc nc smsg- sack- satn- sdp0- sd6+ sd4- sd2- nc vss sd1+ nc sreq+ scd- nc nc nc nc nc nc nc sd0- sd8+ vss vdd vss vdd nc nc nc nc sd0+ ad31 nc ad4 nc ad12 perr/ frame/ ad21 ad25 ad27 nc ad6 ad8 ad13 stop/ irdy/ ad20 ad24 ad3 ad7 ad9 ad14 nc nc ad19 c_be3/ nc vss vdd vss serr/ c_be2/ nc nc sio- nc nc nc nc sdp0+ nc nc nc nc sd8- sreq- scd+ nc nc nc vss vdd vss nc irq/ ad1 nc nc nc vdd vss vdd vss nc ad0 ad2 nc nc ad15 nc ad18 i dsel nc ad29 nc v5bias(p) nc ad10 c_be1/ trdy/ ad17 ad23 nc nc nc ad5 c_be0/ ad11 par devsel/ ad16 ad22 v5bias(p) nc sd9- nc sd9+ sio+ sd10+ vdd sd11+ nc vdd-a vss test nc mac/_testout nc mad2 vdd mad4 nc mad7 vss gpio4 vdd-core vdd-core vdd gpio0_fetch nc v5bias(m) nc gpio2 gpio1_master vss-core gpio3 mad6 vss-core mad3 mad5 mad1 nc mad0 nc sclk vss-a diffsens nc sd11- nc sd10- nc nc nc nc sdp1- vdd sd15- sdp1+ sd15+ nc sd14- nc sd14+ nc sd13+ vss sd13- nc sd12+ sd12- test vdd testin nc test nc test test test nc mas0/ vss-core mas1/ vss mwe/ moe/ nc vdd-core big_lit/ vdd-core vdd rst/ nc mce/ nc gnt/ nc clk req/ ad30 nc ad28 ad26 nc vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss a b c d e f g h j k l m n p t u v w y r vss-core 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
signal descriptions voltage capabilities and limitations 4-4 sym53c895 data manual version 3.0 figure 4-3: sym53c895 pin diagram, 292-ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vss nc sd2+ sd3+ sd4+ nc sd5- sd6- sd7- rbias+ rbias- sat n+ sbsy- sack+ srst + smsg+ ssel+ ssel- sd1+ sd2- sd4- sd6+ sdp0- sat n- sack- smsg- nc nc sd1- sd3- sd5+ sd7+ nc sbsy- srst - nc nc nc nc nc nc nc nc nc sdp0+ nc nc nc nc sio- nc vss vdd vss nc nc nc scd+ sreq- sd8- nc ad29 nc idsel ad18 nc ad15 nc nc ad2 nc nc ad23 ad17 trdy/ c_be1/ ad10 nc nc v5bias(p) ad22 ad16 devsel/ par ad11 c_be0/ ad31 vss vdd vss vdd nc nc nc sd0- nc nc nc nc nc nc nc scd- sreq+ sd0+ nc nc nc nc vdd vss vdd vss sd8+ req/ nc nc nc c_be2/ serr/ vss vdd vss ad1 ad30 ad27 ad25 ad21 frame/ perr/ ad12 nc ad4 nc ad28 nc ad24 ad20 irdy/ stop/ ad13 ad8 ad6 nc nc ad26 c_be3/ ad19 nc nc ad14 ad9 ad7 ad3 sdp1- nc nc nc sd15- vdd sd14- nc sd13- vss sd12+ nc testin vdd test nc mas0/ nc mw e/ vss vdd-core nc rst/ vdd gnt/ nc clk nc mce/ nc vdd-core big_lit/ vss-core moe/ mas1/ vss-core test test test nc test sd12- sd13+ nc sd14+ nc sd15+ sdp1+ sio+ sd9+ nc sd9- sd10- nc sd10+ vdd nc sd11+ nc sd11- nc diffsens vss vdd-a nc test vss-a sclk mad0 nc mac/_t estout nc vdd mad2 nc mad1 nc mad4 mad5 mad3 vss mad7 vss-core vdd-core gpio4 gpio3 vss-core vdd vdd-core gpio1_master gpio2 nc gpio0_fetch nc v5bias(m) ir q / ad0 v5bias(p) nc ad5 nc vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss a b c d e f g h j k l m n p t u v w y r mad6
signal descriptions bga listing location sym53c895 data manual version 3.0 4-5 table 4-1: bga listing location a3 sd2+ a4 sd3+ a5 sd4+ a7 sd5- a8 sd6- a9 sd7- a10 rbias+ a11 rbias- a12 satn+ a13 sbsy+ a14 sack+ a15 srst+ a16 smsg+ a17 ssel+ a18 ssel- b2 sd1+ b3 sd1- b4 sd2- b5 sd3- b6 sd4- b7 sd5+ b8 sd6+ b9 sd7+ b10 sdp0- b12 satn- b13 sbsy- b14 sack- b15 srst- b16 smsg- c1 sd0- c10 sdp0+ c17 scd- c19 sreq+ c20 sio- d1 sd0+ d16 scd+ d18 sreq- d19 sd8+ d20 sd8- e1 sdp1- e17 sio+ e19 sd9+ e20 sd9- f1 sd15+ f2 sd15- f3 sdp1+ f19 sd10+ f20 sd10- g1 sd14+/ g2 sd14- g19 sd11+ g20 sd11- h1 sd13+ h2 sd13- h20 diffsens j1 test j2 sd12+ j3 sd12- j19 test j20 sclk k1 test k2 testin k19 mac/ _testout k20 mad0 l1 test l2 test l3 test l19 mad2 l20 mad1 m1 mas1/ m2 mas0/ m18 mad5 m19 mad4 m20 mad3 n2 mwe/ n3 moe/ n19 mad7 n20 mad6 p3 big_lit/ p18 gpio3 p19 gpio4 r1 mce/ r2 rst/ r18 gpio1_maste r r20 gpio2 t1 clk t2 gnt/ t19 gpio0_fetch u1 req/ u2 ad31 u9 c_be2/ u11 serr/ u18 ad1 u20 irq/ v1 ad30 v2 ad29 v3 ad27 v5 ad25 v6 idsel v7 ad21 v8 ad18 v9 frame/ v11 perr/ v12 ad15 v13 ad12 v17 ad4 v18 ad2 v20 ad0 w1 ad28 w5 ad24 w6 ad23 w7 ad20 w8 ad17 w9 irdy/ w10 trdy/ w11 stop w12 c_be1/ w13 ad13 w14 ad10 w15 ad8 w17 ad6 y3 ad26 y5 c_be3/ y6 ad22 y7 ad19 y8 ad16 y10 devsel/ y12 par y13 ad14 y14 ad11 y15 ad9 y16 c_be0/ y17 ad7 y18 ad5 y19 ad3
signal descriptions bga listing by name 4-6 sym53c895 data manual version 3.0 table 4-2: bga listing by name ad0 v20 ad1 u18 ad10 w14 ad11 y14 ad12 v13 ad13 w13 ad14 y13 ad15 v12 ad16 y8 ad17 w8 ad18 v8 ad19 y7 ad2 v18 ad20 w7 ad21 v7 ad22 y6 ad23 w6 ad24 w5 ad25 v5 ad26 y3 ad27 v3 ad28 w1 ad29 v2 ad3 y19 ad30 v1 ad31 u2 ad4 v17 ad5 y18 ad6 w17 ad7 y17 ad8 w15 ad9 y15 big_lit/ p3 c_be0/ y16 c_be1/ w12 c_be2/ u9 c_be3/ y5 clk t1 devsel/ y10 diffsens h20 frame/ v9 gnt/ t2 gpio0_fetch t19 gpio1_master r18 gpio2 r20 gpio3 p18 gpio4 p19 idsel v6 irdy/ w9 irq/ u20 mac/_testout k19 mad0 k20 mad1 l20 mad2 l19 mad3 m20 mad4 m19 mad5 m18 mad6 n20 mad7 n19 mas0/ m2 mas1/ m1 mce/ r1 moe/ n3 mwe/ n2 pa r y 1 2 perr/ v11 rbias+ a10 rbias- a11 req/ u1 rst/ r2 sack+ a14 sack- b14 satn+ a12 satn- b12 sbsy+ a13 sbsy- b13 scd+ d16 scd- c17 sclk j20 sd0+ d1 sd0- c1 sd1+ b2 sd1- b3 sd10+ f19 sd10- f20 sd11+ g19 sd11- g20 sd12+ j2 sd12- j3 sd13+ h1 sd13- h2 sd14+/ g1 sd14- g2 sd15+ f1 sd15- f2 sd2+ a3 sd2- b4 sd3+ a4 sd3- b5 sd4+ a5 sd4- b6 sd5+ b7 sd5- a7 sd6+ b8 sd6- a8 sd7+ b9 sd7- a9 sd8+ d19 sd8- d20 sd9+ e19 sd9- e20 sdp0+ c10 sdp0- b10 sdp1+ f3 sdp1- e1 serr/ u11 sio+ e17 sio- c20 smsg+ a16 smsg- b16 sreq+ c19 sreq- d18 srst+ a15 srst- b15 ssel+ a17 ssel- a18 stop w11 test j1 test j19 test k1 test l1 test l2 test l3 testin k2 trdy/ w10
signal descriptions bga listing by name sym53c895 data manual version 3.0 4-7 figure 4-4: sym53c895 functional signal grouping clk rst ad31-0 c_be/3-0 par frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ serr/ perr/ bsy+/- rst+/- sel+/- req+/- ack+/- sdp+(1-0) sd+(15-0) sclk sd-(15-0) sdp-(1-0) sctrl+/- gpio0 gpio1 gpio2 gpio3 mac/_testout irq/ big_lit/ diffsens testin gpio4 mwe/ mce/ moe/ mas0/ mas1/ mad7-0 address and data system interface control arbitration error reporting scsi additional interface device local memory bus and control serial eeprom interface
signal descriptions internal pull-ups on sym53c895 pins 4-8 sym53c895 data manual version 3.0 internal pull-ups on sym53c895 pins several pins on the sym53c895 use internal pull-ups. table 4-3 describes the conditions under which these pull-ups are enabled or disabled. table 4-3: sym53c895 internal pull-ups pin name pull-up current conditions for pull-up pci pins except irq, clk and rst 25 m a pull-ups enabled when and-tree mode is enabled by driving testin low irq 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or when the irq mode bit (bit 3 of dcntl (3bh)) is cleared* rst, clk n/a no pull-up mad (7-0) n/a no pull-ups mas/(1-0), mce/, moe/, mwe/ 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or if the zmode bit (bit7 of ctest4 (21h)) is set gpio(4-0) n/a no pull-ups scsi pads and sclk n/a no pull-ups rbias+, rbias- n/a no pull-ups diffsens n/a no pull-up, analog input protect pin big_lit/ 25 m a pull-up enabled when and-tree mode is enabled by driving testin low mac/_testout n/a no pull-up, output only test pin 82 25 m a pull-up all the time test pin 177 25 m a pull-up all the time testin 25 m a pull-up all the time test pins 180, 181, 182, 183 25 m a pull-up enabled when and-tree mode is enabled by driving testin low or if a hidden bit (bit7 of stest0 (4ch)) is cleared (default = cleared) *when bit 3 of dcntl is set, the pad becomes a totem pole output pad and will drive both high and low.
signal descriptions pin descriptions sym53c895 data manual version 3.0 4-9 pin descriptions table 4-4: sym53c895 power and ground pins symbol pin no. ball no. description v ss-pci* 8, 18, 31, 41, 56, 193, 200 (pins) power supplies to the pci i/o pins v dd-pci* 2, 13, 23, 26, 36, 46, 60, 197 (pins) power supplies to the pci i/o pins v ss-scsi* 91, 110, 120, 128, 131, 139, 151, 169 (pins) power supplies to the scsi bus i/o pins v dd-scsi* 86, 96, 115, 125, 134, 144, 164, 174 (pins) power supplies to the scsi bus i/o pins v ss-io* 78, 179 power supplies to the external memory interface v dd-io* 73, 81, 184 power supplies to the external memory interface v ss-core 68, 187 n18, p20, n1, m3 power supplies to the internal logic core v dd-core 64, 190 p17, r19, p2, p1 power supplies to the internal logic core v ss-a 83 j18 power pins used by analog circuitry v dd-a 85 h19 power pins used by analog circuitry note: the v dd-a pin is sensitive to noise above 90 mv at fre- quencies above 140 mhz. refer to ** for information on filter- ing schemes to protect this pin and the phase locked loop from high frequency noise. v5bias(p) 4, 49 w18, y4 5 volt biasing pins for pci signals. these pins must be supplied with 5v in a 5v pci environment, or 3.3v when used in a 3v only pci environment. v5bias(m) 62 t20 5 volt biasing pin for external memory interface signals. when using 5v memory devices, this pin should be supplied with 5v. when using 3.3v memory devices, it should be supplied with 3.3v. all v dd pins must be supplied 3.3 volts. the sym53c895 output signals drive 3.3v . *in the bga option, v dd-scsi , v dd-pci , and v dd-io are connected together and v ss-scsi , v ss-pci and v ss-io are connected together at package. **optional ground pins
signal descriptions sym53c895 power and ground pins 4-10 sym53c895 data manual version 3.0 note: if you apply separate power supplies to the v dd-io and v dd-core pins in a chip testing environment, either power up the pins simultaneously or power up v dd-core before v dd-io. the v dd-io pins must always power down before v dd-core . v ss * a1, d4, h4, n4, ur, d8, h8**, j8, k8**, l8**, m8**, n8**, u8, h9**, j9**, k9**, l9**, m9**, n9**, h10**, j10**, k10**, l10**, m10**, n10**, h11**, j11**, k11**, l11**, m11**, n11**, h12**, j12**, k12**, l12**, m12**, n12**, d13, h13**, j13**, k13**, l13**, m13**, n13, u13, d17, h17, n17, u17 power pins v dd * f4, k4, r4, d6, u6, d11, u10, d15, u15, f17, l17, r17 power supplies table 4-4: sym53c895 power and ground pins (continued) symbol pin no. ball no. description all v dd pins must be supplied 3.3 volts. the sym53c895 output signals drive 3.3v . *in the bga option, v dd-scsi , v dd-pci , and v dd-io are connected together and v ss-scsi , v ss-pci and v ss-io are connected together at package. **optional ground pins
signal descriptions system pins sym53c895 data manual version 3.0 4-11 table 4-5: system pins symbol pin no. ball no. type description clk 195 t1 i clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are defined with respect to this edge. this clock can optionally be used as the scsi core clock; however, the sym53c895 will not be able to achieve fast scsi-2 (or faster) transfer rates. rst/ 194 r2 i reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device. table 4-6: address and data pins symbol pin no. ball no. type description ad(31-0) 199, 201- 204, 3, 5, 6, 10-12, 14- 17, 19, 33- 35, 37-40, 42, 44, 45, 47, 48, 50, 51, 57, 58 u2, v1, v2, w1, v3, y3, v5, w5, w6, y6, v7, w7, y7, v8, w8, y8, v12, y13, w13, v13, y14, w14, y15, w15, y17, w17, v17, y19, v18, u18, v20 t/s physical longword address and data are multiplexed on the same pci pins. during the first clock of a transaction, ad(31-0) contain a physical address. during subsequent clocks, ad(31-0) contain data. a bus transaction consists of an address phase, followed by one or more data phases. pci supports both read and write bursts. ad(7-0) define the least significant byte, and ad(31-24) define the most significant byte.
signal descriptions interface control pins 4-12 sym53c895 data manual version 3.0 c_be(3-0)/ 7, 20, 32, 43 y5, u9, w12, y16 t/s bus commands and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be(3-0)/ define the bus command. during the data phase, c_be(3-0)/ are used as byte enables. the byte enables deter- mine which byte lanes carry meaningful data. c_be(0)/ applies to byte 0, and c_be(3)/ applies to byte 3. par 30 y12 t/s parity is the even parity bit that protects the ad(31-0) and c_be(3-0)/ lines. during address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered. table 4-7: interface control pins symbol pin no. ball no. type description frame/ 21 v9 s/t/s cycle frame is driven by the current master to indicate the begin- ning and duration of an access. frame/ is asserted to indicate a bus transaction is beginning. while frame/ is asserted, data transfers continue. when frame/ is deasserted, the transaction is in the final data phase or the bus is idle. trdy/ 24 w10 s/t/s target ready indicates the selected devices ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad(31-0). during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. irdy/ 22 w9 s/t/s initiator ready indicates the bus masters ability to complete the current data phase of the transaction. this signal is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad(31-0). during a read, it indicates the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 27 w11 s/t/s stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 25 y10 s/t/s device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 9 v6 i initialization device select is used as a chip select in place of the upper 24 address lines during configuration read and write transac- tions. table 4-6: address and data pins (continued) symbol pin no. ball no. type description
signal descriptions arbitration pins sym53c895 data manual version 3.0 4-13 table 4-8: arbitration pins symbol pin no. ball no. type description req/ 198 u1 o request indicates to the arbiter that this agent desires use of the pci bus. this is a point-to-point signal. every master has its own req/. gnt/ 196 t2 i grant indicates to the agent that access to the pci bus has been granted. this is a point-to-point signal. every master has its own gnt/. table 4-9: error reporting pins symbol pin no. ball no. type description perr/ 28 v11 s/t/s parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corrup- tions. serr/ 29 u11 o this open drain output pin reports address parity errors. on detec- tion of a perr/ pulse, the central resource may generate a non- maskable interrupt to the host cpu, which often implies the system will be unable to continue operation once error processing is com- plete.
signal descriptions scsi pins, lvdlink mode 4-14 sym53c895 data manual version 3.0 table 4-10: scsi pins, lvdlink mode symbol pin no. ball no. type description sclk 80 j20 i sclk derives all scsi-related timings. the speed of this clock is determined by the applications requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. for ultra2 scsi operation, this pin must be connected to an external 40 mhz oscillator, used with the internal clock quadru- pler. sd-(15-0), sdp-(1-0) 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 f2, g2, h2, j3, g20, f20, e20, d20, a9, a8, a7, b6, b5, b4, b3, c1, e1, b10 i/o negative half of lvdlink signal pair for scsi data lines. scsi data includes the following data lines and parity signals: sd(15- 0)/(16-bit scsi data bus), and sdp(1-0)/(scsi data parity bits). sd+(15-0), sdp+(1-0) 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 f1, g1, h1, j2, g19, f19, e19, d19, b9, b8, b7, a5, a4, a3, b2, d1, f3, c10 i/o positive half of lvdlink signal pair for scsi data lines. sctrl- 111, 97, 116, 99, 121, 123, 126, 118, 113 c17, c20, b16, d18, b14, b13, b12, b15, a18 i/o negative half of lvdlink signal pair for scsi control, which includes the following signals: scd-scsi phase line, command/data sio-scsi phase line, input/output smsg-scsi phase line, message sreq-data handshake signal from target device sack-data handshake signal from initiator device sbsy-scsi bus arbitration signal, busy satn-scsi attention, the initiator is requesting a message out phase srst-scsi bus reset ssel-scsi bus arbitration signal, select device
signal descriptions scsi pins, lvdlink mode sym53c895 data manual version 3.0 4-15 sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 d16, e17, a16, c19, a14, a13, a12, a15, a17 i/o positive half of lvdlink signal pair for scsi control, which includes the following signals: scd+scsi phase line, command/data sio+scsi phase line, input/output smsg+scsi phase line, message sreq+data handshake signal from target device sack+data handshake signal from initiator device sbsy+scsi bus arbitration signal, busy satn+scsi attention, the initiator is requesting a message out phase srst+scsi bus reset ssel+scsi bus arbitration signal, select device rbias+, rbias- 130, 129 a10, a11 i used to connect an external resistor to generate the bias current used by lvdlink pads. diffsens 84 h20 i the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or high-power differential device. the result is displayed in stest4 bits 7-6. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs will be tri-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3 volts. table 4-10: scsi pins, lvdlink mode (continued) symbol pin no. ball no. type description
signal descriptions scsi pins, single-ended mode 4-16 sym53c895 data manual version 3.0 table 4-11: scsi pins, single-ended mode symbol pin no. ball no. type description sclk 80 j20 i sclk derives all scsi-related timings. the speed of this clock is determined by the applications requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd-(15-0), sdp-(1-0) 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 f2, g2, h2, j3, g20, f20, e20, d20, a9, a8, a7, b6, b5, b4, b3, c1, e1, b10 i/o scsi data includes the following data lines and parity signals: sd(15-0)/(16-bit scsi data bus), and sdp(1-0)/(scsi data par- ity bits). sd+(15-0), sdp+(1-0) 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 f1, g1, h1, j2, g19, f19, e19, d19, b9, b8, b7, a5, a4, a3, b2, d1, f3, c10 o these signals will drive 0 volts. sctrl- 111, 97, 116, 99, 121, 123, 126, 118, 113 c17, c20, b16, d18, b14, b13, b12, b15, a18 i/o scsi control, includes the following signals: scd-scsi phase line, command/data sio-scsi phase line, input/output smsg-scsi phase line, message sreq-data handshake signal from target device sack-data handshake signal from initiator device sbsy-scsi bus arbitration signal, busy satn-scsi attention, the initiator is requesting a message out phase srst-scsi bus reset ssel-scsi bus arbitration signal, select device
signal descriptions scsi pins, high voltage differential mode sym53c895 data manual version 3.0 4-17 sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 d16, e17, a16, c19, a14, a13, a12, a15, a17 o these pins drive 0 volts. diffsens 84 h20 i the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or high-power differential device. the result is displayed in stest4 bits 7-6. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs will be tri-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3 volts. table 4-12: scsi pins, high voltage differential mode sclk 80 i sclk derives all scsi-related timings. the speed of this clock is determined by the applications requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd-(15-0) sdp-(1-0) 167, 170, 172, 175, 87, 89, 92, 94, 135, 137, 140, 142, 145, 147, 149, 162, 165, 132 i/o scsi data lines. scsi data includes the following data lines and parity signals: sd(15-0)/(16-bit scsi data bus), and sdp(1-0)/ (scsi data parity bits). sd+(15-0) sdp+(1-0) 168, 171, 173, 176, 88, 90, 93, 95, 136, 138, 141, 143, 146, 148, 150, 163, 166, 133 o driver direction control for scsi data lines. table 4-11: scsi pins, single-ended mode (continued) symbol pin no. ball no. type description
signal descriptions scsi pins, high voltage differential mode 4-18 sym53c895 data manual version 3.0 sctrl- 111, 97, 116, 99, 121, 123, 126, 118, 113 i/o scsi control includes the following signals: scd- scsi phase line, command/data sio- scsi phase line, input/output smsg- scsi phase line, message sreq- data handshake signal from target device sack- data handshake signal from initiator device sbsy- scsi bus arbitration signal, busy satn- scsi attention, the initiator is requesting a message out phase srst- scsi bus reset ssel- scsi bus arbitration signal, select device sctrl+ 112, 98, 117, 100, 122, 124, 127, 119, 114 o driver direction control for the external transceivers, which includes the following signals: sreq+ data handshake signal from target device sack+ data handshake signal from initiator device sbsy+ scsi bus arbitration signal, busy srst+ scsi bus reset ssel+ scsi bus arbitration signal, select device note: for high voltage differential operation, scd+, sio+, smsg+, and satn+ are not used. diffsens 84 1 the differential sense pin detects the voltage level of an incoming scsi signal to determine whether it is from a single-ended, lvd, or high-power differential device. the result is displayed in stest4 bits 7-6. when external differential transceivers are used and a high level is detected on this pin, all chip scsi outputs will be tri-stated to avoid damage to the transceivers. this pin should be connected to the diffsens signal on the scsi cable. note: the maximum voltage allowed to this pin is 3.3 volts. table 4-12: scsi pins, high voltage differential mode (continued)
signal descriptions additional pins sym53c895 data manual version 3.0 4-19 table 4-13: additional pins testin 178 i test in. when this pin is driven low, the sym53c895 connects all inputs and outputs to an and tree. the scsi control signals and data lines are not connected to the and tree. the output of the and tree is connected to the testout pin. this allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached. when the testin pin is driven low, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals will be tri- stated, and the mac/_testout pin will be enabled. connectiv- ity can be tested by driving one of the sym53c895 pins low. the mac/_testout pin should respond by also driving low. gpio0_ fetch/ 61 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the next bus request will be for an op code fetch. this pin powers up as a general purpose input. this pin has two specific purposes in the symbios software. the software uses it to toggle scsi device leds, turning on the led whenever the sym53c895 is on the scsi bus. the software drives this pin low to turn on the led, or drives it high to turn off the led. this signal can also be used as data i/o for serial eeprom access. in this case, it is used with the gpio1 pin, which serves as a clock. gpio1_ master/ 63 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the sym53c895 is bus master. this pin powers up as a general purpose input. symbios software supports use of this signal in serial eeprom applications, when enabled, in combination with the gpio0 pin. when this signal is used as a clock for serial eeprom access, the gpio0 pin serves as data. gpio4-2 67-65 i/o general purpose i/o pins. gpio4 powers up as an output. symbios software also supports use of this signal as the enable line for v pp , the 12 volt power supply to the external flash memory interface. gpio3-2 power up as inputs. mac/_ testout 79 t/s memory access control. this pin can be programmed to indicate local or system memory accesses (non-pci applications). it is also used to test the connectivity of the sym53c895 signals using and tree scheme. the mac/_testout pin is only driven as the test out function when the testin/ pin is driven low. irq/ 59 o interrupt. this signal, when asserted low, indicates that an inter- rupting condition has occurred and that service is required from the host cpu. the output drive of this pin is programmed as either open drain with an internal weak pull-up or, optionally, as a totem pole driver. refer to the description of dcntl register, bit 3, for additional information.
signal descriptions additional pins 4-20 sym53c895 data manual version 3.0 big_lit/ 192 i big_little endian select. when this pin is driven low, the sym53c895 will route the first byte of an aligned scsi to pci transfer to byte lane zero of the pci bus and subsequent bytes received will be routed to ascending lanes. an aligned pci to scsi transfer will route pci byte lane zero onto the scsi bus first, and transfer ascending byte lanes in order. when this pin is driven high, the sym53c895 will route the first byte of an aligned scsi- to-pci transfer to byte lane three of the pci bus and subsequent bytes received will be routed to descending lanes. an aligned pci- to-scsi transfer will route pci byte lane three onto the scsi bus first and transfer descending byte lanes in order. this mode of operation also applies to the external memory interface. when this pin is driven in little endian mode and the chip is performing a read from external memory, the byte of data accessed at location 00000h will be routed to pci byte lane zero and the data accessed at location 00003h will be routed to pci byte lane three. when the chip is performing a write to flash memory, pci byte lane zero will be routed to location 00000h and ascending byte lanes will be routed to subsequent memory locations. when this pin is driven in big endian mode and the chip is performing a read from external memory, the byte of data accessed at location 00000h will be routed to pci byte lane three and the data accessed at location 00003h will be routed to byte lane zero. when the chip is perform- ing a write to flash memory, pci byte lane three will be routed to location 00000h and descending byte lanes will be routed to subse- quent memory locations. test pins 82, 177, 180, 181, 182, 183 i/o test pins are used by symbios for diagnostic testing. these pins should not be used in actual system design; they must be left float- ing or pulled high. table 4-13: additional pins (continued)
signal descriptions external memory interface pins sym53c895 data manual version 3.0 4-21 table 4-14: external memory interface pins mas0/ 186 o memory address strobe 0. this pin latches in the least significant address byte of an external eprom or flash memory. since the sym53c895 moves addresses eight bits at a time, this pin con- nects to the clock of an external bank of flip-flops which are used to assemble up to a 20-bit address for the external memory. mas/1 185 o memory address strobe 1. this pin latches in the address byte corresponding to address bits 15-8 of an external eprom or flash memory. since the sym53c895 moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which assemble up to a 20-bit address for the external memory. mad7-0 see individual pin descriptions the mad7-0 pins form the memory address/data bus. this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eprom or flash memory. this bus will put out the most significant byte first and finish with the least significant byte. it is also used to write data to a flash memory or read data into the chip from external eprom or flash memory. the eight signals on the mad bus have specific functions. please refer to the individual pin description below. mad7-6 69-70 i/o mad7-6 enable different power-up options related to the external serial eeprom interface. these options are programmed by con- necting a 4.7 k w resistor between the appropriate mad pin and v ss . for more information, refer to the serial eeprom interface section in chapter 2 and the subsystem id/subsystem vendor id register descriptions in chapter 3. mad5 71 i/o the mad5 pin enables/disables the 4k internal ram on the sym53c895. pull this pin high to enable the scripts ram (default), and pull it low (with a 4 k w resistor) to disable the scripts ram. mad(7-6) result 00 vendor specific information is automatically downloaded from the serial eeprom through bpio0 (clock) and bpio1 (data) and loaded into pci configuration registers 2c-2fh. 01 reserved. 10 no download is performed, however, the pci configuration registers 2c-2fh are now writable. 11 vendor-specific information is automatically downloaded from the eeprom through gpio0 (data) and gpio1 (clock) and loaded into pci configuration registers 2c-2fh.
signal descriptions external memory interface pins 4-22 sym53c895 data manual version 3.0 mad4 72 i/o the mad4 pin is reserved and should be pulled up. it may be used by symbios in future devices. mad3-1 74-76 i/o the mad(3-1) pins set the size of the external parallel rom device attached to the sym53c895. encoding for these pins is listed below (0 indicates a pull-down resistor is attached, 1 indi- cates a pull-up resistor is attached). mad0 77 i/o mad0 is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time. this accommodates a 200 ns memory device on the mad bus. when the pin is high, a 150 ns or faster memory device must be used. mwe/ 188 o memory write enable. this pin is used as a write the enable signal to an external flash memory. moe/ 189 o memory output enable. this pin is used as an output enable sig- nal to an external eprom or flash memory during read opera- tions. mce/ 191 o memory chip enable. this pin is used as a chip enable signal to an external eprom or flash memory device. table 4-14: external memory interface pins (continued) mad(3-1) available memory space 000 16 kb 001 32 kb 010 64 kb 011 128 kb 100 256 kb 101 512 kb 110 1024 kb 111 no external memory present
operating registers sym53c895 data manual 5-1 chapter 5 operating registers this section contains descriptions of all sym53c895 operating registers. table 5-1 sum- marizes the sym53c895 operating register set. figure 5-1, the register map, lists registers by oper- ating and configuration addresses. the terms set and assert refer to bits that are programmed to a binary one. similarly, the terms deassert, clear and reset refer to bits that are programmed to a binary zero. reserved bit functions may be changed at any time; these bits should never be set by the us- er. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by set- ting the bit. the bottom row of every register dia- gram shows the default register values, which are enabled after the chip is powered on or reset. note: the only register that the host cpu can access while the sym53c895 is executing scripts is the istat register; attempts to access other registers will interfere with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. note: the sym53c895 cannot fetch scripts instructions from the operating register space. instructions must be fetched from system memory or the internal scripts ram. table 5-1: operating register addresses and descriptions memory or i/o address offset pci configuration address read/write label description page no. 00 80 r/w scntl0 scsi control 0 5-5 01 81 r/w scntl1 scsi control 1 5-7 02 82 r/w scntl2 scsi control 2 5-9 03 83 r/w scntl3 scsi control 3 5-10 04 84 r/w scid scsi chip id 5-12 05 85 r/w sxfer scsi transfer 5-12 06 86 r/w sdid scsi destination id 5-15 07 87 r/w gpreg general purpose bits 5-15 08 88 r/w sfbr scsi first byte received 5-16 09 89 r/w socl scsi output control latch 5-16 0a 8a r ssid scsi selector id 5-17 0b 8b r/w sbcl scsi bus control lines 5-17 0c 8c r dstat dma status 5-18 0d 8d r sstat0 scsi status 0 5-19 0e 8e r sstat1 scsi status 1 5-20
operating registers 5-2 sym53c895 data manual 0f 8f r sstat2 scsi status 2 5-21 10-13 90-93 r/w dsa data structure address 5-22 14 94 r/w istat interrupt status 5-23 18 98 r/w ctest0 reserved 5-25 19 99 r/w ctest1 chip test 1 5-25 1a 9a r ctest2 chip test 2 5-26 1b 9b r ctest3 chip test 3 5-27 1c-1f 9c-9f r/w temp temporary register 5-28 20 a0 r/w dfifo dma fifo 5-28 21 a1 r/w ctest4 chip test 4 5-29 22 a2 r/w ctest5 chip test 5 5-30 23 a3 r/w ctest6 chip test 6 5-31 24-26 a4-a6 r/w dbc dma byte counter 5-32 27 a7 r/w dcmd dma command 5-32 28-2b a8-ab r/w dnad dma next address for data 5-33 2c-2f ac-af r/w dsp dma scripts pointer 5-33 30-33 b0-b3 r/w dsps dma scripts pointer save 5-34 34-37 b4-b7 r/w scratcha general purpose scratch pad a 5-34 38 b8 r/w dmode dma mode 5-35 39 b9 r/w dien dma interrupt enable 5-36 3a ba r/w sbr scratch byte register 5-37 3b bb r/w dcntl dma control 5-37 3c-3f bc-bf r adder sum output of internal adder 5-38 40 c0 r/w sien0 scsi interrupt enable 0 5-39 41 c1 r/w sien1 scsi interrupt enable 1 5-40 42 c2 r sist0 scsi interrupt status 0 5-41 43 c3 r sist1 scsi interrupt status 1 5-42 44 c4 r/w slpar scsi longitudinal parity 5-43 45 c5 r swide scsi wide residue data 5-44 46 c6 r/w macntl memory access control 5-45 47 c7 r/w gpcntl general purpose control 5-45 48 c8 r/w stime0 scsi timer 0 5-46 49 c9 r/w stime1 scsi timer 1 5-47 4a ca r/w respid0 response id 0 5-48 table 5-1: operating register addresses and descriptions (continued) memory or i/o address offset pci configuration address read/write label description page no.
operating registers sym53c895 data manual 5-3 4b cb r/w respid1 response id 1 5-48 4c cc r stest0 scsi test 0 5-49 4d cd r stest1 scsi test 1 5-50 4e ce r/w stest2 scsi test 2 5-51 4f cf r/w stest3 scsi test 3 5-52 50-51 d0-d1 r sidl scsi input data latch 5-54 52 d2 r stest4 scsi test 4 5-54 53 d3 reserved 54-55 d4-d5 r/w sodl scsi output data latch 5-55 56-57 d6-d7 reserved 58-59 d8-d9 r sbdl scsi bus data lines 5-55 5a-5b da-db reserved 5c-5f dc-df r/w scratchb general purpose scratch pad b 5-56 60-7f e0-ff r/w scratchc-j general purpose scratch pad c-j 5-56 table 5-1: operating register addresses and descriptions (continued) memory or i/o address offset pci configuration address read/write label description page no.
operating registers 5-4 sym53c895 data manual mem i/o config scntl3 scntl2 scntl1 scntl0 00 80 gpreg sdid sxfer scid 04 84 sbcl ssid socl sfbr 08 88 sstat2 sstat1 sstat0 dstat 0c 8c dsa 10 90 reserved istat 14 94 ctest3 ctest2 ctest1 reserved 18 98 temp 1c 9c ctest6 ctest5 ctest4 dfifo 20 a0 dcmd dbc 24 a4 dnad 28 a8 dsp 2c ac dsps 30 b0 scratch a 34 b4 dcntl sbr dien dmode 38 b8 adder 3c bc sist1 sist0 sien1 sien0 40 c0 gpcntl macntl swide slpar 44 c4 respid1 respid0 stime1 stime0 48 c8 stest3 stest2 stest1 stest0 4c cc reserved stest4 sidl 50 d0 reserved sodl 54 d4 reserved sbdl 58 d8 scratch b 5c dc scratchc 60 e0 scratchd 64 e4 scratche 68 e8 scratchf 6c ec scratchg 70 f0 scratchh 74 f4 scratchi 78 f8 scratchj 7f ff figure 5-1: sym53c895 register address map
operating registers sym53c895 data manual 5-5 register 00 (80) scsi control zero (scntl0) read/write bit 7 arb1 (arbitration mode bit 1) bit 6 arb0 (arbitration mode bit 0) simple arbitration 1. the sym53c895 waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scid register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the sym53c895 will deassert sbsy/, deassert its id and set the lost arbitration bit (bit 3) in the sstat0 register. 3. after an arbitration delay, the cpu should read the sbdl register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the sym53c895 has won arbitration. 4. once the sym53c895 has won arbitration, ssel/ must be asserted via the socl for a bus clear plus a bus settle delay (1.2 m s) before a low-level selection can be performed. full arbitration, selection/reselection 1. the sym53c895 waits for a bus free condition. 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scid register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the sym53c895 detects a higher priority id, the sym53c895 will deassert bsy, deassert its id, and wait until the next bus free state to try arbitration again. 4. the sym53c895 repeats arbitration until it wins control of the scsi bus. when it has won, the won arbitration bit is set in the sstat0 register, bit 2. 5. the sym53c895 performs selection by asserting the following onto the scsi bus: ssel/, the targets id (stored in the sdid register), and the sym53c895s id (stored in the scid register). 6. after a selection is complete, the function complete bit is set in the sist0 register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the sist1 register, bit 2. bit 5 start (start sequence) when this bit is set, the sym53c895 will start the arbitration sequence indicated by the arbi- tration mode bits. the start sequence bit is accessed directly in low-level mode; during scsi scripts operations, this bit is con- trolled by the scripts processor. an arbitra- tion sequence should not be started if the connected (con) bit in the scntl1 register, bit 4, indicates that the sym53c895 is already connected to the scsi bus. this bit is auto- matically cleared when the arbitration sequence is complete. if a sequence is aborted, bit 4 in the scntl1 register should be checked to verify that the sym53c895 did not connect to the scsi bus. arb1 arb0 start watn epc res aap trg 76543210 default>>> 11000x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection
operating registers 5-6 sym53c895 data manual bit 4 watn (select with satn/ on a start sequence) when this bit is set and the sym53c895 is in initiator mode, the satn/ signal will be asserted during sym53c895 selection of a scsi target device. this is to inform the target that the sym53c895 has a message to send. if a selection time-out occurs while attempting to select a target device, satn/ will be deasserted at the same time ssel/ is deasserted. when this bit is clear, the satn/ signal will not be asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but it may be set manu- ally in low-level mode. bit 3 epc (enable parity checking) when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either initiator or target mode. parity is also checked as data goes from the scsi fifo to the dma fifo. if a parity error is detected, bit 0 of the sist0 register is set and an interrupt may be generated. if the sym53c895 is operating in initiator mode and a parity error is detected, satn/ can optionally be asserted, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. bit 2 reserved bit 1 aap (assert satn/ on parity error) when this bit is set, the sym53c895 automat- ically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in ini- tiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. the enable par- ity checking bit must also be set for the sym53c895 to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ will not be automatically asserted on the scsi bus when a parity error is received. bit 0 trg (target mode) this bit determines the default operating mode of the sym53c895. the user must manually set target or initiator mode. this can be done using the scripts language (set target or clear target). when this bit is set, the chip is a target device by default. when this bit is cleared, the sym53c895 is an initiator device by default. caution: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes.
operating registers sym53c895 data manual 5-7 register 01 (81) scsi control one (scntl1) read/write bit 7 exc (extra clock cycle of data setup) when this bit is set, an extra clock period of data setup is added to each scsi send data transfer. the extra data setup time can provide additional system design margin, though it will affect the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. bit 6 adb (assert scsi data bus) when this bit is set, the sym53c895 drives the contents of the scsi output data latch register (sodl) onto the scsi data bus. when the sym53c895 is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the sym53c895 is a target, the scsi i/o signal must be active for the sodl contents to be asserted onto the scsi bus. the contents of the sodl register can be asserted at any time, even before the sym53c895 is connected to the scsi bus. this bit should be cleared when executing scsi scripts. it is normally used only for diagnostics testing or operation in low- level mode. bit 5 dhp (disable halt on parity error or atn) (target only) the dhp bit is only defined for target mode. when this bit is cleared, the sym53c895 halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is received in the middle of a data transfer, the sym53c895 may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the sym53c895 transfers data until there are no outstanding synchronous offsets. if the sym53c895 is receiving data, any data resid- ing in the dma fifo is sent to memory before halting. when this bit is set, the sym53c895 does not halt the scsi transfer when satn/ or a parity error is received. bit 4 con (connected) this bit is automatically set any time the sym53c895 is connected to the scsi bus as an initiator or as a target. it is set after the sym53c895 successfully completes arbitra- tion or when it has responded to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operat- ing in low-level mode. when this bit is clear, the sym53c895 is not connected to the scsi bus. the cpu can force a connected or discon- nected condition by setting or clearing this bit. this feature would be used primarily during loopback mode. bit 3 rst (assert scsi rst/ signal) setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 m s minimum assertion time defined in the scsi specification must be timed out by the controlling microprocessor or a scripts loop. bit 2 aesp (assert even scsi parity (force bad parity)) when this bit is set, the sym53c895 asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the sym53c895. if parity checking is enabled, then the sym53c895 checks data received for odd parity. this bit is used for diagnostic test- ing and should be clear for normal operation. it can be used to generate parity errors to test error handling functions. exc adb dhp con rst aesp iarb sst 76543210 default>>> 00000000
operating registers 5-8 sym53c895 data manual bit 1 iarb (immediate arbitration) setting this bit causes the scsi core to imme- diately begin arbitration once a bus free phase is detected following an expected scsi discon- nect. this bit is useful for multi-threaded applications. the arb1-0 bits in scntl0 should be set for full arbitration and selection before setting this bit. arbitration will be re-tried until won. at that point, the sym53c895 will hold bsy and sel asserted, and wait for a select or reselect sequence to be requested. the immediate arbitration bit will be reset automatically when the selection or reselection sequence is com- pleted, or times out. an unexpected disconnect condition will clear iarb without attempting arbitration. see the scsi disconnect unexpected bit (scntl2, bit 7) for more information on expected versus unexpected disconnects. an immediate arbitration sequence can be aborted. first, the abort bit in the istat reg- ister should be set. then one of two things will eventually happen: 1. the won arbitration bit (sstat0 bit 2) will be set. in this case, the immediate arbitration bit needs to be reset. this will complete the abort sequence and disconnect the sym53c895 from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, a low-level selection may be performed instead. 2. the abort will complete because the sym53c895 loses arbitration. this can be detected by the immediate arbitration bit being cleared. the lost arbitration bit (sstat0 bit 3) should not be used to detect this condition. no further action needs to be taken in this case. bit 0 sst (start scsi transfer) this bit is automatically set during scripts execution, and should not be used. it causes the scsi core to begin a scsi transfer, includ- ing sreq/sack handshaking. the determi- nation of whether the transfer is a send or receive is made according to the value written to the i/o bit in socl. this bit is self-reset- ting. it should not be set for low-level opera- tion. caution: writing to this register while not connected may cause the loss of a selection/reselection by resetting the connected bit.
operating registers sym53c895 data manual 5-9 register 02 (82) scsi control two (scntl2) read/write bit 7 sdu (scsi disconnect unexpected) this bit is valid in initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error will be generated (see the unexpected disconnect bit in the sist0 register, bit 2). during normal scripts mode operation, this bit is set auto- matically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be reset with a register write (move 0x00 to scntl2) before the scsi core expects a disconnect to occur, nor- mally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. bit 6 chm (chained mode) this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode is primarily used to transfer consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behavior. when this bit is set and a data transfer ends on an odd byte boundary, the sym53c895 will store the last byte in the scsi wide residue data reg- ister during a receive operation, or in the scsi output data latch register during a send oper- ation. this byte will be combined with the first byte from the subsequent transfer so that a wide transfer can be completed. for more information, see the chained mode section in chapter 2, functional description. bit 5 slpmd (slpar mode bit) if this bit is clear, the slpar register functions like the sym53c825. if this bit is set, the slpar register reflects the high or low byte of the slpar word, depending on the state of scntl2 bit 4. it also allows a seed value to be written to the slpar register. bit 4 slphben (slpar high byte enable) if this bit is clear, the low byte of the slpar word is present in the slpar register. if this bit is set, the high byte of the slpar word is present in the slpar register. bit 3 wss (wide scsi send) when read, this bit returns the value of the wide scsi send (wss) flag. asserting this bit will clear the wss flag. this clearing function is self-resetting. when the wss flag is high following a wide scsi send operation, the scsi core is holding a byte of chain data in the sodl register. this data will become the first low-order byte sent when married with a high-order byte dur- ing a subsequent data send transfer. performing a scsi receive operation will clear this bit. also, performing any non-wide trans- fer will clear this bit. bit 2 vue0 (vendor unique enhance- ments bit 0) this bit is a read only value indicating whether the group code field in the scsi instruction is standard or vendor unique. if reset, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. the default for this bit is reset. sdu chm slpmd slphben wss vue0 vue1 wsr 76 5 4 3210 default>>> 00 0 0 0000
operating registers 5-10 sym53c895 data manual bit 1 vue1 (vendor unique enhance- ments bit 1) this bit is used to disable the automatic byte count reload during block move instructions in the command phase. if this bit is reset, the device will reload the block move byte count if the first byte received is one of the standard group codes. if this bit is set, the device will not reload the block move byte count, regardless of the group code. bit 0 wsr (wide scsi receive) when read, this bit returns the value of the wide scsi receive (wsr) flag. setting this bit clears the wsr flag. this clearing function is self-resetting. the wsr flag indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or non-chained block move command, and temporarily stored the high-order byte in the swide register rather than passing the byte out the dma channel. the hardware uses the wsr status flag to determine what behavior must occur at the start of the next data receive transfer. when the flag is set, the stored data in swide may be residue data, valid data for a subsequent data transfer, or overrun data. the byte may be read as normal data by starting a data receive transfer. performing a scsi send operation will clear this bit. also, performing any non-wide trans- fer will clear this bit. register 03 (83) scsi control three (scntl3) read/write bit 7 ultra (ultra enable) setting this bit enables ultra scsi or ultra2 scsi synchronous transfer rates. the default value of this bit is 0. this bit should remain cleared if the sym53c895 is not operating in ultra scsi mode or faster. note: set this bit to achieve ultra scsi transfer rates in legacy systems that use an 80 mhz clock. when this bit is set, the signal filtering period for sreq/ and sack/ automatically changes to 8 ns for ultra2 scsi or 15 ns for ultra scsi, regardless of the value of the extend req/ack filtering bit in the stest2 regis- ter. bits 6-4 scf2-0 (synchronous clock conversion factor) these bits select the factor by which the fre- quency of sclk is divided before being pre- sented to the synchronous scsi control logic. the bits are encoded as per table 5-2. for syn- chronous receive, the output of this divider is always divided by 4 and that value determines the transfer rate. for example, if sclk is 160 mhz, and the scf value is set to divide by one, then the maximum synchronous receive rate is 40 mhz( (160/1)/4 = 40) . for synchronous send, the output of this divider gets divided by the transfer period (xferp) bits in the scsi transfer (sxfer) ultra scf2 scf1 scf0 ews ccf2 ccf1 ccf0 7 6543210 default>>> 0 0000000
operating registers sym53c895 data manual 5-11 register, and that value determines the transfer rate. for valid combinations of the scf and x f e r p, s e e ta b l e 5 - 4 a n d ta b l e 5 - 5 . note: for additional information on how the synchronous transfer rate is determined, refer to chapter 2. bit 3 ews (enable wide scsi) when this bit is clear, all information transfer phases are assumed to be eight bits, transmit- ted on sd7-0/, sdp0/. when this bit is asserted, data transfers are done 16 bits at a time, with the least significant byte on sd7-0/, sdp/ and the most significant byte on sd15-8/, sdp1/. command, status, and mes- sage phases are not affected by this bit. clearing this bit will also clear the wide scsi receive bit in the scntl2 register, which indicates the presence of a valid data byte in the swide register. bits 2-0 ccf2-0 (clock conversion factor) these bits select the frequency of the sclk for asynchronous scsi operations. the bits are encoded as per the following table. note: for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional description. table 5-2: synchronous clock conversion factor scf2 scf1 scf0 factor frequency 000sclk/3 001sclk/1 010sclk/1.5 011sclk/2 100sclk/3 101sclk/4 110sclk/6 111sclk/8 table 5-3: asynchronous clock conversion factor ccf2 ccf1 ccf0 scsi clock (mhz) 0 0 0 50.01-75 0 0 1 16.67-25 0 1 0 25.01-37.5 0 1 1 37.51-50 1 0 0 50.01-75 1 0 1 75.01-80.00 110120 (not normally used) 111160 (with clock qua- drupler and 40 mhz clock)
operating registers 5-12 sym53c895 data manual register 04 (84) scsi chip id (scid) read/write bit 7 reserved bit 6 rre (enable response to reselection) when this bit is set, the sym53c895 is enabled to respond to bus-initiated reselection at the chip id in the respid0 and respid1 registers. note that the sym53c895 will not automatically reconfigure itself to initiator mode as a result of being reselected. bit 5 sre (enable response to selection) when this bit is set, the sym53c895 is able to respond to bus-initiated selection at the chip id in the respid0 and respid1 registers. note that the sym53c895 will not automati- cally reconfigure itself to target mode as a result of being selected. bit 4 reserved bits 3-0 encoded chip scsi id, bits 3-0 these bits are used to store the sym53c895 encoded scsi id. this is the id which the chip will assert when arbitrating for the scsi bus. the ids that the sym53c895 will respond to when being selected or reselected are configured in the respid0 and respid1 registers. the priority of the 16 possible ids, in descending order is: register 05 (85) scsi transfer (sxfer) read/write note: when using table indirect i/o commands, bits 7-0 of this register will be loaded from the i/o data structure. note: for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional description. bits 7-5 tp2-0 (scsi synchronous transfer period) these bits determine the scsi synchronous transfer period (xferp) used by the sym53c895 when sending synchronous scsi data in either initiator or target mode. these bits control the programmable dividers in the chip. note: for ultra scsi transfers, the ideal transfer period is 4, and 5 is acceptable. setting the transfer period to a value greater than 5 is not recommended. use the following formula to calculate the synchro- nous send and receive rates. table 5-4 and table 5-5 show examples of possible bit combina- tions. res rre sre res enc3 enc2 enc1 enc0 76543210 default>>> x00x0000 highest lowest 7654321015141312111098 tp2 tp1 tp0 mo4 mo3 mo2 mo1 mo0 76543210 default>>> 00000000 tp2 tp1 tp0 xferp 0004 0015 0106 0117 1008 1019 11010 11111
operating registers sym53c895 data manual 5-13 table 5-4: examples of synchronous transfer periods and rates for scsi-1 sclk (mhz) scf (scntl3 bits 6-4) xferp (sxfer bits 7-5) sync send rate (mb/s) sync send period (ns) sync receive rate (mb/s) synch receive period (ns) 80 ? 4 4 5 200 5 200 80 ? 4 5 4 250 5 200 66.67 ? 3 4 5.55 180 5.55 180 66.67 ? 3 5 4.44 225 5.55 180 50 ? 2 4 6.25 160 6.25 160 50 ? 2 5 5 200 6.25 160 40 ? 2 4 5 200 5 200 37.50 ? 1.5 4 6.25 160 6.25 160 33.33 ? 1.5 4 5.55 180 5.55 180 25 ? 1 4 6.25 160 6.25 160 20 ? 1 4 5 200 5 200 16.67 ? 1 4 4.17 240 4.17 240 table 5-5: example synchronous transfer periods and rates for fast scsi, ultra scsi, and ultra2 scsi sclk (mhz) scf (scntl3 bits 6-4) xferp (sxfer bits 7-5) sync send rate (mb/s) sync send period (ns) sync receive rate (mb/s) synch receive period (ns) 160 ? 1 4 40 25 40 25 80 ? 1 4 20 50 20 50 80 ? 2 4 10 100 10 100 66.67 ? 1.5 4 11.11 90 11.11 90 66.67 ? 1 5 8.88 112.5 11.11 90 50 ? 1 4 12.5 80 12.5 80 50 ? 1 5 10 100 12.5 80 40 ? 1 4 10 100 10 100 37.50 ? 1 4 9.375 106.67 9.375 106.67 33.33 ? 1 4 8.33 120 8.33 120 25 ? 1 4 6.25 160 6.25 160 20 ? 1 4 5 200 5 200 16.67 ? 1 4 4.17 240 4.17 240 synchronous send rate = (sclk/scf)/xferp synchronous receive rate = (sclk/scf) / 4 key: sclk = scsi clock scf = synchronous clock conversion factor, scntl3 bits 6-4 xferp = transfer period, sxfer register bits 7-5
operating registers 5-14 sym53c895 data manual bits 4-0 mo4-mo0 (max scsi synchronous offset) these bits describe the maximum scsi syn- chronous offset used by the sym53c895 when transferring synchronous scsi data in either initiator or target mode. the following table describes the possible combinations and their relationship to the synchronous data off- set used by the sym53c895. these bits deter- mine the sym53c895s method of transfer for data in and data out phases only; all other information transfers will occur asynchro- nously. table 5-6: scsi synchronous offset values mo4 mo3 mo2 mo1 mo0 synchronous offset 000000-asynchronous 000011 000102 000113 001004 001015 001106 001117 010008 010019 0101010 0101111 0110012 0110113 0111014 0111115 1000016 1000117 1001018 1001119 1010020 1010121 1011022 1011123 1100024 1100125 1101026 1101127 1110028 1110129 1111030 1111131
operating registers sym53c895 data manual 5-15 register 06 (86) scsi destination id (sdid) read/write bits 7-4 reserved bits 3-0 encoded destination scsi id writing these bits sets the scsi id of the intended initiator or target during scsi rese- lection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this register. the scsi id is defined by the user in a scripts select or reselect instruc- tion. the value written should be the binary- encoded id value. the priority of the 16 possi- ble ids, in descending order, is: register 07 (87) general purpose (gpreg) read/write bits 7-5 reserved bits 4-0 gpio4-gpio0 (general purpose) these bits can be programmed through the gpcntl register to become inputs, outputs or to perform special functions. as an output, these pins can enable or disable external termi- nators. these signals can also be programmed as live inputs and sensed through a scripts register to register move instruction. gpio(3-0) default as inputs and gpio4 defaults as an output pin. gpio4 can be used to enable or disable v pp , the 12-volt power supply to the external flash memory. this bit powers up with the power to the external memory disabled. symbios use of gpio pins symbios software uses the gpio0 pin to toggle scsi device leds, turning on the led when- ever the sym53c895 is on the scsi bus. symbios software drives this pin low to turn on the led, or drives it high to turn off the led. symbios software uses the gpio1-0 pins to support serial eeprom access. when serial eeprom access is enabled, gpio1 is used as a clock and gpio0 is used as data. res res res res enc3 enc2 enc1 enc0 76543210 default>>> xxxx0000 highest lowest 765432101514131211098 res res res gpio4 gpio3 gpio2 gpio1 gpio0 76543210 default>>> xxx0xxxx
operating registers 5-16 sym53c895 data manual register 08 (88) scsi first byte received (sfbr) read/write this register contains the first byte received in any asynchronous information transfer phase. for ex- ample, when the sym53c895 is operating in initi- ator mode, this register contains the first byte received in the message in, status, and data in phases. when a block move instruction is executed for a particular phase, the first byte received is stored in this register even if the present phase is the same as the last phase. the first byte received value for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read-modify-writes with the sfbr as the destina- tion. this allows bit testing after an operation. the sfbr is not writable via the cpu, and there- fore not by a memory move. the load instruction may not be used to write to this register. however, it can be loaded via scripts read/write opera- tions. to load the sfbr with a byte stored in sys- tem memory, the byte must first be moved to an intermediate sym53c895 register (such as the scratch register), and then to the sfbr. this register will also contain the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dcntl register is clear. register 09 (89) scsi output control latch (socl) read /write bit 7 req(assert scsi req/ signal) bit 6 ack(assert scsi ack/ signal) bit 5 bsy(assert scsi bsy/ signal) bit 4 sel(assert scsi sel/ signal) bit 3 atn(assert scsi atn/ signal) bit 2 msg(assert scsi msg/ signal) bit 1 c/d(assert scsi c_d/ signal) bit 0 i/o(assert scsi i_o/ signal) this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. socl should only be used when trans- ferring data via programmed i/o. some bits are set (1) or reset (0) when executing scsi scripts. do not write to the register once the sym53c895 starts executing normal scsi scripts. 1b7 1b6 1b5 1b4 1b3 1b2 1b1 1b0 76543210 default>>> 00000000 req ack bsy sel atn msg c/d i/o 76543210 default>>> 00000000
operating registers sym53c895 data manual 5-17 register 0a (8a) scsi selector id (ssid) read only bit 7 val (scsi valid) if val is asserted, the two scsi ids were detected on the bus during a bus-initiated selection or reselection, and the encoded desti- nation scsi id bits below are valid. if val is deasserted, only one id was present and the contents of the encoded destination id are meaningless. bits 6-4 reserved bits 3-0 encoded destination scsi id reading the ssid register immediately after the sym53c895 has been selected or rese- lected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 specification. this condition can be detected by examining the val bit above. register 0b (8b) scsi bus control lines (sbcl) read only bit 7 req (sreq/ status) bit 6 ack (sack/ status) bit 5 bsy (sbsy/ status) bit 4 sel (ssel/ status) bit 3 atn (satn/ status) bit 2 msg (smsg/ status) bit 1 c/d (sc_d/ status) bit 0 i/o (si_o/ status) when read, this register returns the scsi control line status. a bit will be set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the re- sulting read data is synchronized before being pre- sented to the pci bus to prevent parity errors from being passed to the system. this register can be used for diagnostics testing or operation in low-lev- el mode. val res res res enid3 enid2 enid1 enid0 76543210 default>>> 0xxx0000 req ack bsy sel atn msg c/d i/o 76543210 default>>> xxxxxxxx
operating registers 5-18 sym53c895 data manual register 0c (8c) dma status (dstat) read only reading this register will clear any bits that are set at the time the register is read, but will not neces- sarily clear the register because additional inter- rupts may be pending (the sym53c895 stacks interrupts). the dip bit in the istat register will also be cleared. dma interrupt conditions may be individually masked through the dien register. when performing consecutive 8-bit reads of the dstat, sist0 and sist1 registers (in any or- der), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, functional description, for more information on interrupts. bit 7 dfe (dma fifo empty) this status bit is set when the dma fifo is empty. it may be used to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure sta- tus bit and will not cause an interrupt. bit 6 mdpe (master data parity error) this bit is set when the sym53c895 as a mas- ter detects a data parity error, or a target device signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of ctest4). bit 5 bf (bus fault) this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the sym53c895 is bus master, and is defined as a cycle that ends with a bad address or tar- get abort condition. bit 4 abrt (aborted) this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the istat register. bit 3 ssi (single step interrupt) if the single-step mode bit in the dcntl register is set, this bit will be set and an inter- rupt generated after successful execution of each scripts instruction. bit 2 sir (scripts interrupt instruction received) this status bit is set whenever an interrupt instruction is evaluated as true. bit 1 reserved bit 0 iid (illegal instruction detected) this status bit will be set any time an illegal or reserved instruction op code is detected, whether the sym53c895 is operating in sin- gle-step mode or automatically executing scsi scripts. any of the following conditions during instruction execution will also cause this bit to be set: 1. the sym53c895 is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. 2. a block move instruction is executed with 000000h loaded into the dbc register, indicating that zero bytes are to be moved. 3. during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dbc register while the sym53c895 is in target mode. 4. during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. dfe mdpe bf abrt ssi sir res iid 76543210 default>>> 100000x0
operating registers sym53c895 data manual 5-19 5. a transfer control instruction is executed with the reserved bit 22 set. 6. a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode. 7. a load/store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. 8. a load/store instruction is issued when the register address is not aligned with the memory address 9. a load/store instruction is issued with bit 5 in the dcmd register clear or bits 3 or 2 set. 10. a load/store instruction when the count value in the dbc register is not set at 1 to 4. 11. a load/store instruction attempts to cross a dword boundary. 12. a memory move instruction is executed with one of the reserved bits in the dcmd register set. 13. a memory move instruction is executed with the source and destination addresses not byte-aligned. register 0d (8d) scsi status zero (sstat0) read only bit 7 ilf (sidl least significant byte full) this bit is set when the least significant byte in the scsi input data latch register (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch regis- ter before being sent to the dma fifo and then to the host bus. the sidl register con- tains scsi data received asynchronously. syn- chronous data received does not flow through this register. bit 6 orf (sodr least significant byte full) this bit is set when the least significant byte in the scsi output data register (sodr, a hid- den buffer register which is not accessible) con- tains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it cannot be read or written by the user. this bit can be used to determine how many bytes reside in the chip when an error occurs. bit 5 olf (sodl least significant byte full) this bit is set when the least significant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asyn- ilf orf olf aip loa woa rst sdp0/ 76543210 default>>> 00000000
operating registers 5-20 sym53c895 data manual chronous transfers. this bit can be used to determine how many bytes reside in the chip when an error occurs. bit 4 aip (arbitration in progress) arbitration in progress (aip = 1) indicates that the sym53c895 has detected a bus free con- dition, asserted bsy, and asserted its scsi id onto the scsi bus. bit 3 loa (lost arbitration) when set, loa indicates that the sym53c895 has detected a bus free condi- tion, arbitrated for the scsi bus, and lost arbi- tration due to another scsi device asserting the sel/ signal. bit 2 woa (won arbitration) when set, woa indicates that the sym53c895 has detected a bus free condi- tion, arbitrated for the scsi bus and won arbi- tration. the arbitration mode selected in the scntl0 register must be full arbitration and selection for this bit to be set. bit 1 rst/ (scsi rst/ signal) this bit reports the current status of the scsi rst/ signal, and the rst signal (bit 6) in the istat register. this bit is not latched and may be changing when read. bit 0 sdp0/ (scsi sdp0/ parity signal) this bit represents the active high current sta- tus of the scsi sdp0/ parity signal. this sig- nal is not latched and may be changing as it is read. register 0e (8e) scsi status one (sstat1) read only bits 7-4 ff3-ff0 (fifo flags) these four bits, along with sstat2 bit 4, define the number of bytes or words that cur- rently reside in the sym53c895s scsi syn- chronous data fifo. these bits are not latched and they will change as data moves through the fifo. ff3 ff2 ff1 ff0 sdp0l msg c/d i/o 76543210 default>>> 0000xxxx table 5-7: fifo flags bit values ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 00000 0 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 0101010 0101111 0110012 0110113 0111014 0111115 1000016 1000117 1001018 1001119
operating registers sym53c895 data manual 5-21 bit 3 sdp0l (latched scsi parity) this bit reflects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch register (sidl). it changes when a new byte is latched into the least significant byte of the sidl register. this bit is active high, in other words, it is set when the parity signal is active. bit 2 msg (scsi msg/ signal) bit 1 c/d (scsi c_d/ signal) bit 0 i/o (scsi i_o/ signal) these scsi phase status bits are latched on the asserting edge of sreq/ when operating in either initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in low-level mode. register 0f (8f) scsi status two (sstat2) (read only) bit 7 ilf1 (sidl most significant byte full) this bit is set when the most significant byte in the scsi input data latch register (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch regis- ter before being sent to the dma fifo and then to the host bus. the sidl register con- tains scsi data received asynchronously. syn- chronous data received does not flow through this register. bit 6 orf1 (sodr most significant byte full) this bit is set when the most significant byte in the scsi output data register (sodr, a hid- den buffer register which is not accessible) con- tains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not accessible to the user. this bit can be used to determine how many bytes reside in the chip when an error occurs. bit 5 olf1 (sodl most significant byte full) this bit is set when the most significant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asyn- 1010020 1010121 1011022 1011123 1100024 1100125 1101026 1101127 1110028 1110129 1111030 1111131 table 5-7: fifo flags bit values (continued) ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo ilf1 orf1 olf1 ff4 spl1 dm ldsc sdp1 76543210 default>>> 0000xx1x
operating registers 5-22 sym53c895 data manual chronous transfers. this bit can be used to determine how many bytes reside in the chip when an error occurs. bit 4 ff4 (fifo flags bit 4) this is the most significant bit in the scsi fifo flags field, with the rest of the bits in sstat1. for a complete description of this field, see the definition for sstat1 bits 7-4. bit 3 spl1(latched scsi parity for sd15-8) this active high bit reflects the scsi odd par- ity signal corresponding to the data latched into the most significant byte in the sidl reg- ister. bit 2 dm (diffsens mismatch) this bit is set when the diffsens pin detects a single-ended or lvd scsi operating voltage level while the sym53c895 is operating in high-power differential mode (by setting the dif bit in the stest2 register). if this bit is reset, the diffsens value matches the dif bit setting. bit 1 ldsc (last disconnect) this status bit is used in conjunction with the connected (con) bit in scntl1 and allows the user to detect the case in which a target device disconnects, and then another scsi device selects or reselects, the sym53c895. if the connected bit is asserted and the ldsc bit is asserted, a disconnect has occurred. this bit is set when the connected bit in scntl1 is cleared. this bit is cleared when a block move instruction is executed while the con- nected bit in scntl1 is set. bit 0 sdp1 (scsi sdp1 signal) this bit represents the active-high current state of the scsi sdp1 parity signal. it is unlatched and may be changing as it is read. registers 10-13 (90-93) data structure address (dsa) read/write this 32-bit register contains the base address used for all table indirect calculations. the dsa register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate.
operating registers sym53c895 data manual 5-23 register 14 (94) interrupt status (istat) (read/write) this is the only register that can be accessed by the host cpu while the sym53c895 is executing scripts (without interfering in the operation of the sym53c895). it may be used to poll for inter- rupts if hardware interrupts are disabled. there may be stacked interrupts pending; read this regis- ter after servicing an interrupt to check for stacked interrupts. for more information on interrupt han- dling refer to chapter 2, functional description. bit 7 abrt (abort operation) setting this bit aborts the current operation being executed by the sym53c895. if this bit is set and an interrupt is received, reset this bit before reading the dstat register to prevent further aborted interrupts from being gener- ated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the istat register. 4. if the scsi interrupt pending bit is set, then read the sist0 or sist1 register to determine the cause of the scsi interrupt and go back to step 2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 00h value to this register. 6. read the dstat register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. bit 6 srst (software reset) setting this bit resets the sym53c895. all operating registers are cleared to their respec- tive default values and all scsi signals are deasserted. setting this bit does not cause the scsi rst/ signal to be asserted. this reset will not clear the 53c700 compatibility bit or any of the pci configuration registers. this bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset will also clear this bit). bit 5 sigp (signal process) the sigp bit is a r/w bit that can be written at any time, and polled and reset via ctest2. the sigp bit can be used in various ways to pass a flag to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/ reselection. setting this bit causes that instruc- tion to jump to the alternate address immedi- ately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit may be used at any time and is not restricted to the wait for selection/reselection condition. bit 4 sem (semaphore) this bit can be set by the scripts processor using a scripts register write instruction. the bit may also be set by an external proces- sor while the sym53c895 is executing a scripts operation. this bit enables the sym53c895 to notify an external processor of a predefined condition while scripts are running. the external processor may also notify the sym53c895 of a predefined condi- tion and the scripts processor may take action while scripts are executing. bit 3 con (connected) this bit is automatically set any time the sym53c895 is connected to the scsi bus as an initiator or as a target. it will be set after successfully completing selection or when the sym53c895 has responded to a bus-initiated selection or reselection. it will also be set after the sym53c895 wins arbitration when operat- ing in low-level mode. when this bit is clear, the sym53c895 is not connected to the scsi bus. abrt srst sigp sem con intf sip dip 76543210 default>>> 00000000
operating registers 5-24 sym53c895 data manual bit 2 intf (interrupt on the fly) this bit is asserted by an intfly instruction during scripts execution. scripts pro- grams will not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set, when the istat register is read it will not automatically be cleared. to clear this bit, it must be written to a one. the reset operation is self-clearing. note: if the intf bit is set but sip or dip is not set, do not attempt to read the other chip status registers. an interrupt-on-the-fly interrupt must be cleared before servicing any other interrupts indicated by sip or dip. note: this bit must be written to one in order to clear it after it has been set. bit 1 sip (scsi interrupt pending) this status bit is set when an interrupt condi- tion is detected in the scsi portion of the sym53c895. the following conditions will cause a scsi interrupt to occur: n a phase mismatch (initiator mode) or satn/ becomes active (target mode) n an arbitration sequence completes n a selection or reselection time-out occurs n the sym53c895 was selected n the sym53c895 was reselected n a scsi gross error occurs n an unexpected disconnect occurs n a scsi reset occurs n a parity error is detected n the handshake-to-handshake timer is expired n the general purpose timer is expired n a scsi bus mode change is detected to determine exactly which condition(s) caused the interrupt, read the sist0 and sist1 registers. bit 0 dip (dma interrupt pending) this status bit is set when an interrupt condi- tion is detected in the dma portion of the sym53c895. the following conditions will cause a dma interrupt to occur: n a pci parity error is detected n a bus fault is detected n an abort condition is detected n a scripts instruction is executed in single-step mode n a scripts interrupt instruction is executed n an illegal instruction is detected. to determine exactly which condition(s) caused the interrupt, read the dstat register.
operating registers sym53c895 data manual 5-25 register 18 (98) chip test zero (ctest0) read/write this was a general purpose read/write register in previous sym53c8xx family chips. although it is still a read/write register, symbios reserves the right to use these bits for future sym53c8xx family en- hancements. register 19 (99) chip test one (ctest1) read only bits 7-4 fmt3-0 (byte empty in dma fifo) these bits identify the bottom bytes in the dma fifo that are empty. each bit corre- sponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 will be set. since the fmt flags indi- cate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. bits 3-0 ffl3-0 (byte full in dma fifo) these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 will be set. since the ffl flags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. fmt3 fmt2 fmt1 fmt0 ffl3 ffl2 ffl1 ffl0 76543210 default>>> 11110000
operating registers 5-26 sym53c895 data manual register 1a (9a) chip test two (ctest2) read/write bit 7 ddir (data transfer direction) (read only) this status bit indicates which direction data is being transferred. when this bit is set, the data will be transferred from the scsi bus to the host bus. when this bit is clear, the data will be transferred from the host bus to the scsi bus. bit 6 sigp (signal process) (read only) this bit is a copy of the sigp bit in the istat register (bit 5). the sigp bit is used to signal a running scripts instruction. when this reg- ister is read, the sigp bit in the istat register is cleared. bit 5 cio (configured as i/o) (read only) this bit is defined as the configuration i/o enable status bit. this read-only bit indicates if the chip is currently enabled as i/o space. note: both bits 4 and 5 may be set if the chip is dual-mapped. bit 4 cm (configured as memory) (read only) this bit is defined as the configuration mem- ory enable status bit. this read-only bit indi- cates if the chip is currently enabled as memory space. note: both bits 4 and 5 may be set if the chip is dual-mapped. bit 3 srtch (scratcha/b operation) this bit controls the operation of the scratcha and scratchb registers. when it is set, scratchb contains the ram base address value from the pci configuration ram base address register. this is the base address for the 4 kb internal ram. in addi- tion, the scratcha register displays the memory-mapped based address of the chip operating registers. when this bit is clear, the scratcha and scratchb registers return to normal operation. note: bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read- modify-write to this register. bit 2 teop (scsi true end of process) (read only) this bit indicates the status of the sym53c895s internal teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the sym53c895. when this bit is set, teop is active. when this bit is clear, teop is inactive. bit 1 dreq (data request status) (read only) this bit indicates the status of the sym53c895s internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive. bit 0 dack (data acknowledge status) (read only) this bit indicates the status of the sym53c895s internal data acknowledge sig- nal (dack/). when this bit is set, dack/ is inactive. when this bit is clear, dack/ is active. ddir sigp cio cm srtch teop dreq dack 76543210 default>>> 00xx0001
operating registers sym53c895 data manual 5-27 register 1b (9b) chip test three (ctest3) read/write bits 7-4 v3-v0 (chip revision level) these bits identify the chip revision level for software purposes. the value should be the same as the lower nibble of the pci revision id register, at address 08h in configuration space. bit 3 flf (flush dma fifo) when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dnad register. the internal dmawr signal, controlled by the ctest5 register, determines the direction of the trans- fer. this bit is not self clearing; once the sym53c895 has successfully transferred the data, this bit should be reset. note: polling of fifo flags is allowed during flush operations. bit 2 clf (clear dma fifo) when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. this bit automatically resets after the sym53c895 has successfully cleared the appropriate fifo pointers and registers. note: this bit does not clear the data visible at the bottom of the fifo. bit 1 fm (fetch pin mode) when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ will only be active during the op code portion of an instruction fetch. this allows scripts to be stored in a prom while data tables are stored in ram. if this bit is not set, fetch/ will be asserted for all bus cycles during instruction fetches. bit 0 wrie (write and invalidate enable) this bit, when set, causes memory write and invalidate commands to be issued on the pci bus after certain conditions have been met. these conditions are described in detail in chapter 3. v3 v2 v1 v0 flf clf fm wrie 76543210 default>>> xxxx0000
operating registers 5-28 sym53c895 data manual registers 1c-1f (9c-9f) te m p o r a r y ( t e m p ) read/write this 32-bit register stores the return instruction address pointer from the call instruction. the ad- dress pointer stored in this register is loaded into the dsp register when a return instruction is exe- cuted. this address points to the next instruction to be executed. do not write to this register while the sym53c895 is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register 20 (a0) dma fifo (dfifo) read only bits 7-0 bo7-bo0 (byte offset counter) these bits, along with bits 1-0 in the ctest5 register, indicate the amount of data trans- ferred between the scsi core and the dma core. it may be used to determine the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable while data is being transferred between the two cores; once the chip has stopped transferring data, these bits are stable. since the dfifo register counts the number of bytes transferred between the dma core and the scsi core, and the dbc register counts the number of bytes transferred across the host bus, the difference between these two counters represents the number of bytes remaining in the dma fifo. the following steps will determine how many bytes are left in the dma fifo when an error occurs, regardless of the direction of the trans- fer: 1. if the dma fifo size is set to 112 bytes, subtract the seven least significant bits of the dbc register from the 7-bit value of the dfifo register. if the dma fifo size is set to 816 bytes (using bit 5 of the ctest5 register), sub- tract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits 1-0 in the ctest5 register and bits 7-0 of the dma fifo register. bo7bo6bo5bo4bo3bo2bo1bo0 76543210 default>>> x0000000
operating registers sym53c895 data manual 5-29 2. if the dma fifo size is set to 112 bytes, and the result with 7fh for a byte count between zero and 64. if the dma fifo size is set to 816 bytes, and the result with 3ffh for a byte count between 0 and 816. note: to calculate the total number of bytes in both the dma fifo and scsi logic, see the section on data paths in chapter two, functional description. register 21 (a1) chip test four (ctest4) read/write bit 7 bdis (burst disable) when set, this bit will cause the sym53c895 to perform back to back cycles for all transfers. when reset, the sym53c895 will perform back to back transfers for op code fetches and burst transfers for data moves. bit 6 zmod (high impedance mode) setting this bit causes the sym53c895 to place all output and bidirectional pins into a high-impedance state. in order to read data out of the sym53c895, this bit must be cleared. this bit is intended for board-level testing only. do not set this bit during normal system oper- ation. bit 5 zsd (scsi data high impedance) setting this bit causes the sym53c895 to place the scsi data bus sd(15-0) and the par- ity lines sdp(1-0) in a high-impedance state. in order to transfer data on the scsi bus, this bit must be cleared. bit 4 srtm (shadow register test mode) setting this bit allows access to the shadow reg- isters used by memory-to-memory move operations. when this bit is set, register accesses to the temp and dsa registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to- memory move operation. the dsa and temp registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respec- tively. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. bdis zmod zsd srtm mpee fbl2 fbl1 fbl0 76543210 default>>> 00000000
operating registers 5-30 sym53c895 data manual bit 3 mpee (master parity error enable) setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the sym53c895. a parity error during a bus master write is detected by the target, and the sym53c895 is informed of the error by the perr/ pin being asserted by the target. when this bit is reset, the sym53c895 will not interrupt if a master parity error occurs. this bit is reset at power up. bits 2-0 fbl2-fbl0 (fifo byte control) these bits steer the contents of the ctest6 register to the appropriate byte lane of the 32- bit dma fifo. if the fbl2 bit is set, then fbl1 and fbl0 determine which of four byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dnad and dbc regis- ters. each of the four bytes that make up the 32-bit dma fifo can be accessed by writing these bits to the proper value. for normal oper- ation, fbl2 must equal zero. register 22 (a2) chip test five (ctest5) read/write bit 7 adck (clock address incrementor) setting this bit increments the address pointer contained in the dnad register. the dnad register is incremented based on the dnad contents and the current dbc value. this bit automatically clears itself after incrementing the dnad register. bit 6 bbck (clock byte counter) setting this bit decrements the byte count con- tained in the 24-bit dbc register. it is decre- mented based on the dbc contents and the current dnad value. this bit automatically clears itself after decrementing the dbc regis- ter. bit 5 dfs (dma fifo size) this bit controls the size of the dma fifo. when clear, the dma fifo will be 112 bytes deep. when set, the dma fifo size will increase to 816 bytes. using a 112-byte fifo allows software written for other sym53c8xx family chips to properly calculate the number of bytes residing in the chip after a target dis- connect. the default value of this bit is zero. bit 4 masr (master control for set or reset pulses) this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is reset, bit 3 deasserts the corresponding signals. bits 4 and 3 should not be changed in the same write cycle. fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x disabled n/a 1 0 0 0 d(7-0) 1 0 1 1 d(15-8) 1 1 0 2 d(23-16) 1 1 1 3 d(31-24) adck bbck dfs masr ddir bl2 bo9 bo8 76543210 default>>> 00000xxx
operating registers sym53c895 data manual 5-31 bit 3 ddir (dma direction) setting this bit either asserts or deasserts the internal dma write (dmawr) direction sig- nal depending on the current status of the masr bit in this register. asserting the dmawr signal indicates that data will be transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. bit 2 bl2 (burst length bit 2) this bit works with bits 6 and 7 in the dmode register to determine the burst length. for complete definitions of this field, refer to the descriptions of dmode bits 6 and 7. this bit is disabled if an 112-byte fifo is selected by clearing the dma fifo size bit. bits 1-0 bo9-8 these are the upper two bits of the dma fifo byte offset counter. the entire field is described under the dfifo register, bits 7-0. register 23 (a3) chip test six (ctest6) read/write bits 7-0 df7-df0 (dma fifo) writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to pre- vent dma data from being corrupted, this reg- ister should not be accessed during normal operation. this register should only be written when testing the dma fifo using the ctest4 register. reads or writes to this regis- ter while the test mode is not enabled will have unexpected results. df7 df6 df5 df4 df3 df2 df1 df0 76543210 default>>> 00000000
operating registers 5-32 sym53c895 data manual registers 24-26 (a4-a6) dma byte counter (dbc) read/write this 24-bit register determines the number of bytes to be transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the sym53c895. the dbc counter is decremented each time that data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that were transferred. the maximum number of bytes that can be trans- ferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dbc register is ffffffh. if the in- struction is a block move and a value of 000000h is loaded into the dbc register, an illegal instruction interrupt will occur if the sym53c895 is not in tar- get mode, command phase. the dbc register is also used to hold the least sig- nificant 24 bits of the first dword of a script fetch, and to hold the offset value during table indi- rect i/o scripts. for a complete description, see chapter 6, instruction set of the i/o processor. the power-up value of this register is indetermi- nate. register 27 (a7) dma command (dcmd) read/write this 8-bit register determines the instruction for the sym53c895 to execute. this register has a dif- ferent format for each instruction. for complete de- scriptions, see chapter 6, instruction set of the i/ o processor.
operating registers sym53c895 data manual 5-33 registers 28-2b (a8-ab) dma next address (dnad) read/write this 32-bit register contains the general purpose address pointer. at the start of some scripts op- erations, its value is copied from the dsps register. its value may not be valid except in certain abort conditions. the default value of this register is zero. this register should not be used to determine data addresses during a phase mismatch interrupt, as its value is not always correct for this use. the dbc, dfifo, and dsps registers should be used to cal- culate residual byte counts and addresses as de- scribed in the data paths section in chapter 2. registers 2c-2f (ac-af) dma scripts pointer (dsp) read/write to execute scsi scripts, the address of the first scripts instruction must be written to this regis- ter. in normal scripts operation, once the start- ing address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in single-step mode, there is a single step interrupt after each instruction is executed. the dsp register does not need to be written with the next address, but the start dma bit (bit 2, dcntl register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing to this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero.
operating registers 5-34 sym53c895 data manual registers 30-33 (b0-b3) dma scripts pointer save (dsps) read/write this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. registers 34-37 (b4-b7) scratch register a (scratch a) read/write this is a general purpose, user-definable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register will alter its contents. the sym53c895 cannot fetch scripts instructions from this location. when bit 3 in the ctest2 reg- ister is set, this register contains the memory- mapped base address of the operating registers. set- ting ctest2 bit 3 only causes the base address to appear in this register; any information that was previously in the register will remain intact. any writes to this register while ctest2 bit 3 is set will pass through to the actual scratcha register. the power-up value of this register is indetermi- nate.
operating registers sym53c895 data manual 5-35 register 38 (b8) dma mode (dmode) read/write bit 7-6 bl1-bl0 (burst length) these bits control the maximum number of transfers performed per bus ownership, regard- less of whether the transfers are back-to-back, burst, or a combination of both. the sym53c895 asserts the bus request (req/) output when the dma fifo can accommo- date a transfer of at least one burst size of data. bus request (req/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even though less than a full burst of transfers may be performed. the sym53c895 inserts a fairness delay of four clks between burst-length transfers (as set in bl1-0) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. bit 5 siom (source i/o-memory enable) this bit is defined as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; and if reset, then the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when the sym53c895 is i/o mapped. bits 4 and 5 of the ctest2 register can be used to determine the configuration status of the sym53c895. bit 4 diom (destination i/o-memory enable) this bit is defined as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; and if reset, then the destination address is in memory space. this function is useful for memory-to-register operations using the memory move instruction when the sym53c895 is i/o mapped. bits 4 and 5 of the ctest2 register can be used to determine the configuration status of the sym53c895. bit 3 erl (enable read line) this bit enables a pci read line command. if pci cache mode is enabled by setting bits in the pci cache line size register, this chip issues a read line command on all read cycles if other conditions are met. for more informa- tion on these conditions, refer to chapter 3, pci functional description. bit 2 ermp (enable read multiple) setting this bit will cause read multiple com- mands to be issued on the pci bus after cer- tain conditions have been met. these conditions are described in chapter 3. bl1 bl0 siom diom erl ermp bof man 76543210 default>>> 00000000 table 5-8: burst length bit decoding bl2 (ctest5 bit 2) bl1 bl0 burst length 0 0 0 2-transfer burst 0 0 1 4-transfer burst 0 1 0 8-transfer burst 0 1 1 16-transfer burst 1 0 0 32-transfer burst* 1 0 1 64-transfer burst* 1 1 0 128-transfer burst* 1 1 1 reserved * only valid if the fifo size is set to 816 bytes
operating registers 5-36 sym53c895 data manual bit 1 bof (burst op code fetch enable) setting this bit causes the sym53c895 to fetch instructions in burst mode. specifically, the chip will burst in the first two dwords of all instructions using a single bus ownership. if the instruction is a memory-to-memory move type, the third dword will be accessed in a sub- sequent bus ownership. if the instruction is an indirect type, the additional dword will be accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip will access the remaining two dwords in a subsequent bus ownership, thereby fetch- ing the four dwords required in two bursts of two dwords each. this bit has no effect if scripts instruction prefetching is enabled. bit 0 man (manual start mode) setting this bit prevents the sym53c895 from automatically fetching and executing scsi scripts when the dsp register is written. when this bit is set, the start dma bit in the dcntl register must be set to begin scripts execution. clearing this bit causes the sym53c895 to automatically begin fetch- ing and executing scsi scripts when the dsp register is written. this bit normally is not used for scsi scripts operations. register 39 (b9) dma interrupt enable (dien) read/write this register contains the interrupt mask bits corre- sponding to the interrupting conditions described in the dstat register. an interrupt is masked by clearing the appropriate mask bit. masking an in- terrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit will still be set in the dstat register. masking an interrupt will not prevent the istat dip from being set. all dma interrupts are considered fatal, therefore scripts will stop running when this condition occurs, whether or not the interrupt is masked. set- ting a mask bit enables the assertion of irq/ for the corresponding interrupt. (a masked non-fatal in- terrupt will not prevent un-masked or fatal inter- rupts from getting through; interrupt stacking begins when either the istat sip or dip bit is set.) the sym53c895 irq/ output is latched; once as- serted, it will remain asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is as- serted will not cause irq/ to be deasserted. for more information on interrupts, see chapter 2, functional description. bit 7 reserved bit 6 mdpe (master data parity error) bit 5 bf (bus fault) bit 4 abrt (aborted) bit 3 ssi (single -step interrupt) bit 2 sir (scripts interrupt instruction received bit 1 reserved bit 0 iid (illegal instruction detected) res mdpe bf abrt ssi sir res iid 76543210 default>>> x00000x0
operating registers sym53c895 data manual 5-37 register 3a (ba) scratch byte register (sbr) read/write this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register will alter its contents. the default value of this register is zero. this register was called the dma watchdog timer on previous sym53c8xx family products. register 3b (bb) dma control (dcntl) read/write bit 7 clse (cache line size enable) setting this bit enables the sym53c895 to sense and react to cache line boundaries set up by the dmode or pci cache line size regis- ter, whichever contains the smaller value. clearing this bit disables the cache line size logic and the sym53c895 monitors the cache line size via the dmode register. bit 6 pff (pre-fetch flush) setting this bit will cause the pre-fetch unit to flush its contents. the bit will reset after the flush is complete. bit 5 pfen (pre-fetch enable) setting this bit enables the pre-fetch unit if the burst size is equal to or greater than four. for more information on scripts instruction prefetching, see chapter 2. bit 4 ssm (single-step mode) setting this bit causes the sym53c895 to stop after executing each scripts instruction, and generate a single step interrupt. when this bit is clear the sym53c895 will not stop after each instruction; instead it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, this bit should be clear. to restart the sym53c895 after it generates a scripts step interrupt, the istat and dstat regis- ters should be read to recognize and clear the interrupt and then the start dma bit in this register should be set. clse pff pfen ssm irqm std irqd com 76543210 default>>> 00000000
operating registers 5-38 sym53c895 data manual bit 3 irqm (irq mode) when set, this bit will enable a totem pole driver for the irq pin. when reset, this bit will enable an open drain driver for the irq pin with a internal weak pull-up. this bit is reset at power up. the bit should remain clear to retain full pci compliance. bit 2 std (start dma operation) the sym53c895 fetches a scsi scripts instruction from the address contained in the dsp register when this bit is set. this bit is required if the sym53c895 is in one of the following modes: 1. manual start mode C bit 0 in the dmode register is set. 2. single-step mode C bit 4 in the dcntl register is set. when the sym53c895 is executing scripts in manual start mode, the start dma bit needs to be set to start instruction fetches, but does not need to be set again until an interrupt occurs. when the sym53c895 is in single- step mode, the start dma bit needs to be set to restart execution of scripts after a single- step interrupt. bit 1 irqd (irq disable) setting this bit disables the irq pin; clearing this bit enables normal operation. as with any other register other than istat, this register cannot be accessed except by a scripts instruction during scripts execution. for more information on the use of this bit in inter- rupt handling, see chapter 2. bit 0 com (sym53c700 compatibility) when this bit is clear, the sym53c895 will behave in a manner compatible with the sym53c700; selection/reselection ids will be stored in both the ssid and sfbr registers. when this bit is set, the id will be stored only in the ssid register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register-to-register oper- ation. this bit is not affected by a software reset. register 3c-3f (bc-bf) adder sum output (adder) read only this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate.
operating registers sym53c895 data manual 5-39 register 40 (c0) scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corre- sponding to the interrupting conditions described in the sist0 register. an interrupt is masked by clearing the appropriate mask bit. for more infor- mation on interrupts, see chapter 2, functional description. bit 7 m/a (scsi phase mismatch - initiator mode; scsi atn condition - target mode) setting this bit allows the sym53c895 to gen- erate an interrupt when a phase mismatch or atn condition occurs. bit 6 cmp (function complete) setting this bit allows the sym53c895 to gen- erate an interrupt when a full arbitration and selection sequence has completed. bit 5 sel (selected) setting this bit allows the sym53c895 to gen- erate an interrupt when the sym53c895 has been selected by a scsi target device. bit 4 rsl (reselected) setting this bit allows the sym53c895 to gen- erate an interrupt when the sym53c895 has been reselected by a scsi initiator device. bit 3 sge (scsi gross error) setting this bit allows the sym53c895 to gen- erate an interrupt when a scsi gross error occurs.the following conditions are considered scsi gross errors: 1. data underflow - the scsi fifo was read when no data was present. 2. data overflow - the scsi fifo was written to while full. 3. offset underflow - in target mode, a sack/ pulse was received before the corresponding sreq/ was sent. 4. offset overflow - in initiator mode, an sreq/ pulse was received which caused the maximum offset (defined by the mo3- 0 bits in the sxfer register) to be exceeded. 5. in initiator mode, a phase change occurred with an outstanding sreq/sack offset. 6. residual data in scsi fifo - a transfer other than synchronous data receive was started with data left in the scsi synchronous receive fifo. bit 2 udc (unexpected disconnect) setting this bit allows the sym53c895 to gen- erate an interrupt when an unexpected discon- nect occurs.this condition only occurs in initiator mode. it happens when the target to which the sym53c895 is connected discon- nects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scntl2 register for more information on expected versus unexpected disconnects. any disconnect in low-level mode causes this condi- tion. bit 1 rst (scsi reset condition) setting this bit allows the sym53c895 to gen- erate an interrupt when the srst/ signal has been asserted by the sym53c895 or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse. bit 0 par (scsi parity error) setting this bit allows the sym53c895 to gen- erate an interrupt when the sym53c895 detects a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scntl1 register for more information on when this condition will actually be raised. m/a cmp sel rsl sge udc rst par 76543210 default>>> 00000000
operating registers 5-40 sym53c895 data manual register 41 (c1) scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corre- sponding to the interrupting conditions described in the sist1 register. an interrupt is masked by clearing the appropriate mask bit. for more infor- mation on interrupts, refer to chapter 2, func- tional description. bits 7-5 reserved bit 4 sbmc (scsi bus mode change) setting this bit allows the sym53c895 to gen- erate an interrupt when the diffsens pin detects a change in voltage level that indicates the scsi bus has changed between single- ended, lvd, or high-power differential modes. for example, when this bit is clear and the scsi bus changes modes, irq/ does not assert and the sip bit in the istat register is not set. however, bit 4 in the sist1 register is set. set- ting this bit allows the interrupt to occur. bit 3 reserved bit 2 sto (selection or reselection time- out) setting this bit allows the sym53c895 to gen- erate an interrupt when a selection or reselec- tion timeout occurs.see the description of the stime0 register bits 3-0 for more information on the time-out periods. bit 1 gen (general purpose timer expired) setting this bit allows the sym53c895 to gen- erate an interrupt when the general purpose timer has expired. the time measured is the time between enabling and disabling of the timer. see the description of the stime1 reg- ister, bits 3-0, for more information on the general purpose timer. bit 0 hth ( handshake-to-handshake timer expired) setting this bit allows the sym53c895 to gen- erate an interrupt when the handshake-to- handshake timer has expired. the time mea- sured is the scsi request-to-request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the stime0 register, bits 7-4, for more information on the handshake-to-handshake timer. res res res sbmc res sto gen hth 76543210 default>>> xxx0x000
operating registers sym53c895 data manual 5-41 register 42 (c2) scsi interrupt status zero (sist0) read only reading the sist0 register returns the status of the various interrupt conditions, whether they are en- abled in the sien0 register or not. each bit set in- dicates that the corresponding condition has occurred. reading the sist0 will clear the inter- rupt status. reading this register will clear any bits that are set at the time the register is read, but will not neces- sarily clear the register because additional inter- rupts may be pending (the sym53c895 stacks interrupts). scsi interrupt conditions may be indi- vidually masked through the sien0 register. when performing consecutive 8-bit reads of the dstat, sist0, and sist1 registers (in any or- der), insert a delay equivalent to 12 clk periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the istat sip and dip bits may not be set, the sist0 and sist1 registers should be read before the dstat register to avoid missing a scsi inter- rupt. for more information on interrupts, refer to chapter 2, functional description. bit 7 m/a (initiator mode: phase mis- match; target mode: satn/ active) in initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in target mode, this bit is set when the satn/ signal is asserted by the initiator. bit 6 cmp (function complete) this bit is set when an arbitration only or full arbitration sequence has completed. bit 5 sel (selected) this bit is set when the sym53c895 is selected by another scsi device. the enable response to selection bit must have been set in the scid register (and the respid register must hold the chips id) for the sym53c895 to respond to selection attempts. bit 4 rsl (reselected) this bit is set when the sym53c895 is rese- lected by another scsi device. the enable response to reselection bit must have been set in the scid register (and the respid register must hold the chips id) for the sym53c895 to respond to reselection attempts. bit 3 sge (scsi gross error) this bit is set when the sym53c895 encoun- ters a scsi gross error condition. the fol- lowing conditions can result in a scsi gross error condition: 1. data underflow - the scsi fifo register was read when no data was present. 2. data overflow - too many bytes were written to the scsi fifo or the synchronous offset caused the scsi fifo to be overwritten. 3. offset underflow - the sym53c895 is operating in target mode and a sack/ pulse is received when the outstanding offset is zero. 4. offset overflow - the other scsi device sent a sreq/ or sack/ pulse with data which exceeded the maximum synchronous offset defined by the sxfer register. 5. a phase change occurred with an outstanding synchronous offset when the sym53c895 was operating as an initiator. 6. residual data in the synchronous data fifo - a transfer other than synchronous data receive was started with data left in the synchronous data fifo. m/a cmp sel rsl sge udc rst par 76543210 default>>> 00000000
operating registers 5-42 sym53c895 data manual bit 2 udc (unexpected disconnect) this bit is set when the sym53c895 is operat- ing in initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the sym53c895 operates in the initiator mode. when the sym53c895 operates in low-level mode, any disconnect will cause an interrupt, even a valid scsi disconnect. this bit will also be set if a selection time-out occurs (it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect). bit 1 rst (scsi rst/ received) this bit is set when the sym53c895 detects an active srst/ signal, whether the reset was generated external to the chip or caused by the assert srst/ bit in the scntl1 register. this sym53c895 scsi reset detection logic is edge-sensitive, so that multiple interrupts will not be generated for a single assertion of the srst/ signal. bit 0 par (parity error) this bit is set when the sym53c895 detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scntl0 register) must be set for this bit to become active. the sym53c895 always gen- erates parity when sending scsi data. register 43 (c3) scsi interrupt status one (sist1) read only reading the sist1 register returns the status of the various interrupt conditions, whether they are en- abled in the sien1 register or not. each bit that is set indicates the corresponding condition has oc- curred. reading the sist1 and sist0 registers will clear the interrupt condition. bits 7-5 reserved bit 4 sbmc (scsi bus mode change) this bit is set when the diffsens pin detects a change in voltage level that indicates the scsi bus has switched between single-ended, lvd, or high-power differential modes. bit 3 reserved bit 2 sto (selection or reselection time- out) the scsi device which the sym53c895 was attempting to select or reselect did not respond within the programmed time-out period. see the description of the stime0 register, bits 3- 0, for more information on the time-out timer. bit 1 gen (general purpose timer expired) this bit is set when the general purpose timer has expired. the time measured is the time between enabling and disabling of the timer. see the description of the stime1 register, bits 3-0, for more information on the general purpose timer. res res res sbmc res sto gen hth 76543210 default>>> xxx0x000
operating registers sym53c895 data manual 5-43 bit 0 hth (handshake-to-handshake timer expired) this bit is set when the handshake-to-hand- shake timer has expired. the time measured is the scsi request to request (target) or acknowledge to acknowledge (initiator) period. see the description of the stime0 register, bits 7-4, for more information on the handshake-to-handshake timer. register 44 (c4) scsi longitudinal parity (slpar) read/write the slpar register consists of two multiplexed bytes; other register bit settings determine what is displayed at this memory location at any given time. when bit 5 in the scntl2 (slpmd) register is cleared, the chip xors the high and low bytes of the slpar register together to give a single-byte value which is displayed in the slpar register. if the slpmd bit is set, then the slpar register shows either the high byte or the low byte of the slpar word. the slpar high byte enable bit, scntl2 bit 4, determines which byte of the slpar register is visible on the slpar register at any given time. if this bit is cleared, the slpar reg- ister contains the low byte of the slpar word; if it is set, the slpar register contains the high byte of the slpar word. this register performs a bytewise longitudinal pari- ty check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, slpar should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one check byte are received from the scsi bus (all signals are shown active high): a one in any bit position of the final slpar value would indicate a transmission error. data bytes running slpar --- 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity >>>10010110 4. 10010110 00000000
operating registers 5-44 sym53c895 data manual the slpar register can also be used to generate the check bytes for scsi send operations. if the slpar register contains all zeros prior to sending a block move, it will contain the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register resets it to zero. the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. register 45 (c5) scsi wide residue (swide) read only after a wide scsi data receive operation, this reg- ister will contain a residual data byte if the last byte received was never sent across the dma bus. it rep- resents either the first data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate.
operating registers sym53c895 data manual 5-45 register 46 (c6) memory access control (macntl) read/write bits 7-4 typ3-0 (chip type) these bits identify the chip type for software purposes. this data manual applies to devices that have these bits set to d0h. bits 3 through 0 of this register are used to deter- mine if an external bus master access is to local or far memory. when bits 3 through 0 are set, the cor- responding access is considered local and the mac/_testout pin is driven high. when these bits are clear, the corresponding access is to far memory and the mac/_testout pin is driven low. this function is enabled after a transfer con- trol scripts instruction is executed. bit 3 dwr (datawr) this bit defines if a data write is considered local memory access. bit 2 drd (datard) this bit defines if a data read is considered local memory access. bit 1 pscpt (pointer scripts) this bit defines if a pointer to a scripts indirect or table indirect fetch is considered local memory access. bit 0 scpts (scripts) this bit is used to define if a scripts fetch is considered local memory access. register 47 (c7) general purpose pin control (gpcntl) read/write this register determines if the pins controlled by the general purpose register (gpreg) are inputs or outputs. bits 4-0 in gpcntl correspond to bits 4-0 in the gpreg register. bit 7 me (master enable) the internal bus master signal will be pre- sented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1_en). bit 6 fe (fetch enable) the internal op code fetch signal will be pre- sented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0_en). bit 5 res (reserved) bits 4-2 gpio4_enCgpio2_en (gpio enable) general purpose control, corresponding to bits 4-2 in the gpreg register and pins 67-65. gpio4 powers up as a general purpose output, and gpio3-2 power up as general purpose inputs. bits 1-0 gpio1_enC gpio0_en (gpio enable) these bits power up set, causing the gpio1 and gpio0 pins to become inputs. resetting these bits causes gpio1-0 to become outputs. typ3 typ2 typ1 typ0 dwr drd pscpt scpts 76543210 default>>> 11010000 me fe res gpio4 gpio3 gpio2 gpio1 gpio0 76543210 default>>> 00x01111
operating registers 5-46 sym53c895 data manual register 48 (c8) scsi timer zero (stime0) read /write bits 7-4 hth (handshake-to-handshake timer period) these bits select the handshake-to-handshake time-out period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the sist1 regis- ter is set. the following table contains time-out periods for the handshake-to-handshake timer, the selection/reselection timer (bits 3-0), and the general purpose timer (stime1 bits 3-0). for a more detailed expla- nation of interrupts, refer to chapter 2, func- tional description. bits 3-0 sel (selection time-out) these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 m s selection abort time) is exceeded, the sto bit in the sist1 register is set. for a more detailed explanation of interrupts, refer to chapter 2, functional description. hth hth hth hth sel sel sel sel 76543210 default>>> 00000000 table 5-9: handshake-to handshake timer period hth 7-4, sel 3-0, gen 3-0 minimum time-out (40 or 160 mhz) 0000 disabled 0001 125 m s 0010 250 m s 0011 500 m s 0100 1 ms 0101 2 ms 0110 4 ms 0111 8 ms 1000 16 ms 1001 32 ms 1010 64 ms 1011 128 ms 1100 256 ms 1101 512 ms 1110 1.024 sec 1111 2.048 sec these values will be correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. a quadrupled 40 mhz clock is required for ultra2 scsi operation.
operating registers sym53c895 data manual 5-47 register 49 (c9) scsi timer one (stime1) read/write bit 7 reserved bit 6 hthba (handshake-to-handshake timer bus activity enable) setting this bit causes this timer to begin test- ing for scsi req/ack activity as soon as sbsy/ is asserted, regardless of the agents par- ticipating in the transfer. bit 5 gensf (general purpose timer scale factor) setting this bit causes this timer to shift by a factor of 16. res hthba gensf hthsf gen3 gen2 gen1 gen0 76543210 default>>> x0000000 table 5-10: time-out periods, 50 mhz clock hth 7-4, sel 3-0, gen 3-0 minimum time-out (50 mhz clock*) gensf= 0 gensf=1 0000 disabled disabled 0001 100 m s1.6 ms 0010 200 m s3.2 ms 0011 400 m s6.4 ms 0100 800 m s 12.8 ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 sec 1100 204.8 ms 3.2 sec 1101 409.6 ms 6.4 sec 1110 819.2 ms 12.8 sec 1111 1.6 sec 25.6 sec table 5-11: time-out periods, 40/160 mhz clock hth 7-4, sel 3-0, gen 3-0 minimum time-out (40 or 160 mhz clock) gensf= 0 gensf=1 0000 disabled disabled 0001 125 m s2 ms 0010 250 m s4 ms 0011 500 m s8 ms 0100 1 m s 16 ms 0101 2 ms 32 ms 0110 4 ms 64 ms 0111 8 ms 128 ms 1000 16 ms 256 ms 1001 32 ms 512 ms 1010 64 ms 1 sec 1011 128 ms 2 sec 1100 256 ms 4.1 sec 1101 512 ms 8.2 sec 1110 1.024 sec 16.4 sec 1111 2.048 sec 32.8 sec these values will be correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. ultra2 scsi operation requires a quadrupled 40 mhz clock. table 5-10: time-out periods, 50 mhz clock hth 7-4, sel 3-0, gen 3-0 minimum time-out (50 mhz clock*) gensf= 0 gensf=1 these values will be correct if the ccf bits in the scntl3 register are set according to the valid combinations in the bit description. *50 mhz clock is not supported for ultra2 scsi opera- tion.
operating registers 5-48 sym53c895 data manual bit 4 hthsf (handshake to handshake timer scale factor) setting this bit causes this timer to shift by a factor of 16. bits 3-0 gen3-0 (general purpose timer period) these bits select the period of the general pur- pose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the sist1 register is set. refer to the table under stime0, bits 3-0, for the available time-out periods. note: to reset a timer before it has expired and obtain repeatable delays, the time value must be written to zero first, and then written back to the desired value. this is also required when changing from one time value to another. see chapter 2, functional description, for an explanation of how interrupts will be generated when the timers expire. register 4a (ca) response id zero (respid0) read/write register 4b (cb) response id one(respid1) read/write respid0 and respid1 contain the selection or reselection ids. in other words, these two 8-bit reg- isters contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most significant bit of respid1 represent- ing id 15 and the least significant bit of respid0 representing id 0. the scid register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the chip can arbitrate with only one id value in the scid register.
operating registers sym53c895 data manual 5-49 register 4c (cc) scsi test zero (stest0) read only bits 7-4 ssaid (scsi selected as id) these bits contain the encoded value of the scsi id that the sym53c895 was selected or reselected as during a scsi selection or rese- lection phase. these bits are read only and contain the encoded value of 0-15 possible ids that could be used to select the sym53c895. during a scsi selection or reselection phase when a valid id has been put on the bus, and the sym53c895 responds to that id, the selected as id is written into these bits. these bits are used with the respid registers to allow response to multiple ids on the bus. bit 3 slt (selection response logic test) this bit is set when the sym53c895 is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. bit 2 art (arbitration priority encoder te s t ) this bit will always be set when the sym53c895 exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing, but it may be used during low-level mode operation to determine if the sym53c895 has won arbi- tration. bit 1 soz (scsi synchronous offset zero) this bit indicates that the current synchronous sreq/sack offset is zero. this bit is not latched and may change at any time. it is used in low-level synchronous scsi operations. when this bit is set, the sym53c895, as an initiator, is waiting for the target to request data transfers. if the sym53c895 is a target, then the initiator has sent the offset number of acknowledges. bit 0 som (scsi synchronous offset maximum) this bit indicates that the current synchronous sreq/sack offset is the maximum specified by bits 3-0 in the scsi transfer register. this bit is not latched and may change at any time. it is used in low-level synchronous scsi opera- tions. when this bit is set, the sym53c895, as a target, is waiting for the initiator to acknowl- edge the data transfers. if the sym53c895 is an initiator, then the target has sent the offset number of requests. ssaid3 ssaid2 ssaid1 ssaid0 slt art soz som 76543210 default>>> 00000x11
operating registers 5-50 sym53c895 data manual register 4d (cd) scsi test one (stest1) read/write bit 7 sclk setting this bit will disable the external sclk (scsi clock) pin and the internal scsi clock quadrupler, and the chip will use the pci clock as the internal scsi clock. if a transfer rate of 10 mb/s (or 20 mb/s on a wide scsi bus) is to be achieved on the scsi bus, this bit must be reset and at least a 40 mhz external sclk must be provided. bit 6 siso (scsi isolation mode) this bit allows the sym53c895 to put the scsi bi-directional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. bits 5-4 reserved bit 3 qen (sclk quadrupler enable) set this bit to bring the scsi clock quadrupler out of the powered-down state. the default value of this bit is clear (scsi clock quadrupler powered down). set bit 2 after setting this bit, to increase the sclk frequency to 160 mhz. bit 2 qsel (sclk quadrupler select) set this bit after powering up the scsi clock quadrupler to increase the sclk frequency to 160 mhz. this bit has no effect unless bit 3 is set. bits 1-0 reserved quadrupling the scsi clock frequency the sym53c895 scsi clock quadrupler increases the frequency of a 40 mhz scsi clock to 160 mhz. follow these steps to use the clock quadru- pler: 1. set the sclk quadrupler enable bit (stest1, bit 3). 2. poll bit 5 of the stest4 register. the sym53c895 sets this bit as soon as it locks in the 160 mhz frequency. the frequency lockup takes approximately 100 microseconds. 3. halt the scsi clock by setting the halt scsi clock bit (stest3 bit 5). 4. set the clock conversion factor using the scf and ccf fields in the scntl3 register. 5. set the sclk quadrupler select bit (stest1, bit2). 6. clear the halt scsi clock bit. sclk siso res res qen qsel res res 76543210 default>>> 00xx00xx
operating registers sym53c895 data manual 5-51 register 4e (ce) scsi test two (stest2) read/write bit 7 sce (scsi control enable) setting this bit allows all scsi control and data lines to be asserted through the socl and sodl registers regardless of whether the sym53c895 is configured as a target or initia- tor. note: this bit should not be set during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. bit 6 rof (reset scsi offset) setting this bit clears any outstanding synchro- nous sreq/sack offset. this bit should be set if a scsi gross error condition occurs, to clear the offset when a synchronous transfer does not complete successfully. the bit auto- matically clears itself after resetting the syn- chronous offset. bit 5 dif (scsi differential mode) setting this bit allows the sym53c895 to interface properly to external differential trans- ceivers. its only real effect is to tri-state the sbsy/, ssel/, and srst/ pads so that they can be used as pure inputs. this bit must be cleared for single-ended or lvd operation. this bit should be set in the initialization rou- tine if the high voltage differential interface is used. bit 4 slb (scsi loopback mode) setting this bit allows the sym53c895 to per- form scsi loopback diagnostics. that is, it enables the scsi core to simultaneously per- form as both initiator and target. bit 3 szm (scsi high-impedance mode) setting this bit places all the open-drain 48 ma scsi drivers into a high-impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. bit 2 aws (always wide scsi) when this bit is set, all scsi information transfers will be done in 16-bit wide mode. this includes data, message, command, status and reserved phases. this bit should normally be deasserted since 16-bit wide message, com- mand, and status phases are not supported by the scsi specifications. bit 1 ext (extend sreq/sack filter- ing) symbios tolerant scsi receiver technology includes a special digital filter on the sreq/ and sack/ pins which will cause glitches on deasserting edges to be disregarded. setting this bit will increase the filtering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals. note: this bit must never be set during fast scsi (greater than 5m transfers per second) operations, because a valid assertion could be treated as a glitch. note: this bit does not affect the filtering period when the ultra enable bit in the scntl3 register is set. when the sym53c895 is executing ultra2 scsi transfers, the filtering period is automatically set at 8 ns. when the sym53c895 is executing ultra scsi transfers, the filtering period is automatically set at 15 ns. bit 0 low (scsi low level mode) setting this bit places the sym53c895 in low- level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scntl0 register. scsi bus transfers are performed by sce rof dif slb szm aws ext low 76543210 default>>> 00000000
operating registers 5-52 sym53c895 data manual manually asserting and polling scsi signals. clearing this bit allows instructions to be exe- cuted in scsi scripts mode. note: it is not necessary to set this bit for access to the scsi bit-level registers (sodl, sbcl, and input registers). register 4f (cf) scsi test three (stest3) read/write bit 7 te (tolerant enable) setting this bit enables the active negation por- tion of symbios tolerant technology. active negation causes the scsi request, acknowl- edge, data, and parity signals to be actively deasserted, instead of relying on external pull- ups, when the sym53c895 is driving these signals. active deassertion of these signals will occur only when the sym53c895 is in an information transfer phase. when operating in a differential environment or at fast scsi tim- ings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on symbios tolerant technology, refer to chapter 1. note: this bit must be set if the ultra enable bit in scntl3 is set. note: this bit must be set to use the lvdlink transceivers. bit 6 str (scsi fifo test read) setting this bit places the scsi core into a test mode in which the scsi fifo can be easily read. reading the least significant byte of the sodl register will cause the fifo to unload. the functions are summarized in the table below. te str hsc dsi s16 ttm csf stw 76543210 default>>> 00000000 register name register operation fifo bits fifo function sodl read 15-0 unload sodl0 read 7-0 unload sodl1 read 15-8 none
operating registers sym53c895 data manual 5-53 bit 5 hsc (halt scsi clock) asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit may be used for test purposes or to lower i dd during a power down mode. this bit is used when enabling the scsi clock quadrupler. for additional information on the clock quadrupler, please see using the scsi clock quadrupler in chapter 2. bit 4 dsi (disable single initiator response) if this bit is set, the sym53c895 will ignore all bus-initiated selection attempts that employ the single-initiator option from scsi-1. in order to select the sym53c895 while this bit is set, the sym53c895s scsi id and the initiators scsi id must both be asserted. this bit should be asserted in scsi-2 systems so that a single bit error on the scsi bus will not be interpreted as a single initiator response. bit 3 s16 (16-bit system) if this bit is set, all devices in the scsi system implementation are assumed to be 16 bits. this causes the sym53c895 to always check the parity bit for scsi ids 15-8 during bus- initiated selection or reselection, assuming par- ity checking has been enabled. if an 8-bit scsi device attempts to select the sym53c895 while this bit is set, the sym53c895 will ignore the selection attempt, because the parity bit for ids 15-8 will be undriven. see the description of the enable parity checking bit in the scntl0 register for more information. bit 2 ttm (timer test mode) asserting this bit facilitates testing of the selec- tion time-out, general purpose, and hand- shake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers and if the respective bits in the sien1 register are asserted, the sym53c895 will generate interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used. bit 1 csf (clear scsi fifo) setting this bit will cause the full flags for the scsi fifo to be cleared. this empties the fifo. this bit is self-resetting. in addition to the scsi fifo pointers, the sidl, sodl, and sodr full bits in the sstat0 and sstat2 are cleared. bit 0 stw (scsi fifo test write) setting this bit places the scsi core into a test mode in which the fifo can easily be read or written. while this bit is set, writes to the least significant byte of the sodl register will cause the entire word contained in this register to be loaded into the fifo. writing the least signifi- cant byte of the sodl register will cause the fifo to load. these functions are summarized in the table below: register name register operation fifo bits fifo function sodl write 15-0 load sodl0 write 7-0 load sodl1 write 15-8 none
operating registers 5-54 sym53c895 data manual register 50-51 (d0-d1) scsi input data latch (sidl) read only this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data received from the scsi bus can be read from this register. data can be written to the sodl register and then read back into the sym53c895 by read- ing this register to allow loopback testing. when re- ceiving scsi data, the data will flow into this register and out to the host fifo. this register dif- fers from the sbdl register; sidl contains latched data and the sbdl always contains exactly what is currently on the scsi data bus. reading this regis- ter causes the scsi parity bit to be checked, and will cause a parity error interrupt if the data is not valid. the power-up values are indeterminate. register 52 (d2) scsi test 4 (stest4) read only bit 7-6 smode (scsi mode) these bits contain the encoded value of the scsi operating mode that is indicated by the voltage level sensed at the diffsens pin. the incoming scsi signal goes to a pair of analog comparators that determine the voltage window of the diffsens signal. these volt- age windows indicate lvd, single-ended, or high-power differential operation. the bit val- ues are defined in table 5-12. bit 5 lock (frequency lock) this bit is used when enabling the scsi clock quadrupler, which allows the sym53c895 to transfer data at ultra2 scsi rates. poll this bit for a 1 to determine that the clock quadrupler has locked to 160 mhz. for more information on enabling the clock quadrupler, refer to the descriptions for stest1, bits 2 and 3. bits 4-0 reserved smode lock res res res res res 76543210 default>>> xx0xxxxx table 5-12: diffsens voltage levels and scsi operating modes bit 7, bit 6 operating mode 00 not possible 01 high voltage differential or powered down (for high voltage differential mode, the dif bit must also be set) 10 single-ended 11 lvd scsi
operating registers sym53c895 data manual 5-55 registers 54-55 (d4-d5) scsi output data latch (sodl) read/write this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by set- ting the assert data bus bit in the scntl1 regis- ter. this register sends data via programmed i/o. data flows through this register when sending data in any mode. it is also used to write to the synchro- nous data fifo when testing the chip. the power- up value of this register is indeterminate. registers 58-59 (d8-d9) scsi bus data lines (sbdl) read only this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this regis- ter is used when receiving data via programmed i/o. this register can also be used for diagnostic testing or in low-level mode. the power-up value of this register is indeterminate.
operating registers 5-56 sym53c895 data manual registers 5c-5f (dc-df) scratch register b (scratchb) (read/write) this is a general purpose user definable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register will alter its contents. the sym53c895 cannot fetch scripts instructions from this location.when bit 3 in the ctest2 reg- ister is set, this register contains the base address for the 4 kb internal ram. setting ctest2 bit 3 only causes the base address to appear in the scratchb register; any information that was previously in the register will remain intact. any writes to this register while the bit is set will pass through to the actual scratchb register. the power-up values are indeterminate. registers 60h-7fh (e0h-ffh) scratch registers c-j (scratchc-scratchj) read/write these registers are general-purpose scratch regis- ters for user-defined functions. the sym53c895 cannot fetch scripts instructions from this loca- tion.the power-up value of these registers is inde- terminate.
instruction set of the i/o processor scsi scripts sym53c895 data manual 6-1 chapter 6 instruction set of the i/o processor after power up and initialization of the sym53c895, the chip may be operated in the low level register interface mode, or using scsi scripts. with the low-level register interface, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low-level dma sig- nals, which allows creation of complicated board level test algorithms. the low-level interface is use- ful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chips pins. scsi scripts to operate in the scsi scripts mode, the sym53c895 requires only a scripts start address. the start address must be at a dword (four byte) boundary. this will align all the follow- ing scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encoun- tered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the sym53c895 halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the sym53c895 to make decisions based on the sta- tus of the scsi bus, which off-loads the micropro- cessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi-oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery should never be required. the following types of scripts instructions are implemented in the sym53c895: n block moveused to move data between the scsi bus and memory n i/o or read/writecauses the sym53c895 to trigger common scsi hardware sequences, or to move registers n transfer controlallows scripts instructions to make decisions based on real time scsi bus conditions n memory movecauses the sym53c895 to execute block moves between different parts of main memory n load and storeprovides a more efficient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction each instruction consists of two or three 32-bit words. the first 32-bit word is always loaded into the dcmd and dbc registers, the second into the dsps register. the third word, used only by memory move instructions, is loaded into the temp shadow register. in an indirect i/o or move instruction, the first two 32-bit op code fetches will be followed by one or two more 32-bit fetch cycles.
instruction set of the i/o processor scsi scripts 6-2 sym53c895 data manual sample operation the following example describes execution of a scripts instruction. this sample operation is for a block move instruction. 1. the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register file) the starting address in main memory that points to a scsi scripts program for execution. 2. loading the dsp register causes the sym53c895 to fetch its first instruction at the address just loaded. this will be from main memory or the internal ram, depending on the address. 3. the sym53c895 typically fetches two dwords (64 bits) and decodes the high order byte of the first longword as a scripts instruction. if the instruction is a block move, the lower three bytes of the first longword are stored and interpreted as the number of bytes to be moved. the second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. 4. for a scsi send operation, the sym53c895 waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the sym53c895 requests use of the pci bus again to transfer the data. 5. when the sym53c895 is granted the pci bus, it will execute (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then release the pci bus. the sym53c895 stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the sym53c895 releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer register. execution of scripts instruc- tions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the sym53c895 interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and start- ing locations in main memory. in this manner, the sym53c895 performs scatter/gather operations on data without requiring help from the host pro- gram, generating a host interrupt, or requiring an external dma controller to be programmed.
instruction set of the i/o processor scsi scripts sym53c895 data manual 6-3 figure 6-1: scripts overview system processor system memory sym53c895 scsi bus scsi initiator write example select atn 0, alt_addr move from identify_msg_buf, when msg_out move from cmd_buf, when cmd move from data_buf, when data_out move from stat_in_buf, when status move from msg_in_buf, when msg_in move scntl2&7f to scntl2 clear ack wait disconnect alt2 int 10 data structure message buffer command buffer data buffer status buffer s y s t e m b u s write dsp fetch scripts data table byte count address byte count address byte count address byte count address write dsa
instruction set of the i/o processor block move instructions 6-4 sym53c895 data manual block move instructions for block move instructions, bits 5 and 4 (siom and diom) in the dmode register determine whether the source/destination address resides in memory or i/o space. when data is being moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is being moved off of the scsi bus, diom con- trols whether that data goes to i/o or memory space. first dword bits 31-30 instruction type-block move bit 29 indirect addressing when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chips address register and incre- mented as data is transferred. the address of the data to be moved is in the second dword of this instruction. when set, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chips dnad register via a third longword fetch (4- byte transfer across the host computer bus). direct the byte count and absolute address are as fol- lows. indirect use the fetched byte count, but fetch the data address from the address in the instruction. command byte count address of data command byte count address of pointer to data once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows a table of data buffer addresses to be specified. using the symbios scsi scripts assembler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. this feature makes it pos- sible to locate scsi scripts in a prom. note: indirect and table indirect addressing cannot be used simultaneously; only one addressing method may be used at a time. bit 28 table indirect when this bit is set, the 24-bit signed value in the start address of the move is treated as a rel- ative displacement from the value in the dsa register. both the transfer count and the source/destination address are fetched from this address. use the signed integer offset in bits 23-0 of the second four bytes of the instruction, added to the value in the dsa register, to fetch first the byte count and then the data address. the signed value is combined with the data struc- ture base address to generate the physical address used to fetch values from the data structure. sign-extended values of all ones for negative values are allowed, but bits 31-24 are ignored. note: indirect and table indirect addressing cannot be used simultaneously; only one addressing method may be used at a time. command not used dont care table offset
instruction set of the i/o processor block move instructions sym53c895 data manual 6-5 prior to the start of an i/o, the data structure base address register (dsa) should be loaded with the base address of the i/o data structure. the address may be any address on a long word boundary. after a table indirect op code is fetched, the dsa is added to the 24-bit signed offset value from the op code to generate the address of the required data; both positive and negative off- sets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32- bit physical address is brought into the sym53c895. execution of the move begins at this point. figure 6-2: block move instruction register 24-bit block move byte counter i/o c/d msg/ op code table indirect addressing indirect addressing (53c700 compatible) 0 - instruction type - block move 0 - instruction type - block move dcmd register dbc register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dsps register scripts can directly execute operating sys- tem i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: the eight bytes of data in the move instruction must be con- tiguous, as shown below; and indirect data fetches are not available during execution of a memory-to-memory dma operation. 00 byte count physical data address
instruction set of the i/o processor block move instructions 6-6 sym53c895 data manual bit 27 op code this 1-bit field defines the instruction to be executed as a block move (move). target mode 1. the sym53c895 verifies that it is connected to the scsi bus as a target before executing this instruction. 2. the sym53c895 asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as defined by the phase field bits in the instruction. 3. if the instruction is for the command phase, the sym53c895 receives the first command byte and decodes its scsi group code. a) if the scsi group code is either group 0, group 1, group 2, or group 5, and if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is clear, then the sym53c895 overwrites the dbc register with the length of the command descriptor block: 6, 10, or 12 bytes. b) if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is set, the sym53c895 receives the number of bytes in the byte count regardless of the group code. c) if the vendor unique enhancement 1 bit is clear and group code is vendor unique, the sym53c895 receives the number of bytes in the count. d) if any other group code is received, the dbc register is not modified and the sym53c895 will request the number of bytes specified in the dbc register. if the dbc register contains 000000h, an illegal instruction interrupt is generated. 4. the sym53c895 transfers the number of opc instruction defined 0move 1chmov bytes specified in the dbc register starting at the address specified in the dnad register. if the op code bit is set and a data transfer ends on an odd byte boundary, the sym53c895 will store the last byte in the scsi wide residue data register during a receive operation. this byte will be combined with the first byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scntl1 register controls whether the sym53c895 will halt on these conditions immediately, or wait until completion of the current move. initiator mode 1. the sym53c895 verifies that it is connected to the scsi bus as an initiator before executing this instruction. 2. the sym53c895 waits for an unserviced phase to occur. an unserviced phase is defined as any phase (with sreq/ asserted) for which the sym53c895 has not yet transferred data by responding with a sack/. 3. the sym53c895 compares the scsi phase bits in the dcmd register with the latched scsi phase lines stored in the sstat1 register. these phase lines are latched when sreq/ is asserted. 4. if the scsi phase bits match the value stored in the sstat1 register, the sym53c895 will transfer the number of bytes specified in the dbc register starting at the address pointed to by the dnad register. if the op code bit is cleared and a data transfer ends on an odd byte opc instruction defined 0chmov 1move
instruction set of the i/o processor block move instructions sym53c895 data manual 6-7 boundary, the sym53c895 will store the last byte in the scsi wide residue data register during a receive operation, or in the scsi output data latch register during a send operation. this byte will be combined with the first byte from the subsequent transfer so that a wide transfer can be completed. 5. if the scsi phase bits do not match the value stored in the sstat1 register, the sym53c895 generates a phase mismatch interrupt and the instruction is not executed. 6. during a message out phase, after the sym53c895 has performed a select with attention (or satn/ has been manually asserted with a set atn instruction), the sym53c895 will deassert satn/ during the final sreq/sack handshake. 7. when the sym53c895 is performing a block move for message in phase, it will not deassert the sack/ signal for the last sreq/sack handshake. the sack signal must be cleared using the clear sack i/o instruction. bits 26-24 scsi phase this 3-bit field defines the desired scsi infor- mation transfer phase. when the sym53c895 operates in initiator mode, these bits are com- pared with the latched scsi phase bits in the sstat1 register. when the sym53c895 operates in target mode, the sym53c895 asserts the phase defined in this field. the fol- lowing table describes the possible combina- tions and the corresponding scsi phase. bits 23-0 transfer counter this 24-bit field specifies the number of data bytes to be moved between the sym53c895 and system memory. the field is stored in the dbc register. when the sym53c895 trans- fers data to/from memory, the dbc register is decremented by the number of bytes trans- ferred. in addition, the dnad register is incremented by the number of bytes trans- ferred. this process is repeated until the dbc register has been decremented to zero. at that time, the sym53c895 fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this field is not used. the byte count is instead fetched from a table pointed to by the dsa register. msg c/d i/o scsi phase 0 0 0 data out 0 0 1 data in 0 1 0 command 0 1 1 status 1 0 0 reserved out 1 0 1 reserved in 1 1 0 message out 1 1 1 message in
instruction set of the i/o processor i/o instructions 6-8 sym53c895 data manual second dword bits 31-0 start address this 32-bit field specifies the starting address of the data to be moved to/from memory. this field is copied to the dnad register. when the sym53c895 transfers data to or from mem- ory, the dnad register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect address- ing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect address- ing, the value in this field is an offset into a table pointed to by the dsa. the table entry contains byte count and address information. i/o instructions first dword bits 31-30 instruction type - i/o instruction bits 29-27 op code the following op code bits have different meanings, depending on whether the sym53c895 is operating in initiator or target mode. note: op code selections 101-111 are considered read/write instructions, and are described in that section. target mode reselect instruction 1. the sym53c895 arbitrates for the scsi bus by asserting the scsi id stored in the scid register. if the sym53c895 loses arbitration, opc2 opc1 opc0 instruction defined 0 0 0 reselect 0 0 1 disconnect 010wait select 011set 100clear then it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the sym53c895 wins arbitration, it attempts to reselect the scsi device whose id is defined in the destination id field of the instruction. once the sym53c895 has won arbitration, it fetches the next instruction from the address pointed to by the dsp register. therefore, the scripts can move on to the next instructions before the reselection has completed. it will continue executing scripts until a script that requires a response from the initiator is encountered. 3. if the sym53c895 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. the sym53c895 should manually be set to initiator mode if it is reselected, or to target mode if it is selected. disconnect instruction the sym53c895 disconnects from the scsi bus by deasserting all scsi signal outputs. wait select instruction 1. if the sym53c895 is selected, it fetches the next instruction from the address pointed to by the dsp register. 2. if reselected, the sym53c895 fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. the sym53c895 should manually be set to initiator mode when reselected. 3. if the cpu sets the sigp bit in the istat register, the sym53c895 will abort the wait select instruction and fetch the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. set instruction when the sack/ or satn/ bits are set, the corre- sponding bits in the socl register are set. sack/ or satn/ should not be set except for testing pur-
instruction set of the i/o processor i/o instructions sym53c895 data manual 6-9 poses. when the target bit is set, the corresponding bit in the scntl0 register is also set. when the carry bit is set, the corresponding bit in the arith- metic logic unit (alu) is set. note: none of the signals are set on the scsi bus in target mode. clear instruction when the sack/ or satn/ bits are set, the corre- sponding bits are cleared in the socl register. sack/ or satn/ should not be set except for test- ing purposes. when the target bit is set, the corre- sponding bit in the scntl0 register is cleared. when the carry bit is set, the corresponding bit in the alu is cleared. note: the clear instruction does not cause any of the scsi bus signals to be reset when the sym53c895 is in target mode.
instruction set of the i/o processor i/o instructions 6-10 sym53c895 data manual figure 6-3: i/o instruction register encoded destination id 0 encoded destination id 1 encoded destination id 2 encoded destination id 3 reserved reserved reserved reserved select with atn/ set/clear ack/ set/clear atn/ set/clear target mode res table indirect mode relative address mode op code bit 0 op code bit 1 op code bit 2 1 - instruction type - i/o 0 - instruction type - i/o dcmdregister dbc register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dsps register res res res set/clear carry second 32-bit word of the i/o instruction 32-bit jump address
instruction set of the i/o processor i/o instructions sym53c895 data manual 6-11 initiator mode select instruction 1. the sym53c895 arbitrates for the scsi bus by asserting the scsi id stored in the scid register. if the sym53c895 loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the sym53c895 wins arbitration, it attempts to select the scsi device whose id is defined in the destination id field of the instruction. once the sym53c895 has won arbitration, it fetches the next instruction from the address pointed to by the dsp register. therefore, the scripts can move to the next instruction before the selection has completed. it will continue executing scripts until a script that requires a response from the target is encountered. 3. if the sym53c895 is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. the sym53c895 should manually be set to initiator mode if it is reselected, or to target mode if it is selected. 4. if the select with satn/ field is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the sym53c895 waits for the target to perform a legal disconnect from the scsi bus. a legal disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the sym53c895 has received a discon- nect message or a command complete message. wait reselect instruction 1. if the sym53c895 is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. the sym53c895 should be manually set to target mode when selected. 2. if the sym53c895 is reselected, it fetches the next instruction from the address pointed to by the dsp register. 3. if the cpu sets the sigp bit in the istat register, the sym53c895 will abort the wait reselect instruction and fetch the next instruction from the address pointed to by the 32-bit jump address field stored in the dnad register. set instruction when the sack/ or satn/ bits are set, the corre- sponding bits in the socl register are set. when the target bit is set, the corresponding bit in the scntl0 register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/or satn/ bits are set, the corre- sponding bits are cleared in the socl register. when the target bit is set, the corresponding bit in the scntl0 register is cleared. when the carry bit is set, the corresponding bit in the alu is cleared. bit 26 relative addressing mode when this bit is set, the 24-bit signed value in the dnad register is used as a relative dis- placement from the current dsp address. this bit should only be used in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instruc- tions can contain an absolute alternate jump address or a relative transfer address. bit 25 table indirect mode when this bit is set, the 24-bit signed value in the dbc register is added to the value in the dsa register, used as an offset relative to the value in the data structure base address (dsa) register. the scntl3 value, scsi id, opc2 opc1 opc0 instruction defined 0 0 0 select 0 0 1 wait disconnect 010wait reselect 011set 100clear
instruction set of the i/o processor i/o instructions 6-12 sym53c895 data manual synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, the dsa should be loaded with the base address of the i/o data structure. the address may be any address on a longword boundary. after a table indirect op code is fetched, the dsa is added to the 24-bit signed offset value from the op code to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating sys- tem i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: 1. the i/o data structure must lie within the 8 mb above or below the base address. 2. an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the sxfer register. the configuration bits are ordered as in the scntl3 register. this bit should only be used in conjunction with the select, reselect, wait select, and wait reselect instructions. bits 25 and 26 may be set individually or in combination: direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous off- set, and synchronous period indirectly. adds the value in bits 23-0 of the first four bytes of the scripts instruction to the data structure base address to form the fetch address. bit 24 select with atn/ this bit specifies whether satn/ will be asserted during the selection phase when the sym53c895 is executing a select instruction. config id offset/ period (00) bit 25 bit 26 direct 0 0 table indirect 0 1 relative 1 0 ta b l e r e l a t i v e 1 1 command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used alternate jump offset command table offset alternate jump offset
instruction set of the i/o processor read/write instructions sym53c895 data manual 6-13 when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. bits 23-20 reserved bits 19-16 encoded scsi destination id this 4-bit field specifies the destination scsi id for an i/o instruction. bits 15-11reserved bit 10 set/clear carry this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. setting this bit with a clear instruction deasserts the carry bit in the alu. bits 8-7 reserved bit 9 set/clear target mode this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction config- ures the sym53c895 as a target device (this sets bit 0 of the scntl0 register). setting this bit with a clear instruction configures the sym53c895 as an initiator device (this clears bit 0 of the scntl0 register). bit 6 set/clear sack/ bit 3 set/clear satn/ these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal; bit 3 controls the scsi satn/ signal. setting either of these bits will set or reset the corresponding bit in the socl register, depending on the instruction used. the set instruction is used to assert sack/ and/or satn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. since sack/ and satn/ are initiator signals, they will not be asserted on the scsi bus unless the sym53c895 is operating as an initi- ator or the scsi loopback enable bit is set in the stest2 register. the set/clear scsi ack/atn instruction would be used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, an assert scsi atn instruction would be issued before a clear scsi ack instruction. bits 2-0 reserved second dword bits 31-0 start address this 32-bit field contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dsp register value. read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the specified register and the sfbr register, then stores the result back to the specified register or the sfbr. first dword bits 31-30 instruction type - read/write instruction the read/write instruction uses operator bits 26 through 24 in conjunction with the op code bits to determine which instruction is currently selected.
instruction set of the i/o processor read/write instructions 6-14 sym53c895 data manual figure 6-4: read/write instruction register a0 a1 a2 a3 a4 a5 a6 use data8/sfbr operator 0 immediate data operator 1 operator 2 op code bit 0 op code bit 1 op code bit 2 1 - instruction type - r/w 0 - instruction type - r/w dcmd register dbc register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dsps register reserved (must be 0) register address a7
instruction set of the i/o processor read/write instructions sym53c895 data manual 6-15 bits 29-27 op code the combinations of these bits determine if the instruction is a read/write or an i/o instruc- tion. op codes 000 through 100 are considered i/o instructions. bits 26-24 operator these bits are used in conjunction with the op code bits to determine which instruction is cur- rently selected. refer to table 6-1 for field defi- nitions. bit 23 use data8/sfbr when this bit is set, sfbr will be used instead of the data8 value during a read-modify-write instruction (see table 6-1). this allows the user to add two register values. bits 22-16 register address - a(6-0) register values may be changed from scripts in read-modify-write cycles or move to/from sfbr cycles. a(6-0) select an 8-bit source/destination register within the sym53c895. bits 15-8 immediate data this 8-bit value is used as a second operand in logical and arithmetic functions. bits 7-0 reserved second dword bits 31-0 destination address this field contains the 32-bit destination address where the data is to be moved. read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation can be used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. subtraction is not available when sfbr is used instead of data8 in the instruction syntax. to sub- tract one value from another when using sfbr, first xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this cre- ates the 2s compliment of the subtrahend. the two values can then be added to obtain the differ- ence. move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the sfbr. the possible functions of this instruc- tion are: n write one byte (value contained within the scripts instruction) into any chip register. n move to/from the sfbr from/to any other register. n alter the value of a register with and/or/ add/xor/shift left/shift right operators. n after moving values to the sfbr, the compare and jump, call, or similar instructions may be used to check the value. n a move-to-sfbr followed by a move-from- sfbr can be used to perform a register to register move.
instruction set of the i/o processor read/write instructions 6-16 sym53c895 data manual table 6-1: read/write instructions operator op code 111 read modify write op code 110 move to sfbr op code 101 move from sfbr 000 move data into register. syntax: move data8 to rega move data into sfbr regis- ter. syntax: move data8 to sfbr move data into register. syntax: move data8 to rega 001* shift register one bit to the left and place the result in the same register. syntax: move rega shl rega shift register one bit to the left and place the result in the sfbr register. syntax: move rega shl sfbr shift the sfbr register one bit to the left and place the result in the register. syntax: move sfbr shl rega 010 or data with register and place the result in the same register. syntax: move rega | data8 to rega or data with register and place the result in the sfbr register. syntax: move rega | data8 to sfbr or data with sfbr and place the result in the regis- ter. syntax: move sfbr | data8 to rega 011 xor data with register and place the result in the same register. syntax: move rega xor data8 to rega xor data with register and place the result in the sfbr register. syntax: move rega xor data8 to sfbr xor data with sfbr and place the result in the regis- ter. syntax: move sfbr xor data8 to rega 100 and data with register and place the result in the same register. syntax: move rega & data8 to rega and data with register and place the result in the sfbr register. syntax: move rega & data8 to sfbr and data with sfbr and place the result in the regis- ter. syntax: move sfbr & data8 to rega 101* shift register one bit to the right and place the result in the same register. syntax: move rega shr rega shift register one bit to the right and place the result in the sfbr register. syntax: move rega shr sfbr shift the sfbr register one bit to the right and place the result in the register. syntax: move sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: move rega + data8 to rega add data to register without carry and place the result in the sfbr register. syntax: move rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: move sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: move rega + data8 to rega with carry add data to register with carry and place the result in the sfbr register. syntax: move rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: move sfbr + data8 to rega with carry notes: 1. substitute the desired register name or address for rega in the syntax examples 2. data8 indicates eight bits of data 3. use sfbr instead of data8 to operate on two register values. * data is shifted through the carry bit and the carry bit is shifted into the data byte
instruction set of the i/o processor transfer control instructions sym53c895 data manual 6-17 transfer control instructions first dword bits 31-30 instruction type - transfer control instruction bits 29-27 op code this 3-bit field specifies the type of transfer control instruction to be executed. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase field, and/or a comparison of the first byte received with the data compare field. each instruction can operate in initiator or tar- get mode. jump instruction 1. the sym53c895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare and true/false bit fields. if the comparisons are true, the sym53c895 loads the dsp register with the contents of the dsps register. the dsp register now contains the address of the next instruction. 2. if the comparisons are false, the sym53c895 fetches the next instruction from the address pointed to by the dsp register, leaving the instruction pointer unchanged. call instruction 1. the sym53c895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, the sym53c895 loads the dsp register with the contents of the dsps register and that address value becomes the address of the next instruction. when the sym53c895 executes a call instruction, the instruction pointer contained in the dsp register is stored in the temp reg- ister. since the temp register is not a stack and can only hold one dword, nested call instructions are not allowed. 2. if the comparisons are false, the sym53c895 fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modified. opc2 opc1 opc0 instruction defined 0 0 0 jump 001call 010return 0 1 1 interrupt 1 x x reserved
instruction set of the i/o processor transfer control instructions 6-18 sym53c895 data manual return instruction 1. the sym53c895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, then the sym53c895 loads the dsp register with the contents of the dsps register. that address value becomes the address of the next instruction. when a return instruction is executed, the value stored in the temp register is returned to the dsp register. the sym53c895 does not check to see whether the call instruction has already been executed. it will not generate an interrupt if a return instruction is executed without previously executing a call instruction. 2. if the comparisons are false, then the sym53c895 fetches the next instruction from the address pointed to by the dsp register and the instruction pointer will not be modified. interrupt instructions interrupt a) the sym53c895 can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, figure 6-5: transfer control instruction wait for valid phase compare phase compare data jump if: true=1, false=0 interrupt on the fly carry test 0 = reserved relative addressing mode i/o mask for compare c/d msg op code bit 0 op code bit 1 op code bit 2 0 - instruction type - transfer control 1- instruction type - transfer control dcmd register dbc register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 data to be compared with the scsi first byte received 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dsps register
instruction set of the i/o processor transfer control instructions sym53c895 data manual 6-19 and true/false bit fields. if the comparisons are true, then the sym53c895 generates an interrupt by asserting the irq/ signal. b) the 32-bit address field stored in the dsps register (not dnad as in sym53c700) can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the isr to quickly identify the point at which the interrupt occurred. c) the sym53c895 halts and the dsp register must be written to start any further operation. interrupt on-the-fly a) the sym53c895 can do a true/false comparison of the alu carry bit or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, and the interrupt on the fly bit is set (bit 20), the sym53c895 will assert the interrupt on the fly bit (istat bit 2). bits 26-24 scsi phase this 3-bit field corresponds to the three scsi bus phase signals which are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible combinations and their corresponding scsi phase. these bits are only valid when the sym53c895 is operating in initiator mode; when the sym53c895 is operating in the tar- get mode, these bits should be cleared. msg c/d i/o scsi phase 000 data out 001 data in 0 1 0 command bit 23 relative addressing mode when this bit is set, the 24-bit signed value in the dsps register is used as a relative offset from the current dsp address (which is point- ing to the next instruction, not the one cur- rently executing). relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the script currently being executed by the sym53c895. the next address is formed by adding the 32-bit pro- gram counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2s compliment), the jump can be forward or backward. a relative transfer can be to any address within a 16-mb segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new exe- cution address. 011 status 1 0 0 reserved out 101 reserved in 1 1 0 message out 1 1 1 message in command condition codes absolute alternate address command condition codes dont care alternate jump offset msg c/d i/o scsi phase
instruction set of the i/o processor transfer control instructions 6-20 sym53c895 data manual scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it would not require any run time alteration of physical addresses, and could be stored in and executed from a prom. bit 21 carry test when this bit is set, decisions based on the alu carry bit can be made. true/false com- parisons are legal, but data compare and phase compare are illegal. bit 20 interrupt on the fly when this bit is set, the interrupt instruction will not halt the scripts processor. once the interrupt occurs, the interrupt on the fly bit (istat bit 2) will be asserted. bit 19 jump if true/false this bit determines whether the sym53c895 should branch when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition. bit 18 compare data when this bit is set, the first byte received from the scsi data bus (contained in sfbr regis- ter) is compared with the data to be com- pared field in the transfer control instruc- tion. the wait for valid phase bit controls when this compare will occur. the jump if true/false bit determines the condition (true or false) to branch on. bit 17 compare phase when the sym53c895 is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction; if they match, the comparison is true. the wait for valid phase bit controls when the compare will occur. when the sym53c895 is operating in target mode, setting this bit tests for an active scsi satn/ signal. bit 16 wait for valid phase if the wait for valid phase bit is set, the sym53c895 waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is clear, the sym53c895 compares the scsi phase and data immediately. bits 15-8 data compare mask the data compare mask allows a script to test certain bits within a data byte. during the data compare, any mask bits that are set cause the corresponding bit in the sfbr data byte to be ignored. for instance, a mask of 01111111b and data compare value of 1xxxxxxxb allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. bits 7-0 data compare value this 8-bit field is the data to be compared against the scsi first byte received (sfbr) register. these bits are used in conjunction with the data compare mask field to test for a particular data value. bit 19 result of compare action 0 false jump taken 0trueno jump 1falseno jump 1 true jump taken
instruction set of the i/o processor memory move instructions sym53c895 data manual 6-21 second dword bits 31-0 jump address this 32-bit field contains the address of the next instruction to fetch when a jump is taken. once the sym53c895 has fetched the instruc- tion from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dsp register and becomes the current instruction pointer. memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dmode register determine whether the source or destination addresses reside in memory or i/o space. by set- ting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction copies the speci- fied number of bytes from the source address to the destination address. allowing the sym53c895 to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mb may be transferred with one instruction. there are two restrictions: 1. both the source and destination addresses must start with the same address alignment (a(1-0) must be the same). if source and destination are not aligned, then an illegal instruction interrupt will occur. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. 2. indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another script is fetched from system memory. the dsps and dsa registers are additional hold- ing registers used during the memory move; how- ever, the contents of the dsa register are preserved. bits 31-39 instruction typememory move bits 28-25 reserved these bits are reserved and must be zero. if any of these bits is set, an illegal instruction interrupt will occur. bit 24 no flush note: this bit has no effect unless the pre-fetch enable bit in the dcntl register is set. for information on scripts instruction prefetching, see chapter 2, functional description. when this bit is set, the sym53c895 performs a memory move without flushing the prefetch unit. when this bit is clear, the memory move instruction automatically flushes the prefetch unit. the no flush option should be used if the source and destination are not within four instructions of the current memory move instruction. bits 23-0 transfer count the number of bytes to be transferred is stored in the lower 24 bits of the first instruction word. read/write system memory from a script by using the memory move instruction, single or multiple register values may be transferred to or from system memory. because the sym53c895 will respond to addresses as defined in the base i/o or base mem- ory registers, it could be accessed during a mem- ory move operation if the source or destination address decodes to within the chips register space. if this occurs, the register indicated by the lower seven bits of the address is taken to be the data source or destination. in this way, register values can be saved to system memory and later restored, and scripts can make decisions based on data values in system memory.
instruction set of the i/o processor memory move instructions 6-22 sym53c895 data manual the sfbr is not writable via the cpu, and there- fore not by a memory move. however, it can be loaded via scripts read/write operations. to load the sfbr with a byte stored in system mem- ory, the byte must first be moved to an intermedi- ate sym53c895 register (for example, a scratch register), and then to the sfbr. the same address alignment restrictions apply to register access operations as to normal memory-to- memory transfers. second dword bits 31-0, dsps register these bits contain the source address of the memory move. third dword bits 31-0, temp register these bits contain the destination address for the memory move. figure 6-6: memory move instructions 24-bit memory move byte counter no flush 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 - instruction type - memory move 1 - instruction type - memory move 1 - instruction type - memory move dcmd register dbc register dsps register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 temp register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
instruction set of the i/o processor load and store instructions sym53c895 data manual 6-23 load and store instructions the load and store instruction provides a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two-dword op codes. the first dword contains the dcmd and dbc register values. the second dword contains the dsps value. this is either the actual memory location of where to load or store, or the offset from the dsa, depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the destination memory address in the store instruction and the source memory address of the load instruction may not map back to the operating register set of the chip. this excludes the scripts ram and rom memory spaces. if it does, a pci read/write cycle will occur (the data does not actually transfer to/from the chip), and the chip will issue an interrupt (illegal instruction detected) immediately following. the siom and diom bits in the dmode regis- ter determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load/store utilizes the pci commands for i/o read and i/o write to access the i/o space. first dword bit 31-29, instruction type these bits should be 111, indicating the load and store instruction. bit 28, dsa relative when this bit is clear, the value in the dsps is the actual 32-bit memory address to perform the load/store to/from. when this bit is set, the chip determines the memory address to per- form the load/store to/from by adding the 24- bit signed offset value in the dsps to the dsa. bits 27-26, reserved bit 25, no flush (store instruction only) note: this bit has no effect unless the pre-fetch enable bit in the dcntl register is set. for information on scripts instruction prefetching, see chapter 2, functional description. when this bit is set, the sym53c895 performs a store without flushing the prefetch unit. when this bit is clear, the store instruction automatically flushes the prefetch unit. no flush should be used if the source and destina- tion are not within four instructions of the cur- rent store instruction. this bit is has no effect on the load instruction. bit 24, load/store when this bit is set, the instruction is a load. when cleared, it is a store. bit 23, reserved bits 22-16, register address a6-a0 select the register to load/store to/from within the sym53c895. bits a1, a0 number of bytes allowed to load/ store 00 one, two, three or four 01 one, two, or three 10 one or two 11 one bit source destination siom (load) memory register diom (store) register memory
instruction set of the i/o processor load and store instructions 6-24 sym53c895 data manual note: it is not possible to load the sfbr register, although it is possible to store the sfbr contents to another location. bits 15-3, reserved bits 2-0, byte count this value is the number of bytes to load/store. second dword bits 31-0, memory/io address / dsa offset this is the actual memory location of where to load or store, or the offset from the dsa register value. figure 6-7: load and store instruction format a0 a1 a2 a3 a4 a5 a6 a7 load/store no flush 0 - reserved 0 - reserved dsa relative 1 1 instruction type - load and store 1 dcmdregister dbc register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dspsregister - memory/ i/o address/dsa offset reserved (must be 0) register address bytes count (number of bytes to load/store)
electrical characteristics dc characteristics sym53c895 data manual 7-1 chapter 7 electrical characteristics dc characteristics table 7-1: absolute maximum stress ratings symbol parameter min max unit test conditions t stg storage temperature -55 150 c- v dd supply voltage -0.5 5.0 v - v in input voltage v ss - 0.3 v dd + 0.3 v - i lp * latch-up current 150 - ma - esd** electrostatic discharge - 2k v mil-std 883c, method 3015.7 stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operatio n of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not imp lied. * -2v < v pin < 8v ** scsi pins only table 7-2: operating conditions symbol parameter min max unit test conditions v dd supply voltage 3.135 3.465 v - i dd supply current (dynamic) supply current (static) - - 130 1 ma ma - - i dd-scsi lvd pad supply current - 600 ma rbias = 2.2 k w, v dd = 3.3 v t a operating free air 0 70 c- q ja thermal resistance (junc- tion to ambient air) -67 c/w - conditions that exceed the operating limits may cause the device to function incorrectly
7-2 sym53c895 data manual electrical characteristics dc characteristics table 7-3: scsi signals, low voltage differential driverssd (15-0)+/, sdp (1-0)+/-, sreq+/-, sack+/-, smsg+/-, sio+/-, scd+/-, satn+/-, sbsy+/-, ssel+/-, srst+/-* symbol parameter min max units test conditions i o + source (+) current -7 -11 ma asserted state i o - sink (-) current 7 11 ma asserted state i o + sink (-) current 3.5 5.5 ma negated state i o - source (+) current -3.5 -5.5 ma negated state i oz tristate leakage -20 20 m a i oz (srst- only) tristate leakage -500 -50 m a v cm = 0.7 - 1.8 v r l = 0-110 w r bias = 2.2 k w note: positive current is into siop chip figure 7-1: lvd transmitter table 7-4: scsi signals, low voltage differential receiverssd (15-0)+/-, sdp (1-0)+/-, sreq+/-, sack+/-, smsg+/-, sio+/-, scd+/-, satn+/-, sbsy+/-, ssel+/-, srst+/-* symbol parameter min max units v i lvd receiver voltage asserting 60 - mv v i lvd receiver voltage negating - -60 mv v cm = 0.7 - 1.8 v figure 7-2: lvd receiver i o + i o - + v cm - r l 2 r l 2 + v cm - v i 2 v i 2 - + - +
sym53c895 data manual 7-3 electrical characteristics dc characteristics table 7-5: scsi signal diffsens symbol parameter min max unit test conditions v ih high voltage differential sense voltage 2.4 v dd + 0.3 v - v s lvd sense voltage .7 1.9 v - v il single-ended sense voltage v ss - 0.3 0.5 v - i oz tristate leakage -10 10 m a- table 7-6: scsi signalsrbias+/- symbol parameter min max unit test conditions v in input voltage v dd - 0.2 - v - 125 m a table 7-7: capacitance symbol parameter min max unit test conditions c i input capacitance of input pads - 7 pf - c io input capacitance of i/o pads -15pf- table 7-8: output signal mac/_testout symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v -16 ma v ol output low voltage v ss 0.4 v 16 ma i oz tristate leakage -10 10 m a-
7-4 sym53c895 data manual electrical characteristics dc characteristics table 7-9: input signalsclk*, rst/*, idsel, gnt/, sclk/ symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v5bias(+) v - v il input low voltage v ss - 0.3 0.3 v dd v- i in input current -10 10 m a- i pull pull-up current 25 - m a *i pull not possible table 7-10: bidirectional signals ad(31-0), c_be/(3-0), frame/, irdy/, trdy/, devsel/, stop/, perr/, par, req/ irq/, serr/ symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd v5bias(+) v - v il input low voltage v ss - 0.5 0.3 v dd v- v oh output high voltage 0.9 v dd v dd v -0.5 m a v ol output low voltage v ss 0.1 v dd v1.5 m a i oz tristate leakage -10 10 m a- i pull pull-up current 25 m a table 7-11: bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2, gpio3, gpio4, mad(7-0) symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias(-) v - v il input low voltage v ss - 0.5 0.8 v - v oh output high voltage 2.4 v dd v-8 ma v ol output low voltage v ss 0.4 v 8 ma i oz tristate leakage -10 10 m a-
sym53c895 data manual 7-5 electrical characteristics dc characteristics table 7-12: bidirectional signalsmas/(1-0), mce/, moe/, mwe/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias(+ or -?) v - v il input low voltage v ss - 0.5 0.8 v - v oh output high voltage 2.4 v dd v-4 ma v ol output low voltage v ss 0.4 v 4 ma i oz tristate leakage -10 10 m a- i pull pull-up current 25 m a table 7-13: input signal big_lit/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v5bias(+) v - v il input low voltage v ss - 0.5 0.8 v - i in input current -10 10 m a- i pull pull-up current 25 - m a
7-6 sym53c895 data manual electrical characteristics tolerant technology electrical characteristics tolerant technology electrical characteristics table 7-14: tolerant technology electrical characteristics symbol parameter min max units test conditions v oh 1 output high voltage 2.0 v dd + 0.3 v i oh = 7 ma v ol output low voltage v ss 0.5 v i ol = 48 ma v ih input high voltage 2.0 v dd + 0.3 v - v il input low voltage v ss - 0.3 0.8 v referenced to v ss v ik input clamp voltage -0.66 -0.77 v v dd = 4.75; i i = -20 ma v th threshold, high to low 1.0 1.2 v - v tl threshold, low to high 1.4 1.6 v - v th - v tl hysteresis 300 500 mv - i oh 1 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 1 short-circuit output high current - 625 ma output driving low, pin shorted to v dd supply 2 i osl short-circuit output low current - 95 ma output driving high, pin shorted to v ss supply i lh input high leakage - 20 m a -0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage - -20 m a -0.5 < v dd < 5.25 v pin = 0.5 v r i input resistance 20 - m w scsi pins 3 c p capacitance per pin - 15 pf pqfp t r 1 rise time, 10% to 90% 4.0 18.5 ns figure 7-1 t f fall time, 90% to 10% 4.0 18.5 ns figure 7-1 dv h /dt slew rate, low to high 0.15 0.50 v/ns figure 7-1 note: these values are guaranteed by periodic characterization; they are not 100% tested on every device. 1 active negation outputs only: data, parity, sreq/, sack/ 2 single pin only; irreversible damage may occur if sustained for one second 3 scsi reset pin has 10 k w pull-up resistor
sym53c895 data manual 7-7 electrical characteristics tolerant technology electrical characteristics dv l /dt slew rate, high to low 0.15 0.50 v/ns figure 7-1 esd electrostatic discharge 2 - kv mil-std-883c; 3015-7 latch-up 100 - ma - filter delay 20 30 ns figure 7-2 ultra filter delay 10 15 ns figure 7-2 ultra2 filter delay 5 8 ns figure 7-2 extended filter delay 40 60 ns figure 7-2 figure 7-3: rise and fall time test conditions figure 7-4: scsi input filtering table 7-14: tolerant technology electrical characteristics (continued) symbol parameter min max units test conditions note: these values are guaranteed by periodic characterization; they are not 100% tested on every device. 1 active negation outputs only: data, parity, sreq/, sack/ 2 single pin only; irreversible damage may occur if sustained for one second 3 scsi reset pin has 10 k w pull-up resistor 20 pf 2.5 v + - 47 w t 1 v th req/ or ack/ input *t 1 is the input filtering period
7-8 sym53c895 data manual electrical characteristics tolerant technology electrical characteristics figure 7-5: hysteresis of scsi receiver figure 7-6: input current as a function of input voltage figure 7-7: output current as a function of output voltage input voltage (volts) received logic level 1.7 1.5 1.3 1.1 1 0 +40 +20 0 -20 -40 -40481216 input current (milliamperes) input voltage (volts) 8.2 v 14.4 v -0.7 v output active hi-z 100 80 60 40 20 0 0 12345 output source current (milliamperes) output voltage (volts) 0 -200 -400 -600 -800 012 34 5 output sink current (milliamperes) output voltage (volts)
sym53c895 data manual 7-9 electrical characteristics ac characteristics ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to the dc characteristics section). chip timings are based on simulation at worst case voltage, tempera- ture, and processing. timings were developed with a load capacitance of 50 pf. figure 7-8: external clock timing symbol parameter min max units t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk)* 25 60 ns t 2 clk low time** 10 - ns sclk low time** 6 33 ns t 3 clk high time** 12 - ns sclk high time** 10 33 ns t 4 clk slew rate 1 - v/ns sclk slew rate 1 - v/ns timings are for an external 40 mhz clock. a quadrupled 40 mhz clock is required for ultra2 scsi operation. * this parameter must be met to insure scsi timings are within specification **duty cycle not to exceed 60/40 clk/sclk t 1 t 3 t 4 t 2 1.4 v
7-10 sym53c895 data manual electrical characteristics ac characteristics figure 7-9: reset input symbol parameter min max units t 1 reset pulse width 10 - t clk t 2 reset deasserted setup to clk high 0 - ns t 3 mad setup time to clk high (for configuring the mad bus only) 20 - ns t 4 mad hold time from clk high (for configuring the mad bus only) 20 - ns figure 7-10: interrupt output symbol parameter min max units t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 - clks clk t 1 t 2 rst/ valid data mad* *when enabled t t 3 4 clk irq/ t 1 t 2 t 3
sym53c895 data manual 7-11 electrical characteristics pci and external memory interface timing diagrams pci and external memory interface timing diagrams figure 7-11 through figure 7 represent signal activity when the sym53c895 accesses the pci bus. this section includes timing diagrams for access to three groups of external memory configurations. the first group applies to systems with memory size of 64 kb and above; one byte read or write cycle, and fast or normal roms. the second group applies to systems with memory size of 64 kb and above, one-byte read or write cycles, and slow roms. the third group applies to systems with memory size of 64 kb or less, one-byte read or write cycles, and normal or fast rom. note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. timing diagrams included in this section target cycles n pci configuration register read n pci configuration register write n operating register/scripts ram read n operating register/scripts ram write n external memory read n external memory write initiator cycles n op code fetch, non-burst n burst op code fetch n back-to-back read n back-to-back write n burst read n burst write external memory cycles n read cycle, normal/fast memory ( 3 128 kb), single-byte access n write cycle, normal/fast memory ( 3 128 kb), single-byte access n read cycle, normal/fast memory ( 3 128 kb), multiple-byte access n write cycle, normal/fast memory ( 3 128 kb), multiple-byte access n read cycle, slow memory ( 3 128 kb) n write cycle, slow memory 3 128 kb) n read cycle, 64 kb rom n write cycle, 64 kb rom
7-12 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-15: configuration register read timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns figure 7-11: pci configuration register read clk (driven by system) frame/ (driven by system) ad/ 53c895-data) c_be/ (driven by master) addr in par 53c895-data) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) idsel (driven by master) t 1 t 1 t 2 t 2 t 1 t 1 t 1 t 2 t 1 t 2 t 3 t 3 t 3 t 2 t 3 out t 3 in t 2 cmd byte enable data out t 2 (driven by master-addr (driven by master-addr
sym53c895 data manual 7-13 electrical characteristics pci and external memory interface timing diagrams table 7-16: configuration register write timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns figure 7-12: pci configuration register write clk (driven by system) frame/ (driven by master) ad/ (driven by master) data in c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) idsel (driven by master) t 1 t 1 2 t 1 t 1 t 1 t 2 t 1 t 2 t 3 t 3 t 3 t 2 t 2 t 2 1 t t 2 t cmd 2 t byte enable addr in
7-14 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-17: operating register/scripts ram read timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns figure 7-13: operating register/scripts ram read clk (driven by system) frame/ (driven by master) ad (driven by master-addr; 53c895-data) (driven by master) par irdy/ (driven by master) trdy (driven by 53c895) stop/ devsel/ (driven by 53c895) (driven by 53c895) t 3 t 3 t 3 t 2 t 2 t 1 t 2 t 1 2 t t 1 t 2 (driven by master-addr; 53c895-data) t 3 t 3 addr in t 1 cmd 2 t byte enable data out out in t 1 c_be/
sym53c895 data manual 7-15 electrical characteristics pci and external memory interface timing diagrams table 7-18: operating register/scripts ram write timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns figure 7-14: operating register/scripts ram write clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ devsel/ (driven by 53c895) (driven by 53c895) t 3 t 3 t 3 t 2 t 2 t 2 t 1 t 1 t 2 t 1 t 1 2 t t 1 t 1 t 2 t 2 t 1 addr in t 2 cmd data in byte enable
7-16 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-19: external memory read timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns t 4 side signal input setup time 10 - ns t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 14 mce/ low to data clocked in 160 - ns t 15 address valid to data clocked in 205 - ns t 16 moe/ low to data clocked in 100 - ns t 17 data hold from address, moe/, mce/ change 0 - ns t 18 address out from moe/, mce/ high 50 - ns t 19 data setup to clk high 5 - ns
sym53c895 data manual 7-17 electrical characteristics pci and external memory interface timing diagrams figure 7-15: external memory read t 2 t11 t12 t13 t14 t15 t16 t17 t19 t 3 t 3 t 3 t 2 t 1 t 1 t 1 3 t 1 cmd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 middle order address t t3 data out data in byte enable out mad (addr driven by 53c895; data driven by memeory) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) clk (driven by system) frame/ (driven by master) ad (driven by master-addr; 53c895-data) c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) par (driven by master-addr; 53c895-data) high order address t 2 2 t t 2 2 t t 1 in addr in low order address
7-18 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-20: external memory write timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid - 11 ns t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 20 data setup to mwe/ low 30 - ns t 21 data hold from mwe/ high 20 - ns t 22 mwe/ pulse width 100 - ns t 23 address setup to mwe/ low 75 - ns t 24 mce/ low to mwe/ high 120 - ns t 25 mce/ low to mwe/ low 25 - ns t 26 mwe/ high to mce/ high 25 - ns
sym53c895 data manual 7-19 electrical characteristics pci and external memory interface timing diagrams figure 7-16: external memory write t11 t12 t13 t24 t22 t25 t 3 t 3 t 3 t 1 t 1 t 1 t1 addr in t 1 in in t 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 t 2 t 2 t 1 high order address low order address middle order address data out t20 t23 t 26 t 21 data in byte enable mad (driven by 53c895) mas1/ (driven by 53c895) mas0/ (driven by 53c895) mce/ (driven by 53c895) moe/ (driven by 53c895) mwe/ (driven by 53c895) clk (driven by system) frame/ (driven by master) ad (driven by master-addr; 53c895-data) c_be/ (driven by master) irdy/ (driven by master) trdy/ (driven by 53c895) stop/ (driven by 53c895) devsel/ (driven by 53c895) par (driven by master-addr; 53c895-data) 2 t cmd t 2 t 2 t 2 2 t t 2
7-20 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-21: op code fetch, non burst timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 7 clk high to fetch/ low - 20 ns t 8 clk high to fetch/ high - 20 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-21 electrical characteristics pci and external memory interface timing diagrams figure 7-17: op code fetch, non-burst clk gpio0_fetch/ gpio1_master/ req/ gnt/ frame/ c_be/ par/ t 7 t 9 t 3 (driven by system) (driven by 53c895)* (driven by 53c895)* (driven by 53c895) (driven by arbiter) (driven by 53c895) (driven by 53c895) irdy/ (driven by target) (driven by 53c895-addr; target-data) trdy/ stop/ devsel/ (driven by 53c895) (driven by target) (driven by target) t 8 t 10 t 1 t 2 data in addr out addr out cmd cmd be be t 6 t 4 t 5 data in t 3 t 3 t 1 t 3 t 2 t 3 t 1 t 1 t 2 t 3 t 2 ad/ (driven by 53c895-addr; target-data)
7-22 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-22: burst op code fetch timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 7 clk high to fetch/low - 20 ns t 8 clk high to fetch/high - 20 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-23 electrical characteristics pci and external memory interface timing diagrams figure 7-18: burst op code fetch t 7 t 9 t 1 t 2 data in addr out be t 6 data in t 1 t 3 t 2 t 3 t 1 t 1 t 3 out in in gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) gnt/ (driven by arbiter) frame/ (driven by 53c895 ad (driven by 53c895- addr; target-data) c_be/ (driven by 53c895) trdy/ (driven by target) par (driven by 53c895- addr; target-data irdy/ (driven by 53c895 stop/ (driven by target) devsel/ (driven by target) t 5 t 4 t 3 t 3 t 3 t 2 t 2 clk (driven by system) t 8 t 10 cmd t 3
7-24 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-23: back to back read timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-25 electrical characteristics pci and external memory interface timing diagrams figure 7-19: back-to-back read t 5 data in addr out t data in t 9 t 6 t 3 t 2 t 1 t 10 1 t 1 t 3 t 3 t 1 cmd be be t 4 t 3 t 2 t 3 out in out in cmd gpio0_fetch/ (driven by 53c895) gpio1_master/ (driven by 53c895) req/ (driven by 53c895) gnt/ (driven by arbiter) frame/ (driven by 53c895) ad (driven by 53c895- addr; target-data) c_be/ (driven by 53c895) trdy/ (driven by target) par (driven by 53c895- addr; target-data) irdy/ (driven by 53c895) stop/ (driven by target) devsel/ (driven by target) t 2 t 2 clk (driven by system) addr out
7-26 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-24: back to back write timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-27 electrical characteristics pci and external memory interface timing diagrams figure 7-20: back-to-back write t 4 t 6 t 3 t 10 t 1 t 3 t 3 addr out data out cmd cmd t 3 be be t 3 t 1 addr out data out t 3 gpio0_fetch/ (driven by 53c895) gpio1_master/(driven by 53c895) req/ (driven by 53c895) gnt/ (driven by arbiter) frame/ (driven by 53c895) ad (driven by 53c895) c_be/ (driven by 53c895) trdy/ (driven by target) par (driven by 53c895) irdy/ (driven by 53c895) stop/ (driven by target) devsel/ (driven by target) t 9 t 3 t 3 t 5 t 2 t 2 clk (driven by system)
7-28 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-25: burst read timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-29 electrical characteristics pci and external memory interface timing diagrams figure 7-21: burst read gpio0_ fetch / (driven by 53c895) gpio1_ master/ (driven by 53c895) req/ (driven by 53c895) gnt/ (driven by arbiter) frame (driven by 53c895) ad (driven by 53c895-addr, target-data) c_be/ (driven by 53c895) par (driven by 53c895 for address, by target for data irdy/ (driven by 53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) clk t 10 t 9 t 6 t 4 t 3 t 3 t 1 t 2 t 5 data in data in addr out cmd be cmd be addr out data in be t 3 out t 3 in t 1 out in out in t 1 t 2 addr out t 1 t 2 t 2 t 3 t 3 in cmd
7-30 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-26: burst write timings symbol parameter min max unit t 1 shared signal input setup time 7 - ns t 2 shared signal input hold time 0 - ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 - ns t 5 side signal input hold time 0 - ns t 6 clk to side signal output valid - 12 ns t 9 clk high to master/ low - 20 ns t 10 clk high to master/ high - 20 ns
sym53c895 data manual 7-31 electrical characteristics pci and external memory interface timing diagrams figure 7-22: burst write gpio0_fetch / (driven by sym53c895) gpio1_master/ (driven by sym53c895) req/ (driven by sym53c895) gnt/ (driven by arbiter) frame (driven by sym53c895) ad (driven by sym53c895) c_be/ (driven by sym53c895) par (driven by sym53c895) irdy/ (driven by sym53c895) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) clk (driven by system) t 10 t 9 t 6 t 4 t 3 t 3 t 3 t 1 t 2 t 2 t 5 addr out t 3 data out addr out data out addr out data out cmd be be cmd be t 3 t 1 t 3 data out t 3 t 3 cmd
7-32 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-27: read cycle timings, normal/fast memory ( 3 128 kb), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 14 mce/ low to data clocked in 160 - ns t 15 address valid to data clocked in 205 - ns t 16 moe/ low to data clocked in 100 - ns t 17 data hold from address, moe/, mce/ change 0 - ns t 18 address out from moe/, mce/ high 50 - ns t 19 data setup to clk high 5 - ns
sym53c895 data manual 7-33 electrical characteristics pci and external memory interface timing diagrams figure 7-23: read cycle, normal/fast memory ( 3 128 kb), single byte access mad (addr driven by sym53c895; data driven by memory) mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk high order address middle order address low order address valid read data t11 t12 t13 t14 t15 t16 t17 t18 t19
7-34 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-28: write cycle timings, normal/fast memory ( 3 128 kb), single byte access symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 20 data setup to mwe/ low 30 - ns t 21 data hold from mwe/ high 20 - ns t 22 mwe/ pulse width 100 - ns t 23 address setup to mwe/ low 75 - ns t 24 mce/ low to mwe/ high 120 - ns t 25 mce/ low to mwe/ low 25 - ns t 26 mwe/ high to mce/ high 25 - ns
sym53c895 data manual 7-35 electrical characteristics pci and external memory interface timing diagrams figure 7-24: write cycle, normal/fast memory ( 3 128 kb), single byte access mad (driven by sym53c895) mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk t12 high order address middle address low address valid write data t11 t13 t20 t21 t22 t23 t24 t25 t26
7-36 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams figure 7-25: read cycle, normal/fast memory ( 3 128 kb) multiple byte access mad (addr driven by sym53c895; data driven by memory) mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk (driven by system) frame/ (driven by master) ad (driven by master-addr; sym53c895-data) c_be/ (driven by master) par irdy/ (driven by master) trdy (driven by sym53c895) stop/ devsel/ (driven by sym53c895) (driven by sym53c895) (driven by master-addr; sym53c895-data) middle order address high order address addr in cmd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 byte enable low order address dat in
sym53c895 data manual 7-37 electrical characteristics pci and external memory interface timing diagrams figure 7-25: read cycle, normal/fast memory ( 3 128 kb), multiple byte access (continued) data out out 15 16 17 18 19 20 21 22 23 24 25 26 27 2 8 29 30 3 1 32 33 e enable data in low order address data in
7-38 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-29: read cycle timings, slow memory ( 3 128 kb) symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 14 mce/ low to data clocked in 160 - ns t 15 address valid to data clocked in 205 - ns t 16 moe/ low to data clocked in 100 - ns t 17 data hold from address, moe/, mce/ change 0 - ns t 18 address out from moe/, mce/ high 50 - ns t 19 data setup to clk high 5 - ns
sym53c895 data manual 7-39 electrical characteristics pci and external memory interface timing diagrams figure 7-26: read cycle, slow memory ( 3 128 kb) mad (address driven by sym53c895 data driven by memory mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk high order address middle address low order address valid readdata t11 t12 t13 t19 t17 t15 t14 t16 t18
7-40 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-30: write cycle timings, slow memory ( 3 128 kb) symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 20 data setup to mwe/ low 30 - ns t 21 data hold from mwe/ high 20 - ns t 22 mwe/ pulse width 100 - ns t 23 address setup to mwe/ low 75 - ns t 24 mce/ low to mwe/ high 120 - ns t 25 mce/ low to mwe/ low 25 - ns t 26 mwe/ high to mce/ high 25 - ns
sym53c895 data manual 7-41 electrical characteristics pci and external memory interface timing diagrams figure 7-27: write cycle, slow memory ( 3 128 kb) mad (driven by sym53c895) mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk high order address middle address low order address t11 t12 t13 t24 t23 t22 t20 t25 t26 t21 valid write data
7-42 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-31: read cycle timings, 64 kb rom symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 14 mce/ low to data clocked in 160 - ns t 15 address valid to data clocked in 205 - ns t 16 moe/ low to data clocked in 100 - ns t 17 data hold from address, moe/, mce/ change 0 - ns t 18 address out from moe/, mce/ high 50 - ns t 19 data setup to clk high 5 - ns
sym53c895 data manual 7-43 electrical characteristics pci and external memory interface timing diagrams figure 7-28: read cycle, 64 kb rom mad (address driven by sym53c895, data driven by memory mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk high order addr low order address valid read data t11 t12 t13 t19 t17 t15 t14 t16 t18
7-44 sym53c895 data manual electrical characteristics pci and external memory interface timing diagrams table 7-32: write cycle timings, 64 kb rom symbol parameter min max unit t 11 address setup to mas/ high 25 - ns t 12 address hold from mas/ high 15 - ns t 13 mas/ pulse width 25 - ns t 20 data setup to mwe/ low 30 - ns t 21 data hold from mwe/ high 20 - ns t 22 mwe/ pulse width 100 - ns t 23 address setup to mwe/ low 75 - ns t 24 mce/ low to mwe/ high 120 - ns t 25 mce/ low to mwe/ low 25 - ns t 26 mwe/ high to mce/ high 25 - ns
sym53c895 data manual 7-45 electrical characteristics pci and external memory interface timing diagrams figure 7-29: write cycle, 64 kb rom mad (driven by sym53c895) mas1/ (driven by sym53c895) mas0/ (driven by sym53c895) mce/ (driven by sym53c895) moe/ (driven by sym53c895) mwe/ (driven by sym53c895) clk high order address low order address valid write data t11 t12 t13 t20 t21 t22 t23 t24 t25 t26
7-46 sym53c895 data manual electrical characteristics scsi timings scsi timings figure 7-30: initiator asynchronous send symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 - ns t 2 sack/ deasserted from sreq/ deasserted 5 - ns t 3 data setup to sack/ asserted 55 - ns t 4 data hold from sreq/ deasserted 20 - ns figure 7-31: initiator asynchronous receive symbol parameter min max units t 1 sack/ asserted from sreq/ asserted 5 - ns t 2 sack/ deasserted from sreq/ deasserted 5 - ns t 3 data setup to sreq/ asserted 0 - ns t 4 data hold from sack/ asserted 0 - ns valid n valid n+1 n+1 n+1 t 1 t 2 n t 4 n t 3 sreq/ sack/ sd15-0/, sdp1-0/ valid n valid n+1 n n n+1 n+1 t 4 t 3 t 1 t 2 sreq/ sack/ sd15-0/, sdp1-0/
sym53c895 data manual 7-47 electrical characteristics scsi timings figure 7-32: target asynchronous send symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 - ns t 2 sreq/ asserted from sack/ deasserted 5 - ns t 3 data setup to sreq/ asserted 55 - ns t 4 data hold from sack/ asserted 20 - ns figure 7-33: target asynchronous receive symbol parameter min max units t 1 sreq/ deasserted from sack/ asserted 5 - ns t 2 sreq/ asserted from sack/ deasserted 5 - ns t 3 data setup to sack/ asserted 0 - ns t 4 data hold from sreq/ deasserted 0 - ns valid n valid n+1 n n n+1 n+1 t 4 t 1 t 2 sreq/ sack/ sd15-0/, sdp1-0/ t 3 valid n valid n+1 n n n+1 n+1 t 4 t 3 t 1 t 2 sreq/ sack/ sd15-0/, sdp1-0/
7-48 sym53c895 data manual electrical characteristics scsi timings figure 7-34: initiator and target synchronous transfers table 7-33: scsi-1 transfers (single-ended, 5.0 mb/s) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 90 - ns t 2 send sreq/ or sack/ deassertion pulse width 90 - ns t 1 receive sreq/ or sack/ assertion pulse width 90 - ns t 2 receive sreq/ or sack/ deassertion pulse width 90 - ns t 3 send data setup to sreq/ or sack/ asserted 55 - ns t 4 send data hold from sreq/ or sack/ asserted 100 - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 45 - ns valid n valid n+1 valid n valid n+1 n n+1 t 6 t 5 t 1 t 2 t 4 t 3 send data sd15-0/, sdp1-0/ sreq/ or sack/ receive data sd15-0/, sdp1-0/
sym53c895 data manual 7-49 electrical characteristics scsi timings table 7-34: scsi-1 transfers (differential, 4.17 mb/s) symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 96 - ns t 2 send sreq/ or sack/ deassertion pulse width 96 - ns t 1 receive sreq/ or sack/ assertion pulse width 84 - ns t 2 receive sreq/ or sack/deassertion pulse width 84 - ns t 3 send data setup to sreq/ or sack/ asserted 65 - ns t 4 send data hold from sreq/ or sack/ asserted 110 - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 45 - ns table 7-35: scsi-2 fast transfers 10.0 mb/s (8-bit transfers) or 20.0 mb/s (16-bit transfers), 40 mhz clock symbol parameter min max units t 1 send sreq/ or sack/ assertion pulse width 35 - ns t 2 send sreq/ or sack/ deassertion pulse width 35 - ns t 1 receive sreq/ or sack/ assertion pulse width 20 - ns t 2 receive sreq/ or sack/ deassertion pulse width 20 - ns t 3 send data setup to sreq/ or sack/ asserted 33 - ns t 4 send data hold from sreq/ or sack/ asserted 45 - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 10 - ns
7-50 sym53c895 data manual electrical characteristics scsi timings table 7-36: scsi-2 fast transfers 10.0 mb/s (8-bit transfers) or 20.0 mb/s (16-bit transfers), 50 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 - ns t 2 send sreq/ or sack/ deassertion pulse width 35 - ns t 1 receive sreq/ or sack/ assertion pulse width 20 - ns t 2 receive sreq/ or sack/ deassertion pulse width 20 - ns t 3 send data setup to sreq/ or sack/ asserted 33 - ns t 4 send data hold from sreq/ or sack/ asserted 40** - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 10 - ns *transfer period bits (bits 6-4 in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. **analysis of system configuration is recommended due to reduced driver skew margin in differential systems note: for fast scsi, set the tolerant enable bit (bit 7 in stest3). table 7-37: ultra scsi single-ended transfers 20.0 mb/s (8-bit transfers) or 40.0 mb/s (16-bit transfers), quadrupled 40 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 16 - ns t 2 send sreq/ or sack/ deassertion pulse width 16 - ns t 1 receive sreq/ or sack/ assertion pulse width 10 - ns t 2 receive sreq/ or sack/ deassertion pulse width 10 - ns t 3 send data setup to sreq/ or sack/ asserted 12 - ns t 4 send data hold from sreq/ or sack/ asserted 17 - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 7 - ns *transfer period bits (bits 6-4 in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. note: for fast scsi, set the tolerant enable bit (bit 7 in stest3). during ultra scsi transfers, the value of the extend req/ ack filtering bit (stest2, bit 1) has no effect.
sym53c895 data manual 7-51 electrical characteristics scsi timings table 7-38: ultra scsi high voltage differential transfers 20.0 mb/s (8-bit transfers) or 40.0 mb/s (16-bit transfers), 80 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 16 - ns t 2 send sreq/ or sack/ deassertion pulse width 16 - ns t 1 receive sreq/ or sack/ assertion pulse width 10 - ns t 2 receive sreq/ or sack/ deassertion pulse width 10 - ns t 3 send data setup to sreq/ or sack/ asserted 16 - ns t 4 send data hold from sreq/ or sack/ asserted 21 - ns t 5 receive data setup to sreq/ or sack/ asserted 0 - ns t 6 receive data hold from sreq/ or sack/ asserted 6 - ns *transfer period bits (bits 6-4 in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. note: during ultra scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect. table 7-39: ultra2 scsi transfers 40.0 mb/s (8-bit transfers) or 80.0 mb/s (16-bit transfers), quadrupled 40 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 8 - ns t 2 send sreq/ or sack/ deassertion pulse width 8 - ns t 1 receive sreq/ or sack/ assertion pulse width 6 - ns t 2 receive sreq/ or sack/ deassertion pulse width 6 - ns t 3 send data setup to sreq/ or sack/ asserted 10 - ns t 4 send data hold from sreq/ or sack/ asserted 10 - ns t 5 receive data setup to sreq/ or sack/ asserted 4.5 - ns t 6 receive data hold from sreq/ or sack/ asserted 4.5 - ns *transfer period bits (bits 6-4 in the sxfer register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scntl1) is set. note: during ultra2 scsi transfers, the value of the extend req/ack filtering bit (stest2, bit 1) has no effect.
7-52 sym53c895 data manual electrical characteristics scsi timings
register summary sym53c895 data manual a-1 appendix a register summary register 00 (80) scsi control zero (scntl0) read/write bit 7 arb1 (arbitration mode bit 1) bit 6 arb0 (arbitration mode bit 0) bit 5 start (start sequence) bit 4 watn (select with satn/ on a start sequence) bit 3 epc (enable parity checking) bit 2 reserved bit 1 aap (assert satn/ on parity error) bit 0 trg (target mode) register 01 (81) scsi control one (scntl1) read/write bit 7 exc (extra clock cycle of data setup) bit 6 adb (assert scsi data bus) bit 5 dhp (disable halt on parity error or atn) ( ta r g e t o n l y ) bit 4 con (connected) bit 3 rst (assert scsi rst/ signal) bit 2 aesp (assert even scsi parity (force bad parity)) bit 1 iarb (immediate arbitration) bit 0 sst (start scsi transfer) register 02 (82) scsi control two (scntl2) read/write bit 7 sdu (scsi disconnect unexpected) bit 6 chm (chained mode) bit 5 slpmd (slpar mode bit) bit 4 slphben (slpar high byte enable) bit 3 wss (wide scsi send) bit 2 vue0 (vendor unique enhancements bit 0) bit 1 vue1 (vendor unique enhancements bit 1) bit 0 wsr (wide scsi receive) register 03 (83) scsi control three (scntl3) read/write bit 7 ultra (ultra enable) bits 6-4 scf2-0 (synchronous clock conversion factor) bit 3 ews (enable wide scsi) bits 2-0 ccf2-0 (clock conversion factor) register 04 (84) scsi chip id (scid) read/write bit 7 reserved bit 6 rre (enable response to reselection) bit 5 sre (enable response to selection) bit 4 reserved bits 3-0 encoded chip scsi id, bits 3-0 arb1 arb0 start watn epc res aap trg 76543210 default>>> 11000x00 exc adb dhp con rst aesp iarb sst 76543210 default>>> 00000000 sdu chm slpmd slphben wss vue0 vue1 wsr 76 5 4 3210 default>>> 00 0 0 0000 ultra scf2 scf1 scf0 ews ccf2 ccf1 ccf0 7 6543210 default>>> 0 0000000 res rre sre res enc3 enc2 enc1 enc0 76543210 default>>> x00x0000
register summary a-2 sym53c895 data manual register 05 (85) scsi transfer (sxfer) read/write bits 7-5 tp2-0 (scsi synchronous transfer period) bits 4-0 mo4-mo0 (max scsi synchronous offset) register 06 (86) scsi destination id (sdid) read/write bits 7-4 reserved bits 3-0 encoded destination scsi id register 07 (87) general purpose (gpreg) read/write bits 7-5 reserved bits 4-0 gpio4-gpio0 (general purpose) register 08 (88) scsi first byte received (sfbr) read/write register 09 (89) scsi output control latch (socl) read /write bit 7 req(assert scsi req/ signal) bit 6 ack(assert scsi ack/ signal) bit 5 bsy(assert scsi bsy/ signal) bit 4 sel(assert scsi sel/ signal) bit 3 atn(assert scsi atn/ signal) bit 2 msg(assert scsi msg/ signal) bit 1 c/d(assert scsi c_d/ signal) bit 0 i/o(assert scsi i_o/ signal) register 0a (8a) scsi selector id (ssid) read only bit 7 val (scsi valid) bits 6-4 reserved bits 3-0 encoded destination scsi id register 0b (8b) scsi bus control lines (sbcl) read only bit 7 req (sreq/ status) bit 6 ack (sack/ status) bit 5 bsy (sbsy/ status) bit 4 sel (ssel/ status) bit 3 atn (satn/ status) bit 2 msg (smsg/ status) bit 1 c/d (sc_d/ status) bit 0 i/o (si_o/ status) tp2 tp1 tp0 mo4 mo3 mo2 mo1 mo0 76543210 default>>> 00000000 res res res res enc3 enc2 enc1 enc0 76543210 default>>> xxxx0000 res res res gpio4 gpio3 gpio2 gpio1 gpio0 76543210 default>>> xxx0xxxx 1b7 1b6 1b5 1b4 1b3 1b2 1b1 1b0 76543210 default>>> 00000000 req ack bsy sel atn msg c/d i/o 76543210 default>>> 00000000 val res res res enid3 enid2 enid1 enid0 76543210 default>>> 0xxx0000 req ack bsy sel atn msg c/d i/o 76543210 default>>> xxxxxxxx
register summary sym53c895 data manual a-3 register 0c (8c) dma status (dstat) read only bit 7 dfe (dma fifo empty) bit 6 mdpe (master data parity error) bit 5 bf (bus fault) bit 4 abrt (aborted) bit 3 ssi (single step interrupt) bit 2 sir (scripts interrupt instruction received) bit 1 reserved bit 0 iid (illegal instruction detected) register 0d (8d) scsi status zero (sstat0) read only bit 7 ilf (sidl least significant byte full) bit 6 orf (sodr least significant byte full) bit 5 olf (sodl least significant byte full) bit 4 aip (arbitration in progress) bit 3 loa (lost arbitration) bit 2 woa (won arbitration) bit 1 rst/ (scsi rst/ signal) bit 0 sdp0/ (scsi sdp0/ parity signal) register 0e (8e) scsi status one (sstat1) read only bits 7-4 ff3-ff0 (fifo flags) bit 3 sdp0l (latched scsi parity) bit 2 msg (scsi msg/ signal) bit 1 c/d (scsi c_d/ signal) bit 0 i/o (scsi i_o/ signal) register 0f (8f) scsi status two (sstat2) (read only) bit 7 ilf1 (sidl most significant byte full) bit 6 orf1 (sodr most significant byte full) bit 5 olf1 (sodl most significant byte full) bit 4 ff4 (fifo flags bit 4) bit 3 spl1(latched scsi parity for sd15-8) bit 2 dm (diffsens mismatch) bit 1 ldsc (last disconnect) bit 0 sdp1 (scsi sdp1 signal) registers 10-13 (90-93) data structure address (dsa) read/write register 14 (94) interrupt status (istat) (read/write) bit 7 abrt (abort operation) bit 6 srst (software reset) bit 5 sigp (signal process) bit 4 sem (semaphore) bit 3 con (connected) bit 2 intf (interrupt on the fly) bit 1 sip (scsi interrupt pending) bit 0 dip (dma interrupt pending) register 18 (98) chip test zero (ctest0) read/write dfe mdpe bf abrt ssi sir res iid 76543210 default>>> 100000x0 ilf orf olf aip loa woa rst sdp0/ 76543210 default>>> 00000000 ff3 ff2 ff1 ff0 sdp0l msg c/d i/o 76543210 default>>> 0000xxxx ilf1 orf1 olf1 ff4 spl1 dm ldsc sdp1 76543210 default>>> 0000xx1x abrt srst sigp sem con intf sip dip 76543210 default>>> 00000000
register summary a-4 sym53c895 data manual register 19 (99) chip test one (ctest1) read only bits 7-4 fmt3-0 (byte empty in dma fifo) bits 3-0 ffl3-0 (byte full in dma fifo) register 1a (9a) chip test two (ctest2) read/write bit 7 ddir (data transfer direction) bit 6 sigp (signal process) bit 5 cio (configured as i/o) bit 4 cm (configured as memory) bit 3 srtch (scratcha/b operation) bit 2 teop (scsi true end of process) bit 1 dreq (data request status) bit 0 dack (data acknowledge status) register 1b (9b) chip test three (ctest3) read/write bits 7-4 v3-v0 (chip revision level) bit 3 flf (flush dma fifo) bit 2 clf (clear dma fifo) bit 1 fm (fetch pin mode) bit 0 wrie (write and invalidate enable) registers 1c-1f (9c-9f) temporary (temp) read/write register 20 (a0) dma fifo (dfifo) read/write bits 7-0 bo7-bo0 (byte offset counter) register 21 (a1) chip test four (ctest4) read/write bit 7 bdis (burst disable) bit 6 zmod (high impedance mode) bit 5 zsd (scsi data high impedance) bit 4 srtm (shadow register test mode) bit 3 mpee (master parity error enable) bits 2-0 fbl2-fbl0 (fifo byte control register 22 (a2) chip test five (ctest5) read/write bit 7 adck (clock address incrementor) bit 6 bbck (clock byte counter) bit 5 dfs (dma fifo size) bit 4 masr (master control for set or reset pulses) bit 3 ddir (dma direction) bit 2 bl2 (burst length bit 2) bits 1-0 bo9-8 register 23 (a3) chip test six (ctest6) read/write bits 7-0 df7-df0 (dma fifo) fmt3 fmt2 fmt1 fmt0 ffl3 ffl2 ffl1 ffl0 76543210 default>>> 11110000 ddir sigp cio cm srtch teop dreq dack 76543210 default>>> 00xx0001 v3 v2 v1 v0 flf clf fm wrie 76543210 default>>> xxxx0000 bo7 bo6 bo5 bo4 bo3 bo2 bo1 bo0 76543210 default>>> x0000000 bdis zmod zsd srtm mpee fbl2 fbl1 fbl0 76543210 default>>> 00000000 adck bbck dfs masr ddir bl2 bo9 bo8 76543210 default>>> 00000xxx df7 df6 df5 df4 df3 df2 df1 df0 76543210 default>>> 00000000
register summary sym53c895 data manual a-5 registers 24-26 (a4-a6) dma byte counter (dbc) read/write register 27 (a7) dma command (dcmd) read/write registers 28-2b (a8-ab) dma next address (dnad) read/write registers 2c-2f (ac-af) dma scripts pointer (dsp) read/write registers 30-33 (b0-b3) dma scripts pointer save (dsps) read/write registers 34-37 (b4-b7) scratch register a (scratch a) read/write register 38 (b8) dma mode (dmode) read/write bit 7-6 bl1-bl0 (burst length) bit 5 siom (source i/o-memory enable) bit 4 diom (destination i/o-memory enable) bit 3 erl (enable read line) bit 2 ermp (enable read multiple) bit 1 bof (burst op code fetch enable) bit 0 man (manual start mode) register 39 (b9) dma interrupt enable (dien) read/write bit 7 reserved bit 6 mdpe (master data parity error) bit 5 bf (bus fault) bit 4 abrt (aborted) bit 3 ssi (single -step interrupt) bit 2 sir (scripts interrupt instruction received bit 1 reserved bit 0 iid (illegal instruction detected) register 3a (ba) scratch byte register (sbr) read/write register 3b (bb) dma control (dcntl) read/write bit 7 clse (cache line size enable) bit 6 pff (pre-fetch flush) bit 5 pfen (pre-fetch enable) bit 4 ssm (single-step mode) bit 3 irqm (irq mode) bit 2 std (start dma operation) bit 1 irqd (irq disable) bit 0 com (53c700 compatibility) register 3c-3f (bc-bf) adder sum output (adder) read only bl1 bl0 siom diom er ermp bof man 76543210 default>>> 00000000 res mdpe bf abrt ssi sir res iid 76543210 default>>> x00000x0 clse pff pfen ssm irqm std irqd com 76543210 default>>> 00000000
register summary a-6 sym53c895 data manual register 40 (c0) scsi interrupt enable zero (sien0) read/write bit 7 m/a (scsi phase mismatch - initiator mode; scsi atn condition - target mode) bit 6 cmp (function complete) bit 5 sel (selected) bit 4 rsl (reselected) bit 3 sge (scsi gross error) bit 2 udc (unexpected disconnect) bit 1 rst (scsi reset condition) bit 0 par (scsi parity error) register 41 (c1) scsi interrupt enable one (sien1) read/write bits 7-5 reserved bit 4 sbmc (scsi bus mode change) bit 3 reserved bit 2 sto (selection or reselection time-out) bit 1 gen (general purpose timer expired) bit 0 hth ( handshake-to-handshake timer expired) register 42 (c2) scsi interrupt status zero (sist0) read only bit 7 m/a (initiator mode: phase mismatch; target mode: satn/ active) bit 6 cmp (function complete) bit 5 sel (selected) bit 4 rsl (reselected) bit 3 sge (scsi gross error) bit 2 udc (unexpected disconnect) bit 1 rst (scsi rst/ received) bit 0 par (parity error) register 43 (c3) scsi interrupt status one (sist1) read only bits 7-5 reserved bit 4 sbmc (scsi bus mode change) bit 3 reserved bit 2 sto (selection or reselection time-out) bit 1 gen (general purpose timer expired) bit 0 hth (handshake-to-handshake timer expired) register 44 (c4) scsi longitudinal parity (slpar) read/write register 45 (c5) scsi wide residue (swide) read/write register 46 (c6) memory access control (macntl) read/write bits 7-4 typ3-0 (chip type) bit 3 dwr (datawr) bit 2 drd (datard) bit 1 pscpt (pointer scripts) bit 0 scpts (scripts) register 47 (c7) general purpose pin control (gpcntl) read/write bit 7 master enable bit 6 fetch enable bit 5 reserved bits 4-2 gpio4_en Cgpio2_en (gpio enable) bits 1-0 gpio1_enC gpio0_en (gpio enable) m/a cmp sel rsl sge udc rst par 76543210 default>>> 00000000 res res res sbmc res sto gen hth 76543210 default>>> xxx0x000 m/a cmp sel rsl sge udc rst par 76543210 default>>> 00000000 res res res sbmc res sto gen hth 76543210 default>>> xxx0x000 typ3 typ2 typ1 typ0 dwr drd pscpt scpts 76543210 default>>> 11010000 me fe res gpio4 gpio3 gpio2 gpio1 gpio0 76543210 default>>> 00x01111
register summary sym53c895 data manual a-7 register 48 (c8) scsi timer zero (stime0) read /write bits 7-4 hth (handshake-to-handshake timer period) bits 3-0 sel (selection time-out) register 49 (c9) scsi timer one (stime1) read/write bit 7 reserved bit 6 hthba (handshake-to-handshake timer bus activity enable) bit 5 gensf (general purpose timer scale factor) bit 4 hthsf (handshake to handshake timer scale factor) bits 3-0 gen3-0 (general purpose timer period) register 4a (ca) response id zero (respid0) read/write register 4b (cb) response id one(respid1) read/write . register 4c (cc) scsi test zero (stest0) read only bits 7-4 ssaid (scsi selected as id) bit 3 slt (selection response logic test) bit 2 art (arbitration priority encoder test) bit 1 soz (scsi synchronous offset zero) bit 0 som (scsi synchronous offset maximum) register 4d (cd) scsi test one (stest1) read/write bit 7 sclk bit 6 siso (scsi isolation mode) bits 5-4 reserved bit 3 qen (sclk quadrupler enable) bit 2 qsel (sclk quadrupler select) bits1-0 reserved register 4e (ce) scsi test two (stest2) read/write bit 7 sce (scsi control enable) bit 6 rof (reset scsi offset) bit 5 dif (scsi differential mode) bit 4 slb (scsi loopback mode) bit 3 szm (scsi high-impedance mode) bit 2 aws (always wide scsi) bit 1 ext (extend sreq/sack filtering) bit 0 low (scsi low level mode) register 4f (cf) scsi test three (stest3) read/write bit 7 te (tolerant enable) bit 6 str (scsi fifo test read) bit 5 hsc (halt scsi clock) bit 4 dsi (disable single initiator response) bit 3 s16 (16-bit system) bit 2 ttm (timer test mode) bit 1 csf (clear scsi fifo) bit 0 stw (scsi fifo test write) hth hth hth hrh sel sel sel sel 76543210 default>>> 00000000 res hthba gensf hthsf gen3 gen2 gen1 gen0 76543210 default>>> x0000000 ssaid3 ssaid2 ssaid1 ssaid0 slt art soz som 76543210 default>>> 00000x11 sclk siso res res qen qsel res res 76543210 default>>> 00xx00xx sce rof dif slb szm aws ext low 76543210 default>>> 00000000 te str hsc dsi s16 ttm csf stw 76543210 default>>> 00000000
register summary a-8 sym53c895 data manual register 50-51 (d0-d1) scsi input data latch (sidl) read only register 52 (d2) scsi test 4 (stest4) read only bit 7-6 smode (scsi mode) bit 5 lock (frequency lock) bits 4-0 reserved registers 54-55 (d4-d5) scsi output data latch (sodl) read/write registers 58-59 (d8-d9) scsi bus data lines (sbdl) read only registers 5c-5f (dc-df) scratch register b (scratchb) (read/write) registers 60h-7fh (e0h-ffh) scratch registers c-j (scratchc-scratchj) read/write smode lock res res res res res 76543210 default>>> xx0xxxxx
mechanical drawing sym53c895 data manual b-1 all dimensions in millimeters figure b-1: sym53c895 mechanical drawing, 208-pin qfp pin 208 pin 52 pin 104 pin 157 pin 1 indicator 28.00 31.90 0.80 0.15 seating plane .50 3.40 0.20 0.25 min 28.00 31.90 208-pin plastic quad flat package (qfp) 0.27 max 0.17 min 4.10 max 0<3.5< 7 appendix b mechanical drawing
mechanical drawing b-2 sym53c895 data manual all dimensions in millimeters figure b-2:sym53c895 mechanical drawing, 292-ball bga mold compound bt laminate die solder ball side view top view 27.00 (ref.) 27.00 (ref.) pad #1, a1 corner mold compound organic laminate 1.27 solder ball pitch bottom view all dimensions in millimeters 0.635 pad #1, a1 corner a c b a b c d e f g h j k l m n p r t u v w y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.75 +/- 0.15 a = 2.15 -2.35 nom. b = 0.60 +/- 0.10 c = 0.36-0.56 nom. optional thermal matrix up to 6 x 6 balls
external memory interface diagram examples sym53c895 data manual c-1 figure c-1:16 k interface with 200 ns memory sym53c895 27c128 hct374 hct374 moe/ mce/ mad7-0 bus d(7-0) a(7-0) a(13-8) mas0/ mas1/ 8 6 d0 d7 ck q0 q7 oe do qo d5 q5 ck oe mad bus sense logic enabled for 16 kb of slow memory (200 ns device @ 33mhz) oe ce mad0 mad1 mad2 mad3 4.7k 4.7k 4.7k 4.7k vss appendix c external memory interface diagram examples
external memory interface diagram examples c-2 sym53c895 data manual figure c-2:64 k interface with 150 ns memory sym53c895 27c512-15/ 28f512-15/ socket hct374 hct374 mce/ mad7-0 bus d(7-0) a(7-0) a(15-8) mas0/ mas1/ 8 8 d0 d7 ck q0 q7 oe do qo d7 q7 ck oe mad bus sense logic enabled for 64 kb of fast memory (150 ns device @ 33mhz) oe ce mwe/ gpio4 + 12v vpp control vpp optional - for flash memory only, not required for eeproms we vss mad1 mad3 4.7k 4.7k vss moe/ vdd 4.7k mad0 4.7k mad2
external memory interface diagram examples sym53c895 data manual c-3 figure c-3:256 k interface with 150 ns memory sym53c895 27c020-15/ 28f020-15/ socket hct374 hct374 moe/ mce/ mad7-0 bus d(7-0) a(7-0) a(15-8) mas0/ mas1/ 8 4 d0 d7 ck q0 oe do qo d7 q7 ck oe mad bus sense logic enabled for 256kb of fast memory (150 ns device @ 33mhz). the hct374s may be replaced with hct377s. oe ce mwe/ gpio4 + 12v vpp control vpp optional - for flash memory only, not required for eeproms we hct377 do qo d1 q1 ck e 8 mad3-0 bus a(19-16) vdd 4.7k mad3 4.7k mad0 mad1 mad2 4.7k 4.7k vss vss
external memory interface diagram examples c-4 sym53c895 data manual figure c-4:512 k interface with 150 ns memory sym53c895 27c010-15/28f010-15 sockets hct374 hct374 moe/ mce/ mad7-0 bus d(7-0) a(7-0) a(15-8) mas0/ mas1/ 8 3 d0 d7 ck q0 q7 oe do qo d7 q7 ck oe mad bus sense logic enabled for 512 kb of slow memory (150 ns devices, additional time required for hct139 @ 33mhz). the hct374s may be replaced with hct377s. oe mwe/ gpio4 + 12v vpp control vpp optional - for flash memory only, not required for eeproms we hct377 do qo d2 q2 ck e 8 mad2-0 bus a16 a0 a16 oe we a0 a16 oe we a0 a16 oe we a0 a16 d0 d7 d0 d7 d0 d7 d0 d7 hct139 a yo b y3 gb y1 y2 ce ce ce ce mad0 mad2 4.7k 4.7k vss vdd 4.7k mad1 4.7k mad3
circuit board layout issues signal separation sym53c895 data manual d-1 appendix d circuit board layout issues higher data transfer rates, such as ultra2 scsi, make good printed circuit board (pcb) layout practices more critical than ever. some of the lay- out design criteria that need to be considered are separation of lvd and ttl/cmos signals, rout- ing of the differential pairs, trace impedance, stub lengths, decoupling power supplies and the dielec- tric constant of the board material. when certain pcb layout guidelines are not followed, various signal degradation effects can result. reflections are caused by impedance mismatches. cross-talk, dielectric loss, skin effects, dispersion loss and reduction of noise margin are some other unwanted by-products of poor pcb layout prac- tices. note: this information was originally published in symbios system engineering notes 893 (pcb layout for sym53c895) and 898 (analog power filtering for sym53c895). signal separation avoid crosstalk problems by providing a good sep- aration between lvd and ttl/cmos signals. crosstalk is proportional to dv/dt. ttl/cmos signals have larger voltage swings than lvd and can effect them if lines are running in close prox- imity. the best means of separation is to provide a ground trace between the two types of signals. another means of keeping the two kinds of signals apart is to place them on separate layers. if lvd and ttl/cmos signals need to be on the same layer, they should be separated by as much dis- tance as possible. routing signal lines routing of differential lines is an important factor in maintaining signal integrity. differentially paired traces must be kept equidistant. each line should be kept as parallel as possible to its counterpart. to avoid skew issues, the two lines should be exactly the same in length. abiding by these rules ensures that the rejection of common mode noise, inherent to differentially paired signals, remains intact. another consideration in laying out these traces is to avoid sharp orthogonal turns. his type of turn needs to be angled to avoid sharp changes in impedance. impedance matching trace impedance should match the impedance of the media as close as possible to avoid signal reflec- tions. a typical differential impedance for the cable is about 120 ohms. the impedance of a trace on the pcb is controlled by its height and width, as well as the thickness of the dielectric. the imped- ance of a trace pair is controlled by the distance between the two traces. termination and stub length the impedance of the terminator should match that of the cable. terminators need to be placed at the far ends of the cable and as close to the receiver inputs as possible. stub lengths of any device placed along the bus need to be kept short to avoid impedance mismatches that result in reflections. the ultra2 scsi standard stipulates that stub lengths for lvd busses should not exceed 0.1m.
circuit board layout issues decoupling d-2 sym53c895 data manual additionally differences in stub lengths between req, ack, data and parity signals shall not exceed 1.27cm. decoupling decoupling caps need to be as close to the chip vdd pins as possible. the main power supply line should also be decoupled. smt parts are pre- ferred. the long lead lengths of axial leaded parts add inductance to the line. dielectric another design criteria that should be considered is that the dielectric constant of the board material should be as low as possible. teflon has a dielectric constant rating twice as low as fr-4 which is a common material used in pcbs and so has lower losses. the disadvantage of teflon is that it is more expensive. considerations specific to the sym53c895 rbias +/- pins the rbias +/- pins, 130 and 129, need to have a 2.2 kohm resistor between them to provide the correct bias current to the lvd pads. additionally +3 .3v n eeds to be connect ed to rb ias-, pin 129 . n scsi lines should be short, with no ts and all of them are about the same length. n all pci lines need to be less than 1.5 inches long. n all gnds and pwr traces need to be short, wide and doubled. physical dimensions the sym53c895 is packaged in a 28 x 28 mm plastic quad flat package (pqfp). the total space required is 31.9 x 31.9 mm including pins. refer to the mechanical drawing in the data manual for other specific dimensions. power requirements a 3.3v regulator (lt1086) is used to derive the v dd supply voltage. v dd-a pin the v dd-a pin (pin 85 or h19) on the sym53c895 scsi i/o processor (siop) provides power to the phase locked loop (pll) and is sensi- tive to noise. board configurations that expose v dd-a to noise above 90 mv at frequencies above 120 mhz are susceptible. external ac filtering is required to prevent high frequency noise from reaching the pll. neglecting to incorporate this filter may result in unpredictable scsi bus behav- ior. this is particularly problematic during scsi data out and data in phases at ultra2 speeds. analog power noise will affect the ability of the siop to accurately clock req/ and ack/ signals. as a result, the siop may double clock an incom- ing req/ signal or generate an extra ack/ signal. this miscounting will manifest itself as a data underrun or a data overrun. a ferrite bead is required to perform this filtering. the bead should be placed in series between v dd-a and the 3.3v p owe r s u p p ly a s f o llow s : the bead should provide between 50w and 90w impedance above 120 mhz and should be rated to handle currents up to 25 ma. no de-coupling capacitor is needed in this configuration. +3.3v v dd-a
circuit board layout issues considerations specific to the sym53c895 sym53c895 data manual d-3 te r m i n a t o r s unitrode terminators (ucc5630) are recom- mended. they provide both lvd and single-ended termination, depending on what mode of operation is detected by the diffsens pin. all gnds to the terminators should be short, wide and dou- bled. reg is tied to ground through five 1uf caps. capacitive load the total capacitance budget dictated by the scsi parallel interconnect - 2 (spi-2) standard is pres- ently 25pf. the sym53c895 is about 13pf. a high density (68 pin) connector is about 3pf. that leaves a budget of about 10pf for traces. calcula- tions show that the trace lengths should be held to about 4 inches maximum under these conditions. further calculations to determine allowable deltas in trace length between different signals show that +/- 1.46 inches is the maximum. this will accom- modate less than 200ps of skew between signals. spi-2 document refer to the scsi parallel interconnect 2 (spi-2) standard on ultra2 scsi for specific definitions of lvd technology as it pertains to scsi. it also talks about requirements for ultra2 scsi data rates, vhdci connectors, sca-2 connectors, diffsens and termpwr signals. the spec, which is up to revision 11, can be found on the world wide web at: ftp.symbios.com/pub/standards/io/x3t10/drafts/spi2
circuit board layout issues considerations specific to the sym53c895 d-4 sym53c895 data manual
sym53c895 d ata m anual i ndex -1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . numerics 53c700 compatibility bit 5-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a abort operation bit 5-23 aborted bit 5-18, 5-36 absolute maximum stress ratings 7-1 active negation see tolerant technology active termination 2-16 adder register 5-38 adder sum output register 5-38 address and data pins 4-11 always wide scsi bit 5-51 arbitation in progress bit 5-20 arbitration arbitration in progress bit 5-20 arbitration mode bits 5-5 arbitration pins 4-13 immediate arbitration bit 5-8 lost arbitration bit 5-20 won arbitration bit 5-20 arbitration mode bits 5-5 arbitration priority encoder test bit 5-49 assert even scsi parity bit 5-7 assert satn/ on parity error bit 5-6 assert scsi ack/ signal bit 5-16 assert scsi atn/ signal bit 5-16 assert scsi bsy/ signal bit 5-16 assert scsi c_d/ signal bit 5-16 assert scsi data bus bit 5-7 assert scsi i_o signal bit 5-16 assert scsi msg/ signal bit 5-16 assert scsi req/ signal bit 5-16 assert scsi rst/ signal bit 5-7 assert scsi sel/ signal bit 5-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b big and little endian support 2-7 block diagram 1-6 block move instructions 6-4 burst disable bit 5-29 burst length bits 5-31, 5-35 burst op code fetch enable bit 5-36 bus fault bit 5-18, 5-36 byte empty in dma fifo bit 5-25 byte full in dma fifo bit 5-25 byte offset counter bits 5-28, 5-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c cache line size enable bit 5-37 cache mode, see pci cache mode 3-2 chained block moves 2-25C2-27 sodl register 2-26 swide register 2-26 wide scsi receive bit 2-26 wide scsi send bit 2-25 chained mode bit 5-9 chip revision level bits 5-27 chip test five register 5-30 chip test four register 5-29 chip test one register 5-25 chip test six register 5-31 chip test two register 5-26 chip test zero register 5-25 chip type bits 5-45 clear dma fifo bit 5-27 clear scsi fifo bit 5-53 clock address incrementor bit 5-30 clock byte counter bit 5-30 clock conversion factor bits 5-11 clock quadrupler. see scsi clock quadrupler clock timing 7-9
index-2 sym53c895 data manual configuration registers. see pci configuration registers configured as i/o bit 5-26 configured as memory bit 5-26 connected bit 5-7, 5-23 ctest0 register 5-25 ctest1 register 5-25 ctest2 register 5-26 ctest4 register 5-29 ctest5 register 5-30 ctest6 register 5-31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d data acknowledge status bit 5-26 data path 2-10 data request status bit 5-26 data structure address register 5-22 data transfer direction bit 5-26 datard bit 5-45 datawr bit 5-45 dbc register 5-32 dcmd register 5-32 dcntl register 5-37 destination i/o-memory enable bit 5-35 dfifo register 5-28 dien register 5-36 dif bit 5-51 differential mode. see high-voltage differential mode diffsens pin 4-17 diffsens signal 4-15 disable halt on parity error or atn 5-7 disable single initiator response bit 5-52 disconnects scsi data path 2-10 dma byte counter register 5-32 dma command register 5-32 dma control register 5-37 dma core 2-1 dma direction bit 5-31 dma fifo bits 5-31 dma fifo empty bit 5-18 dma fifo register 5-28 dma fifo size bit 5-30 dma interrupt enable register 5-36 dma interrupt pending bit 5-24 dma mode register 5-35 dma next address register 5-33 dma scripts pointer register 5-33 dma scripts pointer save register 5-34 dma status register 5-18 dmode register 5-35 dnad register 5-33 dsa register 5-22 dsp register 5-33 dsps register 5-34 dstat register 5-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e enable parity checking bit 5-6 enable read line bit 5-35 enable read multiple bit 5-35 enable response to reselection bit 5-12 enable response to selection bit 5-12 enable wide scsi bit 5-11 encoded chip scsi id 5-12 encoded destination scsi id bit 5-17 encoded destination scsi id bits 5-15 error reporting pins 4-13 extend sreq/sack filtering bit 5-51 external memory interface 2-4 configuration 2-4 flash rom updates 2-4 gpio4 bit 5-15 memory sizes supported 2-4 multiple byte accesses 7-11 parallel rom interface 2-4 slow memory 2-5 system requirements 2-4 timings 7-34C7-49 extra clock cycle of data setup bit 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . f fetch enable 5-45 fetch pin mode bit 5-27 fifo byte control bits 5-30 fifo flags bits 5-20, 5-22 flush dma fifo bit 5-27 function complete bit 5-39, 5-41 functional signal grouping 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . g general description 1-1 general purpose pin control register 5-45 general purpose register 5-15 general purpose timer expired bit 5-40, 5-42
sym53c895 data manual index-3 general purpose timer period bits 5-48 general purpose timer scale factor bit 5-47 gpcntl register 5-45 gpio enable bit 5-45 gpio pins sdms use of 5-15 gpio4-0 bits 5-15 gpreg register 5-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h halt scsi clock bit 5-52 handshake-to-handshake timer bus activity enable bit 5-47 handshake-to-handshake timer expired bit 5- 40, 5-43 handshake-to-handshake timer period bit 5- 46 high impedance mode bit 5-29 high voltage differential mode auto-switching with lvd and single-ended mode 2-13 description 2-13 diffsens mismatch bit 5-22 fast scsi timings 7-53 scsi-1 timings 7-53 ultra scsi timings 7-55 wiring diagram 2-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i i/o instructions 6-8 illegal instruction detected bit 5-18 immediate arbitration bit 5-8 instruction prefetching 2-3 no flush option 6-21, 6-23 pre-fetch enable bit 5-37 pre-fetch flush bit 5-37 prefetch unit flushing 2-3 instructions block move 6-4 i/o 6-8 load and store 6-23 memory move 6-21 read/write 6-13 transfer control 6-17 interface control pins 4-12 internal ram, see scripts ram interrupt on the fly bit 5-23 interrupt status register 5-23 interrupts 2-22 fatal vs. non-fatal interrupts 2-23 halting 2-24 irq disable bit 2-23 masking 2-23 sample interrupt service routine 2-25 stacked interrupts 2-24 timings 7-10 irq disable bit 5-38 irq mode bit 5-38 istat register 5-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l last disconnect bit 5-22 latched scsi parity bit 5-21 latched scsi parity for sd15-8 bit 5-22 load and store instructions 6-23 no flush option 6-23 prefetch unit and store instructions 2-3 lost arbitration bit 5-20 low voltage differential. see lvdlink lvdlink benefits 1-2 dc characteristics 7-2 diffsens pin 4-15 operation 2-12 scsi bus mode change bit 5-40, 5-42 scsi mode bit 5-54 scsi pin descriptions 4-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m macntl register 5-45 manual start mode bit 5-36 master control for set or reset pulses bit 5-30 master data parity error bit 5-18, 5-36 master enable bit 5-45 master parity error enable bit 5-30 max scsi synchronous offset bits 5-14 memory access control register 5-45 memory move instructions 6-21 and scripts instruction prefetching 2-3 no flush option 2-3 memory read line command 3-5 memory read multiple command 3-5 memory write and invalidate command 3-3 write and invalidate mode bit 3-8
index-4 sym53c895 data manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n new features in the sym53c895 1-2 no flush memory move instruction 6-21 no flush store instruction 6-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o op code fetch bursting 2-4 operating conditions 7-1 operating registers adder sum output 5-38 chip test five 5-30 chip test four 5-29 chip test one 5-25 chip test six 5-31 chip test three 5-27 chip test two 5-26 chip test zero 5-25 data structure address 5-22 dma byte counter 5-32 dma command 5-32 dma control 5-37 dma fifo 5-28 dma interrupt enable 5-36 dma mode 5-35 dma next address 5-33 dma scripts pointer 5-33 dma scripts pointer save 5-34 dma status 5-18 general information 5-1 general purpose 5-15 general purpose pin control 5-45 interrupt status 5-23 memory access control 5-45 register address map 5-4 response id one 5-48 response id zero 5-48 scratch byte 5-37 scratch register a 5-34 scratch register b 5-55 scratch registers c-j 5-56 scsi bus control lines 5-17 scsi bus data lines 5-55 scsi chip id 5-12 scsi control one register 5-7 scsi control register two 5-9 scsi control three 5-10 scsi control zero 5-5 scsi destination id 5-15 scsi first byte received 5-16 scsi input data latch 5-53 scsi interrupt enable one 5-40 scsi interrupt enable zero 5-39 scsi interrupt status one 5-42 scsi interrupt status zero 5-41 scsi longitudinal parity 5-43 scsi output control latch 5-16 scsi output data latch 5-54 scsi selector id 5-17 scsi status one 5-20 scsi status two 5-21 scsi status zero 5-19 scsi test four 5-54 scsi test one 5-50 scsi test three 5-52 scsi test two 5-51 scsi test zero 5-49 scsi timer one 5-47 scsi timer zero 5-46 scsi transfer 5-12 scsi wide residue 5-44 temporary stack 5-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p parity 2-8C2-9 parity error bit 5-42 pci cache mode 3-2 cache line size enable bit 5-37 cache line size register 3-11 enable read multiple bit 5-35 memory read line command 3-5 memory read multiple command 3-5 memory write and invalidate command 3- 3 write and invalidate mode bit 3-8 write and invalidate enable bit 5-27 pci commands 3-1 pci configuration registers subsystem id 3-12 subsystem vendor id 3-12 pci configuration registers 3-6C3-13 base address one (memory) 3-12 base address zero (i/o) 3-12 cache line size 3-11 class code 3-11 command 3-8
sym53c895 data manual index-5 device id 3-8 expansion rom base address 3-12 header type 3-11 interrupt line 3-13 interrupt pin 3-13 latency timer 3-11 max_lat 3-13 min_gnt 3-13 revision id 3-10 status 3-9 vendor id 3-8 pci configuration space 3-1 pci i/o space 3-1 pci memory space 3-1 phase mismatch bit 5-41 pinout diagram 4-2, 4-3, 4-4 pins address and data pins 4-11 arbitration pins 4-13 error reporting pins 4-13 functional signal grouping 4-7 interface control pins 4-12 scsi pins 4-14, 4-16 system pins 4-11 pointer scripts bit 5-45 power and ground pins 4-9 pre-fetch enable bit 5-37 pre-fetch flush bit 5-37 pull-ups, internal, conditions 4-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . q qen bit 3 5-50 qsel bit 2 5-50 quadrupling the scsi clock frequency 5-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . r ram, see scripts ram read/write instructions 6-13 register address map register addresses operating registers 00h 5-5 01h 5-7 02h 5-9 03h 5-10 04h 5-12 05h 5-12 06h 5-15 07h 5-15 08h 5-16 09h 5-16 0ah 5-17 0bh 5-17 0ch 5-18 0dh 5-19 0eh 5-20 0fh 5-21 10-13h 5-22 14h 5-23 18h 5-25 19h 5-25 1ah 5-26 1bh 5-27 1c-1fh 5-28 20h 5-28 21h 5-29 22h 5-30 23h 5-31 24-26h 5-32 27h 5-32 28-2bh 5-33 2c-2fh 5-33 30-33h 5-34 34-37h 5-34 38h 5-35 39h 5-36 3ah 5-37 3bh 5-37 3c-3fh 5-38 40h 5-39 41h 5-40 42h 5-41 43h 5-42 44h 5-43 45h 5-44 46h 5-45 47h 5-45 48h 5-46 49h 5-47 4ah 5-48 4bh 5-48 4ch 5-49 4dh 5-50 4eh 5-51 4fh 5-52 50-51h 5-53
index-6 sym53c895 data manual 54-55h 5-54 58-59h 5-55 5c-5fh 5-55 60-70h 5-56 pci configuration registers 00h 3-8 02h 3-8 04h 3-8 06h 3-9 08h 3-10 09h 3-11 0ch 3-11 0dh 3-11 0eh 3-11 10h 3-12 14h 3-12 18h 3-12 30h 3-12 3ch 3-13 3dh 3-13 3eh 3-13 3fh 3-13 subsystem id 3-12 subsystem vendor id 3-12 register bits 16-bit system 5-52 53c700 compatibility 5-38 abort operation 5-23 aborted 5-18, 5-36 always wide scsi 5-51 arbitration in progress 5-20 arbitration mode 5-5 arbitration priority encoder test 5-49 assert even scsi parity (force bad parity)) 5-7 assert satn/ on parity error 5-6 assert scsi ack/ signal 5-16 assert scsi atn/ signal 5-16 assert scsi bsy/ signal 5-16 assert scsi c_d/ signal 5-16 assert scsi data bus 5-7 assert scsi i_o/ signal 5-16 assert scsi msg/ signal 5-16 assert scsi req/ signal) 5-16 assert scsi rst/ signal 5-7 assert scsi sel/ signal 5-16 burst disable 5-29 burst length 5-31, 5-35 burst op code fetch enable 5-36 bus fault 5-18, 5-36 byte empty in dma fifo 5-25 byte full in dma fifo 5-25 byte offset counter 5-28, 5-31 cache line size enable 5-37 chained mode 5-9 chip revision level 5-27 chip type 5-45 clear dma fifo 5-27 clear scsi fifo 5-53 clock address incrementor 5-30 clock byte counter 5-30 clock conversion factor 5-11 configured as i/o 5-26 configured as memory 5-26 connected 5-7, 5-23 data acknowledge status 5-26 data request status 5-26 data transfer direction 5-26 datard 5-45 datawr 5-45 destination i/o-memory enable 5-35 diffsens mismatch 5-22 disable halt on parity error or atn 5-7 disable single initiator response 5-52 dma direction 5-31 dma fifo 5-31 dma fifo empty 5-18 dma fifo size 5-30 dma interrupt pending 5-24 enable parity checking 5-6 enable read line 5-35 enable read multiple 5-35 enable response to reselection 5-12 enable response to selection 5-12 enable wide scsi 5-11 encoded chip scsi id, bits 3-0 5-12 encoded destination scsi id 5-15, 5-17 extend sreq/sack filtering 5-51 extra clock cycle of data setup 5-7 fetch enable 5-45 fetch pin mode 5-27 fifo byte control 5-30 fifo flags 5-20, 5-22 flush dma fifo 5-27 frequency lock 5-54 function complete 5-39, 5-41
sym53c895 data manual index-7 general purpose timer expired 5-40, 5-42 general purpose timer period 5-48 general purpose timer scale factor 5-47 gpio enable 5-45 gpio4-0 5-15 halt scsi clock 5-52 handshake to handshake timer scale fac- tor 5-48 handshake-to-handshake timer bus ac- tivity enable 5-47 handshake-to-handshake timer expired 5-40, 5-43 handshake-to-handshake timer period 5- 46 high impedance mode 5-29 illegal instruction detected 5-18 illegal instruction detected 5-36 immediate arbitration 5-8 interrupt on the fly 5-23 irq disable 5-38 irq mode 5-38 last disconnect 5-22 latched scsi parity 5-21 latched scsi parity for sd15-8 5-22 lost arbitration 5-20 manual start mode 5-36 master control for set or reset pulses 5-30 master data parity error 5-18, 5-36 master enable 5-45 master parity error enable 5-30 max scsi synchronous offset 5-14 parity error 5-42 phase mismatch 5-41 pointer scripts 5-45 pre-fetch enable 5-37 pre-fetch flush 5-37 reselected 5-39, 5-41 reset scsi offset 5-51 sack/ status 5-17 satn/ status 5-17 sbsy/ status 5-17 sc_d/ status 5-17 sclk 5-50 sclk quadrupler enable 5-50 sclk quadrupler enable bit 5-50 sclk quadrupler select 5-50 sclk quadrupler select bit 5-50 scratcha/b operation 5-26 scripts 5-45 scripts interrupt instruction received 5- 18 scripts interrupt instruction received 5- 36 scsi bus mode change 5-40, 5-42 scsi c_d/ signal 5-21 scsi control enable 5-51 scsi data high impedance 5-29 scsi differential mode 5-51 scsi disconnect unexpected 5-9 scsi fifo test read 5-52 scsi fifo test write 5-53 scsi gross error 5-39, 5-41 scsi high-impedance mode 5-51 scsi i_o/ signal 5-21 scsi interrupt pending 5-24 scsi isolation mode 5-50 scsi loopback mode 5-51 scsi low level mode 5-51 scsi mode 5-54 scsi msg/ signal 5-21 scsi parity error 5-39 scsi phase mismatch - initiator mode 5-39 scsi reset condition 5-39 scsi rst/ received 5-42 scsi rst/ signal 5-20 scsi sdp0/ parity signal 5-20 scsi sdp1 signal 5-22 scsi selected as id 5-49 scsi synchronous offset maximum 5-49 scsi synchronous offset zero 5-49 scsi synchronous transfer period 5-12 scsi true end of process 5-26 scsi valid 5-17 select with satn/ on a start sequence 5-6 selected 5-39, 5-41 selection or reselection time-out 5-40, 5- 42 selection response logic test 5-49 selection time-out 5-46 semaphore 5-23 shadow register test mode 5-29 si_o/ status 5-17 sidl least significant byte full 5-19 sidl most significant byte full 5-21 signal process 5-23, 5-26 single step interrupt 5-18
index-8 sym53c895 data manual single-step interrupt 5-36 single-step mode 5-37 slpar high byte enable 5-9 slpar mode 5-9 smsg/ status 5-17 sodl least significant byte full 5-19 sodl most significant byte full 5-21 sodr least significant byte full 5-19 sodr most significant byte full 5-21 software reset 5-23 source i/o-memory enable 5-35 sreq/ status 5-17 ssel/ status 5-17 start dma operation 5-38 start scsi transfer 5-8 start sequence 5-5 synchronous clock conversion factor bits 5-10 target mode 5-6 timer test mode 5-52 tolerant enable 5-52 ultra enable 5-10 unexpected disconnect 5-39, 5-42 vendor unique enhancements 0 5-9 vendor unique enhancements 1 5-10 wide scsi receive 5-10 wide scsi send 5-9 won arbitration 5-20 write and invalidate enable 5-27 registers see operating registers reselected bit 5-39, 5-41 reset input 7-10 reset scsi offset bit 5-51 respid0 register 5-48 respid1 register 5-48 response id one register 5-48 response id zero register 5-48 revision level bits 5-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s sack/ status bit 5-17 satn/ active 5-41 satn/ active bit 5-41 satn/ status bit 5-17 sbcl register 5-17 sbdl register 5-55 sbr register 5-37 sbsy status bit 5-17 sc_d/ status bit 5-17 scf2-0 bits 5-10 scid register 5-12 sclk bit 5-50 scntl0 register 5-5 scntl1 register 5-7 scntl2 register 5-9 scntl3 register 5-10 scratch register 5-37 scratcha register 5-34 scratcha/b operation bit 5-26 scratchb register 5-55 scripts bit 5-45 scripts interrupt instruction received bit 5- 18 scripts processor 2-1 instruction prefetching 2-3 internal ram for instruction storage 2-2 performance 2-1 scripts ram 2-2 scratcha/b operation bit 5-26 scsi core 2-1 lvdlink 2-12 pins 4-14, 4-16 termination 2-16 timings 7-50 tolerant technology 1-3 ultra2 scsi 2-2 scsi atn condition - target mode 5-39 scsi atn condition bit 5-39 scsi bus control lines register 5-17 scsi bus data lines register 5-55 scsi bus interface 2-12C2-18 scsi bus mode change bit 5-40, 5-42 scsi c_d/ signal bit 5-21 scsi chip id register 5-12 scsi clk frequency quadrupling 5-50 scsi clock quadrupler qen bit 5-50 qsel bit 5-50 scsi clock quadupler frequency lock bit 5-54 scsi clock rates 5-11 scsi control enable bit 5-51 scsi control one register 5-7
sym53c895 data manual index-9 scsi control three register 5-10 scsi control two register 5-9 scsi control zero register 5-5 scsi core 2-1 scsi data high impedance bit 5-29 scsi destination id register 5-15 scsi differential mode bit 5-51 scsi disconnect unexpected bit 5-9 scsi fifo test read bit 5-52 scsi fifo test write bit 5-53 scsi first byte received register 5-16 scsi gross error bit 5-39, 5-41 scsi high-impedance mode bit 5-51 scsi i_o/ signal bit 5-21 scsi input data latch register 5-53 scsi instructions block move 6-4 i/o 6-8 load/store 6-23 memory move 6-21 read/write 6-13 transfer control 6-17 scsi interrupt enable one register 5-40 scsi interrupt enable zero register 5-39 scsi interrupt pending bit 5-24 scsi interrupt status one register 5-42 scsi interrupt status zero register 5-41 scsi isolation mode bits 5-50 scsi longitudinal parity register 5-43 scsi loopback mode bit 5-51 scsi low level mode bit 5-51 scsi msg/ signal bit 5-21 scsi output control latch register 5-16 scsi output data latch register 5-54 scsi parity error bit 5-39 scsi phase mismatch bit 5-39 scsi reset condition bit 5-39 scsi rst/ received bit 5-42 scsi rst/ signal bit 5-20 scsi scripts operation 6-1 sample instruction 6-2 scsi sdp0/ parity signal bit 5-20 scsi sdp1 signal bit 5-22 scsi selected as id bits 5-49 scsi selector id register 5-17 scsi status one register 5-20 scsi status two register 5-21 scsi status zero register 5-19 scsi synchronous offset maximun 5-49 scsi synchronous offset zero bit 5-49 scsi synchronous transfer period bits 5-12 scsi test one register 5-50 scsi test three register 5-52 scsi test two register 5-51 scsi test zero register 5-49 scsi timer one register 5-47 scsi timer zero register 5-46 scsi timings 7-50C7-55, ??C7-55 scsi transfer register 5-12 scsi true end of process bit 5-26 scsi valid bit 5-17 scsi wide residue register 5-44 sdid register 5-15 select with satn/ on a start sequence bit 5-6 selected bit 5-39, 5-41 selection or reselection time-out bit 5-40, 5- 42 selection response logic test bits 5-49 semaphore bit 5-23 sfbr register 5-16 shadow register test mode bit 5-29 si_o/ status bit 5-17 sidl least significant byte full bit 5-19 sidl most significant byte full bit 5-21 sidl register 5-53 sien0 register 5-39 sien1 register 5-40 sigp bit 5-23, 5-26 single step interrupt bit 5-18 single-ended mode scsi pin descriptions 4-16 single-step interrupt bit 5-36 single-step mode bit 5-37 sist0 register 5-41 sist1 register 5-42 slpar high byte enable 5-9 slpar mode bit 5-9 slpar register 5-43 smsg/ status bit 5-17 socl least significant byte full bit 5-19 socl register 5-16 sodl most significant byte full bit 5-21 sodl register 5-54 sodr least significant byte full bit 5-19 sodr most significant byte full bit 5-21 software reset bit 5-23
index-10 sym53c895 data manual source i/o-memory enable bit 5-35 sreq/ status bit 5-17 ssel/ status bit 5-17 ssid register 5-17 sstat0 register 5-19 sstat1 register 5-20 sstat2 register 5-21 stacked interrupts 2-24 start dma operation bit 5-38 start scsi transfer 5-8 start sequence bit 5-5 stest0 register 5-49 stest1 register 5-50 stest2 register 5-51 stest3 register 5-52 stime0 register 5-46 stime1 register 5-47 swide register 5-44 sxfer register 5-12 sym53c895 new features 1-2 synchronous clock conversion factor bits 5- 10 synchronous data transfer rates 2-19 system pins 4-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t target disconnect scsi data path 2-10 target mode bit 5-6 temp register 5-28 temporary register 5-28 termination 2-16 timer test mode bit 5-52 timings back to back read 7-27 back-to-back write 7-30, 7-32 burst op code fetch 7-23 burst read 7-30 burst write 7-32 clock 7-9 external memory read 7-18 interrupt output 7-10 operating register/scripts ram read 7- 15 operating register/scripts ram write 7- 16 pci 7-22, 7-26, 7-28, 7-30 pci configuration register read 7-12 pci configuration register write 7-14 read cycle, normal/fast memory, single byte access 7-34 read cycle, slow memory 7-42 reset input 7-10 scsi 7-50 ultra2 scsi 7-54 write cycle, normal/fast memory, multiple byte access 7-38 write cycle, normal/fast memory, single byte access 7-36 write cycle, slow memory 7-44 tolerant enable bit 5-52 tolerant technology 1-3 benefits 1-3 electrical characteristics 7-6 extend sreq/sack filtering bit 5-51 tolerant enable bit 5-52 tp2-0 bits 5-12 transfer control instructions 6-17 and scripts instruction prefetching 2-4 transfer rate synchronous 2-19 synchronous clock conversion factor bits 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . u ultra enable bit 5-10 ultra2 scsi benefits 1-3 designing an ultra2 scsi system 2-2 lvdlink 2-12 synchronous clock conversion factor bits 5-10 synchronous clock conversion factor bits 5-10 timings 7-54 ultra enable bit 5-10 unexpected disconnect bit 5-39, 5-42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v vendor unique enhancements 0 bit 5-9 vendor unique enhancements 1 bit 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . w watn/ bit 5-6
sym53c895 data manual index-11 what is covered in this manual 1-1 wide scsi always wide scsi bit 5-51 chained block moves 2-25 chained mode bit 5-9 enable wide scsi bit 5-11 swide register 5-44 wide scsi receive bit 5-10 wide scsi send bit 5-9 wide scsi receive bit 5-10 wide scsi send bit 5-9 won arbitration bit 5-20 write and invalidate enable bit 5-27
index-12 sym53c895 data manual
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sym53c895 pci-ultra2 scsi i/o processor data manual version 3.0 symbios, inc.

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