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pd78p098a mos integrated circuit 8-bit single-chip microcontroller the pd78p098a is a member of the pd78098 subseries of the 78k/0 series products, in which the on- chip mask rom of the pd78098a is replaced with one-time prom. because a program can be written by the user, the pd78p098a is ideal for evaluation of a system under development, small-scale production of a variety of systems, and early start of production of a system. the functions are explained in detail in the following manuals. be sure to read these manuals when designing your system. pd78098 subseries user? manual : ieu-1381 78k/0 series user? manual - instruction: u12326e features pin-compatible with mask rom model (except v pp pin) internal prom: 60k bytes note 1 internal high-speed ram : 1024 bytes buffer ram : 32 bytes internal expansion ram : 2048 bytes note 2 operating voltage same as mask rom model (v dd = 2.7 to 5.5 v) supports qtop tm microcontroller notes 1. the internal prom capacity can be changed by using the memory size select register(ims). 2. internal expansion ram capacity can be changed by using the internal expansion ram size select register(ixs). remark ?top microcontroller?is a generic name for one-time prom-containing microcontrollers totally supported by nec? writing service (writing, marking, screening, and inspection). the pd78p098a differs from the mask rom model in the following points: the memory can be mapped in the same manner as the mask rom model by using the memory size select register(ims) and internal expansion ram size select register(ixs). the p60 through p63 pins are not provided with pull-up resistors. document no. u10203ej2v0ds00 (2nd edition) date published june 2001 n cp(k) printed in japan ? 1995 data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points.
2 pd78p098a data sheet u10203ej2v0ds ordering information part number package pd78p098agc-8bt 80-pin plastic qfp (14 14)
3 pd78p098a data sheet u10203ej2v0ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with enhanced uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin ram capacity of the pd780024a increased. pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and increased rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42-/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. pd78054 with added timer and enhanced external interface rom-less version of the pd78078 100-pin pd78078y with enhanced serial i/o and limited function 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b pd78054 with added iebus tm controller. 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip d-can controller 100-pin pd780958 pd780816 pd780703y pd780833y pd780702y for industrial meter control on-chip automobile meter controller/driver meter control 80-pin 80-pin on-chip iebus controller 80-pin 64-pin on-chip d-can controller on-chip controller compliant with j1850 (class 2) specialized for d-can controller function pd780948 on-chip d-can controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd and c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for vfd drive. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338
4 pd78p098a data sheet u10203ej2v0ds the major functional differences among the subseries are shown below. function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface supported pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v pd780816 32 k to 64 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value rom capacity (bytes)
5 pd78p098a data sheet u10203ej2v0ds functional outline item function internal memory prom : 60k bytes note 1 ram internal high-speed ram : 1024 bytes buffer ram : 32 bytes internal expansion ram : 2048 bytes note 2 memory space 64k bytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction variable instruction execution time cycle with main system clock 0.5 s/1.0 s/2.0 s/4.0 s/8.0 s/16.0 s (at 6.0 mhz) with subsystem clock 122 s (at 32.768 khz) instruction set 16-bit operation multiplication/division (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjustment, etc. i/o port total : 69 cmos input : 2 cmos i/o : 63 n-ch open-drain i/o : 4 iebus controller effective transmission rate: 3.9 kbps/17 kbps/26 kbps a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels serial interface 3-line/sbi/2-line mode selectable : 1 channel 3-line mode (with function to automatically transfer/ receive 32 bytes max.) : 1 channel 3-line/uart mode selectable : 1 channel timer 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels watch timer : 1 channel watchdog timer : 1 channel timer output 3 (14-bit pwm output: 1) clock output 15.6 khz, 31.3 khz, 62.5 khz, 125 khz, 250 khz, 500 khz, 1.0 mhz, 2.0 mhz, 4.0 mhz (with 6.0-mhz main system clock) 32.768 khz (with 32.768-khz subsystem clock) buzzer output 977 hz, 1.95 khz, 3.9 khz, 7.8 khz (with 6.0-mhz main system clock) notes 1. the internal prom capacity can be changed by using the memory size select register (ims). 2. 0 or 2048 bytes can be selected by using the internal expansion ram size select register (ixs).
6 pd78p098a data sheet u10203ej2v0ds item function vector maskable interrupt internal: 14, external: 7 interrupt non-maskable interrupt internal: 1 software interrupt 1 test input internal: 1, external: 1 operating voltage v dd = 2.7 to 5.5 v package 80-pin plastic qfp (14 14)
7 pd78p098a data sheet u10203ej2v0ds pin configuration (top view) (1) normal operation mode 80-pin plastic qfp (14 1 4) pd78p098agc-8bt p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p40/ad0 p41/ad1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 reset p127/rtp7 p126/rtp6 p125/rtp5/rx p124/rtp4/tx p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 v pp x1 x2 v dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 cautions 1. directly connect the v pp pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss .
8 pd78p098a data sheet u10203ej2v0ds p00-p07 : port0 rx : receive data (iebus controller) p10-p17 : port1 tx : transmit data (iebus controller) p20-p27 : port2 pcl : programmable clock p30-p37 : port3 buz : buzzer clock p40-p47 : port4 stb : strobe p50-p57 : port5 busy : busy p60-p67 : port6 ad0-ad7 : address/data bus p70-p72 : port7 a8-a15 : address bus p120-p127 : port12 rd : read strobe p130, p131 : port13 wr : write strobe rtp0-rtp7 : real-time output port wait : wait intp0-intp6 : interrupt from peripherals astb : address strobe ti00, ti01 : timer input x1, x2 : crystal (main system clock) ti1, ti2 : timer input xt1, xt2 : crystal (subsystem clock) to0-to2 : timer output reset : reset sb0, sb1 : serial bus ani0-ani7 : analog input si0-si2 : serial input ano0, ano1 : analog output so0-so2 : serial output av dd : analog power supply sck0-sck2 : serial clock av ss : analog ground rxd : receive data (uart) av ref0, 1 : analog reference voltage txd : transmit data (uart) v dd : power supply asck : asynchronous serial clock v pp : programming power supply v ss : ground
9 pd78p098a data sheet u10203ej2v0ds (2) prom programming mode 80-pin plastic qfp (14 14) pd78p098agc-8bt (l) v ss v ss (l) a0 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 reset d7 d6 d5 d4 d3 d2 d1 d0 ce 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 oe (l) v ss v dd (l) open v pp (l) open (l) pgm (l) a9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (l) (l) (l) (l) cautions 1. (l) : individually connect these pins to v ss via a pull-down resistor. 2. v ss : connect this pin to ground. 3. reset : keep this pin to the low level. 4. open : connect nothing to these pins. a0-a16 : address bus reset : reset d0-d7 : data bus v dd : poewr supply ce : chip enable v pp : programming power supply oe : output enable v ss : ground pgm : program
10 pd78p098a data sheet u10203ej2v0ds block diagram 16-bit timer/ event counter to0/p30 ti00/intp0/p00 ti01/intp1/p01 8-bit timer/ event counter 1 to1/p31 ti1/p33 8-bit timer/ event counter 2 to2/p32 ti2/p34 watchdog timer watch timer serial interface 0 si0/sb0/p25 so0/sb1/p26 sck0/p27 serial interface 1 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 serial interface 2 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 a/d converter ani0/p10- ani7/p17 av dd av ss av ref0 d/a converter ano0/p130, ano1/p131 av ss av ref1 interrupt control intp0/p00- intp6/p06 real-time output port rtp0/p120- rtp7/p127 ieb us controller tx/p124/rtp4 rx/p125/rtp5 buzzer output buz/p36 clock output control pcl/p35 port0 p00 p01-p06 p07 port1 p10-p17 port2 p20-p27 port3 p30-p37 port4 p40-p47 port5 p50-p57 port6 p60-p67 port7 p70-p72 port12 p120-p127 port13 p130,p131 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 external access reset x1 x2 xt1/p07 xt2 system control 78k/0 cpu core prom ram v ss v dd v pp
11 pd78p098a data sheet u10203ej2v0ds table of contents 1. differences between pd78p098a and mask rom model .................................... 12 2. pin functions .......................................................................................................................... 13 2.1 pins in normal operation mode ...................................................................................... 13 2.2 pins in prom programming mode ................................................................................. 16 2.3 pin i/o circuits and handling of unused pins .............................................................. 17 3. memory size select register (ims) .............................................................................. 21 4. internal expansion ram size select register (ixs) ............................................ 22 5. prom programming .............................................................................................................. 23 5.1 operation modes ................................................................................................................ 23 5.2 prom writing procedure ................................................................................................. 25 5.3 prom read procedure ..................................................................................................... 29 6. screening of one-time prom model ............................................................................ 30 7. electrical specifications ............................................................................................... 31 8. package drawings ............................................................................................................. 65 9. recommended soldering conditions ........................................................................ 66 appendix a. development tools ......................................................................................... 67 appendix b. related documents ......................................................................................... 71
12 pd78p098a data sheet u10203ej2v0ds 1. differences between pd78p098a and mask rom model the pd78p098a is provided with a one-time prom to which a program can be written only once. the functions of the pd78p098a, except the prom specification and the mask option of p60 through p63 pins, can be set to be the same as those of the mask rom model by using the memory size select register and internal expansion ram size select register. table 1-1 shows the differences between the pd78p098a and mask rom model. table 1-1. differences between pd78p098a and mask rom model item pd78p098a mask rom model ic pin not provided provided v pp pin provided not provided mask option of p60-p63 pins pull-up resistor not provided pull-up resistor can be provided by mask option cautions 1. the internal rom capacity of the pd78p098a can be changed by using the memory size select register. the internal prom capacity is set to 60k bytes at reset. 2. the internal expansion ram capacity of the pd78p098a can be changed by using the internal expansion ram size select register. the internal expansion ram capacity is set to 2k bytes at reset.
13 pd78p098a data sheet u10203ej2v0ds 2. pin functions 2.1 pins in normal operation mode (1) port pins (1/2) pin name i/o function at reset shared with: p00 input port 0. input only input intp0/ti00 p01 i/o 8-bit i/o port can be set in input or output mode in 1-bit input intp1/ti01 p02 units. intp2 p03 when used as an input port, a pull-up intp3 p04 resistor can be connected via software. intp4 p05 intp5 p06 intp6 p07 note 1 input input only input xt1 p10-p17 i/o port 1. input ani0-ani7 8-bit i/o port. can be set in input or output mode in 1-bit units. when used as an input port, a pull-up resistor can be connected via software. note 2 p20 i/o port 2. input si1 p21 8-bit i/o port. so1 p22 can be set in input or output mode in 1-bit units. sck1 p23 when used as an input port, a pull-up resistor can be connected stb p24 via software. busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 i/o port 3. input to0 p31 8-bit i/o port. to1 p32 can be set in input or output mode in 1-bit units. to2 p33 when used as an input port, a pull-up resistor can be connected ti1 p34 via software. ti2 p35 pcl p36 buz p37 notes 1. when using the p07/xt1 pin as an input port pin, set bit 6 (frc) of the processor clock control register to 1 and do not use the feedback resistor of the subsystem clock oscillation circuit. 2. when using the p10/ani0 through p17/ani7 pins as analog input pins of the a/d converter, the pull-up resistors are automatically disconnected.
14 pd78p098a data sheet u10203ej2v0ds (1) port pins (2/2) pin name i/o function at reset shared with: p40-p47 i/o port 4. input ad0-ad7 8-bit i/o port. can be set in input or output mode in 8-bit units. when used as an input port, a pull-up resistor can be connected via software. test input flag (krif) is set to 1 at falling edge of this port. p50-p57 i/o port 5. input a8-a15 8-bit i/o port. can directly drive led. can be set in input or output mode in 1-bit units. when used as an input port, a pull-up resistor can be connected via software. p60 i/o port 6. n-ch open-drain i/o port. input p61 8-bit i/o port. can directly drive led. p62 can be set in input or p63 output mode in 1-bit p64 units. when used as an input port, a pull-up input input rd p65 resistor can be connected via software. wr p66 wait p67 astb p70 i/o port 7. input si2/rxd p71 3-bit i/o port. so2/txd p72 can be set in input or output mode in 1-bit units. sck2/asck when used as an input port, a pull-up resistor can be connected via software. p120-p123 i/o port 12. input rtp0-rtp3 p124 8-bit i/o port. rtp4/tx p125 can be set in input or output mode in 1-bit units. rtp5/rx p126, p127 when used as an input port, a pull-up resistor can be connected rtp6, rtp7 via software. p130, p131 i/o port 13. input ano0, ano1 2-bit i/o port. can be set in input or output mode in 1-bit units. when used as an input port, a pull-up resistor can be connected via software.
15 pd78p098a data sheet u10203ej2v0ds (2) pins other than port pins (1/2) pin name i/o function at reset shared with: intp0 input external interrupt input whose valid edge can be specified (rising input p00/ti00 intp1 edge, falling edge, and both rising and falling edges). p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial data input to serial interface. input p25/sb0 si1 p20 si2 p70/rxd so0 output serial data output from serial interface. input p26/sb1 so1 p21 so2 p71/txd sb0 i/o serial data input/output of serial interface. input p25/si0 sb1 p26/so0 sck0 i/o serial clock input/output of serial interface. input p27 sck1 p22 sck2 p72/asck stb output strobe signal output for serial interface automatic transmission/reception. input p23 busy input busy input for serial interface automatic transmission/reception. input p24 rxd input serial data input to asynchronous serial interface. input p70/si2 txd output serial data output from asynchronous serial interface. input p71/so2 asck input serial clock input to asynchronous serial interface. input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0). input p00/intp0 ti01 capture trigger signal input to capture register (cr00). p01/intp1 ti1 external count clock input to 8-bit timer (tm1). p33 ti2 external count clock input to 8-bit timer (tm2). p34 to0 output 16-bit timer output (shared with 14-bit pwm output). input p30 to1 8-bit timer output (tm1). p31 to2 8-bit timer output (tm2) p32 pcl output clock output (for trimming of main system clock and subsystem input p35 clock) buz output buzzer output input p36 rtp0-rtp3 output real-time output port outputting data in synchronization with input p120-p123 rtp4 trigger. p124/tx rtp5 p125/rx rtp6, rtp7 p126, p127 tx output data output for iebus controller. input p124/rtp4 rx input data input for iebus controller. input p125/rtp5
16 pd78p098a data sheet u10203ej2v0ds (2) pins other than port pins (2/2) pin name i/o function at reset shared with: ad0-ad7 i/o low-order address/data bus when external memory is connected. input p40-p47 a8-a15 output high-order address bus when external memory is connected. input p50-p57 rd output strobe signal output for read operation on external memory. input p64 wr strobe signal output for write operation on external memory. input p65 wait input wait state insertion for external memory access. input p66 astb output strobe output to externally latch address information output to input p67 ports 4 and 5 to access external memory. ani0-ani7 input analog input of a/d converter. input p10-p17 ano0, ano1 output analog output of d/a converter. input p130, p131 av ref0 input reference voltage input of a/d converter. av ref1 input reference voltage input of d/a converter. av dd analog power supply of a/d converter. connected to v dd . av ss ground of a/d converter. connected to v ss . reset input system reset input. x1 input crystal connection for main system clock oscillation. x2 xt1 input crystal connection for subsystem clock oscillation. input p07 xt2 v dd positive power supply. v pp high-voltage application for program write/verify. directly connected to v ss in normal operation mode. v ss ground. 2.2 pins in prom programming mode pin name i/o function reset input prom programming mode setting. when +5 v or +12.5 v is applied to the v pp pin, and low level is applied to the reset pin, prom programming mode is set. v pp input prom programming mode setting and high voltage application for program write/verify. a0-a16 input address bus. d0-d7 i/o data bus. ce input prom enable input/program pulse input. oe input read strobe input to prom. pgm input program/program inhibit input in prom programming mode. v dd positive power supply. v ss ground.
17 pd78p098a data sheet u10203ej2v0ds 2.3 pin i/o circuits and handling of unused pins table 2-1 shows the types of the i/o circuits for the various pins and handling of unused pins. for the configuration of the various i/o circuits, refer to figure 2-1. table 2-1. i/o circuit type of each pin (1/2) pin name i/o circuit type i/o recommended connection when not used p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a i/o individually connect to v ss via resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd or v ss . p10/ani0-p17/ani7 11 i/o individually connect to v dd or v ss via resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0-p47/ad7 5-e individually connect to v dd via resistor. p50/a8-p57/a15 5-a individually connect to v dd or v ss via resistor. p60-p63 13-d individually connect to v dd via resistor. p64/rd 5-a individually connect to v dd or v ss via resistor. p65/wr p66/wait p67/astb
18 pd78p098a data sheet u10203ej2v0ds table 2-1. i/o circuit type of each pin (2/2) pin name i/o circuit type i/o recommended connection when not used p70/si2/rxd 8-a i/o individually connect to v dd or v ss via resistor. p71/so2/txd 5-a p72/sck2/asck 8-a p120/rtp0-p123/rtp3 5-a p124/rtp4/tx p125/rtp5/rx p126/rtp6, p127/rtp7 p130/ano0, p131/ano1 12-a individually connect to v ss via resistor. reset 2 input xt2 16 open av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . v pp directly connect to v ss .
19 pd78p098a data sheet u10203ej2v0ds figure 2-1. i/o circuits of pins (1/2) in pullup enable v dd p-ch in/out input enable output disable data v dd p-ch n-ch type 2 type 5-a schmitt trigger input with hysteresis characteristics type 5-e type 11 type 10-a type 8-a pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch v dd p-ch in/out output disable v dd p-ch n-ch open drain data pullup enable pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) +
20 pd78p098a data sheet u10203ej2v0ds figure 2-1. i/o circuits of pins (2/2) type 12-a type 13-d type 16 p-ch xt2 xt1 feedback cut-off pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch input disable analog output voltage p-ch n-ch n-ch in/out medium-voltage input buffer output disable data v dd p-ch rd
21 pd78p098a data sheet u10203ej2v0ds 3. memory size select register (ims) this register specifies via software that part of the internal memory is not used. by using this register, the internal memory (rom) of the pd78p098a can be mapped in the same manner as a mask rom model. ims is set by an 8-bit memory manipulation instruction. the contents of this register are set to cfh at reset. figure 3-1. format of the memory size select register 765432 symbol 10 rom3 selects internal rom capacity fff0h rom0 ims rom1 rom3 rom2 0 ram0 ram1 ram2 address at reset r/w cfh r/w rom2 rom1 rom0 1 32k bytes 000 1 40k bytes 010 1 48k bytes 100 1 56k bytes note 110 1 60k bytes 111 others setting prohibited ram2 selects internal high-speed ram capacity ram1 ram0 1 1024 bytes 10 others setting prohibited note when using the external device expansion function, set the internal prom capacity to 56k bytes or less. table 3-1 shows the value settings of ims to map the memory of the pd78p098a in the same manner as the respective mask rom models. table 3-1. value settings of the memory size select register mask rom model ims value setting pd78094 c8h pd78095 cah pd78096 cch pd78098a cfh
22 pd78p098a data sheet u10203ej2v0ds 4. internal expansion ram size select register (ixs) this register specifies the internal expansion ram capacity via software. by using this register, the internal expansion ram of the pd78p098a can be mapped in the same manner as a mask rom model. ixs is set by an 8-bit memory manipulation instruction. the contents of this register are set to 08h at reset. figure 4-1. format of internal expansion ram size select register table 4-1 shows the value settings of ixs to map the internal expansion ram of the pd78p098a in the same manner as the respective mask rom models. table 4-1. value settings of internal expansion ram size select register mask rom model ixs value setting pd78094 0ch note pd78095 pd78096 pd78098a 08h note even when a program for the pd78p098a in which mov ixs, #0ch is coded is executed on the pd78094, 78095, or 78096, opera- tion is unaffected. selects internal expansion ram capacity ixram3 ixram2 ixram1 ixram0 765432 symbol 10 fff4h ixram0 ixs ixram1 ixram3 ixram2 0 0 0 0 address at reset r/w 08h w 1 no internal expansion ram 100 1 2048 bytes 000 (f000h-f7ffh) others setting prohibited
23 pd78p098a data sheet u10203ej2v0ds 5. prom programming the pd78p098a is provided with a 60k-byte prom as a program memory. when programming this memory, it must be set in the prom programming mode by using the v pp and reset pins. for the handling of the unused pins, refer to (2) prom programming mode in pin configuration (top view) . caution write the program to addreses in the range 0000h through efffh (specify the last address as efffh). a program cannot be written with a prom programmer that cannot specify write addresses. 5.1 operation modes when +5 v or +12.5 v is applied to the v pp pin and low level is applied to the reset pin, the prom programming mode is set. in this mode, the operation modes shown in table 5-1 can be selected by using the ce, oe, and pgm pins. the contents of the prom can be read in the read mode. table 5-1. operation modes in prom programming mode pin reset v pp v dd ce oe pgm d0-d7 operation mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high impedance byte write l h l data input program verify l l h data output program inhibit h h high impedance ll read +5 v +5 v l l h data output output disable l h high impedance standby h high impedance remark : l or h
24 pd78p098a data sheet u10203ej2v0ds (1) read mode this mode is set when both the ce and oe pins are made low. (2) output disable mode when the oe pin is made high, data output goes into a high-impedance state, and the output disable mode is set. if two or more pd78p098as are connected to the data bus, therefore, data can be read from any one of the devices by controlling the oe pin. (3) standby mode the standby mode is set when the ce pin is made high. in this mode, data output goes into a high-impedance state regardless of the status of the oe pin. (4) page data latch mode the page data latch mode is set when the ce and pgm pins are made high and the oe pin is made low at the beginning of the page write mode. in this mode, data of 1 page and 4 bytes is latched to the internal address/data latch circuit. (5) page write mode page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with the ce and oe pins made high after addresses and data of 1 page and 4 bytes have been latched in the page data latch mode. after that, the program can be verified by making both the ce and oe pins low. if the program cannot be written by one program pulse, writing and verifying are repeated x times (x 10). (6) byte write mode byte write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with the ce pin made low and oe pin high. the program is verified by later making the oe pin low. if the program cannot be written by one program pulse, writing and verifying are repeated x times (x 10). (7) program verify mode program verify mode is set when the ce and oe pins are made low and the pgm pin is made high. after writing the program, check in this mode whether the program has been correctly written. (8) program inhibit mode this mode is used to write a program to one of two or more pd78p098as with the oe, v pp , and d0 through d7 pins connected in parallel. to write a program, the page write or byte write mode described above is used. at this time, the program is not written to those devices whose pgm pin is made high.
25 pd78p098a data sheet u10203ej2v0ds 5.2 prom writing procedure figure 5-1. page program mode flowchart v dd = 6.5 v, v pp = 12.5 v start address = g x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x+1 0.1-ms program pulse address = address + 1 verifies 4 bytes address = n ? v dd = 4.5-5.5v, v pp = v dd verifies all bytes x = 10? end of write defective fail pass yes yes no pass no all pass fail g = start address n = end address of program
26 pd78p098a data sheet u10203ej2v0ds figure 5-2. page program mode timing a2-a16 a0, a1 d0-d7 v pp v pp v dd v dd v dd ce v ih v il pgm v ih v il oe v ih v il v dd + 1.5 page data latch page program program verify data input data output
27 pd78p098a data sheet u10203ej2v0ds figure 5-3. byte program mode flowchart v dd = 6.5 v, v pp = 12.5 v start address = g x = 0 x = x + 1 0.1-ms program pulse address = address + 1 verify address = n ? v dd = 4.5 to 5.5 v, v pp = v dd verifies all bytes x = 10? end of write defective fail pass yes yes no pass no all pass fail g = start address n = end address of program
28 pd78p098a data sheet u10203ej2v0ds figure 5-4. byte program mode timing a0-a16 d0-d7 v pp v pp v dd v dd v dd ce v ih v il pgm v ih v il oe v ih v il v dd + 1.5 program program verify data input data output cautions 1. apply v dd before v pp and turn off v dd after v pp . 2. keep v pp from going above +13.5 v, including overshoot. 3. if the device is inserted into or pulled out of the socket while +12.5 v is applied to v pp , the reliability may be adversely affected.
29 pd78p098a data sheet u10203ej2v0ds 5.3 prom read procedure the contents of the prom can be read out to the external data bus (d0 through d7) in the following procedure: (1) fix the reset pin to the low level. supply +5 v to the v pp pin. process the unused pins as described in (2) prom programming mode in pin configuration (top view) . (2) supply +5 v to the v dd and v pp pins. (3) input the address of the data to be read to the a0 through a16 pins. (4) the read mode is set. (5) data is output to the d0 through d7 pins. figure 5-5 shows the timing of steps (2) through (5) above. figure 5-5. prom read timing a0-a16 d0-d7 data output ce (input) oe (input) address input hi-z hi-z
30 pd78p098a data sheet u10203ej2v0ds 6. screening of one-time prom model the one-time prom model ( pd78p098agc-8bt) cannot be completely tested by nec before shipment. it is recommended that screening be implemented to verify the prom after data has been written to the prom and the device has been stored under the following conditions: storage temperature storage time 125 c 24 hours nec provides a writing, marking, screening, and verifying service for one-time proms, called qtop microcontroller. this service for the pd78p098a is in preparation. for details, consult nec.
31 pd78p098a data sheet u10203ej2v0ds 7. electrical specifications absolute maximum ratings (t a = 25 c) output current low output current high input voltage supply voltage i oh v i1 v ?.3 to v dd +0.3 1 pin parameter symbol test conditions rating unit v dd ?.3 to +7.0 v v pp ?.3 to +13.5 v av dd ?.3 to v dd +0.3 v av ref0 ?.3 to v dd +0.3 v av ref1 ?.3 to v dd +0.3 v av ss ?.3 to +0.3 v p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to 47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain ?.3 to +16 v v i3 a9 prom programming mode ?.3 to +13.5 v output voltage v o ?.3 to v dd +0.3 v analog input voltage v an p10 to p17 analog input pins av ss ?.3 to av ref0 +0.3 v 1 pin ?0 ma total for p01 to p06, p30 to p37, p56, p57, ?5 ma p60 to p67, p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, ?5 ma p50 to p55, p70 to p72, p130, p131 peak value 30 ma r.m.s. value 15 ma total for p50 to p55 peak value 100 ma r.m.s. value 70 ma total for p56, p57, p60 to p63 peak value 100 ma r.m.s. value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 r.m.s. value 20 ma total for p01 to p06, peak value 50 ma p30 to p37, p64 to p67, p120 to p127 r.m.s 20 ma t a ?0 to +85 c storage temperature t stg ?5 to +150 c total power dissipation p d 650 mw operating ambient temperature i ol note note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] x duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics.
32 pd78p098a data sheet u10203ej2v0ds x1 x2 pd74hcu04 notes 1. only the oscillator characteristics are shown. see the ac characteristics for instruction execution times. 2. this is the time required for oscillation to stabilize after a reset or stop mode release. cautions 1. when the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . ? do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. ceramic resonator 1.0 1.0 1.0 4 mhz ms mhz ms mhz crystal resonator external clock 6.0 6.0 main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) resonator recomm ende d circuit parameter test conditions min. typ. max. unit oscillatior frequency v dd = oscillation voltage range (f x ) note1 oscillatior stabilization after v dd has reached min. time note2 of oscillation voltage range oscillatior frequency (f x ) note1 oscillatior stabilization v dd = 4.5 to 5.5 v 10 time note2 30 x1 input frequency (f x ) note1 x1 input high-/low-level width (t xh /t xl ) 6.0 ns 500 85 ns 500 72 when f xx = f x 6.29 6.29 6.29 other than above x1 v pp x2 c2 c1 x1 v pp x2 c2 c1
33 pd78p098a data sheet u10203ej2v0ds resonator recommended circuit parameter test conditions min. typ. max. unit oscillation frequency (f xt ) note1 oscillation stabilization time note2 x1 input frequency (f xt ) note1 x1 input high-/low-level width (t xth /t xtl ) 10 v dd = 4.5 to 5.5 v 1.2 2 xt2 xt1 notes 1. only the oscillator characteristics are shown. see the ac characteristics for instruction execution times. 2. this is the time required for oscillation to stabilize after power (v dd ) is turned on. cautions 1. when the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines carrying a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . ? do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. subsystem clock osillator characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) external clock crystal resonator 32.768 35 mhz khz 100 32 32 5 15 s capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance f = 1 mhz unmeasured pins returned to 0 v. 15 pf p01 to p06, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics. c in c io 15 pf f = 1 mhz unmeasured pins returned to 0 input/output capacitance s xt1 v pp xt2 c4 r2 c3
34 pd78p098a data sheet u10203ej2v0ds parameter symbol conditions min. typ. max. unit input voltage high v ih1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0.7 v dd v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0.8 v dd v dd v reset v ih3 p60 to p63, n-ch open drain 0.7 v dd 15 v v ih4 x1, x2 v dd 0.5 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v input voltage low v il1 p10 to p17, p21, p23, p30 to p32, p35 to p37, p40 to p47, 0 0.3 v dd v p50 to p57, p64 to p67, p71, p120 to p127, p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, p33, p34, p70, p72, 0 0.2 v dd v reset v il3 p60 to p63, n-ch open drain 4.5 v v dd 5.5 v 0 0.3 v dd v 2.7 v v dd < 4.5 v 0 0.2 v dd v v il4 x1, x2 0 0.4 v v il5 xt1/p07, xt2 v dd = 4.5 to 5.5 v 0 0.2 v dd v 0 0.1 v dd v output voltage high v oh1 v dd = 4.5 to 5.5 v, i oh = 1 ma v dd 1.0 v i oh = 100 av dd 0.5 v output voltage low v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v i ol = 15 ma p01 to p06, p10 to p17, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2 v dd v open drain, at pulled up (r = 1 k ? ) v ol3 i ol = 400 a 0.5 v dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) remark unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics.
35 pd78p098a data sheet u10203ej2v0ds dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit p00 to p06, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, i lih1 v in = v dd p60 to p67, p70 to p72, 3 a p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 a i lih3 v in = 15v p60 to p63 80 a p00 to p06, p10 to p17, p20 to p27, i lil1 p30 to p37, p40 to p47, p50 to p57, 3 a p60 to p67, p70 to p72, v in = 0 v p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 20 a i lil3 p60 to p63 3 note a output leakage i loh v out = v dd 3 a current high output leakage i lol v out = 0 v 3 a current low vin = 0 v, p01 to p06, p10 to p17, 4.5 v dd 5.5 v 15 40 90 k ? r p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, 2.7 v dd < 4.5 v 20 500 k ? p120 to p127, p130, p131 input leakage current high input leakage current low software pull-up resistor note for p60-p63, a low-level input leak current of 200 a (max.) flows only during the 1.5 clocks (no-wait time) after an instruction has been executed to read out port 6 (p6) or port mode register 6 (pm6). outside the period of 1.5 clocks following execution a read-out instruction, the current is 3 a (max.). remark unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics.
36 pd78p098a data sheet u10203ej2v0ds dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit 5.0 mhz crystal oscillation operating mode v dd = 5.0v 10% note6 515ma (f xx = 2.5 mhz) note2 v dd = 3.0v 10% note7 0.7 2.7 ma 5.0 mhz crystal oscillation operating mode v dd = 5.0v 10% note6 930ma supply current note 1 i dd1 (f xx = 5.0 mhz) note3 v dd = 3.0v 10% note7 1 3.7 ma 6.29 mhz crystal oscillation operating mode v dd = 5.0v 10% note6 4.8 17.4 ma (f xx = 2.1 mhz) note4 6.29 mhz crystal oscillation operating mode v dd = 5.0v 10% note6 8.5 28.5 ma (f xx = 4.19 mhz) note5 notes 1. currents av ref0 , av ref1 , av dd , and the port current (including the current flowing in the internal pull-up resistor) are not included. 2. when bit 0 of clock switchover selection register 1 has been set to 0, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 00h. 3. when bit 0 of clock switchover selection register 1 has been set to 0, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 01h. 4. when bit 0 of clock switchover selection register 1 has been set to 1, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 00h. indicates only the power supply current characteristic. for iebus ratings, refer to the iebus controller characteristics. 5. when bit 0 of clock switchover selection register 1 has been set to 1, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 01h. indicates only the power supply current characteristic. for iebus ratings, refer to the iebus controller characteristics. 6. when in high-speed mode (when the processor clock control register has been set to 00h). 7. when in low-speed mode (when the processor clock control register has been set to 04h). remark f xx : main system clock frequency
37 pd78p098a data sheet u10203ej2v0ds dc characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd2 5.0 mhz crystal oscillation halt mode v dd = 5.0v 10% note 7 1.5 4.5 ma (f xx = 2.5 mhz) note 2 v dd = 3.0v 10% note 8 0.5 1.5 ma 5.0 mhz crystal oscillation halt mode v dd = 5.0v 10% note 7 1.8 5.4 ma (f xx = 5.0 mhz) note 3 v dd = 3.0v 10% note 8 0.7 2.1 ma 6.29 mhz crystal oscillation halt mode v dd = 5.0v 10% note 7 1.5 4.5 ma (f xx = 2.1 mhz) note 4 6.29 mhz crystal oscillation halt mode v dd = 5.0v 10% note 7 1.8 5.4 ma (f xx = 4.19 mhz) note 5 i dd3 32.768 khz crystal oscillation operating v dd = 5.0v 10% 135 270 a mode note 6 v dd = 3.0v 10% 95 190 a i dd4 32.768 khz crystal oscillation halt v dd = 5.0v 10% 25 55 a mode note 6 v dd = 3.0v 10% 5 15 a i dd5 xt1 = 0 v v dd = 5.0v 10% 1 30 a stop mode v dd = 3.0v 10% 0.5 10 a feedback resistor used i dd6 xt1 = 0 v v dd = 5.0v 10% 0.1 30 a stop mode v dd = 3.0v 10% 0.05 10 a feedback resistor not used notes 1. currents av ref0 , av ref1 , av dd , and the port current (including the current flowing in the internal pull-up resistor) are not included. 2. when bit 0 of clock switchover selection register 1 has been set to 0, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 00h. 3. when bit 0 of clock switchover selection register 1 has been set to 0, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 01h. 4. when bit 0 of clock switchover selection register 1 has been set to 1, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 00h. indicates only the power supply current characteristic. for iebus ratings, refer to the iebus controller characteristics. 5. when bit 0 of clock switchover selection register 1 has been set to 1, bit 0 of clock switchover selection register 2 has been set to 0, and the oscillator mode selection register has been set to 01h. indicates only the power supply current characteristic. for iebus ratings, refer to the iebus controller characteristics. 6. when the main system clock is stopped. 7. when in high-speed mode (when the processor clock control register has been set to 00h). 8. when in low-speed mode (when the processor clock control register has been set to 04h). remark f xx : main system clock frequency
38 pd78p098a data sheet u10203ej2v0ds ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. typ. max. unit note3 note3 cycle time t cy operating on main f xx = f x /3 4.0 v v dd 5.5 v 0.95 64 s (minimum instruction system clock f xx = f x /6 2.7 v v dd 5.5 v 1.91 64 s execution timke) (mcs = 0 note 1 )f xx = f x /9 4.0 v v dd 5.5 v 2.86 64 s f xx = f x /2 2.7 v v dd 5.5 v 0.8 64 s operating on main f xx = 2f x /3 4.5 v v dd 5.5 v 0.48 32 s system clock 4.0 v v dd < 4.5 v 0.95 32 s (mcs = 1 note 2 )f xx = f x /3 2.7 v v dd 5.5 v 0.95 32 s f xx = 2f x /9 4.0 v v dd 5.5 v 1.43 32 s f xx = f x 4.5 v v dd 5.5 v 0.4 32 s 2.7 v v dd < 4.5 v 0.8 32 s operating on subsystem clock 114 122 125 s ti00 input t tih00 , 3.5 v v dd 5.5 v 2/f sam +0.1 s high-/low-level width t til00 2.7 v v dd < 3.5 v 2/f sam +0.2 s ti01 input t tih01 , 10 s high-/low-level width t til01 ti1, ti2 input t ti1 4.5 v v dd 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 , 4.5 v v dd 5.5 v 100 ns high-/low-level width t til1 1.8 s interrupt input t inth , intp0 3.5 v v dd 5.5 v 2/f sam +0.1 s high-/low-level width t intl 2.7 v v dd < 3.5 v 2/f sam +0.2 s intp1 to intp6 10 s kr0 to kr7 10 s reset low-level width t rst 10 s notes 1. when oscillation mode selection register is set to 00h. 2. when oscillation mode selection register is set to 01h. 3. f sam can be selected as f xx /2 n , f xx /32, f xx /64, or f xx /128 by bits 0 and 1 (scs0 and scs1) of the sampling clock selection register (n = 0 to 4). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillatior frequency note3 note3
39 pd78p098a data sheet u10203ej2v0ds 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 0, iecl20 = 0, mcs = 0) operation) 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 1, iecl20 = 0, mcs = 0) operation) guaranteed operation range 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 0, iecl20 = 1, mcs = 0) operation) guaranteed operation range 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 1, iecl20 = 1, mcs = 0) operation) guaranteed operation range guaranteed operation range
40 pd78p098a data sheet u10203ej2v0ds 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 0, iecl20 = 0, mcs = 1) operation) 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 1, iecl20 = 0, mcs = 1) operation) guaranteed operation range 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 0, iecl20 = 1, mcs = 1) operation) 60 10 2.0 1.0 0.5 0.4 0 123456 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (main system clock (iecl10 = 1, iecl20 = 1, mcs = 1) operation) guaranteed operation range guaranteed operation range guaranteed operation range
41 pd78p098a data sheet u10203ej2v0ds (2) read/write operations (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy 50 ns address setup time t ads 0.85t cy 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85+2n)t cy 80 ns t add2 (4+2n)t cy 100 ns data input time from rd t rdd1 (2+2n)t cy 100 ns t rdd2 (2.85+2n)t cy 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2+2n)t cy 60 ns t rdl2 (2.85+2n)t cy 60 ns wait input time from rd t rdwt1 0.85t cy 50 ns t rdwt2 2t cy 60 ns wait input time from wr t wrwt 2t cy 60 ns wait low-level width t wtl (1.15+2n)t cy (2+2n)t cy ns write data setup time t wds (2.85+2n)t cy 100 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (2.85+2n)t cy 60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy +20 ns astb delay time from rd in external fetch t rdast 0.85t cy 10 1.15t cy +20 ns address hold time from rd in external fetch t rdadh 0.85t cy 50 1.15t cy +50 ns write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr t wradh 0.85t cy 1.15t cy +40 ns rd delay time from wait t wtrd 1.15t cy +40 3.15t cy +40 ns wr delay time from wait t wtwr 1.15t cy +30 3.15t cy +30 ns remarks 1. mcs: bit 0 of the oscillation mode selection register 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register 3. t cy = t cy /4 4. n indicates the number of waits.
42 pd78p098a data sheet u10203ej2v0ds (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol test conditions min. max. unit astb high-level width t asth t cy 80 ns address setup time t ads t cy 80 ns address hold time t adh 0.4t cy 10 ns data input time from address t add1 (3+2n)t cy 160 ns t add2 (4+2n)t cy 200 ns data input time from rd t rdd1 (1.4+2n)t cy 70 ns t rdd2 (2.4+2n)t cy 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4+2n)t cy 20 ns t rdl2 (2.4+2n)t cy 20 ns wait input time from rd t rdwt1 t cy 100 ns t rdwt2 2t cy 100 ns wait input time from wr t wrwt 2t cy 100 ns wait low-level width t wtl (1+2n)t cy (2+2n)t cy ns write data setup time t wds (2.4+2n)t cy 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (2.4+2n)t cy 20 ns rd delay time from astb t astrd 0.4t cy 30 ns wr delay time from astb t astwr 1.4t cy -30 ns astb delay time from rd in external fetch t rdast t cy 10 t cy +20 ns address hold time from rd in external fetch t rdadh t cy 50 t cy +50 ns write data output time from rd t rdwd 0.4t cy 20 ns write data output time from wr t wrwd 060ns address hold time from wr t wradh t cy t cy +60 ns rd delay time from wait t wtrd 0.6t cy +180 2.6t cy +180 ns wr delay time from wait t wtwr 0.6t cy +120 2.6t cy +120 ns remarks 1. mcs: bit 0 of the oscillation mode selection register 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register 3. t cy = t cy /4 4. n indicates the number of waits.
43 pd78p098a data sheet u10203ej2v0ds (3) serial interface (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2-50 ns t kl1 t kcy1 /2-100 ns si0 setup time (vs. sck0 )t sik1 v dd = 4.5 to 5.5 v 100 ns 150 ns si0 hold time (vs. sck0 )t ksi1 400 ns so0 output delay time from sck0 t kso1 c = 100pf note 300 ns note c is the so0 output line load capacitance. (ii) 3-wire serial i/o mode (sck0 ... external clock input) note c is the so0 output line load capacitance. parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck0 high-/low-level width t kh2 ,v dd = 4.5 to 5.5 v 400 ns t kl2 800 ns si0 setup time (vs. sck0 )t sik2 100 ns si0 hold time (vs. sck0 )t ksi2 400 ns so0 output delay time from sck0 t kso2 c = 100pf note 300 ns sck0 rise, fall time t r2 , when using external device 160 ns t f2 expansion function when not using external 1000 ns device expansion function
44 pd78p098a data sheet u10203ej2v0ds parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level width t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2-50 ns t kl3 t kcy3 /2-100 ns sb0, sb1 setup time (vs. sck0 )t sik3 v dd = 4.5 to 5.5 v 100 ns 300 ns sb0, sb1 hold time (vs. sck0 )t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1k ?, v dd = 4.5 to 5.5 v 0 250 ns sck0 c = 100pf note 0 1000 ns sb0, sb1 from sck0 t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the sb0 and sb1 output line load resistance and load capacitance. (iii) sbi mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 5.5 v 800 ns 3200 ns sck0 high-/low-level width t kh4 ,v dd = 4.5 to 5.5 v 400 ns t kl4 1600 ns sb0, sb1 setup time (vs. sck0 )t sik4 v dd = 4.5 to 5.5 v 100 ns 300 ns sb0, sb1 hold time (vs. sck0 )t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1k ?, v dd = 4.5 to 5.5 v 0 300 ns sck0 c = 100pf note 0 1000 ns sb0, sb1 from sck0 t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , when using external device 160 ns t f4 expansion function when not using external 1000 ns device expansion function note r and c are the sb0 and sb1 output line load resistance and load capacitance. (iv) sbi mode (sck0 ... external clock input)
45 pd78p098a data sheet u10203ej2v0ds (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 v dd = 4.5 to 5.5 v 1600 ns 3200 ns sck0 high-level width t kh5 t kcy5 /2-160 ns sck0 low-level width t kl5 t kcy5 /2-50 ns sb0, sb1 setup time (vs. sck0 )t sik5 v dd = 4.5 to 5.5 v 300 ns 350 ns sb0, sb1 hold time (vs. sck0 )t ksi5 600 ns sb0, sb1 output delay time t kso5 0 300 ns from sck0 r = 1k ?, c = 100pf note note r and c are the sck0, sb0 and sb1 output line load resistance and load capacitance. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 v dd = 4.5 to 5.5 v 1600 ns 3200 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (vs. sck0 )t sik6 100 ns sb0, sb1 hold time (vs. sck0 )t ksi6 t kcy6 /2 ns sb0, sb1 output delay time t kso6 r = 1k ?, c = 100pf note 0 300 ns from sck0 sck0 rise, fall time t r6 , when using external device 160 ns t f6 expansion function when not using external 1000 ns device expansion function note r and c are the sck0, sb0 and sb1 output line load resistance and load capacitance.
46 pd78p098a data sheet u10203ej2v0ds (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2-50 ns t kl7 t kcy7 /2-100 ns si1 setup time (vs. sck1 )t sik7 v dd = 4.5 to 5.5 v 100 ns 150 ns si1 hold time (vs. sck1 )t ksi7 400 ns so1 output delay time from sck1 t kso7 c = 100pf note 300 ns note c is the so1 output line load capacitance. (ii) 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh8 ,v dd = 4.5 to 5.5 v 400 ns t kl8 800 ns si1 setup time (vs. sck1 )t sik8 100 ns si1 hold time (vs. sck1 )t ksi8 400 ns so1 output delay time from sck1 t kso8 c = 100pf note 300 ns sck1 rise, fall time t r8 , when using external device 160 ns t f8 expansion function when not using external 1000 ns device expansion function note c is the so1 output line load capacitance.
47 pd78p098a data sheet u10203ej2v0ds (iii) automatic transmission/reception function 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh9 ,v dd = 4.5 to 5.5 v t kcy9 /2-50 ns t kl9 t kcy9 /2-100 ns si1 setup time (vs. sck1 )t sik9 v dd = 4.5 to 5.5 v 100 ns 150 ns si1 hold time (vs. sck1 )t ksi9 400 ns so1 output delay time from sck1 t kso9 c = 100 pf note v dd = 4.5 to 5.5 v 300 ns stb from sck1 t sbd t kcy9 /2-100 t kcy9 /2+100 ns strobe signal high-level width t sbw t kcy9 -30 t kcy9 +30 ns busy signal setup time t bys 100 ns (vs. busy signal detection timing) busy signal hold time t byh v dd = 4.5 to 5.5 v 100 ns (vs. busy signal detection timing) 150 ns sck1 from busy inactivation t sps 2t kcy9 ns note c is the so1 output line load capacitance. (iv) automatic transmission/reception function 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck1 high-/low-level width t kh10 ,v dd = 4.5 to 5.5 v 400 ns t kl10 800 ns si1 setup time (vs. sck1 )t sik10 100 ns si1 hold time (vs. sck1 )t ksi10 400 ns so1 output delay time from sck1 t kso10 c = 100 pf note 300 ns sck1 rise, fall time t r10 , when using external device 160 ns t f10 expansion function when not using external 1000 ns device expansion function note c is the so1 output line load capacitance.
48 pd78p098a data sheet u10203ej2v0ds (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck2 high-/low-level width t kh11 ,v dd = 4.5 to 5.5 v t kcy11 /2-50 ns t kl11 t kcy11 /2-100 ns si2 setup time (vs. sck2 )t sik11 v dd = 4.5 to 5.5 v 100 ns 150 ns si2 hold time (vs. sck2 )t ksi11 400 ns so2 output delay time from sck2 t kso11 c = 100pf note 300 ns note c is the so2 output line load capacitance. (ii) 3-wire serial i/o mode (sck2 ... external clock input) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy12 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck2 high-/low-level width t kh12 ,v dd = 4.5 to 5.5 v 400 ns t kl12 800 ns si2 setup time (vs. sck2 )t sik12 100 ns si2 hold time (vs. sck2 )t ksi12 400 ns so2 output delay time from sck2 t kso12 c = 100pf note 300 ns sck2 rise, fall time t r12 , when using external device 160 ns t f12 expansion function when not using external 1000 ns device expansion function note c is the so2 output line load capacitance.
49 pd78p098a data sheet u10203ej2v0ds (iii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate v dd = 4.5 to 5.5 v 78125 bps 39063 bps (iv) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy13 v dd = 4.5 to 5.5 v 800 ns 1600 ns asck high-/low-level t kh13 , v dd = 4.5 to 5.5 v 400 ns width t kl13 800 ns transfer rate v dd = 4.5 to 5.5 v 39063 bps 19531 bps sck rise, fall time t r13 , w hen using external device 160 ns t f13 expansion function w hen not using external device 1000 ns expansion function
50 pd78p098a data sheet u10203ej2v0ds ac timing test point (excluding x1, xt1 input) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points x1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd ?0.5 v 0.4 v ti1, ti2 1/f ti t til1 t tih1 ti00, ti01 t til00 , t til01 t tih00 , t tih01
51 pd78p098a data sheet u10203ej2v0ds read/write operations external fetch (no wait): t asth t adh t add1 hi-z t ads a8-a15 ad0-ad7 astb rd t rdh high-order 8-bit address operation code low-order 8-bit address t rdd1 t rdadh t rdast t rdl1 t astrd external fetch (wait insertion): t asth t add1 hi-z t ads t rdl1 a8-a15 ad0-ad7 astb rd wait t rdh high-order 8-bit address operation code low-order 8-bit address t rdd1 t rdwt1 t adh t rdadh t rdast t wtl t astrd t wtrd
52 pd78p098a data sheet u10203ej2v0ds external data access (no wait): external data access (wait insertion): a8-a15 ad0-ad7 rd wr astb t wrl1 t astwr t wrwd t rdwd t wdh t wds t rdl2 t asth t ads t rdd2 t rdh t astrd t add2 high-order 8-bit address hi-z t adh read data write data hi-z hi-z low-order 8-bit address t wradh a8-a15 ad0-ad7 rd wait t rdwt2 t wrwt t wtwr t wtl t wrwd t rdwd t wdh t astrd t asth t ads t adh t rdh wr astb high-order 8-bit address read data write data hi-z hi-z hi-z t add2 t rdd2 t wtl t wtrd t wds t wradh t wrl1 t rdl2 low-order 8-bit address t astwr
53 pd78p098a data sheet u10203ej2v0ds serial transfer timing 3-wire serial i/o mode: t kcym t khm sck0-sck2 si0-si2 so0-so2 t ksom input data output data t rn t fn t ksim t sikm t klm m = 1, 2, 7, 8, 11, 12 n = 2 , 8 , 12 sbi mode (bus release signal transfer): sbi mode (command signal transfer): t sik3.4 t kcy3.4 t kl3.4 t kh3.4 sck0 t sbl t sbh t ksb t sbk t ksi3.4 t kso3.4 sb0, sb1 t r4 t f4 t sik3.4 t kcy3.4 sck0 t ksb t sbk t ksi3.4 t kso3.4 sb0, sb1 t kh3.4 t kl3.4 t r4 t f4
54 pd78p098a data sheet u10203ej2v0ds 2-wire serial i/o mode: automatic transmission/reception function 3-wire serial i/o mode: automatic transmission/reception function 3-wire serial i/o mode (busy processing): note the signal is not actually low here, but is represented in this way to show the timing. t kso5.6 t sik5.6 t kcy5.6 t kl5.6 t kh5.6 sck0 t ksi5.6 sb0, sb1 t r6 t f6 t sbw t sbd t kcy9,10 t kl9,10 t kh9,10 t f10 t ksi9,10 t kso9,10 t sik9,10 t r10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t bys sck1 t sps busy ( active hi g h ) 789 note 10 note 1 t byh 10+n note
55 pd78p098a data sheet u10203ej2v0ds uart mode (external clock input): t kl13 asck t kh13 t kcy13 t r13 t f13
56 pd78p098a data sheet u10203ej2v0ds a/d converter characteristics (t a = ?0 to +85 c, av dd = v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 888bit total error note iead = 00h 1.8 % fsr iead = 01h v dd = 4.5 to 5.5 v 2.2 3.4 % fsr 2.6 3.8 % fsr conversion time t conv 19.1 200 s sampling time t samp 12/f xx s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 av dd v av ref0 -av ss resistance r airef0 414 k ? note excluding quantization error ( 1/2 lsb). shown as a percentage of the full scale value (% fsr). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillatior frequency d/a converter characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error r = 2 m ? note1 1.2 % r = 4 m ? note1 0.8 % r = 10 m ? note1 0.6 % setting time c = 30 pf note 1 av ref = 4.5 to 5.5 v 10 s 15 s ouput resistor r o0 dacs0 = 55h 10 k ? r o1 dacs1 = 55h 10 k ? analog reference av ref1 2.7 v dd v voltage av ref1 current ai ref1 note2 1.5 ma notes 1. r and c are the d/a converter output pin load resistance and load capacitance. 2. value for one d/a converter channel.
57 pd78p098a data sheet u10203ej2v0ds data retention supply voltage data retention v dddr = 2.0 v supply current i dddr subsystem clock stopped, 0.1 10 a feedback resister disconnected release signal setup time t srel 0 s oscillation release by reset 2 17 /f x ms stabilization t wait wait time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol test conditions min. typ. max. unit v dddr 2.0 5.5 v note 2 12 /f xx , or 2 14 /f xx through 2 17 f xx can be selected by bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register. remark f xx : main system clock frequency f x : main system clock oscillatior frequency data retention timing (stop mode release by reset) data retention timing (stop mode release by standby release signal: interrupt signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
58 pd78p098a data sheet u10203ej2v0ds interrupt input timing reset input timing t intl t inth t rsl intp0-intp6 reset parameter symbol conditions min. typ. max. unit iebus controller system fs when using mode 0, 1 note 1 5.91 6.00 6.09 mhz clock frequency 6.20 6.29 6.39 mhz when using mode 2 5.97 6.00 6.03 mhz 6.26 6.29 6.32 mhz driver delay time c = 50 pf note 2 fs = 6.00 mhz 1.6 s (tx output bus line) fs = 6.29 mhz 1.5 s receiver delay time fs = 6.00 mhz 0.75 s (bus line rx input) fs = 6.29 mhz 0.7 s propagation delay fs = 6.00 mhz 0.9 s time on the bus fs = 6.29 mhz 0.85 s iebus controller characteristics (t a = ?0 to +85?c, v dd = 5 v 10%) notes 1. for the values in the second row, the iebus standards are not satisfied. 2. c is the tx output line load capacitance.
59 pd78p098a data sheet u10203ej2v0ds parameter symbol test conditions min. typ. max. unit input voltage high v ih 0.7 v dd v dd v input voltage low v il 0 0.3 v dd v output voltage high v oh1 i oh = 1 ma v dd 1.0 v v oh2 i oh = 100 av dd 0.5 v output voltage low v ol i ol = 1.6 ma 0.4 v input leakage current i li 0 v in v dd 10 +10 a output leakage current i lo 0 v out v dd , oe = v ih 10 +10 a v pp supply voltage v pp v dd 0.6 v dd v dd +0.6 v v dd supply voltage v dd 4.5 5.0 5.5 v v pp supply current i pp v pp = v dd 100 a v dd supply current i dd ce = v il , v in = v ih 50 ma prom programming characteristics dc characteristics (1) prom write mode (t a = 25 5 ? c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (2) prom read mode (t a = 25 5 ? c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol test conditions min. typ. max. unit input voltage high v ih 0.7 v dd v dd v input voltage low v il 0 0.3 v dd v output voltage high v oh i oh = 1 ma v dd 1.0 v output voltage low v ol i ol = 1.6 ma 0.4 v input leakage current i li 0 v in v dd 10 +10 a v pp supply voltage v pp 12.2 12.5 12.8 v v dd supply voltage v dd 6.25 6.5 6.75 v v pp supply current i pp pgm = v il 50 ma v dd supply current i dd 50 ma
60 pd78p098a data sheet u10203ej2v0ds ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol test conditions min. typ. max. unit address setup time (vs. pgm ) t as 2 s oe setup time t oes 2 s ce setup time (vs. pgm ) t ces 2 s input data setup time (vs. pgm ) t ds 2 s address hold time (vs. oe ) t ah 2 s input data hold time (vs. pgm ) t dh 2 s data output float delay time from oe t df 0 250 ns v pp setup time (vs. pgm ) t vps 1.0 ms v dd setup time (vs. pgm ) t vds 1.0 ms program pulse width t pw 0.095 0.105 ms valid data delay time from oe t oe 1 s oe hold time t oeh 2 s parameter symbol test conditions min. typ. max. unit address setup time (vs. oe ) t as 2 s oe setup time t oes 2 s ce setup time (vs. oe ) t ces 2 s input data setup time (vs. oe ) t ds 2 s address hold time (vs. oe ) t ah 2 s t ahl 2 s t ahv 0 s input data hold time (vs. oe ) t dh 2 s data output float delay time from oe t df 0 250 ns v pp setup time (vs. oe ) t vps 1.0 ms v dd setup time (vs. oe ) t vds 1.0 ms program pulse width t pw 0.095 0.105 ms valid data delay time from oe t oe 1 s oe pulse width during data latching t lw 1 s pgm setup time t pgms 2 s ce hold time t ceh 2 s oe hold time t oeh 2 s
61 pd78p098a data sheet u10203ej2v0ds parameter symbol test conditions min. typ. max. unit data output delay time from address t acc ce = oe = v il 800 ns data output delay time from ce t ce oe = v il 800 ns data output delay time from oe t oe ce = v il 200 ns data output float delay time from oe t df ce = v il 060ns data hold time from address t oh ce = oe = v il 0ns (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol test conditions min. typ. max. unit prom programing mode setup time t sma 10 s (3) prom programming mode setting (t a = 25 c, v ss = 0 v)
62 pd78p098a data sheet u10203ej2v0ds prom write mode timing (page program mode) a2 a16 a0, a1 d0 d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input t as t ds t vps t vds t lw t dh t pgms t ceh t pw t oes t oeh t ah t ahl hi-z hi-z hi-z t oe t df t ahv t ces
63 pd78p098a data sheet u10203ej2v0ds prom write mode timing (byte program mode) notes 1. if you want to read within the t acc range, make the oe input delay time from the fall of ce a maxmum of t acc t oe . 2. t df is the time from when either oe or ce first reaches v ih . cautions 1. v dd shonld be applied before v pp, and cut after v pp . 2. v pp shonld not exceed +13.5 v including overshoot. 3. disconnection during application of 12.5v to v pp may have an adverse effect on reliability. prom read mode timing a0 a16 d0 d7 v pp v pp v dd v dd v dd + 1.5 v dd ce pgm v ih v ih v ih v il v il v il ce program program verify t as t ds t dh t vds t ces t pw t oes t vps hi-z hi-z hi-z t oeh t df t ah t oe data output data input a0 a16 d0 d7 ce v ih v il v ih v il ce t ce t oe t oh t df t acc hi-z hi-z effective address note1 note2 note1 data output
64 pd78p098a data sheet u10203ej2v0ds prom programming mode setting timing t sma a0 - a16 0 v dd 0 v dd v dd v pp effective address reset
65 pd78p098a data sheet u10203ej2v0ds 8. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
66 pd78p098a data sheet u10203ej2v0ds 9. recommended soldering conditions these products should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, please contact your nec sales representative. table 9-1. surface mount type soldering conditions pd78p098agc-8bt : 80-pin plastic qfp (14 x 14) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). soldering method soldering conditions recommended condition symbol infrared reflow ir35-107-2 vps vp15-107-2 wave soldering ws60-107-1 partial heating package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: 2 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: 2 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) pin temperature: 300 c max., time: 3 seconds max. (per pin row)
67 pd78p098a data sheet u10203ej2v0ds appendix a. development tools the following development tools are available for development of systems using the pd78p098a. also refer to (6) notes on using development tools . (1) software package sp78k0 software package common to 78k/0 series (2) language processor software ra78k0 common assembler package for 78k/0 series products cc78k0 common c compiler package for 78k/0 series products df78098 device file for pd78098 subseries cc78k0-l common c compiler library source file for 78k/0 series products (3) prom writing tools pg-1500 prom programmer pa-78p054gc programmer adapter connected to pg-1500 pg-1500 controller control program for pg-1500 (4) debugging tools ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c adapter required when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c adapter required when ibm pc/at compatible is used as host machine (isa bus supported) ie-70000-pci-if-a adapter required when pc incorporating pci bus is used as host machine ie-70000-r-sv3 interface adapter and cable required when ews is used as host machine ie-78098-r-em emulation board to emulate the pd78098 subseries ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect the ep-78230gc-r and the target system board on which 80-pin plastic qfp (gc-8bt type) can be mounted id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df78098 device file for pd78098 subseries (5) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
68 pd78p098a data sheet u10203ej2v0ds (6) notes on using development tools the id78k0, and sm78k0 are used in combination with the df78098. the cc78k0 and rx78k0 are used in combination with the ra78k0 and df78098. for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e). the host machines and os suitable for each software are as follows: host machine pc ews [os] pc-9800 series [japanese windows ] hp9000 series 700 [hp-ux ] ibm pc/at compatibles sparcstation [sunos , solaris ] software [japanese/english windows] ra78k0 note cc78k0 note id78k0 sm78k0 rx78k0 note mx78k0 note note dos-based software
69 pd78p098a data sheet u10203ej2v0ds dimensions and recommended mounting pattern of conversion socket figure a-1. dimensions of ev-9200gc-80 (reference) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g0 item millimeters inches a b c d e f g h i j k l m o n p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059
70 pd78p098a data sheet u10203ej2v0ds figure a-2. recommended mounting pattern of ev-9200gc-80 (reference) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p0 item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
71 pd78p098a data sheet u10203ej2v0ds appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd78098 subseries user s manual ieu-1381 pd78094, 78095, 78096, 78098a data sheet u10146e pd78p098a data sheet this manual 78k/0 series user's manual - instruction u12326e 78k/0 series application note - basic(iii) u10182e documents related to development software tools (user s manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k0s, sm78k0 system simulator ver. 2.10 or later operation u14611e windows based sm78k series system simulator ver. 2.10 or later external parts user open interface specification u15006e id78k0-ns integrated debugger ver. 2.00 or later operation u14379e windows based id78k0 integrated debugger windows based reference u11539e guide u11649e rx78k0 real-time os fundamentals u11537e installation u11536e mx78k0 embedded os fundamental u12257e documents related to development hardware tools (user s manuals) document name document no. ie-78001-r-a in-circuit emulator u14142e ie-78098-r-em emulation board eeu-1473 documents related to prom writing (user s manuals) document name document no. pg-1500 prom programmer u11940e pg-1500 controller pc-9800 series (ms-dos)-based eeu-1291 ibm pc series (pc dos)-based u10540e
72 pd78p098a data sheet u10203ej2v0ds other related documents document name document no. semiconductor selection guide - products & package - x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
73 pd78p098a data sheet u10203ej2v0ds [memo]
74 pd78p098a data sheet u10203ej2v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip, iebus and qtop are trademarks of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc.
75 pd78p098a data sheet u10203ej2v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2

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