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1 semiconductor march 1998 hmp8112 ntsc/pal video decoder features ? supports itu-r bt.601 (ccir601) and square pixel ? 3 composite analog inputs with sync tip agc, black clamping and white peak control ? patented decoding scheme with improved 2-line comb filter, y/c separation ? ntsc m, n, and pal (b, d, g, h, i, m, n, cn) operation ? composite or s-video input ? user-selectable color trap and low pass video filters ? user selectable hue, saturation, contrast, sharpness, and brightness controls ? user selectable data transfer output modes - 16-bit 4:2:2 ycbcr - 8-bit 4:2:2 ycbcr ? user selectable clock range from 20mhz - 30mhz ?i 2 c interface ? vmi compatible video data bus applications ? multimedia pcs ? video conferencing ? video editing ? video security systems ? settop boxes (cable, satellite, and telco) ? digital vcrs ? related products - ntsc/pal encoders: hmp8154, hmp8156, hmp8171, hmp8173 - ntsc/pal decoders: hmp8115 description the hmp8112 is a high quality, digital video, color decoder with internal a/d converters. the a/d function includes a 3:1 analog input mux, sync tip agc, black clamping and two 8-bit a/d converters. the high quality a/d converters minimize pixel jitter and crosstalk. the decoder function is compatible with ntsc m, pal b, d, g, h, i, m, n and special combination pal n video stan- dards. both composite (cvbs) and s-video (y/c) input for- mats are supported. a 2 line comb ?lter plus a user selectable chrominance trap ?lter provide high quality y/c separation. various adjustments are available to optimize the image such as brightness, contrast, saturation, hue and sharpness controls. video synchronization is achieved with a 4xf sc chroma burst lock pll for color demodulation and line lock pll for correct pixel alignment. a chrominance sub- sampling 4:2:2 scheme is provided to reduce chrominance bandwidth. the hmp8112 is ideally suited as the analog video interface to vcrs and cameras in any multimedia or video system. the high quality y/c separation, user ?exibility and inte- grated phase locked loops are ideal for use with todays pow- erful compression processors. the hmp8112 operates from a single 5v supply and is ttl/cmos compatible. table of contents page functional block diagrams . . . . . . . . . . . . . . . . . . . . . . . . 2 functional operation introduction. . . . . . . . . . . . . . . . . . . 6 internal register description tables . . . . . . . . . . . . . . . . . 14 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ac and dc electrical speci?cations . . . . . . . . . . . . . . . . . 24 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . 27 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . 39 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ordering information part number temp. range ( o c) package pkg.no. hmp8112cn 0 to 70 80 ld pqfp ? q80.14x20 hmp8112eval2 pci reference design (includes part) hmp8156eval2 frame grabber evaluation board (includes part) ? pqfp is also known as qfp and mqfp caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1998 file number 4221.3 not recommended for new designs see hmp8115
2 functional block diagrams cbcr[7:0] y[7:0] a ctive field d vld user adjust. color trap output sample rate converter std_err locked input mux white peak level digital comparators black level sync level 8-bit adc agc clamp and vid_in0 vid_in1 vid_in2/y clamp_cap agc_cap comp_filter comp_a/d_in + - clamp digital comparator 8-bit adc clamp chroma_in cr_clamp_cap gain_ctrl + - sda scl reset gain control logic and line pll vsync detect microprocessor interface and control hsync vsync logic color demodulation y/c separation input sample rate converter chroma pll hsync detect lock color adjust hmp8112
3 video input functional block diagrams (continued) input mux white peak level digital comparators black level sync level 8-bit adc agc clamp and lin0 lin1 lin2 lclamp_cap lagc_cap l_out l_adin + - clamp digital comparator 8-bit adc clamp cin3 cclamp_cap gain_ctrl + - gain control logic and logic external antialiasing filter external antialiasing filter source select white peak enable (wpe) c cr[7:0] y, cvbs l[7:0] hmp8112
4 video decoder functional block diagrams (continued) y,cvbs c cr[7:0] l[7:0] m u x isl chroma line comb c,cvbs data y data chroma trap enable y data chroma demodulator y data c,cvbs data c data y data uv agc u,v uv saturation adjust saturation adjust sharpness adjust standard select m u x isl hsync detect chroma phase detector chroma pll nco 4fsc clock clk (20mhz - 30mhz) line locked pll loop filter hue adjust agc adjust vsync detect input rate converter sample filter delay trap cbcr data y data clk to 4fsc ratio low pass filter enable hsync vsync standard error locked field sync & contrast adjust brightness, stripper, output rate converter sample line locked nco lp filter chroma pll loop filter horizontal and vertical sharpness adjust u,v to cbcr color converter and color killer space hmp8112
5 schematic i 2 c control interface output interface functional block diagrams (continued) serial shift address pointer control registers .... .... .... .... a0 control address pointer register sda scl 0 1 . . . . 25 data bus r e g i s t e r r e g i s t e r 8 8 cbcr[7:0] y[7:0] y[7:0] cbcr[7:0] d vld oen m u x 8/16 output select active fifo 32 x 16 deep jp1 jumper v cc r10 50 c13 15pf r2 10k 27mhz 64 63 60 58 57 56 55 54 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 65 66 67 71 70 active d vld field hsync vsync wpe reset sd a scl clk clk test l_out l_adin lagc_cap lclamp_cap cclamp_cap gain_cntl dec_t dec_l lin2 lin1 lin0 cin u1 crcb7 crcb6 crcb5 crcb4 crcb3 crcb2 crcb1 crcb0 cr_cb7 cr_cb6 cr_cb5 cr_cb4 cr_cb3 cr_cb2 cr_cb1 cr_cb0 51 50 49 48 47 45 43 42 y10. .71 y10. .71 cr_cb10. .71 cr_cb10. .71 v cc v cc v cc v cc v cc v cc r11 10k r12 10k r13 10k r14 10k r15 10k r16 4k r17 4k v cc reset 27mhz scl 27 34 40 41 38 13 36 5 6 7 19 9 8 77 76 29 28 78 30 sda active d vld field vdrive hdrive low pass filter r7 680 l1 82 m h r8 5.62k c1 15pf c4 1.0 m f c5 1.0 m f c3 1.0 m f r5 75 r4 75 r3 75 c6 1.0 m f r6 75 luma0 luma1 luma2 chroma c2 15pf c9 0.22 m f c8 0.01 m f c7 0.01 m f c12 0.1 m f c11 0.1 m f r9 5k av cc c10 0.1 m f r1 1k r18 10 hmp8112
6 introduction the hmp8112 is an ntsc/pal compatible video decoder with both chroma burst and line locked digital phase locked loops. the hmp8112 contains two 8-bit a/d converters and an i 2 c port for programming internal registers. analog video/mux inputs the luminance channel has three analog video inputs that can be used for composite or the y input of a s-video signal, and one analog input for chrominance. lin2 is used with cin to interface an s-video input. three composite or two com- posite and one s-video inputs can be applied to the hmp8112 at any one time. control of the analog front end is selected by bits 2 and 1 of the video input control register. anti-aliasing filter an external anti-alias ?lter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image. for the lin inputs a single ?lter is connected to l_out and l_adin. for cin the anti-aliasing ?lter should be connected to the cin input. a recommended ?lter is shown below. agc and clamp circuit inputs lin0-2 contain a sync tip agc amplifier. during the sync tip the value of the a/d is driven to code 0 by gaining up the video input signal. the sync tip agc is sampled during the hagc pulse time which is controlled by the hagc pulse start time and end time registers. the lin0-2 inputs apply a dc clamp reference to the back porch of the video. this is con- trolled by the dc-restore pulse start time and end time registers. after a reset , a change of the video standard, or a pll chrominance subcarrier ratio register load, hagc and dc restore are overlapped, until locked is asserted. (the pll has acquired a stable line lock). this is the acquisition mode of the pll where the decoder is trying to lock to a new video source. once the pll is locked, hagc and dc restore are moved out to the default programmed values in the user programming registers. the hagc should be set coincident to the incoming horizontal sync signal. the hagc pulse should be set to a width of 2 m s. once the pll is locked the dc restore signal is moved out to the default programmed values in the user program- ming registers. the dc restore pulse can be pro- grammed with the dc restore start and end time control registers. dc restore should be asserted 6.5 m s after the falling edge of horizontal sync (0 hsync ) and held for a dura- tion of 2 m s. both hagc and dc restore are synchronous to the output sample rate (osr) converter and are clocked in osr (pixel clock) clock periods. the osr clock rate is dependent on the input standard used. see table 1 for the register values used for the different video standards. white peak enable the white peak enable input, (wpe) enables or disables the white peak control. enabled, (logic high) when the digital outputs exceed code 248, the agc will reduce the gain of the video ampli?er to prevent over-ranging the a/d. if dis- abled, the agc operates normally, keeping the horizontal sync tip at code 0 and allowing the a/ds range to go to 255 at the maximum peak input. ntsc/pal decoder the ntsc/pal decoder is designed to convert incoming composite or separated (svhs, y/c) video into its ycbcr component parts. the digital phase locked loops are designed to synchronize to the various ntsc/pal stan- dards. they provide a stable internal 4xf sc (frequency of the color sub-carrier) video clock for color demodulation, and a line locked clock for vertical spatial pixel alignment. the decoder uses the clk to run the a/d converters and the phase locked loops. this asynchronous master clock for the decoder eliminates the need for a unique clock source in a mul- timedia application. clk can run from 20mhz to 30mhz when using the 16-bit synchronous data output mode. the user must program the clk to color sub-carrier ratio to match the clk frequency used (see internal phase locked loops discus- sion). when using the 8-bit burst data output mode the clk should be a 24.5454mhz, 27mhz or 29.5mhz depending on the output video standard chosen. the crystal oscillator must have a 50ppm accuracy and a 60/40% duty cycle symmetry to ensure proper operation. since the video data from the external a/ds are sampled at the clk frequency a sample rate con- verter is employed to convert the data from the clk rate to the agnd 680 w 82 m h 15pf 15pf 5.62k w l_out (pin 9) l_adin (pin 8) cin (pin 19) 75 w 1.0 m f chroma in figure 1. recommended anti-aliasing filter low pass filter table 1. hagc and dc restore values video output standard hagc start/end values dc restore start/end values hsync start/end values square pixel ntsc 640x480 02f8/0008 h 0028/0040 h 0020/0050 h ccir601 ntsc 720x480 033f/0000 h 0037/0052 h 033b/0060 h ccir601 pal 720x512 033f/0000 h 0037/0052 h 033b/0060 h square pixel pal 768x512 03a0/0018 h 0040/0054 h 0020/0070 h hmp8112
7 internal decoding frequency of 4xf sc . the input sample rate converter will interpolate between existing clk samples to create the chroma locked (4xf sc ) samples needed for the color decoder. an interpolation is done to create the 4xf sc pixel and a correction factor is then applied.. the decoder can be used with the following video sources: analog composite - ntsc m, - pal b, d, g, h, i, n and special combination pal n analog s - vhs (y/c) - ntsc m, pal b, d, g, h, i, n and special combination pal n color separation, and demodulation to separate the chrominance modulated color information from the baseband luminance signal, a 2 line comb ?lter is employed. in ntsc signals the color information changes phase 180 o from one line to the next. this interleaves the chrominance information at half line intervals throughout the ntsc video spectrum. therefore, ntsc has 227.5 cycles of chrominance per ntsc line. the half of a cycle causes the next reference burst to be 180 o out of phase with the previ- ous lines burst. the two line comb ef?ciently removes the chrominance information from the baseband luminance sig- nal. when decoding ntsc, the decoder maintains full lumi- nance bandwidth horizontally throughout the chrominance carrier frequency range. unlike most 2 line comb ?lter sepa- ration techniques, vertical bandwidth is maintained by means of a proprietary transform technique. for pal systems there are 283.75 cycles of chrominance per line. chrominance information is spaced at quarter line intervals with a reference phase of 135 o . the reference figure 2a. pll acquisition mode figure 2b. pll locked mode video input hagc dc restore overlapped control t pw = 2.0 m s 0 hsync video input hagc dc restore start time end time start time end time 6.5 m s 0 hsync time incoming video samples time resampled video 4xf sc figure 3. sample rate conversion frequency amplitude f h /2 f h /2 f h y i, q y frequency amplitude y y i, q figure 4. composite ntsc interleave scheme hmp8112
8 phase alternates from line to line by 90 o . to fully separate the pal chrominance and luminance signals the user select- able ?lters should be enabled. the chroma notch ?lter built into the luminance channel should be enabled for pal sys- tems to reduce cross luminance effects. the low pass ?lter in the chrominance processing chain helps to reduce cross color products. the demodulator in the decoder decodes the color compo- nents into u and v. the u and v components are converted to cb and cr components after the decoding process. ycbcr has a usable data range as shown in figure 4. the data range for y is limited to a minimum of 16. the decoder is compatible with all ntsc and pal video for- mats available throughout the world. table 2 shows the com- patible video standards. horizontal sync detection horizontal sync is detected in the output sample rate con- verter (osr). the osr spatially aligns the pixels in the verti- cal direction by using the horizontal sync information embedded in the digital video data stream. the hsync sync pulse out of the decoder is a video synchronous output pin. this signal follows the horizontal sync of an input video source. if there is no source the hsync pin will continue to run at video rates due to the line locked pll free-running. hsync can be moved throughout the video line using the hsync start and end time registers. this 10-bit register allows the hsync to be moved in osr clock increments (12.27mhz, 13.5mhz or 14.75mhz). vertical sync and field detection the vertical sync and ?eld detect circuit of the decoder uses a low time counter to detect the vertical sync sequence in the video data stream. the low time counter accumulates the low time encounted after the horizontal sync edge or at the start of each line. when the low time count exceeds the vertical sync detect threshold, vsync is asserted immediately. vsync will remain asserted for a minimum of 1 line. the field ?ag is updated at the same time as the vsync line. the field pin is a 0 for odd ?elds and a 1 for even ?elds. in the case of lost vertical sync or excessive noise that would prevent the detection of vertical sync, the field ?ag will continue to toggle. lost vertical sync is declared if after 337 lines a vertical sync period was not detected for 3 succes- sive lines. when this occurs the phase locked loops are ini- tialized to the acquisition state. the vsync pulse out of the decoder follows the vertical sync detection and is typically 6.5 lines long. the vsync will run at the ?eld rate of the selected video standard selected. for ntsc the ?eld rate is 60hz and for pal the ?eld rate is 50hz. this signal will continue to run even in the event of no incoming video signal. internal phase locked loops the hmp8112 has two independent digital phase locked loops on chip. a chroma phase-locked loop is implemented to maintain chroma lock for demodulation of the color chan- nel, and a line locked phase lock loop is implemented to maintain vertical spatial alignment. the phase locked loops are designed to maintain lock even in the event of vcr headswitches and multipath noise. the hmp8112 can use a main crystal (clk) of 20mhz to 30mhz. the crystal is used as a reference frequency for the internal phase locked loops. the ratio of the crystal fre- quency to the video standard is programmed into an internal register for the plls to correctly decode video. the hmp8112 decoder contains 2 sample rate converters and 2 phase locked loops that lock to the incoming video. the input sample rate converter synchronizes the digitized video from the clk rate to a 4xf sc rate. the chrominance is sepa- rated from the luminance and then demodulated. the chroma phase locked loop uses the clk source as the pll reference frequency. to initialize the chroma pll, the clk to 4xf sc ratio must be loaded. for example, if the clk was 27mhz and the video signal is ntsc (4 x 3.579545mhz = 14.318mhz) then the ratio loaded is 0.5302895 in 16-bit precision. frequency amplitude f h /4 f h y i, q y frequency amplitude y y f h /4 i, q i, q i, q figure 5. composite pal interleave scheme y data range cb data range cr data range 16 128 248 255 0 16 128 240 255 0 16 128 240 255 212 44 212 44 black white 100% blue 100% blue 75% yellow 100% yellow 75% red 100% red 75% cyan 100% cyan 75% figure 6. ycbcr data ranges hmp8112
9 (4 x f sc )/clk = chroma pll value (4 x 3.579545mhz) / 27mhz = 0.5302895 this value must be loaded to correctly separate and decode the video signal. a default chroma pll value is used after a system reset is applied. the default assumes a clk of 27mhz and ntsc as the video standard. the default value is 0.5302895. an ideal 4xf sc line should have 910 pixels for ntsc and 1135 for pal. the output sample rate converter is locked to the horizontal line frequency and is used to spatially align pixels in a ?eld. the locked ?ag signals when the phase locked loop is within a 4 pixel range of the horizontal sync edge. when line errors exceed that range the locked ?ag is cleared. in cases where vcrs are used in pause, fast forward or fast reverse, lines are typically dropped or added by the vcr. in a worst case scenario a vcr line tolerance will vary by 8%. the standard detect logic checks the line count against the given standard to determine an error. vcrs in trick mode cannot cause a standard error. with an ntsc standard vcr the number of lines in a ?eld should not exceed 285. greater than 285 lines in a ?eld is interpreted as a pal video source. an ideal ntsc source should have 262.5 lines per ?eld and a pal source should have 312.5 lines per ?eld. the hmp8112 can detect a standard error that signals when the video received does not match the standard that was programmed into the video input control register. this table 2. compatible video input standards standard color subcarrier f sc number of fields per second number of vertical lines line frequency nominal bandwidth black setup to blank ntsc m 3.579545mhz 60hz 525 15,734 ( 0.0003%) 4.2mhz 7.5 ire pal b, d, g, h, i 4.43361875mhz 50hz 625 15,625 ( 0.02%) 5.0mhz 0 ire pal m 3.579545mhz 60hz 525 15,750 ( 0.0003%) 4.2mhz 7.5 ire pal n 4.43361875mhz 50hz 625 15,625 ( 0.15%) 4.2mhz 7.5 ire special combination pal n 3.58205625mhz 50hz 625 15,750 ( 0.15%) 4.2mhz 7.5 ire o v video input low time vsync field vsync detect threshold even field counter 6.5 lines figure 7. vsync timing and the even to odd transition o v video input low time vsync field vsync detect threshold odd field counter 6.5 lines figure 8. vsync timing and the odd to even transition hmp8112
10 ?ag, when asserted, tells the user that the video standard that was expected was not found and a different standard should be selected in the video input control register. the error ?ag is cleared after a reset or after the chroma pll clock ratio register has been loaded via the i 2 c bus. after the ?ag is cleared the standard error logic veri?es the video standard. the error ?ag is set after 2 vertical sync periods have passed and the line count did not match the expected line count. video adjustments the hmp8112 allows the user to vary such video parame- ters as contrast, brightness, sharpness, hue and color sat- uration. these adjustments can be made via the i 2 c interface. contrast, brightness and sharpness are luminance controls. the full dynamic range of the luminance channel can be used by selecting the ire setup cancellation mode. this mode will remove the ire setup and blanking level off- set to take advantage of the full dynamic range of the lumi- nance processing path. the sharpening ?lters allow the enhancement of low, mid and high frequency components of the luminance signal to compensate for low amplitude video. vertical sharpness is also controlled via the i 2 c interface. hue and color saturation controls enhance the cbcr com- ponents of the incoming video, all under user control. luminance adjustments the luminance data can be adjusted in the hmp8112. the user can adjust brightness and contrast of the y or lumi- nance data. the user can also set the ire or setup subtrac- tion value to eliminate the black pedestal offset from ntsc signals. the contrast adjustment range can exceed a value of one so as to take full advantage of the 8-bit dynamic range for y. the user control settings executes the equation y out = (y - ire setup + brightness) x contrast brightness the user can control the brightness of the incoming video by programming the brightness register. the brightness adjust- ment will offset the y component. the brightness register is an 8-bit register where the bottom 7 bits are brightness con- trol and the top bit is the ire setup. the ire setup for ntsc is 70 and the setup for pal is 63. when the ire bit is set (1) then the value of 70 is subtracted from the y data, and if the ire bit is cleared (0) then the val- ues of 63 is subtracted. the brightness control bits br[6-0] will brighten the picture as the value is increased. br = -64 is the darkest and br = +63 is the brightest. the default value of the register after a reset is 0 (80 h ). contrast the contrast adjustment will allow the user to increase and decrease the gain of the y data. the contrast factor is an 8-bit number (as shown below) that ranges from 0 to 1.999. x.xxxxxxx the default value after a reset is 1.47 (bd h ). hue or tint adjust the hue adjustment is applied to the u and the v color differ- ence signal. the hue adjusts the phase of the given uv data. the hue can be adjusted by 30 o in 1/4 o increments. this is achieved by changing the burst phase locked reference point. figure 10 shows the block diagram for the color adjust- ment section. this default value for this register is 0 (00 h ). horizontal/vertical sharpness the frequency characteristics of the video waveform can be altered to enhance the sharpness of the picture. the horizontal sharpness register acts a s a 4 band equalizer where the ampli- tude of specific frequency ranges can be enhanced or dimin- ished. the sharpness control register allows the low (lf), mid (mf) and high frequency (hf) bands of the luminance sig- nal to be enhanced. vertical sharpness can be adjusted to 1 or a factor of 0. the reset def ault is a factor of 1.0 table 3. user controlled settings user video settings brightness contrast hue or tint horizontal sharpness vertical sharpness color saturation ire black setup + + - x brightness contrast y data from decoder y 8 figure 9. luminance control settings path (0 to 1.999) (ntsc = 70, pal = 63) (-64 to +63) demodulated uv data uv data video data hue offset hue adjust + to input sample rate converter loop chroma phase locked color decoder chroma agc and user settings figure 10. hue adjust block diagram hmp8112
11 the 2-bit values allow 4 choices of scaling factors. the sharpness control helps to compensate for losses in the scaling interpolators that can reduce the amplitude of high frequency components. the color killer (agc hysteresis and loop limits) the color killer will disable the color difference path and set the u and v components to zero. the automatic color killer circuitry uses the agc threshold to determine the maximum and minimum gain factor limits. the loop ?lter determines how much the agc gain factor can be changed within one line. the maximum gain factor (max = 8) and the minimum gain factor (min = 0.5) will limit the range of the agc. when the gain factor exceeds the maximum gain factor of 8, the gain factor is limited to 8. once the signal has an amplitude of 1/16th, the nominal video the color killer is enabled and the chroma phase locked loop holds its last phase refer- ence. while the color killer is enabled, the u and v compo- nents are forced to zero. once the input video signal reaches 1/7th the optimum amplitude the color killer is disabled and the color is returned. the dynamic range of the agc allows it to compensate for video that is 1/8 to 2 times the speci?ed nominal of 1v p-p . saturation the color saturation component is controlled via the color saturation registers. the color saturation is applied to the uv components after the agc function. the saturation value is multiplied by the uv data to increase the color intensity. the data range is from 0 to 1.96875 where 1.96875 is the brightest intensity. this is an 8-bit number in the form: x.xxx xxxx the default value after a reset is 1.2074 (9d h ). i 2 c control interface the hmp8112 utilizes an i 2 c control bus interface to pro- gram the internal con?guration registers. this standard mode (up to 100 kbps) interface consists of the bidirec- tional serial data line (sda) and the serial clock line (scl). the implementation on the hmp8112 is a simple slave interface that will not respond to general calls and can- not initiate a transfer. when the device is not active, the sda and scl control pins should be pulled high through external 4k w pullup resistors. the i 2 c clock/data timing is shown below in figure 13. the hmp8112 contains 29 internal registers used to program and configure the decoder. the i 2 c control port contains a pointer register that auto-increments through the entire register space and can be written. the autoincrement pointer will wrap after the last register has been accessed (product id register) and should be set to the desired starting address each time an access is started. for a write transfer, the i 2 c device base address is the first part of a serial transfer. then the internal register pointer is loaded. then a series of registers can be written. if multiple registers are written, the pointer register will autoincrement up through the register address space. a stop cycle is used to end the transfer after the desired number of registers are programmed. for a read transfer, the i 2 c device address is the ?rst part of the serial transfer. then the internal register pointer is loaded. at this point another start cycle is initiated to access the individual registers. figure 14 shows the programming ?ow for read transfer of the internal registers. multiple regis- ters can be read and the pointer register will autoincrement up through the pointer register address space. on the last data read, an acknowledge should not be issued. a stop cycle is used to end the transfer after the desired number of registers are read. product id register the hmp8112 contains a product id register that can be used to identify the presence of a board during a plug n play detection software algorithm. the product id code is 12 h and the register is the last register in the hmp8112 (1b h ). output data port modes the hmp8112 can output data in 2 formats, an 8-bit burst mode and a 16-bit synchronous pixel transfer mode. in 16-bit synchronous pixel transfer mode pixel data is output at the table 4. sharpness gain factor selects xf1 xf0 gain factor 0 0 scaled by 1.0 0 1 scaled by 2.0 1 0 scaled by 4.0 1 1 scaled by 0 ? 4096 factor gain min i 2 c color killer line count uv data agc enable figure 11. loop filter block diagram (hysteresis) factor gain max agc gain factor +5v hmp8112 video decoder +5v sda scl +5v 40 41 4k w 4k w figure 12. pullup resistor configuration hmp8112
12 clk frequency and table 5 shows the number of data points per video line to expect for a given standard. data is output as 4:2:2 subsampled data in a y-cb/y-cr 16-bit sequence. the data valid ( d vld) flag is asserted when video data is present on the 16-bit output port of the hmp8112 (y[7:0], cbcr[7:0]). the active flag is asserted when the active video portion of the horizontal scan line is present on the data output port. see figure 15 for synchronous pixel transfer mode timing. d vld is asserted every time the output sample rate converter has a valid output. when d vld and active are used together the visual portion of the image can be captured. when d vld is used alone all valid data during the horizontal, vertical and ref- erence burst timing are available. active is asserted from lines 22 through 262.5 and lines 285.5 through 525 for ntsc (and pal m). active is asserted from lines 23.5 through 310 and lines 336 through 623.5 for pal (b, d, g, h, i, n, comb n). the clk can be run on a 20mhz - 30mhz clock source. data will be output (on average) at the output data rate shown in table 5 for a given standard. data is clocked out synchronous to clk and will come in bursts. to smooth out the data rate to a regular rate a clk of 2x the average output data rate can be used. in the 16-bit pixel transfer, data is sequenced on the cbcr[7:0] data bus, starting with cb and then cr. for burst mode output format the y[7:0] output bus is used to transfer all ycbcr data in 8-bit format. the data is also 4:2:2 subsampled but will only contain the active video por- tion of the line. the hmp8112 uses an internal 32 deep ?fo to handle latencies between the output sample rate and the clk frequency. in this mode, the data is clocked out at the clk rate and only clock frequencies of 24.5454mhz, 27mhz and 29.5mhz can be used. in 8-bit data mode, the data is sequenced on the y[7:0] bus in cb, y, cr, y format. active is asserted as soon as the mode is selected. d vld when asserted indicates a valid active pixel is available. pixels dur- ing the horizontal and vertical blanking are not available. only the active portions of the video line are output. table 5. output mode standards standard output data rate active pixels/ line total pixels/ line total lines/ field ntsc square pixel 12.27mhz 640 780 262.5 ntsc ccir 601 13.5mhz 720 858 262.5 pal b, d, g, h, i, n, comb n, ccir601 13.5mhz 720 864 312.5 pal m ccir 601 13.5mhz 720 858 262.5 pal b, d, g, h, i, n square pixel 14.74mhz 768 944 312.5 pal m square pixel 14.74mhz 640 780 312.5 sda scl start condition s 1-7 address 8 r/w 9 ack 1-7 data 89 ack stop condition p figure 13. i 2 c serial timing flow s = start cycle p = stop cycle a = acknowledge from master from hmp8112 0x88 data write data data 0x88 data read register pointed to by subaddr register pointed to by subaddr na = no acknowledge 0x89 1000 100 (r/w) 1000 100 (r/w) figure 14. register write programming flow s chip addr a sub addr a data data a a p na a a chip addr s a sub addr a chip addr s p hmp8112
13 reset the reset pin is used to return the decoder to an initializa- tion state. this pin should be used after a power-up to set the part into a known state. the internal registers are returned to their reset state and the serial i 2 c port is returned to inactive state. the reset pin is an active low signal and should be asserted for minimum of 1 clk cycle. after a reset or a software reset has occurred all output pins are three-stated. the following pins must be pulled high to ensure proper operation: hsync vsync d vld active field a 10k or smaller pullup resistor to v cc is recommended. / clk y n y 0 y 1 y 2 t dly d vld y[7-0] active t dvld cr n cb 0 cr 0 cb 1 cbcr[7-0] note 1 note 2 notes: 1. y0 is the first active luminance pixel of a line. cb0 and cr0 are first active chrominance pixels in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. 2. active is asserted for lines 22-262.5 and 285.5-525. d vld is asserted for every valid pixel during both active and blanking regions. d vld is asserted during vertical and horizontal sync. figure 15a. output timing 16-bit mode lines 1-21 (lines 1-23.5) (lines 23.5-310) (lines 311-335) (lines 336-623.5) lines 263.5-284 ntsc m, n pal m (pal b, d, g, h, i, n comb n) (pal b, d, g, h, i, n comb n) ntsc m, n pal m figure 15b. active video regions in 16-bit mode <- pixel 0 lines 285-525 <- pixel 0 lines 22-263.5 pixel 1 pixel 2 pixel 3 pixel n pixel n-1 pixel n-2 pixel n-3 clk d vld y t dly y[7-0] active t dvld cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 figure 16. output timing 8-bit mode hmp8112
14 table 6. video input control destination address = 00 h bit number function description reset state 7 - 6 video input standard these bits select the video input standard. 00 = pal b, g, h, i, n; 4.43mhz subcarrier; 50fps; 625 lines/frame; 01 = pal m; 3.58mhz subcarrier; 60fps; 525 lines/frame; 10 = special pal n; 3.58mhz subcarrier; 50fps; 625 lines/frame; 11 = ntsc m; 3.58mhz subcarrier; 60fps; 525 lines/frame (default); 11 b 5 color trap filter disable this bit enables the color subcarrier trap filter. the filter removes the color subcarrier infor- mation from the luminance channel. the filter should be enabled for pal standard systems. 0 = enabled 1 = disabled (default) 1 b 4 chrominance low pass filter disable this bit enables the chrominance low pass filter. this filter band limits the chrominance channel to remove luminance artifacts. this filter should be enabled for pal standard systems. 0 = enabled 1 = disabled (default) 1 b 3 automatic color gain control this bit enables the color agc function. when this bit is set the color agc will automati- cally adjust the chrominance channel gain, to drive the color reference burst to a nominal 20 ires. when this bit is cleared the color agc gain factor is set to 1.0 and the color saturation must be adjusted to obtain nominal crcb values. 0 = disabled 1 = enabled (default) 1 b 2 - 1 a/d converter multiplexor selects these bits control the a/d input select multiplexers and whether s-video is being input as follows: muxsel1,0 = 0, 0 = select composite video input #0, set decoder for composite 1, 0 = select composite video input #1, set decoder for composite 0, 1 = select composite video input #2, set decoder for composite 1, 1 = select s-video y and c inputs 00 b 0 not used write ignored, read 0s x b table 7. luminance brightness control destination address = 01 h bit number function description reset state 7 ire setup cancellation control this bit enables the black setup cancelation circuit for ntsc sources. when this bit is set a value of 73 is used to strip the sync information from the video signal. when this bit is cleared a value of 64 is used to strip the sync information. 0 = subtract 64 from the luminance signal 1 = subtract 73 from the luminance signal 1 b 6 - 0 luminance brightness control these bits control the brightness adjustment to the luminance channel. the brightness adjustment value is a number that ranges from +63 to -64. this register is in the twos complement format, where bit 6 is the sign bit. 000 0000 b hmp8112
15 table 8. luminance contrast adjust register destination address = 02 h bit number function description reset state 7 - 0 luminance contrast adjust factor this register sets the contrast adjust factor. this value is multiplied by the luminance data and allows the data to be scaled from 0 to a factor of +1.96875. this 8-bit number is a fractional number as shown below: 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 the contrast factor is applied after the brightness. 1011 1101 b table 9. hue adjust register destination address = 03 h bit number function description reset state 7 - 0 hue phase adjust this register sets the hue phase offset adjustment. this 8-bit number is applied as a phase offset to the cbcr data coming out of the demodulator. this 8-bit number is a in the range of +127 to -128. the hue adjust has as range of 30 o with each count in this register allowing a 0.25 o phase adjustment. this register is in twos complement format, where bit 7 is the sign bit. 0000 0000 b table 10. luminance sharpness control register destination address = 04 h bit number function description reset state 7 - 6 high frequency enhancement factor these bits adjust the amplitude of high frequency components in the luminance video signal. the attenuation or multiplication of the high frequency components is adjusted as shown below: 00 = multiply high frequency components by 1.0 01 = multiply high frequency components by 2.0 10 = multiply high frequency components by 4.0 11 = zero out high frequency components. 00 b 5 - 4 middle frequency enhancement factor these bits adjust the amplitude of middle frequency components in the luminance video signal. the attenuation or multiplication of the middle frequency components is adjusted as shown below: 00 = multiply middle frequency components by 1.0 01 = multiply middle frequency components by 2.0 10 = multiply middle frequency components by 4.0 11 = zero out middle frequency components. 00 b 3 - 2 low frequency enhancement factor these bits adjust the amplitude of low frequency components in the luminance video sig- nal. the attenuation or multiplication of the low frequency components is adjusted as shown below: 00 = multiply low frequency components by 1.0 01 = multiply low frequency components by 2.0 10 = multiply low frequency components by 4.0 11 = zero out low frequency components. 00 b 1 - 0 vertical high frequency enhancement factor these bits adjust the amplitude of vertical high frequency components in the luminance video signal. the attenuation or multiplication of the vertical high frequency components is adjusted as shown below: 00 = multiply vertical high frequency components by 1.0 01 = reserved. 10 = reserved. 11 = zero out vertical high frequency components. 00 b hmp8112
16 table 11. color saturation adjust factor destination address = 05 h bit number function description reset state 7 - 0 color saturation adjust factor this register sets the color saturation adjust factor. this value is multiplied by the chromi- nance (cbcr) data and allows the data to be scaled from 0 to a factor of +1.96875. this 8-bit number is a fractional number as shown below: 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 the contrast factor is applied after the brightness. 1001 1101 b table 12. phase locked loop chrominance subcarrier to bus clock frequency ratio destination address = 06 h bit number function description reset state 7 - 0 chroma pll ratio these bits are used to program the ratio of the incoming video chrominance color sub- carrier frequency to the bus clock used. this number serves as the reference frequency of the chrominance pll and must be very accurate. this is the lower byte of the ratio and encompasses the following range: 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 the default value is for a clk frequency of 27mhz and a color subcarrier of 3.579545 mhz. 1100 0001 b table 13. phase locked loop chrominance subcarrier to bus clock frequency ratio destination address = 07 h bit number function description reset state 15 - 8 chroma pll ratio these bits are used to program the ratio of the incoming video chrominance color sub- carrier frequency to the bus clock used. this number serves as the reference frequency of the chrominance pll and must be very accurate. this is the upper byte of the ratio and encompasses the following range: 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 1000 0111 b table 14. horizontal agc start time register destination address = 08 h bit number function description reset state 7 - 0 horizontal agc pulse programmable start time this register provides a programmable delay for the hagc pulse that control the sync tip agc in the a/d converters. the start time of the hagc pulse is set from the detection of horizontal sync in the video data. hagc is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the lower byte of the 10-bit word. 0011 1111 b table 15. horizontal agc start time register destination address = 09 h bit number function description reset state 15 - 10 not used write ignored, read 0s. xxxx xx hmp8112
17 9 - 8 horizontal agc pulse programmable start time this register provides a programmable delay for the hagc pulse that control the sync tip agc in the a/d converters. the start time of the hagc pulse is set from the detection of horizontal sync in the video data. hagc is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 11 b table 16. horizontal agc end time register destination address = 0a h bit number function description reset state 7 - 0 horizontal agc pulse programmable end time this register provides a programmable delay for the hagc pulse that control the sync tip agc in the a/d converters. the end time of the hagc pulse is set from the detection of horizontal sync in the video data. hagc is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the lower byte of the 10-bit word. 0000 0000 b table 17. horizontal agc end time register destination address = 0b h bit number function description reset state 15 - 10 not used write ignored, read 0s xxxx xx 9 - 8 horizontal agc pulse programmable end time this register provides a programmable delay for the hagc pulse that control the sync tip agc in the a/d converters. the end time of the hagc pulse is set from the detection of horizontal sync in the video data. hagc is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 00 b table 18. horizontal sync start time register destination address = 0c h bit number function description reset state 7 - 0 horizontal drive programmable start time this register provides a programmable delay for the external hdrive signal. the start time of the hdrive pulse is set from the detection of horizontal sync in the video data. hdrive is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the lower byte of the 10-bit word. 0011 1011 b table 19. horizontal sync start time register destination address = 0d h bit number function description reset state 15 - 10 not used write ignored, read 0s xxxx xx 9 - 8 horizontal drive programmable start time this register provides a programmable delay for the external hdrive signal. the start time of the hdrive pulse is set from the detection of horizontal sync in the video data. hdrive is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 11 b table 15. horizontal agc start time register (continued) destination address = 09 h bit number function description reset state hmp8112
18 table 20. horizontal sync end time register destination address = 0e h bit number function description reset state 7 - 0 horizontal drive programmable end time this register provides a programmable delay for the external hdrive signal. the end time of the hdrive pulse is set from the detection of horizontal sync in the video data. hdrive is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the lower byte of the 10-bit word. 0010 0000 b table 21. horizontal sync end time register destination address = 0f h bit number function description reset state 15 - 10 not used write ignored, read 0s xxxx xx 9 - 8 horizontal drive programmable end time this register provides a programmable delay for the external hdrive signal. the end time of the hdrive pulse is set from the detection of horizontal sync in the video data. hdrive is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 00 b table 22. phase locked loop adjust register destination address = 10 h bit number function description reset state 7 - 0 phase locked loop filter adjust test register the phase locked loop time constants can be changed for testing purposes. it is rec- ommended that the default value of (20 h ) always be used. the reset state is 00 h . 0000 0000 b table 23. phase locked loop sync detect window register destination address = 11 h bit number function description reset state 7 - 0 phase locked loop horizontal sync detect window these bits control the pll horizontal sync detect window. this window sets the length of time that the line lock pll will allow the detection of the hsync. hsync outside of this window are declared missing and will cause the missing sync logic to start counting missing syncs. for ntsc this value should be dd h and for pal, ff h . 1101 1101 b table 24. dc restore start time register destination address = 12 h bit number function description reset state 7 - 0 dc restore programmable start time this register provides a programmable delay for the internal dc res signal. the start time of the dc res pulse is set from the detection of horizontal sync in the video data. dc res is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this signal is used to run the gate b pin of the a/d con- verter. this is the lower byte of the 10-bit word. 0011 0111 b hmp8112
19 table 25. dc restore start time register destination address = 13 h bit number function description reset state 15 - 10 not used xxxx xx 9 - 8 dc restore programmable start time this register provides a programmable delay for the internal dc res signal. the start time of the dc res pulse is set from the detection of horizontal sync in the video data. dc res is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 00 b table 26. dc restore end time register destination address = 14 h bit number function description reset state 7 - 0 dc restore programmable end time this register provides a programmable delay for the internal dc res signal. the end time of the dc res pulse is set from the detection of horizontal sync in the video data. dc res is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this signal is used to run the gate b pin of the a/d con- verter. this is the lower byte of the 10-bit word. 0101 0010 b table 27. dc restore end time register destination address = 15 h bit number function description reset state 15 - 10 not used xxxx xx 9 - 8 dc restore programmable end time this register provides a programmable delay for the external dc res signal. the end time of the dc res pulse is set from the detection of horizontal sync in the video data. dc res is programmable in clk increments and has a fixed 1 clock delay following the falling edge of horizontal sync. this is the upper byte of the 10-bit word. 00 b table 28. output format control register destination address = 16 h bit number function description reset state 7 square pixel/itu-r bt601 select when 1, square pixel output is selected, when 0 itu-r bt601 output rate is selected. 0 b 6, 5, 4 output field control fld_cont(2-0) these bits control the field capture rate of the hmp8112. the user can select every 4th field, every other field or every field of video to be output to the data port. 000 = no capture enabled 001 = capture every 4th field 010 = capture every 2nd field 011 = capture every 2nd odd field 100 = capture every 2nd even field 101 = capture every odd field 110 = capture every even field 111 = capture all fields 000 b 3 8/16 output select when 1, the 8-bit burst transfer output mode is selected. when 0, the 16-bit synchro- nous pixel transfer output mode is selected. 0 b 2 oen this bit enables the y(7-0), cbcr(7-0), a ctive, hsync, vsync and d vld outputs. 1 = outputs enabled; 0 = three-stated. 0 b hmp8112
20 1 vertical pixel siting when this bit is cleared (0) the chrominance pixels have a 1/2 line pixel offset from their associated luminance pixel in a 4:2:2 subsampled scheme. when this bit is set (1) the pixel siting is line aligned with the luminance pixels in a 4:2:2 subsampled scheme. the bit is cleared by a reset. 0 b 0 not used write ignored, read 0s x table 29. software reset and video status register destination address = 17 h bit number function description reset state 7 software reset when this bit is set to 1, the entire device except the i 2 c bus is reset to a known state exactly like the reset input. the software reset will initialize all register bits to their reset state as well as place the plls back at the power-up state. once set this bit is self clear- ing after only 4 clk periods. this bit is cleared on power-up by the external reset pin. 0 b 6 black screen this flag when set (1) will set the output video to black when a lost vertical sync has been detect. this flag is cleared after a reset. read only 5 line locked flag this flag when set (1) indicates that the line locked-phase locked loop has locked to the video data. the state of this flag is reflected on the locked output pin. this flag is cleared after a reset of software reset. read only 4 standard error flag this flag when set (1) indicates that the standard detected does not match the one se- lected in the video input control register. the standard is checked against a line count and if the line count is significantly different than the expected value then this flag is trig- gered. the state of this flag is reflected on the standard_error output pin. this flag is cleared after a reset or software reset. read only 3 - 0 not used write ignored, read 0s. xxxx xx table 30. reserved destination address = 18 h bit number function description reset state 7 - 0 reserved read only this register is reserved for future use. this register will read all zeros and is write ig- nored. 0000 0000 b table 31. reserved destination address = 19 h bit number function description reset state 7 - 6 reserved read only this register is reserved for future use. this register will read all zeros and is write ig- nored. 00 b 5 lost hsync control this bit controls when the pll will declare lost horizontal sync, leave track mode and re- turn to acquisition to acquire a new hsync reference. this bit should be used with vcrs with extremely gross headswitch errors. when this bit is cleared, lost line lock is declared after 12 missing horizontal syncs. when this bit is set, lost line lock is declared after one missing horizontal sync and the line lock pll will reacquire the first hsync is detects. this bit is cleared by reset. 0 b 4 - 0 reserved read only this register is reserved for future use. this register will read all zeros and is write ignored. 0 0000 b table 28. output format control register (continued) destination address = 16 h bit number function description reset state hmp8112
21 pinout 80 lead pqfp top view table 32. reserved destination address = 1a h bit number function description reset state 7 - 0 reserved read only this register is reserved for future use. this register will read all zeros and is write ig- nored. 0000 0000 b table 33. product id register destination address = 1b h bit number function description reset state 7 - 0 product id code this register contains the last two digits of the product part number for use as a software id. these bits are read only and always read 12 h . 0001 0010 b 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 agnd av cc agnd lin0 nc lin2 lin1 agnd agnd av cc agnd l_out agnd av cc clk dgnd dv cc wpe gain_cntl cclamp_cap dec_l dv cc dgnd dgnd reset dgnd test l_adin 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 y5 dv cc y4 y3 y2 y1 y0 dgnd dv cc cbcr7 cbcr6 cbcr5 cbcr4 cbcr3 dgnd cbcr2 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 dgnd dv cc dec_t lagc_cap lclamp_cap dv cc dgnd dgnd hsync vsync dgnd dv cc d vld a/d_test nc cin nc 63 62 61 a ctive y7 dgnd dgnd/nc 37 38 39 40 dv cc clk dgnd sda dvcc/nc cbcr1 cbcr0 scl 44 43 42 41 17 18 19 20 80 agnd nc field y6 agnd agnd agnd hmp8112
22 pin description name pqfp pin number input/ output description lin[0:2] 5, 6, 7 input analog video inputs. inputs 0 and 1 are composite inputs. input 2 can be either a composite input or the y component of an s-video signal. cin 19 input analog chroma input component of an s-video input. wpe 27 input white peak enable. when enabled (1), the video amplifiers gain is reduced when the digital output code exceeds 248. when disabled (0) the video amplifier will clip when the a/d reaches code 255. gain_ctrl 28 input gain control input. dc voltage to set the video amplifiers gain. dec_t 78 input decoupling for a/d converter reference. connect a 0.01 m f and 0.1 m f capacitors to agnd. dec_l 30 input decoupling for a/d converter reference. connect a 0.01 m f and 0.1 m f capacitors to agnd. lagc_cap 77 input capacitor connection for luminance agc circuit. controls the agc loop time con- stant. lclamp_cap 76 input capacitor connection for luminance clamp circuit. controls the clamp loop time constant. cclamp_cap 29 input capacitor connection for chrominance clamp circuit. controls the clamp loop time constant. l_adin 8 input luminance a/d converters input from antialiasing filter. l_out 9 output luminance or composite analog video amplifier output to antialiasing filter. sda 40 input/ output the serial i 2 c serial input/output data line. scl 41 input the serial i 2 c serial bus clock line. clk 13, 38 input master clock for the decoder. this clock is used to run the internal logic, a/d convert- ers, and phase locked loops. all i/o pins (except the i 2 c) are synchronous to this master clock. a 50ppmcrystal should be used with a waveform symmetry of 60/40% or better. reset 34 input asynchronous reset pin. master chip reset to initialize the internal states and set the internal registers to a known state. cbcr[0:7] 42, 43, 45, 47-51 output cbcr data output port. the chrominance data output port of the decoder. data is in unsigned format and can range from 0 to 255. the cbcr data is subsampled to 4:2:2 format. in 4:2:2 format the cbcr bus toggles between cb and cr samples with the first sample of a line always being cb. the port is designed to minimize external logic needed to interface to a vram serial access port, dram or fifo. y[0:7] 54-58, 60, 63, 64 output y data output port. the luminance data output port of the decoder. data is in un- signed format and can range from 16 to 255. the port is designed to minimize exter- nal logic needed to interface to a vram serial access port, dram or fifo. d vld 66 output data v alid. this pin signals when valid data is available on the data output ports. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. hsync 71 output horizontal sync. this video synchronous pulse is generated by the detection of hor- izontal sync on the video input. in the absence of video, the hsync rate is set when the internal pll counters overflow. the hsync begin and end time can be pro- grammed and is synchronous to clk. this pin is three-stated after a reset or soft- ware reset and should be pulled high through a 10k resistor. hmp8112
23 vsync 70 output vertical sync. this video synchronous pulse is generated by the detection of a vertical sync on the video input. in the absence of video the vsync rate is set by the over flow of the internal line rate counter. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. field 67 output field flag. when set (0) this signals that an odd field is presently being output from the decoder. when cleared (1) this signals an even field. this flag will toggle when no vertical sync is detected and 337 lines have elapsed. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. active 65 output active video flag. this flag is asserted (1) when the active portion of the video line is available on the output port. this signal is always set during burst output data mode. this flag is free running and synchronous to clk. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. test 36 input test input. this pin is used for production test and should be connected to digital ground. dv cc 26, 31,37, 44, 52, 59, 68, 75, 79 input 5v logic supply pins dgnd 25, 32, 33, 35, 39, 46, 53, 61, 62, 69, 72, 73, 80 input digital ground pins av cc 2, 12,14 input 5v analog supply pins agnd 1, 3, 10, 11, 15,16, 21, 22, 23, 24 input analog gnd a/d test 17 output a/d test pin. this pin should be left open. nc 4, 18, 20, 74 na no connect. these pins should be left open. pin description (continued) name pqfp pin number input/ output description hmp8112
24 absolute maximum ratings thermal information digital supply voltage (v cc to dgnd) . . . . . . . . . . . . . . . . . . . 7.0v digital input voltages . . . . . . . . . . . . . . . . . gnd -0.5v to v cc 0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating temperature range hmp8112cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, see note 1) q ja ( o c/w) pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 maximum power dissipation hmp8112cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9w maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum junction temperatures . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. dissipation rating assumes device is mounted with all leads soldered to printed circuit board electrical speci?cations v cc = 5.0v, t a = 25 o c parameter symbol test condition hmp8112c units min typ max power supply characteristics power supply voltage range dv cc , av cc note 2 4.75 5 5.25 v power supply current digital i ccop f clk = 30mhz, dv cc = 5.25v, outputs not loaded -4560ma analog i caop f clk = 30mhz, av cc = 5.25v - 170 180 ma total power dissipation p tot f clk = 30mhz, dv cc = av cc = 5.25, outputs not loaded - 0.95 1.26 w digital i/o bus clock frequency clk note 2 20 - 30 mhz clock cycle time clk 33 - 50 ns clock waveform symmetry 40 - 60 % clock pulse width high t pwh 8- -ns clock pulse width t pwl 13 - - ns input logic high voltage v ih clk dv cc = max 2.8 - - v input logic low voltage v il clk dv cc = min - - 0.8 v input leakage current i ih dv cc = max input = 0v or dv cc --10 m a i il -400 - - m a input/output capacitance c in clk frequency = 1mhz, note 2, all measurements referenced to ground t a = 25 o c --8pf rise/fall time t r , t f note 2 - - 2.0 ns input logic high voltage v ih dv cc = max 2.0 - - v input logic low voltage v il dv cc = min - - 0.8 v input logic current i ih , i il dv cc = max input = 0v or 5v --10 m a hmp8112
25 output logic high voltage v oh i oh = -4ma, dv cc = max 2.4 - - v output logic low voltage v ol i ol = 4ma, dv cc = min - - 0.4 v output logic current i oh dv cc = max, input = 0v or 5v - - 4 ma three-state output current leakage i oz --10 m a i 2 c digital i/o (sda, scl, fast mode) input logic high voltage v ih dv cc = max 0.7xv cc --v input logic low voltage v il dv cc = min - - 0.3xv cc v input logic current i ih , i il dv cc = max input = 0v or 5v --10 m a input/output capacitance c in clk frequency = 400khz, note 2, all measurements referenced to gnd t a = 25 o c --8pf output logic high voltage v oh i oh = -1ma, dv cc = max 3.0 - - v output logic low voltage v ol i ol = 3ma, dv cc = min 0 - 0.4 v scl clock frequency f scl note 2 0 - 100 khz scl minimum low pulse width t low 4.7 - - m s scl minimum high pulse width t high 4.0 - - m s data hold time t hd:data see figure 31 0 - - ns data setup time t su:data see figure 31 250 - - ns rise time t r note 2 - - 1000 ns fall time t f - - 300 ns timing characteristics data setup time t su notes 2, 3 10 - - ns data hold time t hd 0- -ns clock to out t dvld - - 8.0 ns analog performance video input amplifier voltage range v lin[0:2], v cin input termination of 75 w and 1.0 m f ac coupling, note 2 0.625 1.0 2.0 v p-p video input amplifier impedance r ain note 2 200 - - k w color sub-carrier agc range sc agc -6 - +18 db video input amplifier analog bandwidth b1v p-p sine wave input to -3dbc reduction, note 2 - 15 - mhz a/d input range a in + full scale note 2 - av cc - 1.4 -v a in offset/zero - av cc - 3.0 -v a/d input bandwidth b a/d 5 - - mhz electrical speci?cations v cc = 5.0v, t a = 25 o c (continued) parameter symbol test condition hmp8112c units min typ max hmp8112
26 video performance differential gain a v diff ebu 75% color bars, note 2 - 2 - % differential phase q diff -1- o c integral linearity inl best fit linearity - 1.5 2.25 lsb differential linearity dnl no missing codes - 0.5 1.0 lsb snr snrl weighted note 2 - 49.9 - db luminance to chrominance crosstalk x luma in composite input mode, note 2 -40-db chrominance to luminance crosstalk x chroma -40-db horizontal locking and recovery time t lock time from initial lock acquisition to an error of 1 pixel, note 2 - 30 - lines # of missing horizontal syncs before lost lock declared h sync lost note 2 - - 12 # # of missing vertical syncs before lost lock declared v sync lost --3# subcarrier lock in range 400 - - hz pixel jitter - 1/ 8 - pixel -10-ns color saturation adjustment range - - 10 db hue accuracy --2 o c hue adjustment range --30 o c brightness adjustment range - - 10 db notes: 2. guaranteed by design or characterization. 3. test performed with c l = 40pf, i ol = 4ma, i oh = -4ma. input reference level is 1.5v for all inputs. v ih = 3.0v, v il = 0v. electrical speci?cations v cc = 5.0v, t a = 25 o c (continued) parameter symbol test condition hmp8112c units min typ max hmp8112
27 typical performance curves ntsc composite phase figure 17. color bars ntsc 100% (eia) figure 18. color bars vectorscope hmp8112
28 ntsc composite phase (continued) figure 19. color bars vm700 test figure 20. differential phase and gain typical performance curves (continued) hmp8112
29 ntsc frequency response figure 21. multiburst figure 22. multiburst vm700 frequency roll-off test typical performance curves (continued) hmp8112
30 ntsc noise measurements figure 23. signal to noise ratio - flat frequency response figure 24. signal to noise ratio - 5.0mhz low pass filtered typical performance curves (continued) hmp8112
31 ntsc noise measurements (continued) figure 25. signal to noise ratio - 4.2mhz low pass filtered pixel jitter test figure 26. long term jitter - 20 pulse bar 2t typical performance curves (continued) hmp8112
32 pal composite phase figure 27. color bars ntsc 100% (eia) figure 28. color bars vectorscope typical performance curves (continued) hmp8112
33 pal composite phase (continued) figure 29. color bars vm700 test figure 30. differential phase and gain typical performance curves (continued) hmp8112
34 pal frequency response figure 31. multiburst figure 32. ntsc multi-test pattern typical performance curves (continued) hmp8112
35 figure 33. ntsc convergence test pattern figure 34. ntsc multiburst test pattern typical performance curves (continued) hmp8112
36 figure 35. ntsc smpte colorbars test pattern figure 36. pal convergence test pattern typical performance curves (continued) hmp8112
37 figure 37. pal multiburst test pattern figure 38. pal smpte colorbars test pattern typical performance curves (continued) hmp8112
38 figure 39. chrominance amplifier gain vs gain control voltage figure 40. luminance amplifier gain vs agc cap voltage timing waveforms figure 41. timing diagram typical performance curves (continued) 10 8 6 4 2 0 -2 -4 db 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 gain control voltage temperature = 25 o c v cc = 5v 10 8 6 4 2 0 -2 -4 db 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 agc cap voltage temperature = 25 o c v cc = 5v sda scl t buf t low t high t r t f t su:data t hd:data t su:stop hmp8112
39 pcb layout considerations a pcb board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. the pcb layout should implement the lowest possible noise on the power and ground planes by pro- viding excellent decoupling. pcb trace lengths between groups of v cc and gnd pins should be as short as possible. the optimum layout places the hmp8112 as close as possible to the power supply connector and the video output connector. component placement external components should be positioned as close as pos- sible to the appropriate pin, ideally such that traces can be connected point to point. chip capacitors are recommended where possible, with radial lead ceramic capacitors the sec- ond-best choice. power supply decoupling should be done using a 0.1 m f ceramic capacitor in parallel with a 0.01 m f chip capacitor for each group of v cc pins to ground. these capacitors should be located as close to the v cc and gnd pins as possible, using short, wide traces. ground plane a common ground plane for all devices, including the hmp8112, is recommended. all gnd pins on the hmp8112 must be connected to the ground plane. power planes the hmp8112 should have its own power plane that is iso- lated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. all v cc pins on the hmp8112 must be connected to this hmp8112 power plane. the hmp8112 power plane should be con- nected to the boards normal v cc power plane at a single point though a low-resistance ferrite bead, such as a ferrox- cube 5659065-3b, fair-rite 2743001111, or tdk bf45- 4001. the ferrite bead provides resistance to switching cur- rents, improving the performance of hmp8112. a single 47 m f capacitor should also be used between the hmp8112 power plane and the ground plane to control low-frequency power supply ripple. if a separate linear regulator is used to provide power to the hmp8112 power plane, the power-up sequence should be designed to ensure latchup will not occur. a separate linear regulator is recommended if the power supply noise on the v cc pins exceeds 200mv. about 10% of the noise (that is less than 1mhz) on the v cc pins will couple onto the analog outputs. analog signals traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. if this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the ana- log signals. the analog output traces should also not overlay the hmp8112 and v cc power planes to maximize high-fre- quency power supply rejection. evaluation boards the hmp8112eval stand-alone evaluation board allows connecting the ntsc/pal decoder into an ibm pc isa slot for evaluation. the board contains the hmp8112 ntsc/pal decoder, 2 mbytes of vram and a encoder. the board can accept composite or s-video input and display video on a stand composite or s-video display. the isa bus and evalu- ation software allows easy plug and play of the decoder for analysis with such tools as a vm700 video test system. hmp8112
40 hmp8112 metric plastic quad flatpack packages (mqfp/pqfp) d d1 e e1 -a- pin 1 a2 a1 a 5 o -16 o 5 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.10 0.004 -c- -d- -h- q80.14x20 (jedec mo-108cb-1 issue a) 80 lead metric plastic quad flatpack package sym- bol inches millimeters notes min max min max a - 0.134 - 3.40 - a1 0.010 - 0.25 - - a2 0.100 0.120 2.55 3.05 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.904 0.923 22.95 23.45 3 d1 0.783 0.791 19.90 20.10 4, 5 e 0.667 0.687 16.95 17.45 3 e1 0.547 0.555 13.90 14.10 4, 5 l 0.026 0.037 0.65 0.95 - n80 807 e 0.032 bsc 0.80 bsc - nd 24 24 - ne 16 16 - rev. 0 1/94 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and tolerances per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. n is the number of terminal positions. -c- -h-

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