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description the hfbr-7924wz transceiver is a high performance fber optic module for parallel optical data communica - tion applications. it incorporates 8 independent data channels (4 for transmit and 4 for receive) operating from 1 to 2.7 gb/s per channel providing a cost efective solution for very short reach applications requiring 10.8 gb/s aggregate bandwidth. the module is designed to operate on multimode fber systems at a nominal wave - length of 850 nm. it incorporates high performance, highly reliable, short wavelength optical devices coupled with proven circuit technology to provide long life and consistent service. the hfbr-7924wz transceiver module incorporates a 4 channel vcsel (vertical cavity surface emitting laser) array together with a custom 4 channel laser driver inte - grated circuit providing iec-825 and cdrh class 1m laser eye safety. it also contains a 4 channel pin photodiode array coupled with a custom preamplifer / post amplifer integrated circuit. operating on 3.3 v power supply this module provides lvttl/lvcmos control interfaces and cml compatible high speed data lines which simplify external circuitry. the transceiver is housed in mtp ? /mpo receptacled package with integral fnned heatsink. electrical connec - tions to the device are achieved by means of a pluggable 10x10 connector array. applications ? telecom and datacom switch/router rack-to-rack connections ? oc-192 very short reach (vsr), oif-vsr4-03.0, inter - connects ? computer cluster interconnects hfbr-7924wz four-channel pluggable parallel fiber optic transceiver part of the avago technologies metrak family data sheet features ? rohs compliant ? four transmit and four receive channels; 1 to 2.7 gbd per channel ? compatible with sonet scrambled and 8b10b en - coded data formats ? 850 nm vcsel array source ? conforms to pop4 four-channel pluggable optical transceiver multisource agreement ? 50/125 m multimode fber operation ? distance up to 300 m with 500 mhz.km fber at 2.5 gb/s ? distance up to 600 m with 2000 mhz.km fber at 2.5 gb/s ? pluggable package ? outputs (tx & rx) are squelched for loss of signal ? control i/o is compatible with lvttl and lvcmos ? standard mtp? mpo ribbon fber connector inter - face ? integrated heat sink ? manufactured in an iso 9002 certifed facility ? rx signal detect ordering information the hfbr-7924wz product is available for production orders through the avago technologies component field sales ofce. hfbr-7924wz no emi nose shield hfbr-7924ewz with extended emi nose shield hfbr-7924hwz no heatsink, no emi nose shield HFBR-7924EHWZ no heatsink, with emi nose shield
2 figure 1 - block diagram (dimensions in mm) figure 2 - case temperature measurement vcsel array input stage d in ch 0 - 3 + driver 4 channels driver pin array input stage control vcc_tx gnd_tx vcc_rx gnd_rx d in ch 0 - 3 - d out ch 0 - 3 + d out ch 0 - 3 - 4 channels tx_dis tx_en tx_fault* tx_reset* sd point for taking module temperature bar cod e part n um be r 0 5 10 15 20 25 0 0.5 1 1.5 2 air velocity (m/s) module case temperature rise above ambient ( o c) figure 3 - ambient air temperature and air fow for t c = +80 c
3 package dimensions figure 4a - hfbr-7924wz package dimensions (dimensions in mm) notes: 1. module mass approximately 20 grams. figure 4b - hfbz-7492ewz package dimensions (dimensions in mm)
4 figure 5b - hfbz-7492ehwz package dimensions (dimensions in mm) figure 5a - hfbz-7492hwz package dimensions (dimensions in mm)
5 figure 6 - package board footprint (dimensions in mm) 2 x ? 2.54 min. p ad keep -out 18.42 min. 13.72 50 keep-out area for mpo connector 6.73 30.23 1.89 ref. 6.73 9 x 1.27 tot = 11.43 8.95 ref. front sym. 9 x 1.27 tot = 11.43 18 ref. sym. end of modul e 2 x ? 1.7 0.05 holes 3 x ? 4.17 min. p ad keep -out 3 x ? 2.69 0.05 holes for #2 screw (10 x 10 =) 100 x ? 0.58 0.05 p ads pcb top view 100 pin fci meg- array? recept acle connectors ? 0.1 a b- c ? 0.1 a b- c ? 0.1 a b- c ? 0.1 a b- c b a c ? 0.05 a b- c 19.02 mi n 0.50 ma x 13.40 0. 2 3.60 0. 2 15.70 0.25 35.31+/- 0.20 pc b pc b front pane l note: the host electrical connector attached to the pcb must be a 100-position fci meg-array ? pao-ann to provide changes or equiva - figure 7 - host frontplate layout (dimensions in mm)
6 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. limits apply to each parame - ter in isolation, all other parameters having values within the recommended operating conditions. it should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. exposure to the absolute maximum ratings for extended periods can adversely afect device reliability. parameter symbol minimum maximum unit reference storage temperature t s -40 +100 oc supply voltage v cc -0.5 4.6 v data/control signal input voltage v i -0.5 v cc + 0.5 v transmitter diferential input voltage | v d | 2 v 1 output current (dc) i d 25 ma relative humidity (non condensing) rh 5 95 % parameter symbol minimum typical maximum unit reference case temperature t c 0 +80 oc 2, figures 2, supply voltage v cc 3.135 3.3 3.465 v figure 8 signaling rate/channel 1 2.7 gbd data input diferential peak-to-peakvoltage swing d v dinp-p 175 1600 mv p-p 3, figures 11,12 data input rise & fall time (20-80%) t r , t f 160 ps control input voltage high v ih 2.0 v cc v control input voltage low v il v ee 0.8 v power supply noise n p 200 mv p-p 4, figure 8 data i/o coupling capacitors c ac 0.1 f 5, figure 9 receiver diferential data output load r dl 100 w figure 9 notes: 1. this is the maximum voltage that can be applied across the transmitter diferential data inputs without damaging the input circuit. 2. case temperature is measured as indicated in figure 2. 3. data inputs are cml compatible. coupling capacitors are required to block dc. d v din p-p = d v dinh - d v dinl , where d v dinh = high state dif - ferential data input voltage and d v dinl = low state diferential data input voltage. 4. power supply noise is defned at the supply side of the recommended flter for all v cc supplies over the frequency range from 500 hz to 2700 mhz with the recommended power supply flter in place. 5. for data patterns with restricted run lengths, e.g. 8b10b encoded data, smaller value capacitors may provide acceptable results. recommended operating conditions recommended operating conditions specify conditions for which the optical and electrical characteristics hold. optical and electrical characteristics are not specifed for operation beyond the recommended operating conditions, reliability is not im - plied and damage to the device may occur for such operation over an extended time period.
7 transmitter electrical characteristics (over recommended operating conditions: tc= 0oc to +80oc, vcc=3.3v + 5%) parameter symbol minimum typical maximum unit reference diferential input impedance z in 80 100 120 w 6, figure 9 fault* assert time t off 100 s figure 13 reset* assert time t off 7.5 s figure 14 reset* de-assert time t on 18 ms figure 14 transmit enable (tx_en) assert time t on 18 ms figure 15 transmit enable (tx_en) de-assert time t off 7.5 s figure 15 transmit disable (tx_dis) assert time t off 7.5 s figure 15 transmit disable (tx_dis) de-assert time t on 18 ms figure 15 power-on initiation time 21 ms figure 17 control i/os tx _dis, tx_en,tx_ fault*,tx_reset* input current high | i ih | 0.5 ma 2.0 v < ? v ih < v cc input current low | i il | 0.5 ma v ee < v ih < 0.8 v output voltage low v ol v ee 0.4 v i ol = 4.0 ma output voltage high v oh 2.4 v cc v i oh = -0.5 ma parameter symbol minimum typical maximum unit reference output optical power 50/125 m, fiber na = 0.2 p out -8.0 -4.5 -2.0 dbm avg. 7 extinction ratio er 6 7.5 db 8 center wavelength l c 830 850 860 nm spectral width - rms s 0.85 nm rms rise, fall time t r , t f 60 150 ps 9 inter-channel skew 50 100 ps 10 relative intensity noise rin -127 -121 db/hz jitter contribution deterministic dj 20 50 ps p-p 11 total tj 45 120 ps p-p 12 notes: 6. diferential impedance is measured between d in + and d in - over the range 4 mhz to 2 ghz. 7. the specifed optical output power, measured at the output of a 2 meter test cable, will be compliant with iec 60825-1 amendment 2, class 1m accessible emission limits, ael regulatory compliance section. 8. extinction ratio is defned as the ratio of the average output optical power of the transmitter in the high (1) state to the low (0) state and is expressed in decibels (db) by the relationship 10log(p high avg/p low avg). the transmitter is driven with a 550 mbd, 101010 pattern. 9. these are unfltered 20% - 80% values measured with a 550 mbd 101010 pattern. 10. inter-channel skew is defned for the condition of equal amplitude, zero ps skew input signals. 11. deterministic jitter (dj) is defned as the combination of duty cycle distortion (pulse-width distortion) and data dependent jitter. determin - istic jitter is measured at the 50% signal threshold level using a 2500 mbd pseudo random bit sequence of length 2 23 -1 (prbs-23), or equiva - lent, test pattern with zero skew between the diferential data input signals. 12. total jitter (tj) includes deterministic jitter and random jitter (rj). total jitter is specifed at a ber of 10 -12 for the same 2.5 gbd test pattern as for dj and is measured with all channels operating. transmitter optical characteristics (over recommended operating conditions: tc= 0oc to +80oc, vcc=3.3v + 5%)
8 receiver electrical characteristics (over recommended operating conditions: tc= 0oc to +80oc, vcc=3.3v + 5%) parameter symbol minimum typical maximum unit reference diferential output impedance z out 100 w 13, figure 9 data output diferential peak-to-peak voltage swing d v doutp-p 500 650 800 mv p-p 14, figure 10 inter-channel skew 50 100 ps 15 data output rise, fall time t r , t f 120 150 ps 16 control i/o signal detect lvttl & lvcmos compatible output voltage low v ol v ee 0.4 v i ol = 4.0 ma output voltage high v oh 2.4 v cc v i oh = -0.5 ma assert time (off-to-on) t sda 50 s 17 de-assert time (on-to-off) t sdd 50 s 18 parameter symbol minimum typical maximum unit reference input optical power - sensitivity p in min -18 -16.0 dbm avg. 19 input optical power - saturation p in max -2.0 dbm avg. operating center wavelength l c 830 860 nm stressed receiver sensitivity -11.7 dbm 20 stressed receiver eye opening 111 ps 21 return loss 12 db 22 signal detect asserted p a -22 -17 dbm avg. 23 deasserted p d -31 -27 dbm avg. hysteresis p a - p d 0.5 1.0 db notes: 13. measured over the range 4 mhz to 2 ghz. 14. d v d out p-p = d v d out h - d v d out l , where d v d out h = high state diferential data output voltage and d v d out l = low state diferential data output voltage. d v d out h and d v d out l = v d out + - v d out - , measured with a 100 w diferential load connected with the recommended coupling capaci - tors and with a 2500 mbd, 101010 pattern. 15. inter-channel skew is defned for the condition of equal amplitude, zero ps skew input signals. 16. rise and fall times are measured between the 20% and 80% levels using a 550 mhd square wave signal. 17. the signal detect output will change from logic 0 (low) to 1 (high) within the specifed assert time for a step transition in optical input power from the deasserted condition to the specifed asserted optical power level. 18. the signal detect output will change from logic 1 (high) to 0 (low) within the specifed de-assert time for a step transition in optical input power from the specifed asserted optical power level to the deasserted condition. 19. sensitivity is defned as the average input power with the worst case, minimum, extinction ratio necessary to produce a ber < 10 -12 at the center of the baud interval. for this parameter, input power is equivalent to that provided by an ideal source, i.e. one with rin and switching attributes that do not degrade the sensitivity measurement. all channels not under test are operating receiving data with an average input power of up to 6 db above p in min . sensitivity at signal rates from 1 to 2.7 gbd is defned for a prbs 2 23 -1 test pattern. 20. the stressed receiver sensitivity is measured using 2.6 db inter-symbol interference, isi, (min), 30 ps duty cycle dependent deterministic jit - ter, dcd dj (min) and 6 db er (er penalty = 2.23 db). all channels not under test are operating receiving data with an average input power of up to 6 db, above p in min. 21. the stressed receiver eye opening is measured using 2.6 db isi (min), 30 ps dcd dj (min), 6 db er (er penalty = 2.23 db) and an average input optical power of -11.7 dbm. all channels not under test are operating receiving data with an average input power of up to 6 db above p in min . 22. return loss is defned as the ratio, in db, of the received optical power to the optical power refected back down the fber. 23. signal detect assertion requires all optical inputs to exhibit a minimum 6 db extinction ratio at p a = -17 dbm. all channels not under test are op - erating with prbs 2 23 -1patterns, asynchronous with the channel under test, and average input power of up to 6 db above the specifed p in min. receiver optical characteristics (over recommended operating conditions: tc= 0oc to +80oc, vcc=3.3v + 5%)
9 general/control electrical characteristics (over recommended operating conditions: tc= 0oc to +80oc, vcc=3.3v + 5%) regulatory compliance the overall equipment design will determine the certi - fcation level. the module performance is ofered as a fgure of merit to assist the designer in considering their use in equipment designs. electrostatic discharge (esd) there are two design cases in which immunity to esd damage is important. the frst case is during handling of the module prior to mounting it on the circuit board. it is important to use normal esd handling precautions for esd sensitive de - vices. these precautions include using grounded wrist straps, workbenches and foor mats in esd controlled areas. the module performance has been shown to provide adequate performance in typical industry pro - duction environments. the second case to consider is static discharges to the exterior of the equipment chassis containing the mod - ule parts. to the extent that the mt-based connector receptacle is exposed to the outside of the equipment chassis it may be subject to whatever system-level esd test criteria that the equipment is intended to meet. the module performance exceeds typical industry equip - ment requirements of today. electromagnetic interference (emi) most equipment designs using these high-speed mod - ules from avago technologies will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22) in europe and vcci in japan. these modules, with their shielded design, perform to the limits listed in table 1 to assist the designer in the management of the overall equipment emi performance. parameter symbol minimum typical maximum unit reference supply current i cct 300 400 ma power dissipation p dist 1.0 1.39 w immunity equipment utilizing these modules will be subject to radio frequency electromagnetic felds in some environ - ments. these modules have good immunity to such felds due to their shielded design. eye safety these 850 nm vcsel-based transceiver modules provide eye safety by design. the hfbr-7924wz has been registered with cdrh and certifed by tuv as a class 1m device under amend - ment 2 of iec 60825-1. see the regulatory compliannce table for further detail. if class 1m exposure is possible, a safety-warning label should be placed on the product stating the following: laser radiation do not view directly with optical instruments. class 1m laser product mtp ? (mpo) optics cleaning statement the optical port has recessed optics that are visible through the nose of the port. the port plug provided should be installed whenever a fber cable is not con - nected. this ensures the optics remain clean and no cleaning should be necessary. in the event of the optics being contaminated, forced nitrogen or dry clean air at less than 20 psi is the recommended cleaning agent. the features of the optical port and guide pins preclude the use of any solid instrument. liquids are not advised due to potential damage. application of wave soldering, refow soldering and/or aqueous wash processes with the hfbr-7924wz mod - ules device on board is not recommended as damage may occur. normal handling precautions for electrostatic sensitive devices should be taken (see esd section).
10 table 1 - regulatory compliance notes: 24. emi performance only refers to shielded version hfbr-7924ewz and HFBR-7924EHWZ. 25. emi performance could be improved by connecting the following pads to electrical ground : c9, g7 and h9. feature test method performance electrostatic discharge (esd to the electrical pads) jedec human body (hbm) (jesd22-a114-b) jedec machine model (mm) module > 1000 v module > 50 v electrostatic discharge (esd to the connector receptacle) variation of iec 61000-4-2 typically withstand at least 6 kv (module biased) without damage when the connector receptacle is contacted by a human body model probe electromagnetic interference (emi) fcc class b cenelec en55022 class b (cispr 22a) vcci class 1 typically pass with 5 db margin. (see notes 24 and 25) immunity variation of iec 61000-4-3 typically show no measurable efect from a 10 v/m feld swept from 80 mhz to 1 ghz applied to the module without a chassis enclosure. laser eye safety and equipment type testing iec 60825-1 amendment 2 cfr 21 section 1040 iec ael & us fda cdrh class 1m cdrh accession number: 9720151-22 tuv bauart license: e2171095.04 component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equipment including electrical business equipment. ul file number: e173874 rohs complaince less than 1000ppm of cadmium, lead, mercury, hexavalent chromium, polybrominated biphe - nyls, and polybrominated biphenyl ethers
11 4+4 transceiver module pad assignment - hfbr-7924wz dout00- k v ee rx j dout03+ h v ee rx g v ee rx f v ee tx e v ee tx d din03- c v ee tx b din00+ a 1 dout00+ v ee rx dout03- v ee rx v ee rx v ee tx v ee tx din03+ v ee tx din00- 2 v ee rx v ee rx v ee rx v ee rx v ee rx v ee tx v ee tx v ee tx v ee tx v ee tx 3 dout1+ v ee rx dout02- dnc dnc dnc dnc din02+ v ee tx din01- 4 dout1- v ee rx dout02+ dnc dnc dnc dnc din02- v ee tx din01+ 5 v ee rx v ee rx v ee rx dnc dnc dnc dnc v ee tx v ee tx v ee tx 6 v cc b rx v cc b rx v cc b rx dnc dnc dnc dnc v cc tx v cc tx v cc tx 7 dnc reserved tbd ms a reserved tbd ms a reserved tbd ms a dnc tx_dis tx_en dnc dnc dnc 8 dnc reserved tbd ms a reserved tbd ms a sd dnc reset* fault* dnc dnc dnc 9 v cc a rx v cc a rx v ee rx dnc dnc dnc dnc v ee tx v cc tx v cc tx 10 top view (pcb layout) (10 x 10 array)
12 table 2. transceiver module pad description symbol functional description din ch 0 - 3 +/- through din ch 0 - 3 +/- transmitter diferential data inputs for channels 0 through 3: data inputs are cml compatible. tx_dis transmitter disable: lvcmos input (internal pull down). control input used to turn of the transmitter optical outputs. high active. vcsel array is of when high. normal operation is enabled when low. tx_en transmitter enable: lvcmos input (internal pull up). control input used to enable the transmitter optical outputs. high active. vcsel array is of when low. normal opera - tion is enabled when high. tx_fault* transmitter fault: lvcmos output. transmitter status output indicating an eye-safety over-current condition for any vcsel, an out of temperature range condition and/or a calibration data corruption detection. high output state indicates normal operation. low output state indicates the fault condition. an asserted fault* condition disables the vcsel array and is cleared by tx_reset*. tx_reset* transmitter reset: lvcmos input (internal pull up). control input used to reset the transmitter logic functions. active low. vcsel array is of when low. normal operation is enabled when high. v ee _tx transmitter signal common. all transmitter voltages are referenced to this potential un - less otherwise stated. directly connect these pads to the pc board transmitter ground plane. v cc _tx transmitter power supply. dout ch 0 - 3 +/- through dout ch 0 - 3 +/- receiver diferential data outputs for channels 0 through 3: data outputs are cml com - patible. data outputs are squelched for de-asserted signal detect. sd receiver signal detect: lvcmos output. receiver status output indicating valid signal in all channels. high output state (asserted) indicates valid optical inputs to each and every channel. low output state (de-asserted) indicates loss of signal at any of the monitored receiver inputs. all channels are monitored. dnc do not connect. do not connect to any electrical potential. v ee _rx receiver signal common. all receiver voltages are referenced to this potential unless otherwise stated. directly connect these pads to the pc board receiver ground plane. v cc a_rx pin preamplifer power supply rail. v cc b_rx receiver quantizer power supply rail. v cc a_rx and v cc b_rx can be connected to the same power supply. however, to insure maximum receiver sensitivity and minimize the impact of noise from the power supply, it is recommended to keep the power supplies separate and to use the recommended power supply fltering network on v cc a_rx (see figure 8). module case transceiver case common. transceiver case common incorporates all exposed conduc - tive surfaces and is electrically isolated from transmitter signal common and receiver signal common.
13 figure 8 - recommended power supply flter vcca rx vcca rx vccb rx vccb rx vccb rx c12 0.1 f 0603 c11 0.1 f 0603 c10 10 f 1210 c9 10 f 1210 r6 1.0 k ? 0603 r5 100 ? 0603 l6 6.8 nh 0805 l5 1 h 2220 v cc vcc tx vcc tx vcc tx vcc tx hfbr-7924wz r4 1.0 k ? 0603 r3 100 ? 0603 l4 6.8 nh 0805 l3 1 h 2220 c8 0.1 f 0603 c7 0.1 f 0603 c6 10 f 1210 c5 10 f 1210 r2 1.0 k ? 0603 r1 100 ? 0603 l2 6.8 nh 0805 l1 1 h 2220 c4 0.1 f 0603 c3 0.1 f 0603 c2 10 f 1210 c1 10 f 1210 v cc v cc
14 figure 9 - recommended ac coupling and data signal termination receiver d out + d out - d in + d in - c ac c ac zi n r dl ac coupling capacitors (dc blocking capacitors) should be used to connect data outputs to the load. the differential data pair should be terminated with a differential load, r dl , of 100 ? using either an internal load, z in , as shown above, or an external load, if necessary. v di/o refers to either v din or v dout as appropriate. receiver d out + d ? out - ? v dout + - ? v d i/ol v di/o + v di/o - ? v di/oh ? v di/oh ? v di/ol ? v di/o p-p - + + - transmitter d in + d in - ? v din d in - d in + z in 50 ? 50 ? v bias (n onimal 1.9v) v cct v ee d out+ v ee 50 ? d out- v cc 50 ? figure 11 - transmitter data input equivalent circuit figure 12 - receiver data output equivalent circuit. figure 10 - diferential signals
15 figure 13 - transmitter fault* signal timing diagram no fault detected fault detected tx out ch 0 - 3 fault* < 100 s ~ 100 ns tx_out ch 3 tx_out ch 2 tx_out ch 1 7.5 s (max) shutdown normal reset* fault* 18 ms (max) >100 ns ~4.2 ms ~4.6 ms (typ) tx_out ch 0 figure 14 - transmitter reset* timing diagram
16 figure 15 - transmitter tx_en and tx_dis timing diagram ~ 7.5 s tx_en tx out ch 0 - 3 normal shutdown (a) ~ 7.5 s tx_dis normal shutdown tx out ch 0 - 3 (b) (c) ~4.2 ms ~4.6 ms ~18 ms tx out ch 0 tx out ch 1 tx_en [1] tx out ch 3 note [1] : tx_dis, which is not shown, is the functional complement of tx_en. tx out ch 2 > 1 ms ~ 200 ns ~18 ms ~4.2 ms tx_en [1] note [1] . tx_dis, which is not shown, is the functional complement of tx_en. ~4.6 ms tx out ch 0 tx out ch 1 fault* tx out ch 3 tx out ch 2 figure 16 - transmitter fault recovery via tx_en timing diagram
17 tx_out 0 tx_out 1 tx_out 3 tx_out 2 vc c vcc > 2.8v ~21 ms 6.5m s ~4.6ms ~4.6ms ~4.6ms normal normal normal normal figure 17. typical transmitter power-up sequence for product information and a complete list of distributors please go to our web site: www.avagotech.com avago avago technologies and the a logo are trademarks of avago technologies limited in the united states and other countries. data subect to change. copyright 2005-2008 avago technologies limited. all rights reserved. a02-1159en - april 9 2008

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